Electrical Load Emulation using Optimal Feedback
Control Technique
Y. Srinivasa Rao
Mukul Chandorkar
Department of Electrical Engineering
Indian Institute of Technology, Mumbai, India 400 076
Email: [email protected]
Department of Electrical Engineering
Indian Institute of Technology, Mumbai, India 400 076
Email: [email protected]
Abstract—The paper presents a method of emulating electrical
loads using power electronic converters. The loads include machines such as induction motors and their associated mechanical
load and also more complex machine systems such as winddriven generators. The load emulator is effectively a dynamically
controllable source or sink which is capable of bidirectional
power exchange with either a grid or another power electronic
converter system. Using load emulation, the feasibility of connecting a particular machine to a grid under various load conditions
can be examined without the need for any electromechanical
machinery. The paper considers the case of a power electronic
Voltage Source Inverter (VSI) emulating a three phase induction
motor connected to a three phase ac grid. The VSI is operated in
a mode where the current drawn from the ac grid is controlled by
closed loop control. Experimental results are provided to verify
the scheme.
I. I NTRODUCTION
Load emulation is the concept of controlling a power
electronic converter such as a Voltage Source Inverter (VSI) in
such a manner that its behavior resembles that of an electrical
load such as an induction machine. Rapid prototyping [1] [2]
is a method of verifying the control techniques that are
implemented in embedded systems such as Digital Signal
Processors (DSP). [1] describes a method of simulating the
details of DSPs and their associated analog-to-digital interface.
[2] describes a method of combining simulations of the power
circuit and the control circuit to closely describe the behavior
of the practical system that would be implemented. On the
other hand, load emulation provides a platform where the
exact behavior of an electrical load can be described in
hardware at real power levels using a controllable VSI. The
load emulator can provide different load characteristics with
which the control algorithms and inverter design can be tested.
Therefore, load emulation offers a more flexible platform for
testing inverters in a laboratory environment.
The primary objective of load emulation is to design the
power interface for the actual electrical load. Therefore, the
behavior of the load emulator must be close to the actual load
when connected to a power supply. The power supply can
be a three-phase grid or another three-phase VSI. Therefore,
accurate information of the phase angle of the power supply
voltages is essential. A popular method of obtaining the
phase angle of a three phase voltage is through a Phase
Locked Loop (PLL). The PLL takes as its input the three
Grid /
Inverter
under
test
vs
Ls
Lf
vf
Vdc
i inv
is
Converter
bridge
Cf
FPGA
Modulator
Signal cond. & ADC
Control
i ref system
PLL
Emulator
Fig. 1.
θ
Load Model
DSP
Schematic diagram of Load Emulator.
phase voltages of the power supply and produces a sinusoidal
signal of the same frequency as the frequency of the supply
voltages. The topic of PLL has been extensively reported in
literature [3] [4] [5]. However, the effectiveness of the PLL
has not been investigated when the input voltages are the Pulse
Width Modulated (PWM) voltages of a VSI with a switching
frequency of approximately 5 kHz.
The main component of load emulation is the algorithm that
generates the desired currents to be drawn so as to mimic the
actual load. Thereafter, the control system ensures that the VSI
draws or supplies currents that are as close as possible to the
desired current references. The load emulator VSI is connected
to the power supply through an interface impedance known as
the filter. The topology of this filter has been discussed in
this paper and has been chosen to be an inductor-capacitorinductor (L-C-L) filter. Since, the load emulator VSI mimics
the behavior of an electrical load, it would have to draw or
source active power as per the load characteristics. In order
to enable the emulator VSI to be a sink or source of active
power, a back-to-back VSI topology has been proposed. The
dc link of the emulator VSI is common to another VSI known
as the reverse power flow converter. This reverse power flow
converter is a three phase VSI whose ac output is interfaced
to the three phase ac grid. The reverse power flow converter
draws or supplies active power from the three phase ac grid
for the emulator VSI.
Two controllers are implemented for the entire system. In
order to ensure bidirectional power flow, the reverse power
Lf
flow converter is controlled in current control mode. The
voltage of the dc link common to both the emulator VSI and
the reverse power flow converter is maintained constant by this
controller. This current controller of the reverse power flow
converter is not the focus of this paper and reported literature
contains this in sufficient detail [6]. The load emulator VSI that
is interfaced to the three phase power supply through the L-CL filter has been controlled through optimal control strategy.
The optimal feedback controller used is a Linear Quadratic
Regulator (LQR) that has been discussed in this paper. The
paper also investigates the capability of the optimal controller
and therefore the limits of load emulation are presented.
Vdc
Inverter i f
Grid
(a) Inverter interface with inductor.
Lf
Vdc
Inverter
if
Pcc
ic
is
Cf
Grid
(b) Inverter interface with LC filter.
Fig. 2.
II. P RINCIPLE OF L OAD E MULATION
Fig. 1 depicts the schematic diagram of the load emulator
with the associated digital control consisting of a DSP and a
Field Programmable Gate Array (FPGA). The diagram shows
the L-C-L filter that is used to interface the load emulator VSI
to the three phase power supply. The diagram shows the three
phase power supply to be the three phase distribution level ac
grid. In the later sections, the power supply will also be a three
phase VSI. The supply voltages vs are used for generating the
references for the currents to be drawn by the emulator VSI.
The references are generated by an algorithm in the DSP. The
PLL is also an essential component of the reference generation
and is implemented in DSP. The current is drawn from the
three phase ac grid is the current that must be controlled to
be approximately equal to the reference currents. The optimal
control algorithm is implemented in the DSP and requires the
feedback of both the currents is and the emulator VSI currents
iinv . The PWM signals are generated by the FPGA and fed
to the gate drivers of the emulator VSI. Before describing the
optimal feedback control strategy, a justification of using the
L-C-L filter as an interface between the emulator VSI and the
ac grid is provided.
The well-reported method for current injection requires an
inverter with an output inductor filter Fig. 2(a). In Fig. 2(a),
the VSI is connected to the ac grid as a node called the Point
of Common Coupling (PCC). With this topology, the current
injected into the PCC would contain a substantial amount of
switching harmonic ripple. Due to internal impedance of grid
shown in the Fig. 2(a), the voltage at the PCC will be distorted.
Therefore, by connecting a VSI to the ac grid, a power quality
problem has been introduced.
As shown in Fig. 2(b), by connecting a capacitor Cf , a
low pass filter is present at the output of the VSI. The low
pass filter provides a low impedance path for high switching
frequency ripple. Therefore the PCC voltages will be smooth.
However, since is = ic + if , current drawn from grid will be
different from the desired references. Though a larger filter
capacitor Cf will provide smoother PCC voltages, the error
in the currents drawn from the grid will increase as ic =
Cf · dvpcc /dt. Moreover, if the ac grid were to be replaced
by another inverter, the current injection strategy would not
work as the VSI replacing the grid would not have an internal
impedance.
Pcc
Inverter interface with LC filter.
Lf
Vdc
Inverter
if
ic
vf
Ls
Cf
Pcc
vs
is
Grid /
Inverter
Vdc
Emulator
Fig. 3.
Emulator interface with LCL filter.
Fig. 3 shows an LCL output filter structure which will
provide a solution to the above two mentioned drawbacks.
The Lf Cf filter removes some of the switching frequency
harmonics resulting in a current through Ls that is relatively
smooth. The control strategy employed will attempt to control
the current is through the inductor Ls . Therefore, the error
in the current is from its desired reference will be negligible.
Moreover, in the case of the inverter being interfaced to another inverter, the voltage at the filter capacitor Cf resembles a
back-emf and therefore, the interfacing problems are removed.
Two methods of controlling is to be approximately equal to the
desired references have been examined. The first method is an
indirect method where the reference for vf has been generated
from the reference for is . The voltage vf can be controlled to
be approximately equal to its reference by the flux modulator
strategy [7]. The direct method of controlling the current is is
using the optimal feedback controller. This controller is a state
feedback controller designed using the LQR technique [8].
Both currents is and if are measured and fed back to be
compared with their respective references. The voltage vf
is implicitly controlled. In the case of the VSI emulating
an induction motor, the voltage across the capacitor Cf is
related to the induced rotor voltage of the induction motor.
The detailed description of the optimal feedback controller is
provided in the next section.
III. C ONTROLLER D ESIGN
Control system ensures the emulator draws a current is that
is approximately equal to the desired reference. The transient
response of the system determines the tracking accuracy
between the demanded and actual current drawn from the
inverter under test. Here the control technique used is a state
feedback control strategy. Fig. 4 shows the closed loop control
e
xr
uc
K
+
u
y
Inverter
Bode Diagram
0
x
−50
Fig. 4.
Magnitude (dB)
−
Hysteresis
switching
Closed loop control scheme.
−100
−150
scheme employed for the VSI of Fig. 3. The state vector is:
x(n + 1) = Gx(n) + Hu u(n) + Hw w(n)
(4)
y(n) = Cx(n)
(5)
where w(n) = vs (nTs ) which is a disturbance, and Ts is
the sampling time interval. The LQR seeks to minimize a
performance index,
∞
1 [e (n)Qe(n) + uc (n)Ruc (n)]
2 n=0
(6)
where e = xr −x and the stands for the transpose of a vector.
In (6), Q is a diagonal matrix that decides the importance to
be given to the state variables and R is the penalty which is
imposed on the controller. The dlqr function of the simulation
provides the state feed back matrix K,
uc (n) = K (xr (n) − x(n))
(7)
x(n + 1) = Gx(n) + Hu K (xr (n) − x(n)) + Hw w(n) (8)
Y (n) = Cx(n)
180
90
0
−90
2
(9)
3
10
10
Fig. 5.
4
10
5
10
Frequency (rad/sec)
6
10
7
10
8
10
Closed loop frequency response of the system.
6
(3)
The output variable y is therefore the current is that is
injected into the grid. However, as stated in the previous
section both currents if and is are measured. The voltage vf
across the filter capacitor Cf also forms the state vector along
with if and is . However, its measurement has been avoided
as will be described later in the section.
The objective of the VSI is to inject a current is that is
approximately equal to a desired reference isr . In the above
equation, u is the emulator inverter’s switching function and
ac grid voltage vs is considered to be a disturbance. The state
feed back controller is an optimal controller designed using the
Linear Quadratic Regulator (LQR) to achieve the objective [8].
For implementation using DSP, the controller is realized in
a discrete-time form. The continuous time state equations are
converted to standard state space discrete-time form.
J=
270
Phase (deg)
The state space equations are obtained by applying Kirchoff’s
Current Law and Kirchoff’s Voltage Law to to Fig. 3:
⎡
⎤
−rs /Ls −1/Ls
0
0
−1/Cf ⎦ x
ẋ = ⎣ 1/Cf
0
1/Lf −rf /Lf
⎤
⎤
⎡
⎡
1/Ls
0
⎦ u + ⎣ 0 ⎦ vs
0
(2)
+⎣
0
−Vdc /Lf
y = is = [1 0 0] x
−200
360
(1)
4
Currents (A)
x = [is vf if ]T
2
0
-2
-4
-6
0.8 0.820.840.860.88 0.9 0.920.940.960.98 1
Time (seconds)
Fig. 6.
Simulation of control system for harmonic references.
To obtain the transfer function between the output variable
y and the reference state vector xr , the disturbance w(n) is
neglected. The equation (8) can be written as
x(n + 1) = Gx(n) + Hu Kxr (n) − Hu Kx(n)
(10)
which can be written as
x(n + 1) = (G − Hu K)x(n) + Hu Kxr (n)
(11)
y(n) = Cx(n)
(12)
Equation (11), (12) are the closed loop state equations. The
system parameters are chosen as Ls = 3 mH, rs = 0.01 Ω, Lf
= 1 mH, rf = 0.01 Ω, Cf = 50 μF. The choice of Q and R
are:
⎡
⎤
50
0
0
0 ⎦ ; R = 65
Q = ⎣ 0 0.05
(13)
0
0
0.01
where the weighting for is is chosen to be much larger than the
other states in the matrix Q. K = [0.6188 0.0404 0.0929]
with a sampling time of 20 μs. Since the control coefficient
for error in vf is extremely small [0.0404], it is possible to
set this constant to zero. This also provides another advantage
of eliminating measurement of vf .
The closed loop frequency response characteristics can be
represented in a Bode plot as shown in Fig. 5. From Fig. 5, it
va
vb
15
Currents (A)
10
vc
vq
ω
abc
to
dq
0 −
vd
5
PID
sinωt cosωt
Notch
Filter
0
Oscillator
+ v
dnf
-5
(a) Block diagram of the control system
-10
Im (z)
-15
0.8 0.820.840.860.88 0.9 0.920.940.960.98 1
Time (seconds)
Fig. 7.
Simulation of control system for transient references.
can be observed that the gain of the closed loop system is unity
for frequencies up to 10000 rad/s. Moreover, the phase lag is
approximately zero for frequencies up to 350 rad/s. From the
simulations results of Fig. 6, current references isr containing
fundamental 50 Hz components can be tracked with negligible
error. Harmonics in the current reference will be tracked with
a phase lag. The controller tracks zero current references
with negligible error. Fig. 7 shows the results of transient
response and stability of the system. To enable the VSI to be
able to inject currents containing harmonic components, the
bandwidth of the controller can be increased by appropriately
adjusting the matrix K.
X
X
1
Re (z)
X
0.97
(b) Notch filter design
Fig. 8.
Closed loop scheme of the PLL
frequency ω
= ω. In the steady state the cosine wave cos ω
t
has a frequency equal to the frequency of the grid voltages and
is in phase with the voltage va . When the grid voltages va ,vb ,vc
are balanced, vd can be forced very close to zero and therefore
IV. T HREE PHASE P HASE -L OCKED L OOP SYSTEM
the estimated angular frequency ω
will be constant. However,
In the proposed system the reference voltages for the
when the grid voltages are unbalanced, they possess a negative
load models in DSP are derived from the PCC. In Fig. 3
sequence component. On transformation to the d-q frame,
voltage vs may be a PWM waveform, or may be distorted
the negative sequence component appears as a component
by various external factors. Sometimes even grid voltages
whose frequency is twice that of the fundamental frequency.
possess a certain degree of unbalance which may also be
Therefore, ω
will contain oscillations of a frequency twice that
extreme in certain untoward situations. In all these cases the
of the fundamental frequency. To prevent this, a notch filter [4]
control system requires accurate information of the phase
is included after the d-q transformation to remove the double
angle of the voltage at the PCC. Therefore, synchronization
harmonic component from vd .
and frequency estimation using a phase locked loop (PLL)
Fig. 8(b) shows the design of the notch filter. The “O”s
scheme is employed. This system using a notch filter and PID
represent
zeros and “X”s represent poles in the complex Z
controller which produces accurate information of the phase
plane.
The
fundamental frequency of the grid is close to the
angle is discussed in this section.
nominal
expected
frequency of ω0 = 100π rad/s. The sampling
The basic control scheme of the PLL can be described as
frequency
of
the
analog to digital conversion is fs = 1250
follows. The grid voltages va , vb and vc are converted to the
3
=
2.5π
∗
10
rad/s. Since, the objective of the notch
Hz,
ω
s
d-q reference frame through the standard transformation of
filter
is
to
remove
the
double frequency harmonic term, a pair
[3]–[5]
±j2ω0 /ωs
= e±j0.08 .
of complex zeroes are added at z = e
2
1 √
−1/2 −1/2
vd
cos ω
t sin ω
t
It is to be noted that conjugate zeroes are added to ensure
√
=
vq
t cos ω
t
3/2 − 3/2
0
3 − sin ω
that the co-efficients of the filter are real. To ensure that the
T
va vb vc
(14) notch filter is selective and has a low gain only for frequencies
close to the double frequency harmonic, complex poles are
The closed loop control scheme of the PLL is shown in added at the same frequency as the zeroes but within the
Fig. 8(a). The block “abc to dq transformation” implements unit circle to ensure stability of the system. By adding the
the transformation of (14). The voltage vd is forced to zero complex poles close to the unit circle at a magnitude of 0.97
through a PID controller whose output is the estimated angular (z = 0.97e±j0.08 ), the system is fairly resonant with a sharp
frequency ω
. From Fig. 8(a), by forcing vd to zero, the d- notch. To ensure that the dc quantity produced by the d-q
axis of the rotating reference frame is forced to be aligned transformation corresponding to the fundamental frequency is
with the voltage vector Vs . Therefore, the estimated angular not attenuated, another real pole is added at z = 0.97. The
va
20
vc
vb
200
A
0
V
isa
0
-10
-100
-200
-20
0
20
-300
10
0.1
0.05
0.15
isb
isb_ref
0
-10
cos ωt
0.5
V
0.1
0.05
A
0
1
-20
va
0
0
0.05
0
0.05
vsa
0.1
vsa_pll
0.15
V
50
-0.5
0
0
-50
(350v/div)
-1
0.1
0.05
Time (s)
Fig. 9.
isa_ref
10
100
Experimental results of PLL for unbalanced utility voltages.
total transfer function of the notch filter is given by
z 2 − 1.9974z + 1
Hnf (z) =
4.7692 2
z − 1.7976z + 0.81z
0.03
z − 0.97
0.1
0.15
Time (s)
Fig. 10.
Performance of control system and PLL for harmonic currents.
to produce smooth waveforms despite notches in the PCC
voltages.
(15)
To prevent quantization errors while implementing in DSP,
the notch filter is implemented in cascade form with the two
transfer functions within brackets converted separately into
difference equations.
The transfer function of the PID regulator is as follows:
Ki
+ Kd s · E(s)
(16)
Y (s) = Kp +
s
In the system transfer function (16) the derivative term is
added in order to improve the system response. Sampling time
step dt for the PLL is selected as 80 μs. Therefore Ki = 12.5,
Kp = 1.0 and Kd = 0.00004.
V. E XPERIMENTAL R ESULTS
Fig. 9 shows the performance of the PLL for unbalanced
t is seen
grid voltages, where vb = 0. The cosine wave cos ω
to have the same frequency and phase as that of va . By
increasing the filter’s order, the filter gets sharper and hence
suppresses the undesired components even more effectively
but this makes the response slower. This will also make the
filter more sensitive to the variations of the center frequency
ωo which may happen in some power systems.
A three-phase experimental setup has been built to verify
the accuracy of the proposed system. In this setup the power
circuit is rated at 30 A, 415 V input/output line to line voltages
and 750 V dc bus formed by 1100 μF capacitors. Various linear
and nonlinear current references are emulated to evaluate the
control system.
A. Current Harmonics
The source of the current harmonics can be considered as
nonlinear loads such as rectifiers.
The upper trace of Fig. 10 shows the tracking performance
of the current controller for current references containing
harmonic components. The lower trace shows the effectiveness
of the PLL for distorted PCC voltages. The PLL can be seen
B. Induction motor model
To finally implement the controller for the 3-phase 4pole squirrel cage induction motor emulator, the parameters
mentioned in Table I are taken as a reference model. The
reference currents are generated from this model [9].
TABLE I
I NDUCTION MOTOR MODEL PARAMETERS
rs = 2.7 Ω
lls = 0.01235 H
lm = 0.2485 H
J = 0.025524 kgm2
LLvg = 415 Vrms
rr = 2.849 Ω
llr = 0.01325 H
Tl = 14.247 N m
P =4
F req. = 50 Hz
The model is simulated in real-time to obtain the free
acceleration characteristics of the machine when started directon-line with no load. While the motor is running under no load
steady state, a 80% rated torque is suddenly applied at t = 1
second to the rotor in order to observe the transient behavior
of the system. Fig. 11 shows the experimental waveform of aphase stator current wherein the measured currents are nearly
identical to reference currents. Fig. 12 shows the experimental
waveforms of rotor mechanical speed, electromagnetic torque
and active power drawn by the emulator. For the given parameter values shown in table I, the transient and steady state
currents of the emulator are as desired. The current waveforms
have nominal ripple and the control system is stable.
C. PWM reference voltages
Under the circumstances when both the source and load are
VSIs, the reference voltages will be PWM type signals as the
source is also a VSI. The switching frequency of the source
VSI is 5 kHz and the control algorithm is executed every 20
μs. The upper trace of Fig. 13 shows the tracking accuracy of
the load VSI, where the currents drawn are from the inverter
under test. The lower trace shows the effectiveness of the PLL
in synchronizing with the PWM output of the source VSI. The
PLL is seen to synchronize to PWM voltages with negligible
phase error.
15
isa
10
isb
isc
10
5
A
A
5
0
-5
0
-5
-10
-10
-15
0
0.2
0.4
0.8
0.6
isa_ref
1
isa
10
5
isa_ref
5
A
A
0.1
0.05
isa
0
0
-5
-5
-10
1.1
1.05
0
1.15
Time (s)
Fig. 11.
Time (s)
Experimental results of a-phase stator current.
Fig. 14. Experimental results of emulator for three phase unbalanced current
references.
rad/sec
150
rotor mechanical speed
100
50
0
0
30
0.1
0.2
0.3
0.4
0.5
Nm
20
This paper has discussed load emulation which is capable of
simulating an electrical load in real-time with power electronic
converter. The state feedback controller has been designed and
implemented in a DSP-FPGA platform and has been shown
to perform satisfactorily in steady state and transients. The
system was operated to emulate various electrical load models
for steady state and transient conditions. Experimental results
of control system and PLL are discussed.
electromagnetic torque
0
0
0.2
0.4
0.6
Watts
3000
active power
2000
1000
0
0
0.2
Fig. 12.
0.4
time (sec)
VI. C ONCLUSIONS
0.7
0.6
10
4000
0.6
Physical variables of IM model.
isa_ref
R EFERENCES
[1]
isa
A
5
0
[2]
-5
0
0.01
0.02
vsa
0.03
vsa_pll
0.04
0.05
50
V
0.1
0.05
[3]
[4]
0
-50
[5]
0
0.01
0.02
0.03
0.04
Time (s)
Fig. 13.
[6]
Emulator performance for PWM reference voltages.
[7]
D. Unbalanced three phase three wire load
Fig. 14 shows the emulator drawing unbalanced currents
from the source VSI. It is to be noted that the source VSI
being a three phase three wire VSI, the sum of the currents
drawn must equal zero. Therefore, the sum of the references
for the currents to be drawn by the load VSI are also zero with
a 50% unbalance in the b phase current. The lower trace shows
the tracking performance where the reference is tracked with
negligible error. These results demonstrate that this control
system along with PLL can be used to test the inverters with
acceptable accuracy.
[8]
[9]
Joep Jacobs, Dirk Detjen, Claus-Ulrich Karipidis, and Rik W. De
Doncker, ‘Rapid prototyping tools for power electronic systems: Demonstration with shunt active power filters,’ IEEE Transactions on Power
Electronics, vol. 19, no. 2, pp. 500-507, March 2004.
Antonello Monti, Enrico Santi, Roger A. Dougal, and Marco Riva, ‘Rapid
prototyping of digital controls for power electronics,’ IEEE Transactions
on Power Electronics, vol. 18, no. 3, pp. 915-923, May 2003.
V. Kaura, V. Blasko ‘Operation of a phase locked loop system under distorted utility conditions,’ IEEE Transactions on Industrial Applications,
Vol. 33, No. 1, pp 58-63, Jan/Feb 1997.
S-J. Lee, J-K. Kang, S-K. Sul, ‘ A new phase detecting method for power
conversion systems considering distorted conditions in power system,’
Proceeding of IEEE Industry Applications Conference, Vol. 4, pp 21672172, October 1999.
S.K Chung, ‘Phase-locked loop for grid-connected three-phase power
conversion systems,’ IEE Proceedings of Electric Power Applications,
Vol. 147, No. 3, pp 213-219, May 2000.
R. R. Sawant and M. C. Chandorkar, ‘A Multi-functional Power Electronic Compensator using Instantaneous p-q-r Theory,’ in Proceedings of
2nd National Power Electronic Conference, Indian Institute of Technology, Kharagpur, India December 2005, pp. 321-326.
M. C. Chandorkar, ‘New Technique for Inverter Flux Control,’ IEEE
Transactions on Industry Applications, vol. 37, no. 3, pp. 880-887,
May/June 2001.
Komurcugil H, Kukrer O, Doganalp A, ‘Optimal control for singlephase UPS inverters based on linear quadratic regulator approach,’
Proceedings of SPEEDAM-06 International Symposium on Power Electronics, Electrical Drives, Automation and Motion pp 1137 - 1142, May,
23rd - 26t h, 2006.
Roger Champagne, Louis-A. Dessaint, Handy Fortin-Blanchette, and
Gilbert Sybille, ‘Analysis and validation of a real-time AC drive simulator,’ IEEE Transactions on Power Electronics, vol. 19, no. 2, pp. 336-345,
March 2004.