Electrical Load Emulation using Power Electronic
Converters
Y. Srinivasa Rao
Mukul Chandorkar
Department of Electrical Engineering
Indian Institute of Technology
Mumbai, India 400 076
Email: [email protected]
Department of Electrical Engineering
Indian Institute of Technology
Mumbai, India 400 076
Email: [email protected]
Abstract—The paper presents a method of emulating electrical
loads using power electronic converters. The loads include
machines such as induction motors and its associated mechanical
load and also more complex machine systems such as wind
power generation systems. The load emulator is effectively a
dynamically controllable source or sink which is capable of
bidirectional power exchange with either a grid or another
power electronic converter system. Using load emulation, the
feasibility of connecting a particular load to a grid under various
conditions can be studied in the absence of any electromechanical
machinery. This paper considers the case of a power electronic
Voltage Source Inverter (VSI) emulating a three phase induction
motor connected to a three phase ac grid. The VSI is operated in
a mode where the current drawn from the ac grid is controlled
by closed loop control. Experimental results have been provided
to verify the scheme.
^
L1
E
Inverter
under
test
L2
E
Is
I_act
Converter
bridge
Signal
cond.
Modulator
ADC
FPGA
I_ref
Load
Model
Emulator
Fig. 1.
Current
controller
DSP
Schematic diagram of Load Emulator
I. I NTRODUCTION
Load emulation is the concept of controlling a power
electronic converter such as a Voltage Source Inverter (VSI) in
such a manner that its behavior resembles that of an electrical
load such as an induction machine. The load emulator can
provide different load characteristics with which the control
algorithms and inverter design can be tested. Therefore, load
emulation allows the user to test both the hardware and the
software of the inverter, thus offering a more flexible platform
for testing inverters in a laboratory environment.
The main component of load emulation is the algorithm that
generates the desired currents to be drawn so as to mimic the
actual load. The current controller ensures that the VSI draws
or supplies currents that are as close as possible to the desired
current references. It achieves this by connecting the inverter to
a power electronic converter through an appropriate interface
impedance. The power electronics of the virtual load simply
consists of two back to back, three-phase, six-switch, bridge
converters in conventional fashion. This arrangement allows
bidirectional power to flow to and from the inverter. The power
electronics is then controlled by the real time system (DSP) to
draw or source the currents to emulate the electromechanical
system on an instant by instant basis.
The load emulation system has regeneration capability, as
the power flow from the inverter can be returned to the mains
supply. While testing an inverter with an actual machine, the
machine uses this power for rotation and it is therefore lost.
Although the converter losses will have to be practically supplied by the source, the testing would ideally be lossless as the
power that the converter will draw can be fed back to another
supply. This work is concerned with the issues involved in the
use of power electronic converter to emulate machine type
loads, and the limits within which load emulation can be
achieved. For this purpose, special attention will be paid to
three phase induction motor which acts as a reference load.
II. P RINCIPLE OF L OAD E MULATOR
The load emulator is composed of a bidirectional power
converter and a digital closed loop control system. This emulator produces a programmable load or source currents, which
can be connected directly to the power electronic inverter
under test (or utility) as a replacement for an electrical load.
Fig. 1 depicts the schematic diagram of digitally controlled
load emulator. In this block diagram, the digital controller
consists of ADC, DSP and FPGA. The digital controller is
interfaced with the inverter through signal conditioning circuit.
The sensing of real time variables and their digitization are
done by the ADC. The electrical load model is coded in
DSP processor and generates reference currents for the current
controller. The output of the digital current controller in DSP
is fed to the PWM Modulator in FPGA section to generate the
switching pulses for the inverter. Therefore the load emulator
is effectively a power level active impedance controlled by
Magnitude (db)
a digital control system. However the complexity of the
emulation is limited only by the capability of the converter,
interface impedances and the digital controller.
III. C URRENT C ONTROLLER D ESIGN
60
40
20
0
1
400 V
Vdc
S1
S3 Lf (1 mH) Rf (0.1Ω)
+
uVdc
−
S4
Fig. 2.
if
The current if through the filter inductor Lf can be expressed in the Laplace domain as follows,
(1)
where Uc (s) is the Laplace transform of the continuous control
signal uc that will be obtained from the controller. uc will be
used to obtain the switching control signal u = ±1 shown in
Fig. 2. The grid voltage vs can be considered as a disturbance
signal while designing the controller. Therefore, the output
(If (s)) to control signal (Uc (s)) transfer function of the system
can be written in the Laplace domain from (1) as follows:
G(s) =
Vdc
If (s)
=
Uc (s)
sLf + Rf
1000
10000
100000
10000
100000
-20
-40
-60
-80
1
10
100
1000
Frequency (Hz)
Fig. 3.
Frequency response of the VSI with output filter inductor
Saturation
Controller
if r
e
+
uc
K
−
Fig. 4.
Sine
Triangle
PWM
u
G
if
Closed loop current control scheme
The objective of the VSI is to inject a current if that is
approximately equal to a desired reference if r . A proportionalintegral (PI) current controller can be designed to achieve
the objective. Fig. 4 shows the closed loop control scheme
employed for the VSI of Fig. 2. The PI controller K(s) is
chosen as follows,
s + 1500
Uc (s)
= 0.03
E(s)
s
(3)
The controller K(s) will be implemented in digital form. The
sampling time is chosen to be T = 20 μs. The controller
of (3) can be expressed in the Z domain by using bilinear
transformation as follows,
50 Hz
Topology of the single-phase VSI with inductor filter
Uc (s)Vdc − Vs (s)
If (s) =
sLf + Rf
100
K(s) =
vs
230 V
S2
10
Frequency (Hz)
Phase angle (degrees)
The performance of the emulator largely depends on the
quality of the applied current control strategy [1]. Current control loop ensures that the converter together with three-phase
line inductors draw an appropriate current from the inverter.
The transient response of the current loops determines the
tracking accuracy between the demanded and actual current
drawn from the inverter being tested.
Fig. 2 shows the diagram of a single phase VSI with
its output inductor filter interfaced to a grid. The controller
designed can be implemented for a three phase system with
a three phase VSI as will be shown in the later sections.
The system analysis and controller design are performed with
respect to the single-phase system shown in the Fig. 2. The
dc link of the VSI is considered to be a constant dc voltage
Vdc . The switches S1 to S4 are power electronic switches
such as IGBTs with their associated anti-parallel diodes. The
switching frequency of the devices has been chosen to be 10
kHz. The output of the VSI is the switched voltage waveform
uVdc where u = ±1 is the switching logic that controls the
VSI. The resistor Rf represents the loss in the inductor Lf and
the VSI. The grid has been represented by a voltage source
vs of 230 V Root Mean Square (R.M.S) value and 50 Hz
frequency.
(2)
The frequency response characteristics can be represented in
a Bode plot as shown in Fig. 3.
K(z) =
0.0305z − 0.0295
Uc (z)
=
E(z)
z−1
(4)
The controller output at any instant of time nT can be obtained
from (4),
uc (n) = uc (n − 1) + 0.0305e(n) − 0.0295e(n − 1)
(5)
In the above equation, T has been dropped but is implicitly
present in all terms.
The closed loop transfer function Gcl of the control scheme
is written as,
Gcl (s) =
G(s)K(s)
If (s)
=
If r (s)
1 + G(s)K(s)
(6)
The frequency response characteristics for the closed loop
control system is shown in Fig. 5. From Fig. 5, it can be
observed that the gain of the closed loop system is unity for
frequencies up to 1000 Hz. Moreover, the phase lag is approximately zero for frequencies up to 100 Hz. Therefore, current
Magnitude (db)
0
va
ia
-10
-20
-30
(50V/div)
1
10
100
1000
10000
(2.5A/div)
vb
100000
ib
Phase angle (degrees)
Frequency (Hz)
0
-20
-40
-60
-80
(50V/div)
(2.5A/div)
vc
1
10
100
1000
10000
(50V/div)
100000
(2.5A/div)
Vdc
Frequency (Hz)
Fig. 5.
ic
Closed loop frequency response of the system
(100V/div)
4
Fig. 7. Utility voltage and 7th order harmonic current of three phase emulator
Amp
2
stator reference frame with respect to the stator [2]. The system
is represented using linear differential equations as follows:
0
dλds
dt
dλqs
vqs = rs iqs +
dt
dλdr
+ ωr λqr
vdr = rr idr +
dt
dλqr
− ωr λdr
vqr = rr iqr +
dt
3
3
= Lls + Lms ids + Lms idr
2
2
3
3
= Lls + Lms iqs + Lms iqr
2
2
3
3
= Llr + Lms idr + Lms ids
2
2
3
3
= Llr + Lms iqr + Lms iqs
2
2
d
P Tem − TL
ωr =
dt
2
J
vds = rs ids +
-2
-4
0.01
0.02
0.03
Time (s)
Fig. 6.
isa_ref
0.04
isa
Response of current controller for 7th order harmonic
λds
references if r containing fundamental 50 Hz components can
be tracked with negligible error. To enable the VSI to be
able to inject currents containing harmonic components, the
bandwidth of the controller can be increased by appropriately
adjusting the gain of the controller K(s).
To study the bandwidth of the proposed current controller
7th order harmonic currents are given as reference currents
to the controller. The continuous time system equations for
harmonic oscillator are:
x = +ωy
x(0) = 0
(7)
y = −ωx
y(0) = 1
(8)
where x = sin 7ωt and y = cos 7ωt.
Fig. 6 shows the tracking accuracy of current controller for
7th order harmonic current. Fig. 7 shows the experimental
waveforms with respect to utility voltages. The performance
of the controller for the 7th harmonic can be seen to be in
accordance with the bandwidth of the controller shown in
Fig. 5.
IV. T HREE PHASE I NDUCTION MOTOR MODEL
A three-phase squirrel-cage induction machine is modeled
using a two-phase d − q model, formulated in the stationary
λqs
λdr
λqr
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
P3
(λds iqs − λqs ids )
(18)
22
where the symbols v, i and λ represent the instantaneous
voltage, current and motor flux linkage, respectively. Also the
sub-script q and d refer to q-axis and the d-axis quantities
respectively. The subscript s and r refer to the stator side
and rotor side quantities respectively. Rotor angular velocity
is denoted by ωr . The terms rs and rr are stator and rotor
resistances respectively. The terms Lls , Llr and Lms are stator
leakage inductance, rotor leakage inductance and magnetizing
inductance respectively. The rotor inertia is denoted by J and
the load torque by TL .
Tem =
TABLE I
I NDUCTION MOTOR MODEL PARAMETERS
Amp
500
rs = 2.7 Ω
lls = 0.01235 H
lm = 0.2485 H
J = 0.025524 kgm2
LLvg = 415 Vrms
0
-500
0
1
0.5
1.5
Amp
500
rr = 2.849 Ω
llr = 0.01325 H
Tl = 14.247 N m
P =4
F req. = 50 Hz
0
20
-500
0.5
20
Amp
0.52
Forward Euler
0.54
Adam−Bashforth
0
10
Amp
0.48
40
0
-10
-20
1.48
Fig. 8.
1.49
1.5
1.51
Time (s)
1.52
1.53
1.54
-20
0.1
0.2
0.3
Amp
V. E XPERIMENTAL R ESULTS
A three-phase experimental setup has been built in a laboratory to verify the accuracy of the proposed system. In
this setup the power circuit is rated at 30 Arms , 415 Vrms
input/output line to line voltages and 750 Vdc bus with three
3300 μF capacitors. A laboratory type 3-phase 4-pole squirrel
cage induction motor with the parameters mentioned in table I
is taken as a reference model, and the reference currents are
generated from this model.
For experimentation the phase voltage for the motor model
is set as 135 Vrms and reference dc bus voltage set as 360 V.
0.6
isa
2
By applying a numerical integration method the model is
solved at every time step. Integration gives the evolution of
the state variables with time. The selection of a solver for
the differential equations is a trade-off between the accuracy
requirement and the algorithm complexity [3].
Adams-Bashforth method is used to solve the motor model
equations 9 to 18. This is an explicit linear multi step method
that depend on multiple previous solution points to generate a
new approximate solution point. Even though Euler’s method
is easy to implement in real time systems, it has a serious
flaw in its approach to determining the slope to use in taking
each step of the iteration. The iteration step from tn to tn+1
uses only the slope at the endpoint. Adams-Bashforth method
uses linear combination of earlier values like yn−1 , yn−2 , ..,
in order to reduce the number of times f (x, y) [4]. A two-step
Adams-Bashforth method is written as
3
yi (n + 1) = yi (n) + h( fi (y1 (n), ..., yN (n))
2
1
− fi (yi (n − 1), ..., yN (n − 1))) (19)
2
Fig. 8 shows the real time simulation of 300kW induction
motor using Euler and Adams-Bashforth algorithm for a 20
μs time step. Using Euler algorithm the error varies for the
time step 10 to 100 μs. However for time step <10 μs the
results are identical. Therefore, for larger time steps Adams
algorithm is more accurate and reasonably stable.
0.5
isa_ref
4
Real time simulation using Euler and Adams-Bashforth Method
0.4
0
-2
-4
0.5
0.51
Fig. 9.
0.52
0.53
Time (s)
0.54
0.55
Induction motor a-phase stator current
The interface impedance chosen to be L = 4 mH.
Fig. 9 demonstrates the performance of load emulator for
steady state and transient conditions of the stator a-phase
current. The model is simulated in real-time to obtain the free
acceleration characteristics of the machine when started directon-line with no load. While the motor is running under no
load steady state, an 80% rated torque is suddenly applied at
t = 0.5 seconds to the rotor in order to observe the transient
behavior of the system. From Fig. 9 it is observed that the
measured currents are nearly identical to reference currents.
Fig. 10 shows the experimental waveforms of rotor mechanical
speed, electromagnetic torque and active power drawn by the
emulator. The oscillogram 11 shows the a-phase stator current.
For the given parameter values shown in table I, the transient
and steady state currents of the emulator are as desired. The
current waveforms have nominal ripple and the control system
is stable.
The digital signal processor which is currently used to perform the simulation has a clock frequency of 75 MHz, which
gives it an instruction cycle time of 13.33 ns. The entire load
emulation software is driven by an Interrupt service routine
(ISR). The main code (background loop) consist of simply
peripheral initialization (Timers, ADC, Interrupt control and
buffer). The remainder of the code is taken up entirely by
Timer 0 ISR. This ISR is invoked every 20 μs by the period
event flag on Timer 0. Calculation of reference currents from
model, sampling of ADC and generation of PWM waveforms
for power switches are done within 20 μs.
Table II shows the tasks performed and time taken by each
task. The tasks carried out by DSP take 9.8 μs in total for a
time step of 20 μs. Three analog to digital converters sample
TABLE II
P ROCESSOR EXECUTION TIME FOR
rad/sec
150
rotor mechanical speed
100
0.1
0.2
0.3
0.4
20
Nm
Integration Time Step (rate of execution)
Control cycle (total process time)
Motor model
Current controller
ADC Sample time
Transformations
FPGA
Buffer
50
0
0
30
0.5
0.6
0.7
electromagnetic torque
10
0
4000
0
0.2
0.4
Watts
active power
1000
i dc
Pcc
2000
Reverse
flow
converter
3Φ
0
0.2
Fig. 10.
0.4
time (sec)
0.6
Transient response of the emulator
(5A/div)
a−phase stator current
Fig. 11.
20 μs
9.8 μs
2.04 μs
1.93 μs
3.42 μs
680 ns
1.39 μs
1.76 μs
0.6
3000
0
LOAD EMULATION
Startup response of the emulator
time is 3.42 μs and PI current controller execution time is
1.93 μs. Data conversion and communication between DSP
and FPGA is 1.39 μs. Motor model using Euler algorithm
is 1.52 μs and for Adam-Bashforth algorithm the execution
time is 2.04 μs which is well justified in terms of precision.
Buffer save task execution time is 1.76 μs and data transfer
between PC and DSP buffer is offline. The measurements are
taken with the help of external flag XF0 of the DSP processor.
These results are sufficient for IM load emulation and can be
more optimized when using better methods.
VI. R EGULATION OF DC BUS VOLTAGE
In the block schematic of load emulator Fig. 1 initially the
dc bus capacitor is charged with a diode bridge rectifier, so
the dc bus voltage in no case falls during load emulation.
However, when the load model is regenerative in nature, the
emulator draws real power from the utility. This will result in
the dc bus voltage increasing to dangerous values. Since the
emulator needs to draw the currents as per the load model, it
Lf
Inverter
Ls
Cf
Grid /
Inverter
under
test
Emulator
Vdc ref
Fig. 12.
Control
system
dc bus
feed back
Block schematic of lossless emulator using reverse flow converter
is not possible to regulate the dc bus voltage using existing
control loop.
Fig. 12 shows the block schematic of a lossless emulator for
high power applications. In this system the emulator dc bus is
connected to the three-phase mains supply via a regeneration
unit. This unit transfers power from the emulator converter
back into the mains supply when the dc bus voltage of the
emulator rises above a predefined value. In this way power
which is taken by the converter, and usually absorbed in a
load, is returned to the mains supply.
The power exchange is based on instantaneous power theory
using pqr transformation. The control scheme for operation
of the front end converter is well elaborated [5]. The main
advantage of this front end converter that is it utilizes its entire
capacity to return the power to the grid. Fig. 13 shows the
experimental results of bidirectional active power exchange.
The figure shows the instantaneous real powers drawn by the
emulator and returned by the reverse power converter.
VII. DSP-FPGA H ARDWARE P LATFORM
This section describes the digital hardware structure for
implementation of load emulation. Fig. 14 shows the block
diagram of DSP-FPGA digital hardware system. In this system
separate digital controllers are employed to carry out data
acquisition, communication and control [6] [7]. This system
is centered on Texas TMS320VC33 Digital Signal Processor
(DSP), which is a high performance floating point processor
with 34 K × 32-bit on-chip SRAM. It supports 16/32 bit
integer and 32/40 bit floating point operations. Communication
between the host computer USB port and DSP is done using
a USB controller. On board program/data transfer between the
USB and the DSP is implemented using Texas MSP430F168
micro controller which acts as Communication Link Interface
Manager (CLIM). The role of CLIM is to convert synchronous
serial data to 8-bit parallel form. In order to get flexible I/O
active +ve power
Watts
2000
1500
1000
500
0
0.01
0.02
0.03
0.04
0.05
0.06
0
active −ve power
discussed. This technique allows implementation of more
complex models.
For experimentation and real time verification, the design of
a 32-bit floating point DSP processor interfaced to FPGA is
described. The program environment and code was set up in
assembly language of processor, which best utilizes resources
and results in reduced execution time. Measured control cycle
time and load model time are reported.
Watts
-500
R EFERENCES
-1000
-1500
-2000
0
Fig. 13.
0.01
0.02
0.03
0.04
Time (s)
0.05
0.06
Bidirectional active power transfer by reverse flow converter
Mixed signal
controller
8−bit
Data
USB Controller
USB
PWM O/P
Synchronous
Serial Data
Address
JTAG
DSP
TMS320vc33
SPARTAN3
Control
12−bit
Data
FPGA
PROM
CLOCK
ADC−1
ADC−2
AD7864AS−2
AD7864AS−2
CH0−3
Fig. 14.
CH4−7
ADC−3
AD7864AS−2
CH8−11
Block diagram of DSP-FPGA platform
interface and data acquisition, this system has three analog
to digital converters and a Xilinx XC3S200 FPGA. Three
AD7864-AS2 analog to digital converters are interfaced to
sensor unit for data acquisition of voltage and currents. DSP
is used as a processor which simulates the load model and
generates the current references with a 75 MHz clock. FPGA
act as a pulse width modulator and control the power switches
of the converter using 20 MHz clock reference.
VIII. C ONCLUSIONS
This paper has discussed load emulation which is capable of simulating an electrical load in real-time with power
electronic converter. The PI controller has been designed and
implemented in DSP. The system was operated to simulate
three phase induction motor model for steady state and transient conditions. Experimental results of emulator and reverse
power converter for bidirectional active power exchange are
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