Reliability of Single and Dual Layer Pt Nanocrystal
Devices for NAND Flash Applications: A 2-Region
Model for Endurance Defect Generation
Pawan K Singh, Gaurav Bisht, Sivatheja M, Sandhya C, Ralf Hofmann, Kaushal Singh,
Gautam Mukhopadhyay, Nety Krishna, Souvik Mahapatra
Pawan K Singh, Gaurav Bisht, Sivatheja M, Sandhya C, Gautam Mukhopadhyay, Souvik Mahapatra
Indian Institute of Technology Bombay
Mumbai-400076. India
Ph: +91-22-25764481, e-mail: [email protected]
Ralf Hofmann, Kaushal Singh, Nety Krishna
Applied Materials
Santa Clara, CA, 95054 USA
retention, provided optimal NC area coverage is obtained [12]
for good memory window.
Abstract— Nanocrystal (NC) based memory devices are
considered a possible alternative for floating gate (FG)
replacement below 30nm node. In this work, endurance
reliability of Pt NC devices is investigated for single layer (SL)
and dual layer (DL) structures. The degradation in the devices
due to Program/Erase (P/E) stress is investigated. Relative
improvement in reliability of DL structure over SL structure is
shown. A physical model for defect generation in the gate stack is
proposed which is able to explain endurance and post-cycling
characteristics. Dual layer structure is shown to have better
inherent reliability over single layer structure.
Use of metal as NC material offers significant advantage
over the semiconductor NC like Si [3] and Ge [4] as metals
have large WF, very little to no quantum confinement [13] due
to large density of states and better control of NC size. Metals
Au, Ni, Pt, W, etc. [5]-[9] embedded in SiO2 and high-k
dielectrics have been studied till now. Use of dual layer (DL)
NC structure is reported to increase the memory window
[13],[14] over single layer (SL) NC structure, but no work on
relative reliability of the two structures has been reported.
Keywords-component; Metal nanocrystal, Flash memory, MLC,
reliability
I.
In this work, endurance reliability of metal NC memory
devices with SL and DL Pt NCs as storage node and optimized
low-leakage Al2O3 as control dielectric is reported. Pre and
post-cycling retention measurements are also reported. Pt metal
is chosen due to large WF, good thermal stability, chemical
inertness, and good NC size control [15].
INTRODUCTION
Difficulty in scaling the tunnel oxide (TO) and control
dielectric (CD) thickness, and single defect induced state
change are the most important scaling limitations for
conventional floating gate (FG) devices. FG [1] structure is
thus unlikely to scale below the 30 nm node [2]. Localized
charge storage structures like metal nanocrystal (NC) [3]-[9]
and charge trap flash (CTF) [10],[11] devices are considered as
possible alternatives for FG devices. The devices are termed
localized as the charge storage is in discrete storage nodes
which are Si3N4 bulk traps in CTF and Fermi level of isolated
metal NC. Discretization of charge storage can increase
reliability of the memory device by providing immunity to
complete charge loss through a single defect, reduction in TO
and CD thickness and better channel control. So far, reported
CTF devices have shown good memory window but poor
retention, while NC devices poor memory window. Poor
retention of CTF is linked to shallow trap depth of the nitride
storage layer which is an inherent material property and is
difficult to control. Choice of tunable workfunction (WF) of the
metal-NC storage layer is advantageous for achieving good
978-1-4244-2889-2/09/$25.00 ©2009 IEEE
II.
FABRICATION DEAILS
Device fabrication is performed on low resistivity p-type
wafers with doping of ~1x1015 cm-3. After surface cleaning,
40Ǻ SiO2 was thermally grown using in-situ steam generation
(ISSG) process as tunnel oxide (TO) in an Applied Materials
Centura RTP tool. Subsequently, a thin film of Pt is deposited
and annealed to form metal NCs. For dual layer NC formation,
60Ǻ Al2O3 film is deposited as the inter layer dielectric (ILD).
This is followed by another thin film of Pt and NC-anneal to
form the second NC layer. 120Ǻ Al2O3 is then deposited and
annealed to form the control dielectric (CD). 1000Ǻ Pt metal is
deposited as control gate (CG) to complete the device
formation process. Schematic of the NC devices is shown in
Fig.1. Process details are summarized in Table 1.
301
IEEE CFP09RPS-CDR 47th Annual International Reliability
Physics Symposium, Montreal, 2009
Area coverage and number density were estimated to be
between ~26% - 30% and 2.5x1012 – 3.4x1012 cm-2 respectively.
Average NC size is ~4nm. More information on NC statistics
can be found in [15]. Obtained area coverage is found to be
very close to the optimal area coverage required for good
performance [12]. The device splits are shown in Table 2.
p-Si
p-Si
TABLE II.
SL AND DL DEVICE SPLITS WITH THE RESPECTIVE
LAYER AREA COVERAGE AND NUMBER DENSITY
Figure 1. Schematic of SL and DL NC devices showing the random
position of NC in the gate stack.
TABLE I.
FABRICATION PROCESS DETAILS FOR THE SL AND DL NC
FLASH MEMORY DEVICES
SL
Area Coverage
SL-S1
SL-S3
DL-S3
0.5 / -/ 1.0 / -/ 0.5/ 6.0/ 0.5
26%
30%
26%
Area Density
(#/cm2)
3.40 x1012
2.50 x1012
3.40 x1012
DL-S9
1.0/ 6.0/ 1.0
30%
2.50 x1012
IV.
ILD Al2O3 deposition
Pt Deposition
NC Anneal
ANALYTICAL RESULTS
Cross-section TEM images of SL and DL devices in Fig.
2(a) and Fig. 2(b) respectively, show formation of discrete NC
embedded in the gate dielectric. NC layers of the DL device are
clearly separated from each other by Al2O3 ILD. Plane view
TEM image is used to extract information regarding the
number density, area coverage and size distribution of the NCs.
Fig. 2(c) and Fig 2(d) show the plane view TEM image of NCs
formed with initial metal (Pt) thickness of 0.5 nm and 1 nm
respectively.
(a)
RESULTS AND DISCUSSION
A. Program/Erase (P/E) Transients and Pre-Cycling
Retention
Capacitors with 100μm diameter are used for electrical
testing. Program and erase transients, obtained using flatband
voltage (VFB) shift from CV measurements for SL device are
shown in Fig. 3. SL devices can be programmed to VFB 8V and
overerased to -2V. Large overerase allows split window
operation, thereby reducing the highest operating voltage used.
Similarly, DL devices show large positive VFB saturation and
overerase. High quality low leakage CD film prevents
tunneling of charge from the NC to control gate during
programming and (along with high WF metal gate) prevents
electron injection from CG during erase. Maximum memory
windows of ~10V and ~15V are observed for SL and DL
devices respectively.
Control Dielectric: 120Ǻ Al2O3
Post Deposition Anneal
CG Metallization: 1000Ǻ Pt
III.
Pt/Al2O3/Pt (nm)
DL
Wafer Clean
Tunnel Oxide: ISSG (40Ǻ)
Surface Preparation
Pt Deposition
NC Anneal
--
Device ID
VFB (V)
8
(b)
+18V +20V
6
4
2
Virgin VFB
0
ΔVFB
-18V -20V
-2
-5
10
INT
-4
10
-3
10
-2
10
-1
10
Time (s)
(c)
(d)
Figure 3. Program and erase transient of SL device.
Fig. 4 shows the memory window of SL and DL devices
operated at SL equivalent gate voltage. Observed increase in
the memory window of DL over SL when both devices are
programmed at equal field is ~190%. The increase has been
explained as additional charge storage in the 2nd NC layer. DL
charge estimated is estimated to be ~1.5 times SL charge [13].
Figure 2. Cross sectional TEM image of (a) Sl and (b) DL NC device.
plane view TEM images for devices with (c) 0.5nm and (d) 1nm Pt
deposition. Thicker film shows larger area coverage
302
6
5
4
3
2
1
0
-1
SL
DL
8
6
Improvement in
memory window
over SL
4
2
0
-2
-4
17
18
19
20
21
22
0
6
5
4
Figure 4. Comparison of memory window between SL and DL device at
identical equivalent gate voltage
Fig. 5 shows the retention measurement performed at 25oC,
80 C, and 150oC for both SL and DL devices. Excellent precycling retention is observed for both SL and DL device. At
room temperature the retention loss is for SL and DL is -0.18V
and -0.13V respectively. At 150°C, the P-state retention loss
increases to -0.3V in SL and -0.6V in DL. Change in E-state
loss is even smaller at high-temperature.
VFB (V)
8
0
1
10
2
10
3
10
4
1
2
3
10
10
10
# P/E Cycles
4
10
Endurance characteristics for DL-S9 cycled with memory
windows of 6V, 7V, and 8V are shown in Fig. 7(a), Fig. 7(b)
and Fig. 7(c) respectively. Overerase is used to split the
memory window, between positive and negative VFB, reducing
the maximum positive voltage required for same window.
Negligible memory window closure is observed in all
measurement. The number of cycles reduces as the memory
window is increased, due to increase in cumulative P/E stress.
Increasing the P level greater than +6V is found to cause rapid
breakdown, possibly due to the large programming voltage
required. Reducing E-state below -2V is also found to cause
degradation in endurance. Maximum cycles are obtained when
the P and E states are kept between +6V and -2V respectively.
104 cycles are possible with maximum 7V window, while
2x103 cycles can be achieved with maximum 8V memory
window. Similar trends are shown in Fig. 8 for DL-S3 where
optimal P/E levels between +6V and -2V give maximum cycle
endurance of ~103 cycles at 7V memory window and 500
cycles at 8V memory window (not shown).
2
10
4
10
Figure 6. Endurance characteristics of (a) SL and (b) DL devices under
different P/E memory window
0
10
3
(b)
0
4
SL
2
10
10
# P/E Cycles
DL-S3
DL-S9
3
2
1
10
6
25C
80C
150C
1
10
0
-1
VFB (V)
VFB (V)
o
DL
(a)
10
Eq. Gate Voltage (V) (w.r.t SL)
9
8
7
6
5
4
3
2
1
0
Open: SL-S1
Solid: SL-S3
VFB (V)
Saturation VFB (V)
10
-2
Time (s)
Figure 5. High temperature retention of SL and DL devices. No
significant change in retention loss is seen at higher T
B. Endurance
Fig. 6(a) and Fig. 6(b) show the endurance of SL and DL
devices respectively. Memory window closure with P/E
cycling is a serious reliability concern in the CTF devices
[9][11]. Window closure occurs due to defect generation and
permanent charge trapping in the gate dielectrics due to
repeated P/E stress. Unlike CTF/FG, no window closure is
observed in both SL and DL NC devices as shown in Fig. 6(a)
and Fig. 6(b) respectively. It is possible to cycle NC device
with constant memory window until breakdown. After
breakdown, no programming can be performed on the devices.
Although the memory window remains constant, SL devices
show poor cycling endurance of no more than 4x103 cycles for
any combination of P/E levels as shown in Fig. 6(a). DL
devices show better endurance characteristics with 104 cycles
without breakdown as illustrated in Fig. 6(b). DL device
endurance may be sufficient to meet the minimum required
specifications for typical MLC NAND flash [16].
While the memory window remains constant during
endurance, both P and E VFB levels decrease with cycling. This
suggests permanent positive charge trapping in the gate stack
for all SL and DL devices. Amount of permanent trapping is
found to be dependent on the starting E-state VFB of the device.
This is illustrated in Fig. 9 for DL-S9 cycled at 6V memory
window with increasing negative E-state VFB. This behavior of
NC devices is different from CTF devices which show both
window closure and permanent electron trapping with cycling
stress which causes positive shift in VFB [9].
303
8
P state
-0.20
(a)
-0.25
6
-0.30
ΔVFB (V)
4
VFB (V)
DL-S9
~6V
2
0
-0.35
-0.40
-0.45
-0.50
-2
0
10
1
10
2
3
-3
4
10
10
# P/E Cycles
8
10
6
2
It is observed that measured HFCV curves show skew
(stretch-out) when devices are cycled with negative E-state
VFB. The HFCV for DL-S9 devices cycled with different E
level are shown in Fig. 10. More negative VFB is achieved by
increasing the erase voltage. Tunneling of holes through the TO
during erase can cause generation of interface states which can
cause the skew in the observed CV characteristics.
4
VFB(V)
-2
-1
0
1
Starting E-state VFB
Figure 9. Negative shift of E state VFB with different starting VFB level
after 104 cycles.
(b)
2
~7V
0
Experiment
-0.55
E state
-2
-4
1
2
10
3
10
10
# P/E Cycles
4
10
Capacitance (F)
0
10
(c)
6
VFB(V)
4
2
~8V
-3V
-2V
-1V
0V
Before Stress
0
VG (a. u.)
-2
10
0
10
1
2
10
10
# P/E Cycles
3
Figure 10. CV curves for DL devices cycled with different erase VFB and
constant 7V memory window.
4
10
C. Post-Cycling Retention
Fig. 11 shows the room temperature pre and post-cycling
retention loss of SL and DL devices.
Figure 7. Endurance of DL-S9 device with 6V, 7V and 8V memory
window with different P and E levels
8
DL-S3
6
~7V
0
-2
0
10
1
10
2
3
10
10
# P/E Cycles
4
10
8
DL
7
6
5
4
Open: Pre Cycling
3 Solid: Post Cycing
2
1
0
0
10
Figure 8. Endurance of DL-S3 device at 7V memory window with
different P and E levels
1
10
2
8
6
4
SL
2
VFB (V)
2
VFB (V)
4
VFB(V)
Starting E level
for endurance
0
3
10
10
Time (s)
4
10
Figure 11. Pre and post-cycling P/E transients and retention
comparison for SL and DL devices
304
window during endurance can be explained as the permanent
hole trapping in R2. Breakdown of NC devices is explained by
the leakage path formed in R2 which shorts CG and substrate
preventing charging of NC. The model also explains the
enhanced reliability of DL device over SL as the reduction in
R2 in DL due to increase of effective area coverage. Difference
in DL-S3 and DL-S9 endurance can be explained by the
difference in area coverage of the NC layers, where DL-S9
with larger area coverage shows better endurance.
Retention loss from P-state and E-state of both SL and DL
devices are found to have minimal impact of cycling. P/E
transients, although not shown here, show negligible difference
between pre and post-cycling characteristics.
D. Physical Mechanism
In the previous sections, it is shown that SL devices cycle
for maximum of ~4x103 cycles before breakdown, while DL
devices are capable of 104 cycle endurance for 7V memory
window. DL-S3 (less area coverage) shows worse endurance
compared to DL-S9. Positive charge trapping is observed with
P/E cycling which increases with increasing (negative) erase
state VFB. Negligible degradation in the post-cycling retention
and P/E characteristics of the devices suggest very small defect
generation with endurance stress, which is in contradiction to
the endurance characteristics of SL and DL devices, which
show breakdown after cycling and therefore defect generation.
A 2-region degradation model for defect generation in the NC
devices is therefore proposed to explain the observed
experimental results. It is proposed in the model that the
degradation in the NC devices is primarily due to hole injection
from substrate during erase. Hole injection is suggested to
occur in the region between NCs and therefore the defect
generation does not impact post-cycling P/E or retention.
eR1
e-
Al2O3
SiO2
NC
h+
No Defect
Generation
eR2
The regions defined in the model are shown in Fig. 12 for
both SL and DL devices. NC device gate area is divided in two
regions; region 1 (R1) is defined as the area under NC coverage
and region 2 (R2) is the area between NC with no NC
coverage.
Al2O3
SiO2
h+
Defect
Generation
Figure 13. Illustrative energy band diagram in R1 and R2 of SL devices.
Similar results are true for DL devices.
R2 R1 R2 R1 R2
p-Si
R2
The model is verified using 2 dimensional (2D) numerical
simulations on the SL and DL device structure to extract
electric fields and electric field lines during erase. SL and DL
simulation structures are made in using method similar to [12].
Potential on each NC is computed using capacitance extraction
method [12]. The region is divided into very fine square grid.
Potential at each point on the grid is computed by solving
Laplace Equation using finite difference method in the region
between CG and substrate. Potential on the grid point is
defined to be equal to the average of its nearest neighbors and
iteratively updating potential on each grid point till saturation is
reached. Electric field is then obtained from the derivative of
the potential. Electric field lines are then computed from the
2D electric field data.
R2
p-Si
Figure 12. Schematic of SL and DL device showing Region 1 (R1) and
Region 2 (R2, possible degradation zone)
Defect generation occurs in R2 due to hole injection during
erase. Although TO field is sufficiently high during erase, hole
injection in R1 is difficult as no states are available for holes in
the metal NC. Holes injected in R2 cause impact ionization in
the CD/ILD causing defect generation and permanent trapping.
Due to random nature of the NC placement, R2 in DL device is
reduced significantly compared to SL but not completely
eliminated. Maximum reduction in R2 is obtained when 2nd
layer NCs are placed between the bottom layer NC, instead of
being placed directly on top of bottom layer NCs. The model is
summarized by the schematics of R1 and R2 in Fig. 13.
Simulated 2D electric field in SL and DL device during
erase is shown in Fig. 14. SL and DL devices simulated at VG =
-20V and -25.7V (-20V SL equivalent) respectively at E-state
VFB of -2V. To obtain the required VFB, appropriate charges are
placed on individual NCs. In DL structure, top layer NCs are
given slightly lesser charge than bottom layer NCs. Electric
field lines are shown in Fig. 15. Most of the field lines from the
CG are observed to terminate at the metal NC (R1) and only a
few field lines (from the CG) reach the substrate. The region
where field lines reach the substrate directly is R2. Magnitude
of simulated TO electric field during erase is estimated to be
~15MV/cm in both SL and DL which is sufficient for hole
injection in R2. Since more field lines from the CG reach the
Since the P/E and retention characteristics are primarily
governed by quality of the dielectric directly above and below
the NC (R1), the model correctly explains the negligible
degradation in post-cycling P/E and retention behavior by
dielectric degradation only in R2. Negative shift of memory
305
NC devices are shown to have better endurance than SL
devices. 104 cycle endurance is shown to be possible in DL
devices with 7V memory window. Degradation in NC devices
is shown to be related to the erase operation, specifically hole
injection during erase. The proposed 2-region degradation
model is able to correctly explain the P/E, retention, and
endurance measurements. The model suggests further
improvement in NC device reliability by a) increasing the NC
layer area coverage b) optimal placement of top layer NC and
c) optimization of erase conditions to minimize hole injection.
Good overall performance of DL NC devices with large
memory window, good retention and 7V window cycling
endurance presents them as suitable candidates for MLC
NAND Flash.
substrate in SL compared to DL, this implies larger R2 area in
SL. Due to small R2 area, DL will have less hole injection and
better reliability, as seen by the experiments, confirming the 2region model.
REFERENCES
[1]
[2]
[3]
[4]
[5]
Figure 14. Simulated 2D electric field (MV/cm) in SL and DL devices
during erase at -20V SL eq. gate voltage.
[6]
[7]
R2
R2
R2
R2
[8]
[9]
[10]
[11]
R2
[12]
[13]
[14]
Figure 15. Electric field lines in SL and DL devices during erase at -20V
SL eq. gate voltage. More field lines reach the substrate in SL compared
to DL confirming reduction in R2.
[15]
V.
CONCLUSION
Comprehensive endurance reliability analysis of SL and DL
NC devices is presented in this work. It is found that NC
devices show large memory window excellent retention. DL
[16]
306
P. Cappelletti, C. Golla, P. Olivo and E. Zanoni, Flash Memories,
Kluwer Academic Publishers, Boston, 1999.
International Technology Roadmap for Semiconductors, ITRS 2007,
available at http://www.itrs.net.
J. De Blauwe, et al., “A novel, aerosol-nanocrystal floating-gate device
for non-volatile memory applications” in proc. International Electron
Devices Meeting, pp. 683-6. 2000.
J. H. Chen, et al., “Nonvolatile Flash Memory Device Using Ge
Nanocrystals Embedded in HfAlO High-k Tunneling and Control
Oxides: Device Fabrication and Electrical Performance”, IEEE
Transactions on Electron Devices, vol. 51, pp. 1840 - 1848, 2004.
Z. Liu, C. Lee, V. Narayanan, G. Pei and E. C. Kan, “Metal Nanocrystal
Memories—Part I: Device Design and Fabrication”, IEEE Transactions
on Electron Devices, vol. 49, pp. 1606 - 1613, 2002
Z. Liu, C. Lee, V. Narayanan, G. Pei and E. C. Kan, “Metal Nanocrystal
Memories—Part II: Electrical Characteristics”, IEEE Transactions on
Electron Devices, vol.49, pp. 1614 - 1622, 2002.
M. She and T.-J. King, “Impact of crystal size and tunnel dielectric on
semiconductor nanocrystal memory performance”, IEEE Transactions
on Electron Devices, vol. 50, pp. 1934 - 1940, September 2003.
J. J. Lee and D. L. Kwong, “Metal nanocrystal memory with high-k
tunneling barrier for improved data retention“, IEEE Transactions on
Electron Devices, vol. 52, pp. 507-511, April 2005.
C. Lee, J. Meteer, V. Narayanan, E. C. Kan, “Self-assembly of metal
nanocrystals on ultrathin oxide for nonvolatile memory applications”,
Journal of Electronic Materials, v 34, n 1, January, 2005, p 1-11
Sandhya. C, et al., “Nitride engineering and the effect of interfaces on
Charge Trap Flash performance and reliability”, in proc. IEEE
International Reliability Physics Symposium, pp. 406-411, 2008.
K-H Wu, H-C Chien, C-C Chan, T-S Chen, C-H Kao, “SONOS Device
With Tapered Bandgap Nitride Layer”, IEEE Transactions on Electron
Devices v.52 no.5, 2005, pp.987-992.
A Nainani, et al., “Development of s 3D simulator for metal nanocrystal
(NC) flash memories under NAND operation”, IEDM Tech. Dig. 2007,
pp. 947-950.
P K Singh, et al., “Metal nanocrystal nemory with Pt single - and dualdayer NC with low-leakage Al2O3 blocking dielectric”, IEEE Electron
Device Letters, Vol. 29, no. 12, pp. 1389-1391, December 2008.
S. K. Samanta, et al., “Enhancement of memory window in short
channel non-volatile memory devices using double layer tungsten
nanocrystals”, in proc. International. Electron Devices Meeting, pp.
170-173, 2005.
R. Hofmann and N. Krishna, “Self-assembled metallic nanocrystal
structures for advanced non-volatile memory applications”,
Microelectronic Engineering, v 85, n 10, pp. 1975-1978, October, 2008.
N. Mielke, et al., “Bit Error Rate in NAND Flash Memories”, IEEE
International Reliability Physics symposium, pp. 9-19. 2008.