Performance Analysis of CMOS Mode Locked Class
E Power Amplifier
Pankaj Arora
Jayanta Mukherjee
Vivek Agarwal
Department of Systems and Control
Engineering, Indian Institute of
Technology, Bombay Powai,
Mumbai, 400076
[email protected]
Department of Electrical Engineering
Indian Institute of Technology,
Bombay Powai, Mumbai, 400076,
India
[email protected]
Department of Electrical Engineering
Indian Institute of Technology,
Bombay, Powai, Mumbai 400076,
India
[email protected]
performance metrics of the Mode Locked circuit with and without
inductor loss compensation and the final conclusions are drawn in
Section VI.
Abstract – The design of Class E Amplifiers is more difficult than
other type of amplifiers as it is imposed by time domain
constraints. This paper presents the performance analysis of
Mode Locked class E Power Amplifiers using State Space
Analysis Algorithm. A technique is introduced which is used to
curb the negative effect of parasitic resistance of DC Feed Choke
and the Power Amplifier operates at 2.4GHz and simulated with
a 0.18µm CMOS process at a supply voltage of 2V.
Index Terms-Class E, CMOS, power amplifier, State
Space
I.INTRODUCTION
A Power Amplifier is a device that converts a DC power
from the supply voltage into RF by sufficient amplification of the
input RF signal. Only in the ideal case this conversion is lossless
which means that the PA itself will drain more power than it
delivers. The distinction between the different power amplifiers is
made based on their bias points, the working principle of the active
devices and the voltage and current shaping done by different
external components [1].
The Power Amplifiers are considered to be one of the
most Power hungry blocks in a wireless transceiver
System. Therefore, its efficiency is crucial to maximize time
between batteries recharging for a mobile device. High efficiencies
can be achieved through the use of switching mode PA’s. In
particular, the class E PA is a simple configuration switching mode
PA that achieves a theoretical efficiency of 100%.
For lower price and lower form factor mobile terminals,
CMOS technology is an attractive option. As the down-scaling of
MOS devices continues, CMOS technology is able to operate well
into the GHz range. However, when it comes to PA design,
CMOS is not the optimum technology of choice. Performancewise, CMOS suffers from problems like low oxide breakdown
voltage, low current drive capability, substrate coupling and low
quality and high tolerances of on-chip passives [1]. Some of these
even get worse with the technology downscaling. This makes
CMOS PA design and implementation a major challenge.
A class E amplifier is a non-linear amplifier but it poses
no obstruction for constant envelope modulation schemes like
Bluetooth. This paper investigates the feasibility of modeling a
Mode Locked Class E amplifier including all important losses and
thereby introducing a technique to reduce the negative effect of DC
Feed Resistance.
This paper is organized as follows. In section II, the basic
operation of class E amplifier is overviewed. Section III presents
the operation principle of Mode Locked Class E amplifier with its
advantages. In Section IV, the modeling of Mode Locked amplifier
using state space technique is shown. Section V compares the
978-1-4244-7773-9/10/$26.00 ©2010 IEEE
Fig 1 Basic Class E Amplifier Topology
II. GENERAL PRINCIPLES OF CLASS E OPERATION
An ideal Class E amplifier configuration is shown in Fig.
1, which consists of a single supply voltage Vdd, an RF choke
inductor Ldc, a switch with a parallel capacitor Cp, a resonant
circuit L0-C0, and a load RL. The switch is turned on and off
periodically at the input frequency. L0-C0 resonates at the input
frequency and only passes a sinusoidal current to the load RL. Cp
ensures that at the time the switch is turned off the voltage across
the switch still stays relatively low until after the drain current is
reduced to zero. The switch usually uses active devices such as
silicon bipolar transistors or field effect transistors (FETs). In
practice, in order to make the switch near ideal and reduce onresistance, the transistor is designed with a large gate width.
Maximum output power can be obtained if the duty ratio of
the input frequency is made approximately 50 percent [2]. Since
the operating frequencies are different in the on and off states of
the active device, the load network may include filters to suppress
harmonics of the output signal. The well known Class E switching
conditions [3] include:
• Voltage return to zero at switch turn on: This ensures that the
voltage of the switch and the current flowing through it cannot
happen simultaneously, and thereby the power dissipation in
the switch is zero.
• Zero voltage slope at switch turn on: Although the former
point can be satisfied with proper circuit design, the condition
of slight mistuning of the amplifier may happen. This point
can prevent severe power loss at the transient point.
Based on the Class E switching conditions, the ideal Class
E voltage and current waveforms are illustrated in Fig. 2. t1 and t2
represent the periods of switch closed and open, respectively.
During t1 period vD is zero; during t2 period the current iD is zero.
Because of the characteristic of non-overlap of the current and
voltage, the power dissipation of the switch is zero.
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iD
vD
t
t1
t2
t
Fig.2 Ideal Class E Voltage and Current waveforms
Fig. 4(a) Mode Locked Amplifier Model including all important
losses when Vin1 is high and Vin2 is low
There are a number of limitations of Single Ended Class E
power amplifier in CMOS GHz implementation. One of them is
that the size of the device is made as large as possible so as to
reduce the finite Ron but by doing so, the parasitic capacitance of
the transistor also increases and it is typically tuned by an
inductive load. However, beyond a certain device size, the
inductance value required to tune out the input capacitance
becomes too small to be physically realizable. The other one is that
the large gate-drain capacitance induces a strong input-output
coupling. So, the single ended circuit discharges a large current to
the ground. This leads to substrate coupling and it can only be
removed by Mode Locking Differential Technique described in the
next section.
Fig. 4(b) Mode Locked Amplifier Model including all important
losses when Vin2 is high and Vin1 is low
Where,
X (t ) = [ x1 (t ) x 2 (t) x 3 (t) x 4 (t) x 5 (t) x 6 (t) x 7 (t) x 8 (t)]
III. MODE LOCKED CLASS E OPERATION
This Technique is a condition in which a cross coupled self
oscillating circuit is made to run at the input signal frequency. It
thus results in a reduced input driving requirement.
= [i L1 (t) Vsw1 (t) i x1 (t) VC01 (t) i L2 (t) i x2 (t) Vsw2 (t) VC02 (t)] (1)
The circuit is governed by a set of first order differential
equations with respect to each variable shown above. During the
conducting phase i.e. when Vin1 is high and Vin2 is low, the model is
described by the following set of differential equations:
dx 1
= − x 2 − R1 x1 + Vdd
dt
dx 2
x2
C1
= − x1 − x3 −
dt
Ron1 || Ron 2
L1
(L x + L 0 )
dx 3
= x 2 − ( R x + R0 + R L ) x 3 − x 4
dt
(2)
(3)
(4)
dx 4
= x3
(5)
dt
dx
L1 5 = − x 7 − R1 x 5 + Vdd
(6)
dt
dx
C1 7 = x5 − x 6 − ( I leak 1 + I leak 2 )
(7)
dt
dx
(L x + L 0 ) 6 = x 7 − ( R x + R0 + R L ) x 6 − x8
(8)
dt
dx
C 0 8 = x6
(9)
dt
C0
Fig. 3 Mode Locking Circuit
As shown in Fig. 3, the two input voltages to the two input
transistors are 180o out of phase. The capacitors parallel to the switch are
replaced by Cgs of the cross coupled devices. The output network is
designed in such a way that input1 and output2 runs in phase. In this the
two output voltages are also out of phase. The current flowing in each
tuned load is now used for switching. The mode locking circuit has a
fixed frequency range like any other tuned circuit. This Locking range is
The operation of the power amplifier of Fig. 4(a) and Fig.
higher as verified by experiments and simulations before. The only
disadvantage of the Mode Locking Circuit is that it requires D-SE 4(b) can be seen as linear time-invariant circuit containing a
periodically operated switch Ron with two states in the switching
conversion at the end [4].
period T. In one of the states (τ1) as shown in Fig 5, a small value
IV. MODELING OF MODE LOCKED CLASS E POWER AMPLIFIER
represents the low on resistance value. In the other one (τ2), a high
resistance value appear across the switch.
The model of a Mode Locked Class E Power Amplifier is
shown in Fig.4. Here, all the important losses are taken into
account. The Fig. clearly shows how the switching between the
two states is taking place. When Vin1 is high and Vin2 is low, the
model looks like as shown in Fig.4 (a), while when Vin1 is low and
Vin2 is high, the model switches to Fig.4(b). The state variables
associated with the overall schematic are given by matrix X(t) [5].
Fig.5 nth Switching Period Notation
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VI. DESIGN OF MODE LOCKED CIRCUIT WITH INDUCTOR LOSS
COMPENSATION
The above differential equations can be written in the matrix
format as:
•
x n ,k = Ak xn ,k + Bk u (t )
(10)
y n ,k = C k xn ,k + Dk u (t )
(11)
Fig. 9 shows the schematic of a Mode Locked circuit with Inductor
Loss Compensation (ILC). In this Design, a cross coupled PMOS
pair is used along with the cross coupled pair of NMOS in original
Mode Locked Topology making it an all CMOS circuit. The
PMOS pair produces the negative resistance effects, thereby
reducing the effective resistance offered by the DC Feed Inductor
[7]. This design helps to compensate for the inductor losses which
are predominant in the design of Power Amplifiers as depicted in
the previous section. This circuit employs the Complementary
CMOS topology instead of NMOS topology.
σ n, k < t < σ n, k +1 k = 1,2
in each portion of the nth switching period τk , k=1,2, has a solution
in the form of:
xn, k = Ak e
Ak ( t −σ n , k )
t
xn, kσ ( n, k ) + e Ak t
∫e
− Ak t '
Bk u (t )dt (12)
σ n ,k
since the matrices ate time independent, so
t
∫e
Ak ( t − t ')
dt = (A k ) -1 (e
A k (t -σ n, k )
- I)
(13)
σ n ,k
where I is the identity matrix. The general solution of eq. to an
input signal u(t) = u at switching instant σn,k is given by:
A (t -σ )
A (t -σ )
xn, k (t) = A k e k n,k x n, kσ (n, k) + (A k )-1 (e k n,k - I) (14)
The above eq. is the general equation for any duty cycle
in case of switching Power Amplifiers. The initial conditions can
be found from the fact that values of state variables at the end of
the conducting phase remains the same as the value of the state
variables at the beginning of the non conducting phase. The Mode
Locked Amplifier model is solved for 50% duty cycle input and
the steady state solution for Power Output and Power Added
Efficiency is reached with the help of LYAPUNOV equation [5].
Fig.6 Surface Plot of Pout as a function of RL and R1
V. LOSS ANALYSIS OF MODE LOCKED CLASS E POWER AMPLIFIER
The above set of differential equations was implemented
as a set of MATLAB functions and the different tradeoff curves
varying with different parameters are generated. As described in
section II, the value of C1 and LX are calculated based on class E
operation conditions. Only the variation of load resistance, the
transistor ON resistance and DC Feed Resistance can be studied
for proper loss analysis of the Amplifier.
The amplifier is designed in 0.18µm CMOS process at
2.4GHz with off chip loading network. The 0.18µm Technology
has a breakdown voltage of just 4.2 volts. The supply voltage of
the power amplifier, therefore, should be lowered to avoid
breakdown of the transistor.
Fig.7 Surface Plot of Pout as a function of RL and R1
The parameters are given in Table 1. The two input
voltages are out of phase with each other by 180o. The circuit is
optimized for obtaining maximum power output and efficiency and
an downward impedance matching network is used, since to
achieve higher output power, small load resistance need to be used
as depicted in section V.
Fig. 10 shows the maximum optimized power output
obtained from both the circuits. As the supply voltage is increased,
the power output increases exponentially. Similarly, the
comparison in PAE between the Mode Locked circuit and Mode
Locked with ILC circuit is shown in Fig. 11. The Differences are
indicated at the voltage level at which the circuit is designed.
The interesting thing to note here is that at lower supply
voltages the Mode Locked circuit gives a better performance. The
reason being , at lower voltage levels, the resistance offered by the
PMOS device exceeds the resistance offered by the inductor itself.
The result is the increase in value of R1 and thereby, a reduction in
Power output as depicted by Fig.6. Moreover, as the voltage level
is reduced, the decrease in power output happens at a faster rate as
compared to decrease in DC Supply power, the result being a
lower PAE.
A .Negative Effects of R1 and RL on Pout and PAE
Fig. 6 and Fig. 7 are the surface plots showing the
variation of Pout and PAE with RL and R1. Each point of the plot in
itself represents an altogether different Mode Locked Class E
Power Amplifier. Because of the condition to keep the switch
voltage within the limits of 4.2 V, the pout and PAE increases
initially with increasing RL and then decreases significantly.
The variation of R1 is the most significant as far as Power
Output is concerned. Both Pout and PAE decreases significantly
with the increase in the DC Feed Resistance.
The Mode Locked Class E Amplifier with the parameter
values specified in Table 1 is modeled using state space algorithm
specified in section IV and the negative effect of DC Feed
resistance R1 is analyzed. The increase in Power Output and PAE
is plotted against the decrease in DC Feed Resistance R1 value
(Fig. 8). It shows the trend with which the Power Output and PAE
should increase with the decrease in the DC Feed Resistance value.
907
The Inductor Loss compensation circuit and the mode
locked circuit with output matching to 50Ω was simulated in
CADENCE SpectreRF and the performance metrics of two are
compared. Fig 10 and Fig 11 depicts the advantages of the ILC
circuit while Table 1 illustrates the values so obtained.
In section 5, Fig. 8 shows the increase in PAE and Pout
with the decrease in DC Feed Resistance R1 Table.2 illustrates the
effect of inclusion of cross coupled PMOS pair in the Mode
Locked circuit. Table 3 shows the Modeling and Simulation
comparison between the two approaches.
Fig. 11 Comparison of PAE vs DC Supply Voltage
Fig.8 Variation of Pout and PAE with the decrease of DC Feed Resistance R1
Performance Metric
Mode Locked
Circuit
Frequency
Pout
V dd
Power Gain
PAE
Effective Resistance
Offered by Ldc Choke
2.4GHz
21.76 dbm
2
16.76 dB
36.66%
9.953 Ω
Mode Locked Circuit
with Inductor Loss
Compensation
2.4GHz
23.8 dbm
2
18.8 dB
41.06%
7Ω
Table 2: Comparison between performance metrics of Mode Locked and Mode
Locked with ILC Circuit
Change in R1
(ΔR1)
Modeling
Simulation
2.953Ω
2.953Ω
Increase in
Pout
Increase in
PAE
125 mW
90 mW
6.9 %
4.4%
Table 3: Comparison between Modeling and Simulation Results
VII. CONCLUSION
The Modeling of Mode Locked Power Amplifier was done using
state space algorithm. Loss analysis of the circuit is done with the
tradeoff curves obtained depicting the negative effects of R1 on the
performance metrics of Power Amplifier. A technique to negate
the negative effects of R1 was introduced and comparisons shows
the improved performance of the Power Amplifier.
Fig. 9 Schematic of Mode Locked Circuit with Inductor Loss Compensation
W/L of M1,M2
W/L of M5,M6
L0,L0’
Ldc, Ldc’
Rs
525 µm
/0.18µm
840 µm
/0.18µm
0.2n
585p
50 Ω
W/L of
M3,M4
L1,L1’
630 µm
/0.18µm
0.8n
C0,C0’
V dd
RL
5.1p
2
50 Ω
REFERENCES
[1]
Table 1 Parameter Values for Mode Locked with ILC Circuit
[2]
[3]
[4]
[5]
[6]
Fig. 10 Comparison of Pout vs DC Supply Voltage
[7]
908
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