Phase Noise Reduction in Quadrature LC Oscillators Using InverterBased Tail Noise Shaping
Jayanta Mukherjee1, Maryam Shojaei-Baghini1, and Manoj Johnson1
1
: Electrical Engineering Department, Indian Institute of Technology, Mumbai 400076, India
Abstract - A technique to reduce the Phase Noise of a
Quadrature Differential Oscillator is described. The technique
uses inverters to shape the tail noise of differential oscillators. In
this approach an inverter is used to increase the “squareness” of
the switching signal from the differential output and thereby
improve the switching speed. Simulations are done to obtain the
results to verify the new technique. The simulation tool used is
Eldo RF in Mentor Graphics and the technology used is UMC
0.18 um process.
I. INTRODUCTION
One popular application of differential oscillators is to
generate quadrature signals [1]. This basically involves
coupling two symmetric tank oscillators in series as shown in
[2] or parallel as shown in [3]. While the series coupling is
shown to have a better phase noise performance, it is not
optimally loaded and also provides less voltage headroom
under low supply voltage conditions. The basic parallel
coupled quadrature oscillator is shown in Fig 1. Several
approaches have been developed to model and reduce Phase
Noise of quadrature oscillators [4], [5], [6], [7] [8] and [9].
Fig. 1. A basic parallel coupled Quadrature Oscillator
II. THEORY OF PULSED TAIL GATE BIASING
In [10], it was shown that only the flicker noise produced by
the tail transistor of a differential oscillator contributes
significantly to the oscillator phase noise, while the white
noise produced is largely suppressed. The output noise
spectral density of the oscillator has a component produced
due to the tail transistor flicker noise given as,
S V tail
=
KS
tail
3
Δω
(1)
where, K is a constant and the power spectral density of flicker
noise produced by the tail transistor is given by,
Flicker noise in MOSFET is either theorized as a random
variation in the carrier-density in the MOSFET channel or as a
variation in the mobility of the carriers in the channel [11] or
alternatively a unified model that approximates one of these
two processes depending on the bias voltage [12]. The carrierdensity variation theory is more popular, in this model, random
trapping and releasing of charges near the Si-SiO2 interface
causes fluctuation in the channel carrier density. This charge
trapping process has a large time constant and hence this
random noise appears only at low frequencies (typically less
than 10 KHz). Fig 2(a) shows a simple stand alone differential
oscillator biased using a pulse voltage.
As shown in [8] this topology produces a lower phase noise in
3
the 1/f region as compared to the fixed bias topology shown in
Fig 2(b). In Fig 2(a), the tail MOSFET is periodically switched
between an active state during which the MOSFET is on and an
inactive state in which the MOSFET is off. During the inactive
phase trap formation ceases and the traps release their stored
charge.
Instead of providing an external pulse to the tail transistors,
the outputs A and B shown in Fig 2(a) can used as the pulse
signal [8]. The advantage of this technique instead of using an
external pulse is that the tail transistors can be switched on and
off exactly when the currents through the cross coupled
transistors are at their peak and trough respectively. But since
the outputs at A and B are sinusoidal, switching of the
transistors is not perfect. This results in increased phase noise.
III. EXISTING SWITCHED TAIL TRANSISTOR BIASED
QUADRATURE OSCILLATOR TOPOLOGIES
In [13] two separate oscillator topologies in which tail
transistors are switched by their own outputs were described.
These circuits, shown in Figs. 3 and 4, utilize the concept of
switched tail gate biasing as described in Section II.
IV. NOVEL QUADRATURE OSCILLATOR TOPOLOGY
A new technique which employs an inverter to increase the
“squareness” of the oscillator output before applying to the
biasing transistors will enable us to switch the tail transistor
more efficiently. Figs 5 and 6 show the circuits corresponding
to Figs 3 and 4, respectively now with the inverters Inv1, Inv2,
Inv3 and Inv4 in the signal paths. In Figs 3 and 4 gate voltage of
tail transistors are close to a sine wave and in Figs 5 and 6 it is
close to a square wave. Note that the inverter itself also
contributes some noise to the tail transistor, but circuits can be
designed so that added noise is less than that reduced by the
switching. The circuit of the inverter used is shown in Fig 7.
The additional diode connected transistor MQ is introduced to
provide sufficient bias voltages to the tail transistors.
The noise source In2 corresponds to the combined output
current referred noise of MQ and MR while In2 corresponds to
the output current referred noise of MP. Fig 8 shows the
equivalent circuit of the inverter for computing the output
impedance. The diode connected NMOS MQ is assumed to be
forward biased. The output impedance is given by,
From which, the equivalent output noise voltage of the
inverter, is given by,
2
Note that the value of v n ,inv increases with increase in the
size of the inverter transistors due to increasing their current
[14]. However the switching speed also increases with increase
in the inverter transistor size, which in return reduces the trap
formation in the tail transistor [15]. The signal appearing at the
gate of the tail transistors with and without the inverter is
shown in Fig 9.
V. SIMULATION RESULTS
The circuits shown in Figs 5 and 6 were simulated in a 0.18
μm CMOS process using a standard circuit simulator at a
supply voltage of 2V. The corresponding reduction in noise
density at an offset of 10 KHz, across M13 in Fig 5, top and
bottom tail transistors in Fig 6 are shown in Fig 10. The top
tail transistors refer to transistors M13, M14, M15 and M16 in Figs
4 and 6. While the bottom tail transistors refer to transistors
M17, M18, M19 and M20 in same figures. Fig 10 is obtained by
varying sizes of NMOS and PMOS transistors, keeping a
constant aspect ratio. The width of a finger for all cases is 5
μm. The sizes of the transistors were varied by varying the
number of fingers. It can also be seen from Fig 10 that noise
voltage density of the tail transistor reaches a minima after
which it increases. The tail noise reduces with increase in the
inverter size due to faster switching to a limit after which the
added noise of the inverter causes the total noise to increase.
Fig 11 shows the variation in phase noise at an offset of 10
KHz from the oscillation frequency of the circuits shown in
Figs 5 and 6 with respect to inverter size. It can be seen that
the phase noise spectra also follows the trend of the flicker
noise. The variation of tail transistor noise density and Phase
Noise of the various circuits with frequency, at their optimized
configurations is shown in Figs 12 and 13 respectively. As
shown in Fig 12 a 13dB drop in noise density at 10 KHz offset
(corresponding to the flicker noise region) can be seen from
the circuit of Fig 3 to that of Fig 5. Table I summarizes the
performance of the various circuits obtained from simulations.
The FOM of an oscillator can be given by the following
equation,
We wish to express our gratitude to Europractice for kindly
giving us access to the UMC 0.18um RF design kit. All
simulation results shown in this work were obtained at the
VLSI Lab of IIT Bombay.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Here Pdiss is the power consumed by each oscillator circuit in
milliwatts, L is the phase noise and fc is the oscillation
frequency. From Table I it can be seen that at an offset of
10KHz, there is a reduction of phase noise by 7dB from the
circuit of Fig 3 to that of Fig 5, while at an offset of 100KHz,
the reduction is by 4dB. The circuit of Fig. 5 offers the best
FOM at 10KHz offset. At 100KHz offset, which is the
boundary of 1/f region, its FOM is better though not the best.
Finally the circuit of Fig. 5 exhibits the lowest phase noise at
both 10KHz and 100KHz offsets, among all the topologies
considered.
[10]
[11]
[12]
[13]
VI. CONCLUSION
A new technique to reduce Phase Noise in quadrature
oscillators using an inverter-based tail gate switching was
demonstrated in CMOS technology. Using accurate
simulations it was shown that this technique offers better
Phase Noise and FOM, compared to other existing topologies.
This technique is useful for wireless standards requiring high
phase purity during down-conversion.
ACKNOWLEDGEMENT
[14]
[15]
A. Rofougaran, J. Real, M. Rofougaran and A. Abidi, “A 900
MHz CMOS LC Oscillator with Quadrature Outputs,” IEEEInt
Solid State Circuits Conf (ISSCC), pp. 392--393, 1996.
P. Andreani, A. Bonfanti, L. Romano and C. Samori,
“Analysis and Design of a 1.8 GHz CMOS LC quadrature
VCO” IEEE Journal of Solid State Circuits, pp. 1737--1747,
Dec 2002.
Hsien-Ku Chen, Da-Chiang Chang, Ying-Zong Juang and
Shey Shi Lu, “A Low Phase Noise 9GHz CMOS Quadrature
VCO with Novel Source-Follower Coupling Technique,”
IEEE/MTTS International Microwave Symposium, pp. 851-854, 3-8 June 2007.
Mukherjee J., Kim Y.G., Suh I., Roblin P., Liou W.R., and
Shojaei-Baghini M. “Microstrip Equivalent Parasitic
Modeling of RFIC Interconnects,” IEEE Midwest Symp. On
Ckts. And Sys. Aug 2007, in press
R. Van de Ven, J. Van der Tang, D. Kasperovitz and A. Van
Roermund, “An Optimally Coupled 5 GHz Quadrature LC
Oscillator” in IEEE VLSI Tech Digest, pp. 115--118, 2001.
Huijung Kim, Seonghan Ryu, Yujin Chung, Jinsung Choi and
Bumman Kim “A Low Phase-Noise CMOS VCO with
Harmonic Tuned LC Tank,” in IEEE Trans. on MIT, pp. 115-118, vol.54, no. 7, July 2006.
S.L.J Gierkink, S. Levantino, R.C. Frye, C. Samori and V.
Boccuzzi “A low Phase Noise 5GHz CMOS quadrature VCO
with super-harmonic coupling,” in IEEE J.Solid-State
Circuits, pp. 1148—1154, vol.38, no.7, July 2003.
C.C. Boon, M.A. Do, K.S. Yeo, J.G. Ma and X.L. Zhang “RF
CMOS Low-Phase-Noise LC Oscillator Through Memory
Reduction Tail Transistor,” in IEEE Trans. on Circuits and
Systems-II:Express Briefs, pp.85—90, vol.51, no.2, Feb 2004.
Jung-Yu Chang, Chia-Hsin Wu, and Shen-Iuan Liu “A 2.4
GHz CMOS Quadrature VCO for 2.4GHz WLAN/Bluetooth
Applications,” Asian Solid-State Circuits Conference, Nov
2005, pp. 493-496.
Mukherjee J., Roblin P. and Akhtar S. “An Analytic CircuitBased Model for White and Flicker Phase Noise in LC
Oscillators,” IEEE Trans. on Ckts. and Sys-I: Regular paper,
vol.54, July 2007, pp.1584—1598
A. Van der Ziel, “Noise Sources, Characterization,
Measurement,” Prentice-Hall, Inc., Eaglewood Cliffs, N.J.,
first edition, 1970.
Hunk K.K., Ko P.K., Hu C. and Chen Y.C. “A unified model
for flicker noising metal-oxide semiconductor field-effect
transistors,” IEEE Trans. Electron Devices, vol.37, pp.654 —
665, Mar. 1990
Jeong Chan-Young and Yoo Changsik “5-GHz Low Phase
Noise CMOS Quadrature VCO,” IEEE Microwave and
Wireless Component Letters, pp.609—611, vol.16, no.11, Nov
2006.
Yuhua Chen and Chenming Hu “MOSFET modeling &
BSIM3 Users Guide” Kluwer Academic Publishers, 1999.
Klumpernik E.A.M., Gierkink S.L.J., Van der Wel, A.P. and
Nanta B. “Reducing MOSFET 1/f noise and power
consumption by switch biasing,” IEEE J.Solid-State Circuits,
vol.35,
vol.16,
pp.
994—1001,
July
2000.