Semiconductor Memory:
DRAM and SRAM
Department of Electrical and Computer Engineering, National University of Singapore
Outline
•
Introduction
•
Random Access Memory (RAM)
– DRAM
– SRAM
•
Non-volatile memory
– UV EPROM
– EEPROM
– Flash memory
– SONOS memory
– QD memory
Department of Electrical and Computer Engineering, National University of Singapore
Introduction
•
Slow memories
– Magnetic and optical disk
– Magnetic tape
– Slow and high capacity
•
Semiconductor memories
– DRAM
– SRAM
– Non-volatile memory
– High cost, fast, and use of
MOSFET
Department of Electrical and Computer Engineering, National University of Singapore
Introduction (2)
Department of Electrical and Computer Engineering, National University of Singapore
Introduction (3)
Department of Electrical and Computer Engineering, National University of Singapore
DRAM (1)
•
Introduction
– The highest density semiconductor
product
– Used as the indicator of the technology
level
– Forerunner of the most advanced
technology
– Consist of 1T1C (1 transistor and 1
capacitor)
– Charge stored in capacitor
– When capacitor is charged to a “high”
voltage, the DRAM cell stores a “1”
state; when C is charged to a “low”
voltage, the DRAM cell stores a “0”
state.
Department of Electrical and Computer Engineering, National University of Singapore
DRAM (2)
•
Operation principle (I)
Write and read operation
- Write:
When WL is selected, the data stored on BL will be stored in the capacitor
- Read:
BL is pre-charged to VDD/2, when WL is selected, the potential at X will be
higher than VDD/2 or lower than VDD/2 depends on the stored data.
Department of Electrical and Computer Engineering, National University of Singapore
DRAM (3)
•Operation principle (I)
Charge sharing sensing
- CB/CS (bit line capacitance over memory cell capacitance, normally larger than
10) is one of most important parameter in DRAM design
- when read, the potential will be charged. The sense amplifier must be sensitive
enough to read this signal
- the change of potential in memory cell node can be given as below:
- in practice, the minimum
voltage detected by the
sense amplifier is 100mV.
For higher density, the
sensitivity of sense amplifier
should be much increased.
Department of Electrical and Computer Engineering, National University of Singapore
DRAM (4)
•Operation principle (I)
Refresh
- The voltage stored on “1” memory cell
will slowly decades to a “0” voltage state
through various leakage mechanisms
- Periodically reading the data and
rewriting the same data is necessary which
is called refresh.
- Leakage mechanisms include
- Junction leakage
- Pass transistor sub-threshold leakage
- Leakage through capacitor dielectrics
- Other parasitic leakage paths
Department of Electrical and Computer Engineering, National University of Singapore
DRAM (5)
•Operation principle (I)
Soft errors
- alpha particle
Æ double charged helium nuclei that originates from the decay of radioactive
elements in the package or metallization material.
Æ only determined by the total amount of charge collected by the cell node.
- cosmic rays
Æ a very small percentage of high-energy neutrons will interact by colliding
with silicon nucleus, which generate charges.
Department of Electrical and Computer Engineering, National University of Singapore
DRAM (6)
•Operation principle (I)
Cell scaling
Approaches to cell scaling
Æ reduce thickness
Æ increase dielectric constant
Æ increase capacitance area
(i) stacked capacitor DRAM cell
(ii) trench capacitor DRAM cell
Department of Electrical and Computer Engineering, National University of Singapore
DRAM (7)
•Operation principle (I)
Cell scaling
Reducing dielectric thickness “t”
- this approach is mainly limited by Fowler-Nordheim tunneling current
- primarily constrains in reducing the dielectric thickness originate from
dielectric reliability, leakage current, etc.
Increasing dielectric constant
- O (oxide) Æ ONO (oxide nitride oxide) Æ NO (oxide nitride) Æ Ta2O5 Æ
higher dielectric constant material (BST, PZT, etc.)
- combination of oxide and nitride can provide at best 4 nm in effective oxide
thickness
- Ta2O5 film has a higher dielectric constant, and demonstrated with 3 nm
effective oxide thickness, but the process feasibility is still not proven yet.
- for PZT, BST, a lot of process issues exist.
Department of Electrical and Computer Engineering, National University of Singapore
DRAM (8)
•Operation principle (I)
Cell scaling
Increasing area “A”
Stacked capacitor DRAM cell
Æ the capacitor dielectric film
is formed between the two
heavily doped poly-Si (or
metal) and is stacked over
the pass transistor.
Æ the device structure is simple
Æ process is less sensitive
Department of Electrical and Computer Engineering, National University of Singapore
DRAM (9)
•Operation principle (I)
Cell scaling
Increasing area “A”
Trench capacitor DRAM cell
Æ the capacitor dielectric film
is formed inside a trenched
etched into the silicon substrate
and between two heavily doped
silicon layers or metals
Æ has advantage in super
planarity
Æ process is complicated and
difficult
Department of Electrical and Computer Engineering, National University of Singapore
DRAM (10)
•
Comments
– Cell scaling
– New memory architecture and circuit technique to reduce cell size
– On-chip integration of DRAM and logic circuits (embedded DRAM)
– Increasing difficult to meet soft-error requirement
Department of Electrical and Computer Engineering, National University of Singapore
DRAM (11)
Department of Electrical and Computer Engineering, National University of Singapore
1G DRAM
Department of Electrical and Computer Engineering, National University of Singapore
SRAM (1)
•
Introduction
– An SRAM cell is a bistable transistor flip-flop, or two inverters
connected back to back.
– Type of SRAM
• Depletion load
• Resistor load
• Full CMOS
• TFT load
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SRAM (2)
•
Example
– TFT load SRAM cell structure
– P-channel TFT is fabricated on top of an n+ poly-Si gate
– The n+ poly-Si gate is shared with bottom n-channel bulk MOSFET and
p-channel TFT
– The drain of TFT is offset from the gate to reduce the leakage current
Department of Electrical and Computer Engineering, National University of Singapore
SRAM (3)
•
Comparison of different SRAM structures
– Depletion load
• Use depletion-mode n-MOS transistor as load
• Oldest type before CMOS technology
– Resistor load
• Use high-resistance polysilicon resistor as load
• Small cell area and high density
– Full CMOS load
• Use bulk p-MOS transistor as load
• Cell size tend to be larger than R-load cell
• Very low standby current
• Currently the dominant technology due to good stability at low power
supply
– TFT load
• Use p-channel TFT as load
• Combines the low-power advantages of the full CMOS load cell and the
high density advantages of R-load cell
• Has been popular for a while, but received less attention recently due to
poor stability at low power supply and process complexity
Department of Electrical and Computer Engineering, National University of Singapore
SRAM (4)
•
Operation principles
Write operation (writing “1” as example)
-
Word line of the cell is selected
(raised to VDD, 5V) Æ T5 and T6
turn ON
Bit-bar line must be forced low Æ T1
turns OFF and T3 turns ON
The drain voltage at C5 rises due to
the current flowing through T5 and
T3
When T2 has been turned ON, the bit
line can be returned to its steady
level, leaving the cell in the state of
storing a “1”.
Department of Electrical and Computer Engineering, National University of Singapore
SRAM (5)
•
Operation principles
Read operation (reading “1” as example)
- The word line of the cell is selected
(raised to VDD) Æ T5 and T6 are turned
ON.
- Both the Bit line and Bit-bar line must be
biased at some voltage (for example, 3V)
- When the cell is selected, currents flow
through T6 and T2 to Vss and through T3
and T5 to the bit line.
- Since T2 remaining ON, the voltage of
bit-bar line is reduced to less than 3V
- While the voltage of bit line is pulled up
above 3V since T1 is OFF but T3 is ON
- The differential output signal between the
bit and bit-bar lines is fed into the sense
amplifier, which in SRAMs is a
differential amplifier capable of providing
rapid sensing.
Department of Electrical and Computer Engineering, National University of Singapore
SRAM (6)
•
Cell stability analysis
– Cell stability determines the soft-error rate and the sensibility of the
memory cell to variation in process and operating condition
– Cell ratio (β ratio)
• Recall, β=µCox(W/L)
• The ratio between the β of the driver transistor and the β of the
access transistor
• One important parameter that determines the SRAM cell stability
• If the ratio is too low, it can bring the cross-coupled low side too
high and can flip the cell
• Higher ratio result in better stability, however cause larger cell
size.
Department of Electrical and Computer Engineering, National University of Singapore
SRAM (7)
Department of Electrical and Computer Engineering, National University of Singapore
SRAM (8)
•
Soft errors
– Alpha particles
• When an alpha-particle hits the high side of cell, the collected charge
lowers the potential of the high node and can flip the cell, thus cause
a soft error
– Cosmic rays
• Same as DRAM
Department of Electrical and Computer Engineering, National University of Singapore
SRAM (9)
•
Comments
– SRAM memory cell size trends
– Full CMOS memory cell becoming dominate due to low-voltage advantage
– Increasing difficulty in meeting soft-error requirement.
Department of Electrical and Computer Engineering, National University of Singapore
Department of Electrical and Computer Engineering, National University of Singapore
References
•
S. Shichijo, “DRAM and SRAM”, Chapter 7, “ULSI Devices” (Editors: CY
Chang and SM Sze), John Wiley & Sons, 2000.
• J. A. Mandelman, et al, “Challenges and future directions for the scaling of
dynamic random-access memory (DRAM),” IBM J of Res & Dev, Vol. 46,
No. 2/3, pp. 187, 2002.
• P. W. Diodato, “Embedded DRAM: More than just a memory,” IEEE
Communication Magazine, July, 2000.
• Proceedings of ISSCC
• Proceedings of IEDM
• Proceedings of VLSI Symp on Technology
• IEEE Trans on ED, IEEE EDL
Department of Electrical and Computer Engineering, National University of Singapore