Single-Event-Induced Barrier Lowering in
Deep-Submicron MOS Devices and Circuits
Palkesh Jain, J. Vasi and Rakesh La1
Department of Electrical Engineering,
Indian Institute of Technology, Bombay, Mumbai 400076, India
E m a i l : [email protected]
Ab3tmct- In this paper, we report a novel reliability issue, coined Single-Event-induced Barrier Lowering (SEBL),
which deals with harrier lowering along the channel and the
source-substrate junction during a single event high energy
particle strike on MOS devices. We have comprehensively
studied SEBL for different channel lengths and our results
suggest that it can cause significant charge enhancement,
and therefore can bring down the critical energy to low values. Thus SEBL can he a strong deterrent to further P R
duction of the stored charge on a node and can have serious
scaling implications.
wc.
KeywordsSingle event upset (SEU), charge enhancement, single-event-induced harrier lowering (SEBL), deep
submicron, scaling, SRAM.
s
I. INTHODUCTION
INGLE event upsets have been one of the most impor. . .
tant reliability concerns in the technological develop
ment of memories. These are caused when highly energetic
particles present in the natural space environment (e.g., Fig. 1. Device schematic depicting X-Y directions, location and angle
protons, neutrons, alpha particles, or other heavy ions) of the particle strike.
strike sensitive regions of a microelectronic circuit [l]. D o
pending on various factors, the particle strike may cause
no observable effect, a transient disruption of circuit oper- study develops it further and extends the understanding
ation, an erroueous logic state - "upset" or in some cases, by the analysis of barrier lowering along the surface and
even permanent damage to the device or the circuit. One of the source-substrate juuction, induced because of the parthe first circuits to be directly affected by, and researched ticle strike (termed single-event-induced barrier lowering,
for SEUs was the DRAM. With technological advancement, SEBL). With the help of extensive device simulations, we
the problem has become an important issue for SRAMs as show that SEBL can cause more than 40 % charge enhancewell.
ment in short channel transistors. Thc circuit implications
During a single event particle strike, the most sensi- of the problem are explored through investigations on a
tive regions are usually reverse biased p-n juctions. The standard and a resistive hardened (RH) 6T SRAM cell.
high field present here efficiently collects the "ion-induced"
charge, first by drift and then by diffusion, thereby lead11. SIMULATION
METHODOLOGY
ing to transient cnrrent at the junction contact. This current is generally presumed to be accurately depicting the
Various transistors, isolated p-n junctions (for each techresponse of a long channel transistor t o the single event.
However with the constantly decreasing channel lengths, nology node) and the SRAM cells (standard and RH) were
various charge enhancement (and deprivation) phenomena designed using DIOS (process simulator) and DESSIS (detake place, which alters the actual charge that a junction vice simulator) available in the ISETCAD suite. To study
is subjected to, after the particle strike. While the charge the single event effect, the length of the heavy ion track
enhancement helps the upset process [Z], [3]:charge depri- wass made 0.5 pm arid a particle of LET 0.2 pC/pni (corvation actually works against it [4]. One of the charge en- responding to an energy of 19.4 MeV-cm2/mg) was hit at
hancement phenomena, direct chaniiel conduction, caused the drain-gate edge of an OFF (V& = 0, VDS= V D D )
because of radial electric fields getting on the order of d o NMOS transistor (Fig. l), which accounts for the worst
vice size, was reported in [5].That work was limited to 0.3 case. 2-D device simulations were performed to extract
pni discrete transistors at a fixed 3.3 V drain contact bias, relevdnt information like potential, carrier distribution and
not representative of a device in an operating circuit. This also the currents generated.
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111. PHYSICAL
MECHANISM
The sharp current transients that are produced in response to the particle strike in a 0.1 pm OFF NMOS transistor are shown in Fig. 2. The presence of an electric field
.... .....
Fig. 3 shows the potential profile along tlie channel (Ydirection in Fig. 1)during this strike at various times. As is
evident, just after tlic strike, the potential barrier collapses
and additionally, there is also a harrier lowering along the
source-substrate junction (X-direction in Fig. l ) ,as shown
in Fig. 4. These events go along with the peaking of the
drain current. As the time elapses, tlie potential barrier
recover to its original profile.
0.002
,-.
5
a...
.
;
1
0.001
g
a
z2
2
-0.001
-0.002
0.1
1
10
Time (psec)
at the drain-bulk junction induces the separation of the
generated carriers which are then collected at the contacts,
first hy drift and then by diffusion, leading to such a trailsicnt. The depletion region of this junction collapses due
to the induced high free carrier density arid the potential
lines, usually confined to the junction; are then distributed
over the entire bulk. At the very beginning, thesource-bulk
capacitance is heing charged. The presence of electric field
around the drain-bulk junction induces the charge collection hy drift. As the depletion region around this junction
hcgins t o reform: the diffusion process becomes predominant and the source-hulk capacitance is discharged.
I
...
0.1 ps 5ps
1 ps .............
1 ns
--,*-
............
+.
...
+
....
+-.-+--,.+--i'--'+--tt------
0.1 ps
1 ps
....
5 ps ............
0.1 ns
1 ns .......
~
o
-0.4
Fig. 2. Currents produced in the 0.1 pm O F F NMOS transistor after
the particle strike of LET 0.2 pC/prn.
*
0.2
-0.2
100
.,. ......... ..................
* .........
......e.* ......BB.--~-~.--*..-(t---(t...e
.........
0.4
0
c
g
2,51
k eaED-o
n.-*-
0.6
0
3
...... *....
0.8
..........
-0.6
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Distance from the source into the substrate (X direction) um
Fig. 4. Potential barrier dong t h e vertical cut - through the source
into t h e substrate of the 0.1 prn O F F NMOS transistor, at various
time instants (along X-direction).
This effect, i.e. lowering of the source-channel potential harrier, is attributed to the spreading of the electric
field (because of the particle strike). For channel lengths
comparable to the ion track, the radial field sets up a potential gradient that encompasses the entire channel region
and removes the barrier at source. The potential gradient
along the channel also emphasizes the fact t h a t sonrcesubstrate barrier lowering in this case is significantly different from the bipolar effect [6], which requires tlie substrate
to be field-free for the diffusion of carriers injected from the
source-substrate junction. A similar, total dose radiationenhanccd drain induced barrier lowering was reported by
Yonk et al. for submicron devices with trench isolation [7]>
but that was a case of static barrier lowering.
IV. IMPLICATIONS
O F SEBL
m
6
a
The barrier, as shown in Fig. 3 is similar to that of an
ON MOS transistor, thus making the conduction process
alike. As a result, SEBL contributes t o the charge col-
......
....
0.5
0 '
0.05
0.1
0.15
0.2
Distance from the source (Y-direction) um
I
0.25
Fig. 3. Potential barrier across the channel (7 nrn bclaw the interface)
of the 0.1 p m O F F NMOS transistor, a t various time instants (along
Y-direction)
0-7803-8454-7/04/$20.00 02004 IEEE.
lection a t the drain, which adds t o the "particle-induced'
charge resulting in charge enhancement. In order to evaluate this charge enhancement, we compare the charge collection of transistors t o that for isolated p-n junctions for
various technologies. As these diodes do not have any short
channel or enhancement mechanism, a particle strike would
result only in a current that can be entirely attributed to
the particle. Table. I summmizes the findings for various
devices with a particle strike of LET 0.2 pCIpni. As can
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be seen, for a 0.1 pm transistor, charge collected at the
draiu (143 fC) is much greater than the charge deposited
(100 fC), thus bringing down the critical LET.
TABLE I
Cornpvrison of charge collections in isoiatcd pn junctions (of same
technology) and OFF NMOS transistors. hlaximum charge that
particle can deposit is 10OfC.
NMOSFET
0.lpm
0.2/1m
0.5pm
1P
2 nm
Charge C o l l e c t e d
(Drain - fC)
143
137
122
98
Charge Enhancement
urt diode %
43.7
38.6
23
1.2
95
0
0 '
Fig. 6.
~
I
I
1
I
P
2
1 -
2
m
w 0.8 v)
0.6
0.4 0.2
'
0
0.5
1
Channel LengVl (urn)
1.5
2
Fig. 5 . SEBL (parameterized here as the ratio of AV (described in
Fig. 3) and the original poteritid barrier lor each transistor), as a
functioii of channel length. Ratio of '1' indicates a barrier lowerins
equal to the original barrier.
Fig. 6 shows an increasiug trend in SEBL with the particle energy. Our simulation results at various values of drain
voltage also show an increasing trend in SEBL, which can
be attributed t o the fact that higher VDSsupports larger
penetration of electric fields into the source.
0-7803-8454-7/04/$20.00 02004 IEEE.
0.15
0.2
0.25
SEBL for particles of different energies in a 0.1 p m OFF
NMOS transistor.
To elaborate the parametric dcpendencies in SEBL, Fig.
5 shows the impact of scaling on SEBL, depicting that
harrier gets lowered t o a much largcr extent for d e e p
submicron transistors. Here, t,he ratio of AV - the change
in harrier before and after the strike (at the mid-point along
the channel) aud V the absolute barrier before the strikc
(at the samc point of thc channel) is plotted for various
channel lengths. This trend seems to be reasonahlc, since
shortcr the channcl, more would be the impact of the source
on the drain and denser would be t,he radial electric fields
created by the particle strikc.
1.2
0.1
Distance from the source (Y direction) urn
V. PARAMETRIC
DEPENDENCIES IN SEBL
1.6 i
I
0.05
VI. UPSET I N SRAM
CELL :
SEBL PERSPECTIVE
An irriportant part of the present study is to observe
thc circuit implications of SEBL. Two test, circuits were
chosen for this purpose - a standard SRAM cell (6T) and
a. feedback rcsistive hardencd (RH) SRAM cell (6T). The
modeling of the cross-coupled SRAM cell was performed in
the device domain and it was constructed using the process
generated NMOS and PMOS transistors. The feedback
resistors (for RH SRAM) and the access transistors wcre
iricluded as circuit elements. The circuits are shown as
insets in Figs. 8 and 9.
The upset process in S U M S is strongly dependent on
the z t i v e fcedback in thc cross-coupled inverter pair. Because of single event, particle strike at a sensitive location
in the SRAM (typically the drain of the OFF NMOS transistor), charge collected at the junction results in a current
transicnt. As this current flows through the struck (OFF
NL4OS) transistor, the restoriug transistor (ON PMOS)
sources currcnt in an attcrupt t o balauce the particleinduced current. Limited by the finite current drive and
channel conductance of the PMOS, this current transient
causes a voltage drop at the drain of PMOS. This voltage
transient is actually fed as input to the cross-coupled inverter and therefore if the voltage drop exceeds the threshold, a wrong logic state is triggered and upset occurs [8].
Thus, a simple way to avoid upsets is to increase the delay
in the feedback path [9]. This is done by having resistors,
which delay the voltagc transieut from reaching the othcr
inverter, thus avoiding the upset. The voltage tramsients
for the staudard arid RH SRAM are as shown in Fig. 7.
Fig. 8 shows the barrier lowcring in the transistor of the
standard SRAM ccll- depicting the flipping of the barrier
(along with barrier loweriug at sourcc-end) from logic '1'
to '0'. Because of this barrier lowering, the energy required
to flip the standard SRAM ccll is lowered. Thus, we can
qualitatively say that the critical energy for a 1 pm SRAM
cell, built with 0.1 pm technology, would be more than that
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2.5
k
...........
1.5
Bitiine Std. SRAM Bitline RH SRAM ............
Bitbar Std. SRAM
Bitbar RH SRAM . . . - ....
-
2
.....
-t
E
-
1
1.5
m
.0.5
'
a
0.5
0
-0.5
IT-
-
O t
I
-0.5
-1
0
1
10
100
1000
0.04
0.06
0.08
0.1
Distance from the source (Y-direction) urn
0.02
Time (psec)
Fig. 7. SEU shown in a standard SRAM alongwith the recovery in
s RH SRAM
Fig. 9. Potentials for the O F F 0.1 fim NMOS transistor of t h e RHSRAM cell (ckt. in the inset) a t various times. Shows the recovery
of the cell along with SEBL. RH SRAM has feedback resistors of 1
MR.
of a 0.1 pm SRAM cell. This argument is substantiated by
the fact that SEBL (and therefore charge enhancement)
for a 1 pm transistor is negligible as compared to 0.1 pm
transistor (refer Table I and Fig. 5 ) . In contrast, even
though the barrier of the transistor in the RH SRAM cell
lowers initially along-with the flipping of logic (Fig. 9), the
slow feedback (because of the resistors) forces the cell to
recover.
I
0
0.02
0.04
0.06
0.08
Distance from the source (Y-direction) urn
0.1
will carry significant scaling implications. Intelligent channel and substrate engineering could he among the possible
ways to suppress SEBL, since the study shows that the
source plays an important role during SEBL.
REFERENCES
[I] P. Dodd, L. W. Massengill, "Basic Mechanisms and Modeling of
IEEE %macSingle-Event Upset in Digital
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121 T. R. Weatherford, W. T. Anderson, Jr., "Historical Perspective
on Radiation Effects in 111-V Devices", IEEE Pansaclions on
~~~i~~~ science,
vol. so, NO. 3, J U " ~zoos, pp.704-in.
[3] E. Takeda, K . Itoh, "A Cross Section of a-Particle-Induced SoftError Phenomena in VLSIs", IEEE 'Tbansaclions an Electron
Deuiees, Vol. 3 6 , No. 11, Nov. 1989, pp.2567-75.
141 P. Saxena, N. Bhat, "SEU Reliability Improvement Due to
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[SI S. Velacheri, L. W. Massengill, S . E. Kerns, "Single Event Induced
Charge Collection and Direct Channel Conduction in Submicron
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[GI C. Dachs, J. M. Palau, R. Ecoffet, "SEU Critical Charge and
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[7] G. U. Youk, P. S. Khare, R. D. Schrimpf, L. W. Massengill, K .
F. Galloway, "Radiation-Enhmced Short Channel Effects due
t o Multi-Dimensional Influence irom Charge a t Ttiench Isolation
Oxides", IEEE Pansaclions o n Nuclear Science, Vol. 46, No. 6 ;
Dec. 1999, pp.1830-35.
Fig. 8. Potentials for the OFF 0.1 prn NMOS transistor of the SRAM
cell (ckt. in thr inset) at various times (along Y-direction). Shows
the upset along with SEBL.
[8] P. Roche, J . M. Palau, 6 . Bruguier, C. Tavernier, R. Ecoffet, J.
Gasiot, "Determination of key parameter for the SEU occ~rrence
using 3-D full cell SRAM simulation", IEEE Tknsaclions on
Nvclear Science, Vol. 46, No. 6, Dec. 1999, pp.1353-62.
IS] F. W. Sexton, J. S. Fu,R. A. Kohler, R. Koga "SEU Characterization of a hardened CMOS 64K and 256K S R A W , IEEE Tmnsactions o n Nuclear Science, Vol. 36, No. 6, Dec. 1989, pp.2311-17.
VII. CONCLUSION
Wc have studied a novel reliability concern, termed
single-event-induced barrier lowering (SEBL), using extensivc device simulations. Our results show that SEBL increase with diminishing channel length and causes charge
enhancement of upto 40 %. Being a short channel effect, it
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