IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 2, JUNE 2005
289
SEU Reliability Analysis of Advanced
Deep-Submicron Transistors
Palkesh Jain, Member, IEEE, Juzer Vasi, Fellow, IEEE, and Rakesh K. Lal, Senior Member, IEEE
Abstract—A systematic evaluation of the single-event-upset
(SEU) reliability of the advanced technologies—high- gate dielectric, elevated source-drain (E-SD), and lateral asymmetric
channel (LAC) MOSFETs is presented for the first time in this
work. Our simulations results gives a clear view of how the short
channel effects in a device governs its SEU reliability and how this
reasoning evolves at the circuit level. It is shown that devices with
worsened short-channel effects (high- gate dielectric transistors)
have a significantly reduced SEU-reliability in contrast to the
devices with controlled short-channel effects (LAC and E-SD) or
even a conventional device.
Index Terms—charge enhancement, elevated source-drain,
high- , lateral asymmetric channel (LAC), single event upset
(SEU), short channel effects, scaling, SRAM.
I. INTRODUCTION
S
INGLE event upsets (SEUs) have been an important reliability concern in the technological development of memories. These are caused when highly energetic particles present
in the natural space environment (e.g., protons, neutrons, alpha
particles, or other heavy ions) strike sensitive regions of a microelectronic circuit [1]. Depending on various factors, the particle
strike may cause no observable effect, a transient disruption of
circuit operation, an erroneous logic state—“upset” or in some
cases, even permanent damage to the device or the circuit.
Recently, many changes in transistor design methodology
have been proposed to keep pace with the aggressively scaled
technology node. However, one of the primary goals for future
development work is to achieve reliability characteristics that
closely match, or exceed, those of conventional transistors.
Therefore, it is the aim of this paper to evaluate some of the
advanced technologies, namely high- , elevated source-drain
(E-SD) and lateral asymmetric channel (LAC) for their SEU
reliability. high- gate dielectric material are likely to be implemented in the Si-CMOS process in the near future to alleviate
the gate current increases associated with aggressive oxide
thickness scaling [2]. On the other hand, E-SD MOSFETs
have long been proposed to achieve ultra shallow junctions (to
minimize short-channel effects, SCEs) and to provide a reliable
low-resistance contact to these junctions [3]. LAC MOSFETs
have shown better suppression over SCEs due to their laterally
Manuscript received January 5, 2005.
P. Jain was with the Department of Electrical Engineering, IIT Bombay. He
is now with the Reliability CAD Group, Texas Instruments India, Bangalore
560093, India (e-mail: [email protected])
J. Vasi is with the Department of Electrical Engineering, IIT Bombay, Powai,
Mumbai 400076, India (e-mail: [email protected]).
R. Lal is with the Department of Electrical Engineering, IIT Bombay, Powai,
Mumbai 400076, India (e-mail: [email protected]).
Digital Object Identifier 10.1109/TDMR.2005.848325
asymmetric channel doping profile and improved current drive
by exploiting velocity overshoot [4].
In the present study, for the first time we have examined
the import of introducing the above changes in the CMOS device-design flow (individually and combinationally) on SEU reliability, both at device as well as circuit level. The reliability of
a device toward SEU is parameterized as a function of: 1) critical
of the SRAM cell made with similar devices; 2)
LET
transient SEU current; and 3) the transient barrier lowering in
the device during the particle strike [5].
The simulation methodology for the various transistors
and circuits used for comparison study is described in the
next section. We briefly review the behavior of conventional
MOSFETs toward SEU and explain the metrics used for
SEU-reliability-evaluation. We then describe in detail about
the impact of high- , E-SD, and halo transistors respectively
on the SEU reliability. We conclude the paper with a brief
discussion on how the combination of such changes affects the
SEU reliability of the device.
II. SIMULATION METHODOLOGY
Various transistors, isolated p-n junctions (for each technology node) and the SRAM cells were designed using the
DIOS process simulator available in the ISE-TCAD suite.
MDRAW tool was used for making the simulation grid for
these structures and the two-dimensional (2-D) device simulations were done in DESSIS, which also allows mixed mode
simulations. Device simulation has been the most important
tool in providing the insight into the SEU phenomenon from the
earliest history of numerical device modeling. We have opted
using 2-D simulations for this work, since much comprehension
has been gained in the past through the use of 2-D simulation
programs [1], [6] and often, three-dimensional (3-D) simulations are necessary only for angular strikes [7]. The identical
electrical-behavior prediction by 2-D and 3-D simulations has
indeed been noted before [6], and it has been shown by others
that 2-D simulations match well with experimental data [8].
For the conventional transistor, a retrograde profile with a low
impurity concentration at the interface and a high concentration
at a finite depth below the interface was used to provide nonuniform channel doping profile. For the high- gate dielectric transistors, simulation results for three permittivity (19, 29, and 39)
are presented, keeping the “effective” gate dielectric thickness
constant (2.5 nm). The spacer dielectric constant is not varied
for above simulations. Two elevated source-drain (E-SD) transistors (with junction depths 25 and 15 nm, respectively) were
made by selective epitaxial growth. For the LAC and double
halo MOSFETs, the boron pocket was realized at a tilt angle
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Fig. 3. Currents produced in the 0.1 m OFF nMOS transistor after the particle
strike of LET 0.2 pC/m.
Fig. 1. Device schematic depicting X-Y directions, location, and angle of the
particle strike.
Fig. 2.
Schematic for resistive load SRAM.
implantation of 9 degrees. For all the comparison studies involving various technologies (high- , E-SD, and LAC), the implant dose was adjusted to achieve an identical threshold voltage
and the transistors had a drawn channel length of 0.1 m (
is around 70 nm).
In order to study the single event effect, the length
of the heavy ion track was made 0.5 m and a particle of LET 0.2 pC/ m (corresponding to an energy of
19.4 MeV-cm /mg) was struck at the drain-gate edge of an
nMOS transistor (Fig. 1), which
OFF
accounts for the worst case since, SEU charge collection is
highly dependent on the initial electric field at the junction,
[1]. The
which is maximum when the node voltage is
radiation charge was Gaussian in space and time (charge generation being maximum at 5 ps), with a characteristic radius
of 0.5 m and a characteristics time of 2 ps. Two-dimensional
device simulations were then performed to extract relevant
information like potential, carrier distribution and also the
currents generated. The channel potential profiles are taken at
distances of 1.5 nm below the interface for various transistors.
To study how the SEU performance of various devices at
transistor level translates at circuit level, a simple, yet relevant
circuit of resistive load SRAM cell (Fig. 2) was chosen. The
modeling of the cross-coupled resistive load SRAM cell was
performed in the device domain and it was constructed using
the process generated nMOS transistors. Even though SEU is
a strong function of the feedback circuitry of the memory, the
trends observed from the results of this circuit can be applicable,
in general, to other memory circuits as well (including the 6 T
SRAM cell) [9], since the actual device response (that of nMOS
transistor) would still be same. The minimum particle energy,
which is able to flip the state of the SRAM cell is called as crit[10]. While calculating
, the SRAM
ical LET
cell was first written with ‘1’ with the help of access transistors,
followed by a particle strike at the drain-gate edge of the OFF
nMOS transistor, as shown in Fig. 2. The particle energy was
increased in steps, till the logic could flip.
III. CONVENTIONAL TRANSISTOR
The sharp current transients that are produced in response to
the particle strike in a 0.1 m OFF
conventional nMOS transistor (CON) are shown in Fig. 3. The
presence of electric field at the drain-bulk junction induces the
separation of the generated carriers, which are then collected
at the contacts, first by drift and then by diffusion (current at
1 ns is about 10 nA, not visible in this plot because of linear
y-scale), leading to such a transient. Fig. 4 shows the potential profile along the channel (Y-direction in Fig. 1) during this
strike at various times. As is evident, just after the strike, the potential barrier collapses and additionally, there is also a barrier
lowering along the source-substrate junction (not shown here).
These events go along with the peaking of the drain current. As
time elapses, the potential barrier recovers to its original profile.
This effect, i.e., lowering of the source-channel potential
barrier, is attributed to the spreading of the electric field because of the particle strike. For channel lengths comparable to
the ion track, the radial field sets up a potential gradient that
encompasses the entire channel region and removes the barrier
at source. The effect was first reported in similar form in [11],
where it was named ion-triggered-channeling. However, we
quantify it as single-event induced barrier lowering, or SEBL
, the change in barrier:
[5], which refers to the ratio of
before and after the strike (at the midpoint along the channel)
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JAIN et al.: SEU RELIABILITY ANALYSIS OF ADVANCED DEEP-SUBMICRON TRANSISTORS
291
TABLE II
SEU-RELIABILITY COMPARISON FOR 0.1 m CON AND BL TRANSISTORS.
VALUES ARE AT LET OF 0.2 pC/m
SEBL AND I
Fig. 4. Potential barrier across the channel (1.5 nm below the interface) of the
0.1 m OFF nMOS transistor, at various time instants (along Y-direction).
TABLE I
CHARGE COLLECTIONS IN CORRESPONDING ISOLATED PN JUNCTIONS
AND OFF nMOS TRANSISTORS. MAXIMUM CHARGE THAT PARTICLE
CAN DEPOSIT IS 100 fC
Fig. 5. Potential barrier across the channel (1.5 nm below the interface) of the
0.1 m OFF nMOS transistors with high- gate dielectrics, before, and after
(t = 5 ps) the strike (along Y-direction).
and , the absolute barrier before the strike (at the same point
of the channel) as seen in Fig. 4. Since SEBL contributes to
the charge collection at the drain, it adds to the “particle-deposited’” charge, thereby resulting in charge enhancement [12].
Table I depicts the charge enhancement caused because of
SEBL across the technologies.
This charge enhancement can eventually cause a reduction
in critical energy required to flip an SRAM cell, and therefore,
SEBL can be a useful metric to evaluate SEU reliability of a
given technology. Above reasoning is verified by our simulation results on a transistor, which was designed to have suppressed SEBL. The said transistor was realized by having an
/cm and energy
extra boron-implant step (of dose
65 keV) just before the threshold adjustment implant step to give
a buried layer beneath the active region. This buried layer (BL)
acts like a shield for electron–hole pairs generated below the
layer [13] and therefore has a diminished SEBL. The co-rela, SEBL, and
is further substantiated
tion between
by the observations from Table II. We now look at the SEU behavior of advanced technologies in following sections.
IV. HIGH-K GATE DIELECTRIC TRANSISTORS
According to the SIA roadmap, CMOS with gate length
below 70 nm will need an oxide thickness of less than 1.5 nm,
which corresponds to two to three layers of silicon dioxide
atoms. With such a thin gate oxide, direct tunneling occurs
resulting in an exponential increase of gate leakage. high- gate
dielectrics have received much attention recently, primarily to
prevent direct gate tunneling. However, high- materials have
been linked to serious reliability concerns, like charge trapping
and increased fringing fields, which results in poor subthreshold
performance and increased short channel effects. Thus, it is
desirable to assess the single-event reliability of high- transistors. In this section, we present our SEU simulation results on
discrete devices and SRAM circuits with different high- gate
dielectric transistors.
ps)
Fig. 5 shows the barriers before and after the strike (
in three different transistors with values of 19, 29, and 39,
respectively. Table III shows the extracted SEBL values and the
transient currents resulting because of SEU for these transistors.
As can be seen from the table, even though high- MOSFETs
show slightly degraded SEBL, the transient currents are significantly larger as compared to conventional device (with similar
threshold voltage and channel length).
The degraded SEU performance of high- transistors, relative to conventional transistors (Table II), can be attributed to
the high fringing fields from gate to source/drain [14], [15]. The
drain electrode in a normal transistor is coupled to the channel
through two paths: gate dielectric and through silicon. Coupling through silicon is normally reduced by controlling the
junction depth, but coupling through the gate dielectric is a
strong function of physical thickness of the gate dielectric. Because of this, more field lines originating from bottom of the
gate electrode, terminate on source/drain region as compared to
those terminating on the channel region. These field lines induce an electric field from source to channel, thereby reducing
the source-channel barrier height. Drain control on the potential barrier is also increased because of fringing, resulting in
a fringing-induced barrier lowering. Therefore, during the particle strike, the already lowered potential barrier (because of
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TABLE III
SEU-RELIABILITY COMPARISON FOR 0.1 m HIGH- DIELECTRIC
VALUES ARE AT LET OF 0.2 pC/m
TRANSISTORS. SEBL AND I
Fig. 6. Device schematic of the E-SD MOSFET.
fringing), gets further lowered. This effect, coupled with degraded short-channel performance of high- gate dielectric transistors results into larger current at the drain contact and smaller
, as shown in Table III. The scaling of the SEU current with gate-dielectric constant can be explained with k-dependence of fringing [15]. It is important to revisit the fact that
since the drift component of the “direct” charge collection depends only on the electrical properties of the struck junction,
high- gate dielectric is not expected to directly impact it. It,
however, strongly impacts the charge enhancement process resulting in increased charge collection.
We have not considered stacked gate dielectric transistors in
this study. It is interesting to note that based on the stack nature,
the transistor can be designed to suppress this abnormalities and
thus, it is expected that stacked high- transistors with SiO
at the interface will have better have SEU reliability than the
normal high- gate dielectric transistor.
V. ELEVATED SOURCE-DRAIN TRANSISTORS
Two critical issues in MOSFET scaling are reduction of short
channel effects and junction leakage. Shortening the lateral extension of junctions (by reducing their depth) ensures moderate
control over short channel effects. At the same time, a silicide
layer needs to be grown on gate, source, and drain to minimize
the parasitic access resistance of these electrodes. However, the
scaling of silicide thickness cannot be carried out in the same
ratio as that of junction depth, and thus, forming of shallow
junctions in a conventional device brings the silicide bottom
very close to the junction, eventually causing severe junction
leakage [16]. E-SD MOSFETs (schematic in Fig. 6) have long
been proved effective in allowing both junction depth reduction
and leakage control. It is reported in [16] that E-SD MOSFETs
are indeed effective in controlling leakage of shallow silicided
junctions, which allows to shift the device intrinsic performance
higher at the same leakage when compared with conventional
MOSFETs. It must also be noted that roll-off characteristics of
E-SD MOSFETs are similar to optimized conventional MOSFETs.
In this section, we report our results on two E-SD MOSFETs with shallow junction depths of 25 nm (E-SD1) and 15 nm
Fig. 7. Potential barrier across the channel (1.5 nm below the interface) of the
0.1 m OFF E-SD MOSFETs, before and after (t = 5 ps) the strike (along
Y-direction). E-SD1/2 refers to 25 nm and 15 nm junction depth, respectively.
TABLE IV
SEU-RELIABILITY COMPARISON FOR 0.1 m ELEVATED SOURCE-DRAIN
VALUES ARE AT LET OF 0.2 pC/m
TRANSISTORS. SEBL AND I
(E-SD2), respectively. Fig. 7 shows the barriers before and after
ps) in two E-SD transistors. Table IV shows
the strike (
the extracted SEBL values and the transient currents resulting
because of SEU for these transistors. As can be seen from the
table, E-SD transistors show significantly reduced SEBL and
also, the transient current resulting because of SEU are substantially lesser when compared to conventional device (with similar
threshold voltage and channel length).
The improved SEBL and SEU performance of E-SD MOSFETs, relative to conventional MOSFETs (Table II), can be attributed to their better control over short channel effects and to
shallow junction depths [17]. It has also been reported in the
literature that source doping plays an important role in charge
collection during SEU [11]. Higher source dopings can support larger drift current and would be capable of sourcing more
carriers during the barrier lowering, assisting SEBL. Thus, in
E-SD MOSFETs, with ultra shallow junctions and low dopings
of the source/drain extensions, it becomes imperative that SEBL
would be suppressed. It is also well known that electric field
at the struck junction is critical in initial drift collection of the
charge. With smaller drain electric fields, E-SD MOSFETs thus
have a lesser charge collection and an overall better SEU performance.
VI. HALO IMPLANTED TRANSISTORS
Of the various technologies, halo implanted MOSFETs
namely, double halo (DH) and single halo, or laterally asymmetric channel (LAC) MOSFETs (schematic in Fig. 8) have
been reported to effectively improve short-channel effects.
It has indeed been noted in [18] that LAC MOSFETs result
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TABLE V
SEU-RELIABILITY COMPARISON FOR 0.1 m HALO TRANSISTORS. SEBL AND
I
VALUES ARE AT LET OF 0.2 pC/m
Fig. 8.
Device schematic and doping profiles in halo MOSFETs.
Fig. 10. Electric Field across the channel (1.5 nm below the interface) of the
0.1 m OFF LAC, Double Halo and conventional nMOS transistor, before and
after (t = 5 ps) the strike (along Y-direction).
Fig. 9. Potential barrier across the channel (1.5 nm below the interface) of the
0.1 m OFF LAC and Double Halo nMOS transistor, before and after (t = 5 ps)
the strike (along Y-direction).
in significant improvement in the output resistance, reduced
DIBL, and channel length modulation and simultaneously,
offer lesser parasitic capacitance when compared with conventional MOSFETs. It also reports that LAC MOSFETs show
roll-up characteristics initially and then show the expected
roll-off, which was attributed to the initial increase in the
average channel dopant concentration with decreasing channel
length. Thus, in context of the reduced short channel effects
in LAC device, it is expected that they will have better SEU
performance. In this section, we report our simulation results
on two halo MOSFETs, double halo (DH), and single halo
or laterally asymmetric channel (LAC) MOSFETs. Both of
the transistors are similar to conventional device in terms of
threshold voltage and drawn channel length.
Fig. 9 shows the barriers before and after the strike (
ps) in two halo transistors. Table V shows the extracted SEBL
values and the transient currents resulting because of SEU for
these transistors. As can be seen from the table, both the halo
transistors show significantly suppressed SEBL and additionally, the LAC transistor shows greatly reduced transient current
(Table V). It can also be seen that both the halo transistors perform better than all other devices in terms of SEBL and SEU.
The impressive SEU and SEBL performance of halo transistors, relative to conventional transistors (Table II), is mainly because of the halo implant. It is well known that because of high
concentration pockets, structures like halo control the drain-induced barrier lowering in a better way [19]. Also, even though
double halo device shows better SEBL as compared to LAC device, the actual SEU current in LAC device is much smaller
compared to DH. This behavior of LAC transistors can be explained from the lateral electric fields. Fig. 10 shows the electric fields before and just after the strike in conventional, DH,
and LAC transistors. The nonuniform doping of the channel
in LAC devices reshapes the lateral electric field. LAC device
shows an increased electric field at the source end and therefore, a decreased field at the drain end, since area under the curve is constant for an applied voltage. As discussed in last
section, the initial drain electric field plays an important role in
determining the charge collection at the junction—higher electric fields supports higher drift collection. Thus, we can see that
DH device, which has large field at the drain end, has higher
transient current when compared to the LAC device. Also, the
higher doping at the source-end in both the halo devices increases the source-channel barrier for carriers.
Hence, with the reshaping of the lateral electric fields (increment at source and reduction at drain), LAC transistors exhibit
excellent SEU and SEBL performance.
VII. DISCUSSION
The strong co-relation between short channel effects of various devices and their SEU vulnerability can be seen from the
results of foregoing sections. However, a technology might use
several of the above mentioned techniques to meet the scaling
requirements and thus, it would be interesting to assess how the
SEU understanding translates. In order to evaluate if these effects add up linearly, we designed an LAC device, which also
had a buried layer (BL) implant. This device, as expected, has
better SEU performance compared to performances of LAC and
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 2, JUNE 2005
BL taken individually. The device exhibited SEBL of 0.6 and
of 0.081. Ref. [20] reports the
the SRAM cell had an
characteristics of the LAC device with high- gate dielectric. It
was noted that the strong coupling of source to the drain via the
high- gate insulator is only slightly affected by channel engineering. Thus, it is expected that the improvement in the SEU
performance of the device brought by LAC might not be enough
to compensate the decremental effects of high- gate dielectric.
It would be interesting to note how the reliability of various
devices changes with altitude, environment, and the angle of
the strike. In the present study, we have not accounted them
(particle strike was always vertically), but it is expected that the
reliability should degrade with all of these. It has indeed been
shown that because of extreme charge enhancement, angular
as much as three times lower than the
tracks can have
vertical strike [7].
VIII. CONCLUSION
In this work, we have evaluated how the SEU reliability of
a device is impacted by introduction of some key changes,
namely high- gate dielectric, elevated source-drain and lateral
asymmetric channel, in the CMOS device design. While these
changes were addressed individually, a qualitative reasoning
was also developed for a device which has a combination of
such changes. It was found that SEU reliability of a device
(being quantified by the corresponding SRAMs
and the transient barrier lowering, SEBL) largely depends on
the short channel effects and that devices with degraded short
channel effects are more prone to SEU. This was attributed
primarily to the severe charge enhancement that arises in
such devices, which leads to increased charge collection and
.
eventually a lowered
Thus, we show that with poor short-channel effects, highdevices are more vulnerable to SEU (20% reduction in critical LET of the SRAM cell when compared with conventional
SRAM). On the other hand, LAC MOSFETs, which demonstrate controlled short-channel effects are more reliable toward
SEU (an improvement of about 50% in critical LET over the
conventional transistors).
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Palkesh Jain (S’02–M’05) received the B.Tech. degree in electrical engineering and M.Tech. Degree in
microelectronics from the Indian Institute of Technology (IIT), Bombay, in 2004. His thesis research
was focused on single event and radiation effects in
CMOS devices.
He is presently working as a Design Engineer with
the Reliability-CAD Group of Texas Instruments
Incorporated, India. His research interests are in the
area of MOS devices and reliability.
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JAIN et al.: SEU RELIABILITY ANALYSIS OF ADVANCED DEEP-SUBMICRON TRANSISTORS
Juzer Vasi (M’73–SM’96–F’05) received the
B.Tech. degree in electrical engineering from the
Indian Institute of Technology (IIT), Bombay, in
1969, and the Ph.D. degree from The Johns Hopkins
University, Baltimore, MD, in 1973.
He taught at The Johns Hopkins University and the
IIT, Delhi, before moving to the IIT, Bombay in 1981,
where he is currently a Professor. He was Head of
the Electrical Engineering Department from 1992 to
1994. His research interests are in the area of CMOS
devices, technology, and design. He has worked on
MOS insulators, radiation effects in MOS devices, degradation, and reliability
of MOS devices, and modeling and simulation of MOS devices.
He is a Fellow of IEEE, IETE, and the Indian National Academy of Engineering.
295
Rakesh K. Lal (M’98) received the B.Tech. degree
in electronics and communication engineering
(Hons.) from the Indian Institute of Technology
(IIT), Kharagpur, India, the M.D. degree in electronics from NUFFIC, The Netherlands, and the
Ph.D. degree in electrical engineering from IIT,
Kanpur, India.
He has been on the faculty of IIT, Bombay, since
1984 and is a Professor of electrical engineering.
He has been actively involved with the engineering
curricula development, has contributed to structural
advancement of undergraduate and graduate programs, and has designed and
taught courses spanning devices to biosensing microsystems. He has been a
Consultant to industry, advising engineering teams on design and prototyping
of computer-aided measurement systems for the power industry, yarn testing,
particle, and cell sizing and characterization, single-cell electroporation, and
sensor electronics. He has given process integration and test advise to an
industry-research-institute consortium for fabricating high-energy radiation
and particle detectors for CERN, and advised the Government of India on
Computer and Electronics policies. His research interests include the physics
and modeling of semiconductor devices and systems, radiation and high-field
effects in MOS, bipolar, and heterostructure devices and circuits, and instrumentation for device characterization.
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