JTAG
N1
P6.0
P6.1
P6.3
P6.5
P6.6
P6.7
P6.10
P6.15
129 WUP0/P6.0
130 WUP1/P6.1
132 WUP3/P6.3
134 WUP5/P6.5
135 WUP6/P6.6
136 WUP7/P6.7
139 WUP8/P6.10
144 WUP9/P6.15
57 WUP16/P2.10
58 WUP17/P2.11
P2.10
P2.11
P1.4
P1.5
WUP14/RDI1/P2.9 56
TDO1/P2.8 55
INT8/RDI2/P5.10 120
INT9/TDO2/P5.11 121
WUP2/RDI3/P6.2 131
WUP4/TDO3/P6.4 133
27 P1.4
28 P1.5
(Projekt)
Datum 10.03.2006
Bearbeitet M.Schindler
Geprueft
Frei gegeben
Ersetzt
STR730 Eval-Board
Ersetzt durch
C6
P4.5
P4.4
5V+
P6.11
P6.12
P6.13
P6.14
R2
2.2k
N7
STM1001L
P5.1
P5.0
1 RST
P4.15
P4.14
S1
P5.7
P5.6
P5.5
P5.4
VCC 2
VSS
3
5V+
M1
Switch_TACT
X6
GND
Reset
P6.8
P6.9
M0
2
1
2
1
1x2p
P2.9
P2.8
X5
1x2p
P5.10
P5.11
GND
P6.2
P6.4
P2.14
P2.15
P4.6
P4.7
WUP19/SCL1/P4.6 100
SDA1/P4.7 101
P5.8
P5.9
P5.12
P5.13
P5.14
P5.15
INT6/P5.8 118
INT7/P5.9 119
INT10/P5.12 122
INT11/P5.13 123
INT12/P5.14 124
INT13/P5.15 125
INT14/P2.12 59
INT15/P2.13 60
Hitex Development Tools GmbH
Greschbachstrrasse 12
D-76229 Karlsruhe
C7
P2.1
P2.2
WUP15/SCL0/P2.14 61
SDA0/P2.15 62
(Adresse)
GND
P1.14
P1.15
P2.12
P2.13
STR730FZ2T7
Funktionsstand
Erzeugnisstand
Unterlagenstand
15pF
Port_6
Port_5
GND
10k
WUP10/RDI0/P6.8 137
TDO0/P6.9 138
GPIO PORT
Port_4
Port_2
Port_1
P2.0
P2.3
P2.4
P2.5
P2.6
P2.7
MISO0/P6.11 140
MOSI0/P6.12 141
WUP11/SCK0/P6.13 142
SS0/P6.14 143
MISO2/P5.7 117
MOSI2/P5.6 116
SCK2/WUP23/P5.5 115
SS2/P5.4 114
1.5M
15pF
GENERAL
JTAG
TIMER
PWM
R17
CAN2RX/WUP18/P4.5 98
CAN2TX/P4.4 99
MISO1/P5.1 111
MOSI1/P5.0 110
SCK1/WUP22/P4.15 109
SS1/P4.14 108
NC
GND
R5
67 AIN0/P3.0
68 AIN1/P3.1
69 AIN2/P3.2
70 AIN3/P3.3
71 AIN4/P3.4
72 AIN5/P3.5
73 AIN6/P3.6
74 AIN7/P3.7
77 AIN8/P3.8
78 AIN9/P3.9
79 AIN10/P3.10
80 AIN11/P3.11
81 AIN12/INT2/P3.12
82 AIN13/INT3/P3.13
83 AIN14/INT4/P3.14
84 AIN15/INT5/P3.15
JRST
JTDI
JTMS
JTCK
JTDO
1
G1
8.000MHz
3
1.3M
10k
R4
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.14
P3.15
R1
1nF
P5.2
P5.3
2
4
C5
INTERRUPT
CAN0-2
P4.0
P4.1
P4.2
P4.3
P4.8
P4.9
P4.10
P4.11
P4.12
P4.13
SPI0
GND
RSTIN
NC
WUP12/CAN0RX/P1.14 37
CAN0TX/P1.15 38
WUP13/CAN1RX/P2.1 40
41
CAN1TX/P2.2
SPI1
P1.8
PWM0/P2.0 39
PWM1/P2.3 42
PWM2/P2.4 43
PWM3/P2.5 44
PWM4/P2.6 45
46
PWM5/P2.7
SPI2
S2
Switch_TACT
P1.0
P1.1
P1.2
P1.3
P1.6
P1.7
P1.8
P1.9
P1.10
P1.11
P1.12
P1.13
JTRST 87
JTDI 88
JTMS 89
JTCK 90
JTDO 91
UART0
R3
10k
5V+
RSTIN
TEST 63
VBIAS 64
ADC
Port_6
RSTIN
XTAL1 52
XTAL2 53
UART1
Port_4
Port_5
RSTIN 48
UART2
Port_3
M0 47
M1 49
UART3
Port_2
1 OCMPB2/P0.0
2 OCMPA2/P0.1
3 ICAPA2/P0.2
4 ICAPB2/P0.3
7 OCMPA5/P0.4
8 OCMPB5/P0.5
9 ICAPA5/P0.6
10 ICAPB5/P0.7
11 OCMPA6/P0.8
12 OCMPB6/P0.9
13 OCMPA7/P0.10
14 OCMPB7/P0.11
17 ICAPA3/P0.12
18 ICAPB3/P0.13
19 OCMPB3/P0.14
20 OCMPA3/P0.15
21 OCMPA4/P1.0
22 OCMPB4/P1.1
23 ICAPB4/P1.2
24 ICAPA4/P1.3
29 OCMPB1/P1.6
30 OCMPA1/P1.7
31 OCMPA0/INT0/P1.8
32 OCMPB0/INT1/P1.9
33 ICAPB0/WUP28/P1.10
34 ICAPA0/WUP29/P1.11
35 ICAPA1/WUP30/P1.12
36 ICAPB1/WUP31/P1.13
94 ICAPA7/WUP24/P4.0
95 ICAPB7/WUP25/P4.1
96 ICAPA8/WUP26/P4.2
97 ICAPB8/WUP27/P4.3
102 OCMPA8/P4.8
103 ICAPB6/P4.9
104 ICAPA6/WUP20/P4.10
105 OCMPB8/P4.11
106 ICAPA9/WUP21/P4.12
107 ICAPB9/P4.13
112 OCMPA9/P5.2
113 OCMPB9/P5.3
I2C0
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
Port_1
I2C1
Port_0
uController
BMK-Projekt-Nr. ent207.00-y1
BMK-Leiterplatten-Nr. 15-2019-1
M1 M0
Default
Boot Mode
Memory Mapping
0
0
User Boot mode 1
FLASH sector B0F0 mapped at 0h
0
1
User Boot mode 2
FLASH sector B0F0 mapped at 0h
BOF1+System Mem. not accessable
1
0
System Memory
SystemMemory mapped at 0h
1
1
Reserverd
--
(Titel d. Seite)
(Zeichnungs-Nr.)
37.17.0008.0
Uhrzeit
Datum
Seite
15:57:16
10.03.2006 Gesamt
1
6
TP_VIN
GND
GND
GND
GND
76 VDDA
VSSA 75
6 VDD1
15 VDD2
26 VDD3
50 VDD4
VSS1 5
VSS2 16
VSS3 25
VSS4 51
VSS9 54
VSS5 65
VSS6 86
VSS7 92
VSS8 127
66 VDD5
85 VDD6
93 VDD7
128 VDD8
C44
C14
V18 126
GND
5V+
N1
100nF
C15
100nF
C1
TP_GND
100nF
TP4
5V+
GND
1
10uF/16V
C13
BYM10-1000
Power
C2
1A
5V+
N8
LD1085V50
3 IN
OUT 2
100uF/16V
C8
V1
TP3
TP2
TP_GND
+
-
F1
100uF/16V
TP_5V
7V - 9V
0,1A
1
2
3
1uF/10V
TP1
X1
STR730FZ2T7
GND
R18
B
V5
BC847B
22k
E
R38
C3
R39
47k
100uF/16V
5V_OK
C
GND
5V+
10nF
C43
10nF
C38
C22
10nF
GND
10nF
C4
100uF/16V
RSTIN
V2
LED gruen
C11
10uF/16V
C9
10uF/16V
GND
5V+
820R
5V+
5V+
C37
GND
GND
5V+
15 GND
GND
ST3232
N6
VS+ 8
4 GND
VCC 20
C33
C30
GND
C29
CHASSIS1
N5
VCC 16
100nF
N2
100nF
100nF
C41
C42
100nF
C36
100nF
C39
100nF
C40
100nF
Z1
47R
100nF
5V+
10 GND
LM75
74AC244
GND
Funktionsstand
Erzeugnisstand
Unterlagenstand
(Projekt)
Datum 10.03.2006
Bearbeitet M.Schindler
Geprueft
Frei gegeben
Ersetzt
STR730 Eval-Board
Ersetzt durch
(Adresse)
Hitex Development Tools GmbH
Greschbachstrrasse 12
D-76229 Karlsruhe
Power
BMK-Projekt-Nr. ent207.00-y1
BMK-Leiterplatten-Nr. 15-2019-1
(Titel d. Seite)
(Zeichnungs-Nr.)
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Uhrzeit
Datum
Seite
15:57:16
10.03.2006 Gesamt
2
6
D-Sub9_Female
GND
H2
Port_6
X8
1x2p
NC
2
1
Port_2
P6.9
P2.8
330nF/25V
TX_enable
C45
TX0
TX1
6 V-
V+ 2
1 C1+
C2+ 4
3 C1-
47nF
RX0
RX1
H1
C48
330nF/25V
C2- 5
11 T1IN
10 T2IN
12 R1OUT
9 R2OUT
T1OUT 14
T2OUT 7
R1IN 13
R2IN 8
SERIAL_1
2
6
1
GND
GND
X7
1x2p
2
1
NC
N2
C47
5
9
4
8
3
7
X15
C46
330nF/25V
R24
R25
100R
100R
ST3232
D-Sub9_Female
GND
2
1
X9
1x2p
H2
NC
P6.8
P2.9
X10
1x2p
2
1
RS232
RX_enable
NC
SERIAL_2
2
6
1
H1
X16
Port_1
Port_2
5V+
5V+
1
2
10k
R15
10k
R7
R27
X3
X2
5
9
4
8
3
7
2
6
1
H2
D-Sub9_Male
RX/TX_enable
GND
H2
GND
H1
GND
GND
TERMINATION
CAN 1
(Projekt)
NC
L9615
GND
TERMINATION
Datum 10.03.2006
Bearbeitet M.Schindler
Geprueft
Frei gegeben
Ersetzt
C_H 7
C_L 6
RX1 5
ASC 8
120R
H2
D-Sub9_Male
RX/TX_enable
100nF
1x2p
C34
6
1
1
2
H2
5
9
4
NC
8
3
7
2
6
1
NC
N4
3 VS
1 TX0
4 RX0
2 GND
GND
P2.2
P2.1
1x2p
GND
GND
7
2
1x2p
R9
10k
R26
L9615
GND
120R
NC
1x2p
1x2p
1
2
X11
C_H 7
C_L 6
RX1 5
ASC 8
H1
NC
X14
C32
100nF
1x2p
2
1
X12
N3
3 VS
1 TX0
4 RX0
2 GND
GND
P1.15
P1.14
5
9
4
8
3
2
1
5
9
4
NC
8
3
7
2
6
1
NC
NC
X18
5V+
H1
1
2
H1
X13
R10
10k
X17
5V+
Funktionsstand
Erzeugnisstand
Unterlagenstand
5
9
4
8
3
7
CAN 2
STR730 Eval-Board
Ersetzt durch
(Adresse)
Hitex Development Tools GmbH
Greschbachstrrasse 12
D-76229 Karlsruhe
RS232 / CAN0/ CAN1
BMK-Projekt-Nr. ent207.00-y1
BMK-Leiterplatten-Nr. 15-2019-1
(Titel d. Seite)
(Zeichnungs-Nr.)
37.17.0008.0
Uhrzeit
Datum
Seite
15:57:16
10.03.2006 Gesamt
3
6
JTAG
5V+
5V+
10k
R11
10k
R12
R6
10k
5V+
JRST
JTDI
JTMS
JTCK
Port_2
R23
JTDO
RSTIN
100R
NC
DBGACK
P2.0
X19
2
4
6
8
10
12
14
16
18
20
X17 Jumper
3-4
Normal Operation
X
JTAG-Debugger
--
2x10p
10k
R22
R28
0R_n.b.
R8
5V+
10k
1x2p
2
1
X32
5V+
1
3
5
7
9
11
13
15
17
19
JTAG CONNECTOR
R31
B
C
B
V4
BC846B_n.b.
E
V3
BC846B_n.b.
C49
C
GND
10nF_n.b.
R32
10k_n.b.
47k_5%_n.b.
R30
R29
22k_n.b.
22k_n.b.
GND
JTAG INTERFACE
E
GND
Funktionsstand
Erzeugnisstand
Unterlagenstand
(Projekt)
Datum 10.03.2006
Bearbeitet M.Schindler
Geprueft
Frei gegeben
Ersetzt
STR730 Eval-Board
Ersetzt durch
GND
GND
(Adresse)
Hitex Development Tools GmbH
Greschbachstrrasse 12
D-76229 Karlsruhe
JTAG INTERFACE
BMK-Projekt-Nr. ent207.00-y1
BMK-Leiterplatten-Nr. 15-2019-1
(Titel d. Seite)
(Zeichnungs-Nr.)
37.17.0008.0
Uhrzeit
Datum
Seite
15:57:16
10.03.2006 Gesamt
4
6
Port_0
Port_1
Port_2
Port_3
Port_4
Port_5
Port_6
P6.0
P6.2
P6.4
P6.6
P6.8
P6.10
P6.12
P6.14
1
3
5
7
9
11
13
15
X25
2
4
6
8
10
12
14
16
P6.1
P6.3
P6.5
P6.7
P6.9
P6.11
P6.13
P6.15
P5.0
P5.2
P5.4
P5.6
P5.8
P5.10
P5.12
P5.14
2x8p_n.b.
1
3
5
7
9
11
13
15
X26
2
4
6
8
10
12
14
16
P5.1
P5.3
P5.5
P5.7
P5.9
P5.11
P5.13
P5.15
P4.0
P4.2
P4.4
P4.6
P4.8
P4.10
P4.12
P4.14
1
3
5
7
9
11
13
15
2x8p_n.b.
X24
2
4
6
8
10
12
14
16
P4.1
P4.3
P4.5
P4.7
P4.9
P4.11
P4.13
P4.15
2x8p_n.b.
PORT_6
1
3
5
7
9
11
13
15
X20
2
4
6
8
10
12
14
16
P3.1
P3.3
P3.5
P3.7
P3.9
P3.11
P3.13
P3.15
2x8p_n.b.
(Projekt)
Datum 10.03.2006
Bearbeitet M.Schindler
Geprueft
Frei gegeben
Ersetzt
STR730 Eval-Board
Ersetzt durch
P2.0
P2.2
P2.4
P2.6
P2.8
P2.10
P2.12
P2.14
1
3
5
7
9
11
13
15
X22
2
4
6
8
10
12
14
16
P2.1
P2.3
P2.5
P2.7
P2.9
P2.11
P2.13
P2.15
P1.0
P1.2
P1.4
P1.6
P1.8
P1.10
P1.12
P1.14
2x8p_n.b.
PORT_4
PORT_5
Funktionsstand
Erzeugnisstand
Unterlagenstand
P3.0
P3.2
P3.4
P3.6
P3.8
P3.10
P3.12
P3.14
1
3
5
7
9
11
13
15
X23
2
4
6
8
10
12
14
16
P1.1
P1.3
P1.5
P1.7
P1.9
P1.11
P1.13
P1.15
2x8p_n.b.
PORT_2
Hitex Development Tools GmbH
Greschbachstrrasse 12
D-76229 Karlsruhe
PORTS
BMK-Projekt-Nr. ent207.00-y1
BMK-Leiterplatten-Nr. 15-2019-1
1
3
5
7
9
11
13
15
X21
2
4
6
8
10
12
14
16
P0.1
P0.3
P0.5
P0.7
P0.9
P0.11
P0.13
P0.15
2x8p_n.b.
PORT_0
PORT_3
(Adresse)
P0.0
P0.2
P0.4
P0.6
P0.8
P0.10
P0.12
P0.14
PORT_1
(Titel d. Seite)
(Zeichnungs-Nr.)
37.17.0008.0
Uhrzeit
Datum
Seite
15:57:16
10.03.2006 Gesamt
5
6
5V+
Port_3
Port_2
C35
10nF
1x2p
X4
1k
R21
GND
RANGE 0V to +5V (ADC)
1k
E
R37
EN_DISP1
V7
BCV46
B
3.3k
C
R36
P0.9
C50
5V+
R20
P0.8
EN_DISP2
5V+
E
B1
V8
BCV46
B
3.3k
PLUS P
MINUS M
C
F/QMB-111P
10k
R44
R46
R48
R50
120R
120R
120R
120R
2
1
X31
1x2p
DISPLAY
ENABLE
GND
(Projekt)
10R
1k
10k
N5
P2.15
P2.14
P2.13
1 SDA
2 SCL
3 O.S.
A0 7
A1 6
A2 5
LM75
GND
SA39-11EWA
P2
TEMPERATURE SENSOR
USER_DISPLAY
Datum 10.03.2006
Bearbeitet M.Schindler
Geprueft
Frei gegeben
Ersetzt
10k
8
A1+
R13
3
A0+
R14
10 a
9b
7c
5d
4e
2f
1g
6 DP
10k
5V+
120R
120R
120R
120R
R16
R49
R47
R45
R43
1x2p
e
f
g
DP
1
2
9
2Y1
2Y2 7
2Y3 5
2Y4 3
1
2
11 2A1
13 2A2
15 2A3
17 2A4
74AC244
Funktionsstand
Erzeugnisstand
Unterlagenstand
R19
1
2
2G
1x2p
X29
P0.4
P0.5
P0.6
P0.7
GND
SPEAKER
SA39-11EWA
P1
N6
19
V6
BC847B
E
1x2p
a
b
c
d
B
3.3k
X27
2 1A1 1Y1 18
4 1A2 1Y2 16
6
14
1A3 1Y3
8
12
1A4 1Y4
74AC244
C
R35
P2.3
8
A1+
1
2
P0.0
P0.1
P0.2
P0.3
1G
3
A0+
1x2p
X30
1
10 a
9b
7c
5d
4e
2f
1g
6 DP
X28
R40
R34
5V+
N6
100nF
CCW
1
2
ADC
R33
10k
P3.0
W
CW
Port_0
STR730 Eval-Board
Ersetzt durch
(Adresse)
Hitex Development Tools GmbH
Greschbachstrrasse 12
D-76229 Karlsruhe
DISPLAY,Peripherals
BMK-Projekt-Nr. ent207.00-y1
BMK-Leiterplatten-Nr. 15-2019-1
(Titel d. Seite)
(Zeichnungs-Nr.)
37.17.0008.0
Uhrzeit
Datum
Seite
15:57:16
10.03.2006 Gesamt
6
6