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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 7, JULY 2010
Study of P/E Cycling Endurance Induced
Degradation in SANOS Memories
Under NAND (FN/FN) Operation
C. Sandhya, Student Member, IEEE, Apoorva B. Oak, Nihit Chattar, Udayan Ganguly, C. Olsen, S. M. Seutter,
L. Date, R. Hung, Juzer Vasi, Fellow, IEEE, and Souvik Mahapatra, Senior Member, IEEE
Abstract—Program/Erase (P/E) cycling endurance in
poly-Si/Al2 O3 /SiN/SiO2 /Si (SANOS) memories is systematically
studied. Cycling-induced trap generation, memory window
(MW) closure, and eventual stack breakdown are shown to be
strongly influenced by the material composition of the silicon
nitride (SiN) charge trap layer. P/E pulsewidth and amplitude,
as well as starting program and erase flatband voltage (VFB )
levels (therefore the overall MW), are shown to uniquely impact
stack degradation and breakdown. An electron-flux-driven anode
hole generation model is proposed, and trap generation in both
SiN and tunnel oxide are used to explain stack degradation
and breakdown. This paper emphasizes the importance of SiN
layer optimization for reliably sustaining large MW during P/E
operation of SANOS memories.
Index Terms—Charge trap flash (CTF), endurance, erase, impact ionization, memory window, program, retention, SANOS,
silicon nitride (SiN), SONOS.
I. I NTRODUCTION
D
EMAND due to the growth of portable electronics in
recent years has made NAND flash memories [1] scale
faster than logic [2]. So far, scaling has largely been successful due to advancements made in lithography, process optimization, and software-level system management (e.g., error
correction code, program/verify algorithms, and block redundancy) [3], [4]. However, it is anticipated that somewhere
beyond the 2X node, scaling conventional floating-gate (FG)
flash memories may be challenging due to the difficulty in
scaling tunnel oxide (TO) and interpoly dielectric (due to
susceptibility to single pin-hole defects) and increased cell-tocell interference [1], [5]–[7]. Charge trap flash (CTF) memories
[e.g., poly-Si/Al2 O3 /SiN/SiO2 /Si (SANOS)] are the potential
alternatives to FG flash with better resilience to defects in the
TO and blocking dielectric (BD), planar structure with reduced
Manuscript received September 9, 2009; revised March 29, 2010; accepted
April 1, 2010. Date of publication May 18, 2010; date of current version
June 23, 2010. This work was supported in part by the Global Research
Collaboration (GRC) from the Semiconductor Research Corporation (SRC) and
in part by the Department of Information Technology, Government of India,
through the Centre of Excellence in Nanoelectronics. The review of this paper
was arranged by Editor S. Deleonibus.
C. Sandhya, A. B. Oak, N. Chattar, J. Vasi, and S. Mahapatra are with
the Centre of Excellence in Nanoelectronics and Department of Electrical
Engineering, Indian Institute of Technology Bombay, Mumbai 400 076, India
(e-mail: [email protected]).
U. Ganguly, C. Olsen, S. M. Seutter, L. Date, and R. Hung are with the
Applied Materials, Santa Clara, CA 95054-3299 USA.
Digital Object Identifier 10.1109/TED.2010.2048404
gate stack height, and hence reduced cell-to-cell coupling and
fully CMOS compatible process flow with ease of integration
[5]–[7]. However, similar to FG flash, CTF memories also
suffer from reliability issues associated with trap generation in
the gate stack during program/erase (P/E) cycling, e.g., reduction in memory window (MW), stress-induced leakage current
(SILC)-assisted charge loss, and random telegraph noise [8]–
[10]. These issues are further aggravated for multiple-level cell
(MLC) operation due to higher P/E biases and also as the
distinction between different threshold voltage (VT ) levels becomes finer [11]–[13]. Although FG flash reliability has largely
been associated with trap generation in TO bulk and Si/SiO2
interface [14], [15], the same cannot be said for CTF devices
due to the presence of multiple dielectrics and interfaces. Trap
generation and breakdown of SANOS stacks under bipolar
pulsed stress must be understood to develop CTF memory that
can sustain large MW under P/E cycling as necessary for MLC
operation.
It has been shown that endurance degradation strongly depends on SiN composition [16] and processing conditions
[17]. Larger degradation in more N-rich SiN films has been
attributed to higher electric fields required for P/E to achieve a
particular MW due to a smaller number of charge traps [16].
Erase is slow in CTF memories; thus, the erase step of the
P/E cycle needs higher electric fields and is identified to be
crucial in determining the endurance degradation. Therefore,
technological improvement of erase efficiency can directly be
linked to reducing degradation under P/E endurance stress [18].
Determining the possible location of trap generation in the
gate stack is also critical for understanding and minimizing
endurance degradation [19]–[21]. In both FG and CTF memories, postcycling MW degradation has been associated with
TO degradation [4], [22], [23]. In CTF memories, the impact of
P/E cycling on SiN/BD interface degradation and improvement
in performance and reliability with engineered bandgap storage
layers [24]–[26] has also been discussed. Trap-to-trap tunneling
is reported to be a significant postcycling retention charge
loss mechanism, in addition to thermal emission and direct
tunneling induced leakage [27]. Additional degradation may
also appear in the dielectric SiN layer in CTF memories. Understanding the impact of P/E endurance on the reliability and
performance of CTF memories with varying SiN compositions
[28] (and therefore the interaction of different interfaces) is
essential for improving device operation lifetime. However, this
area is largely unexplored and requires careful analysis.
0018-9383/$26.00 © 2010 IEEE
SANDHYA et al.: P/E-CYCLING-ENDURANCE-INDUCED DEGRADATION IN SANOS MEMORIES
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TABLE I
SPLIT TABLE FOR THE SANOS DEVICES. THE FLOW RATIO AND RI ARE
PROVIDED FOR DISTINGUISHING THE DISTINCT SiN COMPOSITIONS
Fig. 1. Schematic and energy-band diagram of SANOS capacitors with p+
S/D implants for supplying minority charge carriers. The devices have RTO TO
with a thickness of 3–6 nm, a 6-nm-thick LPCVD SiN of varying composition,
and 12–20-nm-thick CVD Al2 O3 as BD.
In this paper, the reliability of SANOS gate stacks with
different SiN composition, TO, and BD thicknesses is critically
examined under P/E cycling endurance stress. First, it is shown
that P/E-cycling-induced trap generation that leads to MW
closure and maximum achievable MW before electrical stack
breakdown (loss of programmability) is a strong function of
the SiN-trap-layer composition. Second, several experimental
factors are shown to impact MW closure and stack breakdown
during P/E cycling and are systematically explored. The role
of P/E pulsewidth, pulse amplitude, program, and erase VFB
levels (hence the overall MW) in determining the number
of P/E cycles sustained by CTF devices with different SiN
compositions are investigated. Third, unlike FG flash whose
reliability is mainly dictated by the TO quality, it is shown
that CTF memory reliability is governed by trap generation in
both TO and SiN layers, although that in BD has been found
to be low and requires further work. Fourth, the impact SiN
composition on postcycling retention is explored. Finally, SiNcomposition-dependent CTF stack degradation and breakdown
are qualitatively explained by invoking an electron-flux-driven
anode hole generation model. The importance of the SiN layer
and difference in reliability mechanism of CTF compared to FG
[29] flash memories is clearly demonstrated.
II. D EVICE D ETAILS
Electrical characterization was conducted on large-area
(100 × 100 μm) SANOS capacitors, as schematically shown
in Fig. 1. The devices have n-substrate and p+ S/D diffusion
ring for providing the minority carriers during inversion. Gate
stacks consist of a rapid thermal oxidation (RTO)-based tunnel
SiO2 with a thickness of 4–6 nm, low-pressure chemical vapor
deposition (LPCVD) SiN charge storage layer with a thickness
of 6 nm, chemical vapor deposition (CVD) Al2 O3 BD with
a thickness of 12–15 nm, and n+ poly-Si gate. Composition
of the SiN trap layer was controlled by varying Si2 H6 and
NH3 gas flow ratio during LPCVD deposition at a temperature
of 650 ◦ C [28], [30]. Table I summarizes the device details
with the flow ratios and measured refractive index (RI) of
different gate stacks. Note that the Si, N, and H contents of
SiN vary with the flow ratio, yielding different RI for different
LPCVD SiN deposition conditions, as explained in [30]. The
SiN films used in this paper show RI of 1.97 (strongly N
rich, hereafter referred to as N+ SiN) to 2.13 (strongly Si
rich, referred to as Si+ SiN). The RI of stoichiometric SiN is
known to be ∼2.01 [31]. Note that, although N1 (RI = 1.97)
and N2 (RI = 2.006) have rather close RI values, Rutherford
backscattering spectroscopy (RBS) shows ∼2% more Si and
∼1% less N for N2 compared to N1 stacks [30]. The Al2 O3 BD
is annealed at 1050 ◦ C for 15 s in N2 ambient. High-frequency
capacitance voltage (HFCV) measurements at 100 kHz
were performed to estimate the flatband voltage (VFB ) shifts
during P/E, cycling, and retention. The devices show negligible
CV skewing during program, erase, retention, and endurance
measurements; therefore, the VFB shifts would be identical to
VT shifts and can be attributed to the charge trapped in the
dielectric gate stack. The SiN composition variation is studied
on devices with identical TO, SiN, and BD thickness (4 nm/
6 nm/12 nm) with total stack equivalent oxide thickness (EOT)
in the range of 12.0 ± 0.3 nm. The initial VFB of all devices
with similar EOTs and varying SiN compositions was found
to be in a narrow range of −0.1 V to 0.2 V. The TO and
BD thickness variation has been studied on N2-type SiN with
identical SiN layer thickness of 6 nm.
III. R ESULTS AND D ISCUSSION
A. Effect of SiN Composition on P/E Performance
Unlike FG flash where charges are stored as free carriers
in the poly-Si FG, CTF devices rely on the trapping and
detrapping of charges (electron trapping/hole detrapping for
program, electron detrapping/hole trapping for erase) during
P/E operation. It has been shown that the composition of the
SiN trap layer significantly affects electron/hole trap properties
and, hence, P/E performances. The electron trap depth reduces,
and the hole trap depth increases as the SiN layer is changed
from N+ to Si+ [28], [30]. Consequently, electron/hole trapping/detrapping efficiencies would vary with the Si:N ratio of
the SiN layer, which will determine how much charge would
flow through the gate stack during P/E pulses (and eventually
govern trap generation and reliability) to obtain a particular
value of program and erase states and, hence, a particular
magnitude of the overall MW.
To study the impact of SiN composition, devices were programmed and erased, respectively, using incremental step pulse
programming (ISPP) [3] and incremental step pulse erasing
(ISPE) [30] methods. Program and erase pulsewidths were
kept fixed at 200 μs and 20 ms, respectively, with 0.3-V
pulse increment steps. ISPP was performed on fresh devices,
whereas ISPE was performed after programming the devices to
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 7, JULY 2010
Fig. 2. VFB shifts due to ISPP (LHS; 0.3-V step, pulsewidth of 200 μs) and
ISPE (RHS; 0.3-V step, pulsewidths of 20 ms) for varying SiN compositions
(N1–N4).
VFB = 5.5 V. Fig. 2 shows measured ISPP and ISPE characteristics and presents clear evidence of the impact of SiN
composition on the P/E performance of SANOS stacks. N1 and
N2 (N+ SiN) stacks show higher saturation level compared to
N3 and N4 (Si+ SiN), the differences being more apparent
at higher program VG . Lower program saturation level for
Si+ SiN has been explained by the increased emission of
charges trapped in shallow energy levels, resulting in reduced
trapping efficiency [32]. On the other hand, the overerase capability (natural VFB ∼ 0 V for all stacks) progressively increases
from the most N+ SiN (N1) to the most Si+ SiN (N4). This
case is due to larger hole trap depth for Si+ SiN, as explained
in [30]. Moreover, the two-slope ISPE characteristics observed
in all stacks (see [30] for details) demonstrate different physical regimes of charge conduction—electrons backtunneling to
substrate at low erase VG (VGE ) and holes tunneling into SiN
at higher VGE [33]. The ISPE for N+ SiN indicates that erase
at normal VGE is dominated by electron detrapping rather than
hole trapping [34] due to significantly lower hole trap density.
On the other hand, erase in Si+ SiN shows both electron detrapping and hole trapping, which also explains overerase observed
in these devices. Note that the P/E saturation levels obtained
from ISPP and ISPE are in agreement with trends obtained
using constant voltage P/E transient [28], [30]. As we will show
later, the magnitude of hole trapping during erase plays a crucial
role in erase VFB and overall MW degradation during cycling.
Therefore, unlike FG flash, the composition of the charge trap
layer of CTF devices plays a critical role in determining the
endurance degradation under different experimental conditions
and is presented next.
B. Effect of SiN Composition on Cycling Endurance
Fig. 3 shows P/E cycling results on devices with different
SiN composition. Cycling under identical program (VGP ) and
erase (VGE ) biases and program (tP ) and erase (tE ) times
[see Fig. 3, left-hand side (LHS)] shows clear SiN composition
dependence of P/E VFB levels, overall MW, and the extent of
erase-state degradation. Strong N+ SiN (N1) shows maximum
program VFB level while erasing, incompletely yielding a small
starting MW. Incomplete erase progressively builds up with
P/E cycling and results in MW closure. Moderate N+ SiN
(N2) shows better erase, higher initial MW, and lower MW
Fig. 3. P/E endurance measured at constant P/E bias conditions (LHS) and
P/E of +16 V/−16 V with time varied to achieve identical starting MW (RHS)
for different SiN compositions. All stacks have similar EOT.
Fig. 4. Dependence of BD thickness on P/E cycling, with P/E biases and
duration adjusted to achieve identical starting TO field and MW (LHS), and
identical starting TO field and constant stored charge (RHS).
degradation than N1. In contrast, Si+ SiN (N3, N4) stacks
show complete erase and largest starting MW that is maintained
through 104 P/E cycles. Comparison of P/E cycling endurance
at identical starting MW [see Fig. 3, right-hand side (RHS)],
which was achieved by using much longer tE for N+ SiN,
shows reemergence of erase VFB degradation primarily for
N+ SiN stacks at higher P/E cycles. However, Si+ SiN stacks
again show negligible erase VFB and overall MW degradation.
TO and BD quality, and thickness and stack EOT are the same
across all splits; therefore, Fig. 3 uniquely highlights the SiNcomposition-dependent cycling endurance of CTF memories.
To understand erase VFB degradation during cycling, Fig. 4
shows the P/E cycling results in N2 (N+ SiN) stacks with different BD thickness but identical TO and SiN layer thickness.
VGP and VGE were adjusted to have identical TO field during
P/E cycling, whereas tP and tE were adjusted to have identical
starting MW (see Fig. 4, LHS) or identical charge trapping
(see Fig. 4, RHS) for all stacks. Note that the charge centroid
position has been identified to be at the SiN/Al2 O3 interface for
these stacks [30]. Therefore, identical starting MW is achieved
in thicker BD stacks at reduced charge trapping, whereas identical charge trapping results in larger starting MW for thicker BD.
The extent of erase VFB degradation is smaller for thicker BD
when cycled under identical MW and is clearly due to lower
SANDHYA et al.: P/E-CYCLING-ENDURANCE-INDUCED DEGRADATION IN SANOS MEMORIES
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Fig. 5. Comparison of P/E cycling at identical MW for 6-nm N2-type SiN
(12 nm BD) with varying TO thicknesses. P/E biases are adjusted to achieve
identical fields across TO.
charge trapping, whereas all stacks show similar erase VFB
degradation when cycled under similar charge trapping. Fig. 4
clearly shows that erase VFB degradation in N+ SiN during P/E
cycling is due to gradual buildup of trapped electrons, as more
trapping eventually leads to higher charge accumulation and
higher erase VFB degradation, and vice versa. Moreover, note
that the spacing between program VFB levels for different BD
thickness remains constant when cycled under identical charge
trapping condition (see Fig. 4, RHS). Therefore, it can be
inferred that trapped electron buildup during cycling essentially
takes place at the SiN/Al2 O3 interface and that no significant
trapping takes place in the bulk of the Al2 O3 BD. Note that,
for significant BD trapping, a thicker BD will show a larger
program VFB shift during P/E cycling due to larger trapping
volume, contrary to the observed result. Negligible BD trapping
is attributed to the robustness of Al2 O3 used in these stacks.
Finally, as discussed in Fig. 2, Si+ SiN stacks show better
erase due to significant hole trapping and, therefore, low erase
VFB degradation with P/E cycling. The magnitude of trapped
electron buildup (if any) during cycling in Si+ SiN is difficult
to quantify due to the presence of significant hole trapping in
these stacks.
It is evident in Fig. 4 that erase VFB degradation during
P/E cycling is driven by electron trapping, which, in turn, is
related to charge fluence. As further verification, Fig. 5 shows
P/E cycling results in N2 (N+ SiN) stacks with different TO
thickness but identical BD and SiN layer thickness. VGP and
VGE were adjusted to have identical TO field during P/E
cycling, whereas tP and tE were adjusted to have identical
charge fluence, as well as identical starting P/E VFB levels and
overall MW for all stacks. Note that erase VFB degradation
during P/E cycling remains almost similar for all TO stacks and
confirms fluence-driven erase VFB degradation.
C. Stack Degradation—Impact of Erase Pulse Parameters
Erase VFB degradation in N+ SiN is shown to be due to the
gradual buildup of trapped electrons. It is important to identify
if this buildup is due to the incomplete erase of electrons
trapped in preexisting SiN traps or additional electron trapping
in energetically deep traps generated during P/E cycling that
is difficult to erase. To isolate these effects, P/E cycling is
Fig. 6. P/E cycling with fixed program level and varying erase pulse duration
(to vary erase level) in (LHS) N2-type SiN and (RHS) N4-type SiN, 4-nm
TO and 12-nm BD thickness, respectively. The P/E bias is kept constant at
+16/−16 V, respectively.
performed under progressively varying erase pulse durations
tE . Fig. 6 shows P/E cycling at a fixed program but varying
erase conditions for N2 (N+ SiN) and N4 (Si+ SiN) devices.
For N+ SiN, an increase in tE results in a significantly lower
starting erase VFB and, hence, larger MW, because larger erase
pulse allows more time for detrapping of electrons from deep
N+ SiN traps. A moderate increase in tE also reduces the extent
of the erase VFB degradation. However, a further increase in
tE results in the reemergence of erase VFB degradation and
leads to eventual stack breakdown (breakdown is indicated by
a significant rise in stack conductance and complete loss of
programmability and will be discussed later). Note that, under
long erase durations (>∼ 100 ms), a significant reduction of
spacing between erase levels is observed due to gate backtunneling, resulting in erase saturation effect. Although starting
erase VFB reduces with higher tE , N+ SiN devices cannot
significantly be overerased (beyond VFB ∼ −1 V) due to stack
breakdown. On the other hand, Si+ SiN stacks always show
much lower starting erase VFB and significant overerase at
comparable tE and much lower erase VFB degradation during
P/E cycling. As previously mentioned, better erase ability of
Si+ SiN stacks can be attributed to shallower electron traps
and significant hole trapping due to the presence of the high
density of deep hole traps [28], [30]. However, the maximum
extent of overerase (beyond VFB ∼ −3 V) that can be sustained
is also eventually determined by stack breakdown. Note that
Si+ SiN also show erase VFB degradation at longer P/E cycles
(before stack breakdown) when erased under larger tE and will
be discussed next.
In Fig. 7, the impact of varying tE on the magnitude of erase
VFB degradation measured after 100 P/E cycles is quantified
for both N+ SiN (N2) and Si+ SiN (N4) stacks. Two competing
processes are consistently observed. Initially, high erase VFB
degradation is observed at short tE , which is much larger for
N+ compared to Si+ SiN. This case is a consequence of residual charge buildup in preexisting traps due to incomplete erase.
The large difference between N+ and Si+ SiN is observed due
to large difference in erase ability of these films, with Si+ SiN
showing better erase due to shallower electron trap depth and
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Fig. 7. Comparison of relative erase-state degradation after P/E cycling (see
Fig. 6) in N2- and N4-type SiN.
Fig. 8. (a) Comparison of P/E (+18 V/−18 V) transients before and after
cycling (see Fig. 3, RHS) for N2-type SiN (LHS) and N4-type SiN (RHS).
(b) Comparison of the magnitude of erase inability (permanent trapping) after
cycling across SiN compositions, measured before and after P/E cycling (Fig. 3,
RHS) at −18 V, 400 ms. Devices have 4-nm TO and 12-nm BD thickness,
respectively.
additional hole trapping. Increasing tE reduces erase VFB
degradation as erase becomes better, and both N+ and Si+ SiN
show similar VFB degradation. However, the use of much
longer tE results in the reemergence of erase VFB degradation,
most likely due to electron trapping in stress-induced generated
deep traps, which is difficult to erase. Although there is still a
difference between N+ and Si+ SiN at larger tE (N+ SiN shows
higher VFB degradation after turnaround), it may not reflect the
true relative extent of trap generation in these stacks due to hole
trapping in Si+ SiN.
To verify that the reemergence of erase VFB degradation at
higher tE is indeed due to trap generation, Fig. 8 compares P/E
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 7, JULY 2010
Fig. 9. Comparison of P/E cycling for N+ SiN (LHS) and Si+ SiN (RHS) at
varying energies (VGE ), with identical MWs.
transients measured before and after P/E cycling for N+ SiN
(N2) and Si+ SiN (N4) stacks, respectively. Both stacks were
cycled using identical P/E biases, whereas the P/E time was
adjusted to have identical P/E VFB levels and MW, as shown
in Fig. 3, RHS. No significant change in program transients is
observed after cycling for both N+ and Si+ SiN stacks. The program saturation level is strongly influenced by leakage through
the BD [33]; therefore, identical erase saturation before and
after cycling implies negligible trap generation (∼-trap-assisted
Poole Frenkel conduction) in the Al2 O3 BD. During erase for
N+ SiN stack, the erase transient after cycling always remains
above the precycling case, irrespective of erase pulse duration,
although almost-identical erase transients are observed before
and after cycling for Si+ SiN. However, no soft programming
at higher erase time is observed for both N+ and Si+ stacks,
both before and after P/E cycling. This result suggests that
BD gate dielectric integrity is maintained [33] before and after
P/E cycling. Fig. 8(b) summarizes the extent of the lack of
erase ability across all SiN compositions after P/E cycling at
identical starting MW [as shown in Fig. 3 (RHS)]. N+ SiN
shows incomplete erase after cycling with ΔVFB , which cannot
be reduced at longer erase time. This result clearly indicates
energetically deep trap generation followed by electron trapping (which cannot easily be detrapped) as the primary cause of
erase VFB degradation for N+ SiN stacks when cycled under
large tE [to obtain low starting erase VFB for large MW, as
shown in Fig. 3 (RHS)]. In contrast, Si+ SiN shows no change
in erase ability after cycling, with no visible evidence of net
electron trapping within the dielectric stack. Note that, due to
improved erase, tE is smaller for Si+ SiN during cycling, which
results in negligible trap generation (see Fig. 7). Moreover,
hole trapping during erase also compensates for any trapping
in generated deep electron traps in Si+ SiN stacks.
It is important to check whether the erase ability during
P/E cycling, in particular for N+ SiN, can be improved (to
obtain larger MW) by using higher (more negative) erase bias
VGE . P/E cycling was done on devices with fixed starting
program VFB but different starting erase VFB , obtained by
suitably adjusting VGE and tE . The program conditions were
kept constant. The obtained results are shown in Fig. 9 for N2
(N+ SiN) and N4 (Si+ SiN) devices. Erase ability is poorer for
N+ SiN, and program ability is poorer for Si+ SiN (as shown
SANDHYA et al.: P/E-CYCLING-ENDURANCE-INDUCED DEGRADATION IN SANOS MEMORIES
Fig. 10. P/E endurance measured by varying program pulse duration, maintaining erase state fixed for N2-type SiN (LHS) and N4-type SiN (RHS).
Devices have 4-nm TO and 12-nm BD thickness, respectively. The P/E bias is
constant (+16/−16 V). Longer cycling is achieved at longer program times for
N+ SiN. Si+ SiN shows early breakdown at longer program pulse durations.
in Fig. 2); therefore, P/E cycling was done at identical MW but
different starting program and erase levels across N2 and N4.
Note that a device sustains fewer P/E cycles before breakdown
when a particular erase VFB level is achieved at higher VGE
and lower tE , and this case is true for both N+ and Si+ SiN
stacks. Furthermore, it is also interesting to note that, although
Si+ SiN exhibits better overerase ability and hence lower erase
VFB degradation for a given VGE compared to N+ SiN, it
sustains fewer P/E cycles before stack breakdown. Note that the
early stack breakdown observed for Si+ SiN is not an artifact
of different program VFB levels used during cycling, because
early breakdown for Si+ SiN is also observed when cycled
under similar program VFB level, as shown in Fig. 6. Finally,
Si+ SiN shows lower erase VFB degradation primarily due to
significant hole trapping, as discussed earlier, but also shows
early breakdown due to larger trap generation due to its smaller
bandgap as will be discussed later, and there is no contradiction
in these results.
D. Stack Degradation—Impact of Program Pulse Parameters
Larger MW can also be obtained by increasing program VFB
for a given erase VFB . Therefore, it is important to study stack
degradation and breakdown during P/E cycling under varying
program tP and/or VGP (but fixed erase tE and VGE ) conditions. Fig. 10 shows results on N2 (N+ SiN) and N4 (Si+ SiN)
devices for P/E cycling at a fixed starting erase VFB level and
varying program VFB levels, achieved by varying tP but at
fixed VGP . For a given tP , higher program VFB is achieved
for N+ SiN, which is consistent with the ISPP results in Fig. 2.
Higher erase VFB degradation is also observed for N+ SiN as
tP is increased to attain higher initial program state VFB and
larger overall MW. However, Si+ SiN sustains relatively fewer
cycles and shows relatively early breakdown as the program
VFB level is increased. Once again, there is no contradiction
in terms of the magnitude of erase VFB degradation and the
number of P/E cycles sustained before breakdown for N+ and
Si+ SiN devices, because hole trapping in Si+ SiN masks the
true extent of trap generation during P/E cycling as previously
mentioned.
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Fig. 11. Comparison of P/E cycling for N+ SiN (LHS) and Si+ SiN (RHS)
at varying energies (VGP ) at identical MWs. Devices have 4-nm TO and
12-nm BD thickness, respectively. Faster breakdown is observed in both at
higher biases.
Finally, it is also important to verify the impact of VGP
on P/E-cycling-induced degradation and breakdown. Fig. 11
shows the impact of cycling N2 (N+ SiN) and N4 (Si+ SiN)
devices at identical MW, with fixed starting erase VFB but
varying program VFB levels, obtained by suitably adjusting
both VGP and tP . Once again, note that both N2 and N4 devices
sustain fewer P/E cycles (before breakdown) when a particular
program VFB level is achieved at higher VGP and lower tP .
Si+ SiN sustains relatively fewer cycles and shows relatively
early breakdown as programmed level is increased.
Note that large MW can be obtained by using either higher
program VFB or higher erase VFB , which are respectively
obtained by adjusting program and erase pulse parameters. For
identical pulse magnitude, positive program VGP pulse of the
P/E cycle has been observed to cause higher device degradation
and early breakdown compared to the negative erase VGE pulse
and is consistent with published literature [17]. For example,
N2 (N+ SiN) sustains 1000 and 200 P/E cycles at VGE /tE of
−18 V/3 ms and −20 V/0.8 ms, respectively (see Fig. 9, LHS),
relative to only 400 and 40 P/E cycles at VGP /tP of +18 V/
0.8 ms and +20 V/1 ms, respectively (see Fig. 11, LHS).
Similarly, N4 (Si+ SiN) sustains 1000 and 40 P/E cycles with
VGE /tE of −18 V/0.12 ms and −20 V/0.3 ms, respectively
(see Fig. 9, RHS), relative to only 40 and 2 P/E cycles at
VGP /tP of +18 V/1.2 ms and +20 V/5 ms, respectively (see
Fig. 11, RHS). Therefore, SiN-composition-dependent CTF
stack degradation is clearly evident with Si+ SiN, showing
lower tolerance to higher VGP and VGE compared to N+ SiN.
E. Postcycling Retention
The precycling and postcycling (see Fig. 3, RHS for cycling
results) charge loss during retention from excess electron programmed state for different SiN compositions are compared
in Fig. 12. Precycle retention loss increases for Si+ SiN due
to shallower electron traps, as explained in [30]. Based on FG
flash results [29], [35], it is expected that stress-induced leakage
current (SILC) due to trap generation in TO will result in higher
retention loss after cycling. However, it is interesting to note
1554
Fig. 12. Comparison of precycling and postcycling program-state roomtemperature data retention characteristics for different SiN compositions. Devices have 4-nm TO and 12-nm BD thickness and were programmed to
VFB = 5.5 V.
Fig. 13. Higher energy (VG )-induced degradation in thicker TO results in
increased SILC-related room-temperature postcycling retention loss. Devices
have 4-nm TO and 12-nm BD thickness and were initially programmed to
VFB = 5.5 V.
that N+ SiN stacks show similar charge loss, whereas Si+ SiN
stacks exhibit improvement in charge retention characteristics
(similar to published results [24]) after cycling. Identical charge
loss after cycling for N+ SiN clearly suggests insignificant
trap generation in the TO during cycling. The observation of
reduced charge loss for Si+ SiN is consistent with excess
hole trapping during cycling, because hole detrapping or hole
redistribution [36], [37] during retention can offset electron loss
and can explain the reduced postcycling retention loss observed
in these stacks.
Fig. 13 shows the comparison of precycling and postcycling
(see Fig. 5 for cycling results) charge loss during retention from
excess electron programmed state as a function of TO thickness
for N2 (N+ SiN) and N4 (Si+ SiN) stacks. Precycling retention
loss reduces at thicker TO due to larger direct tunneling barrier,
as explained in [30]. For thinner TO, postcycling retention loss
is similar to precycling loss and indicates insignificant trap
generation in TO during cycling as previously mentioned. However, enhanced postcycling retention loss for thicker TO clearly
indicates higher trap generation and SILC in these stacks. As
previously mentioned (see text corresponding to Fig. 5), VGP
and VGE were adjusted for different TO thickness stacks to
have identical TO field during P/E cycling. Therefore, thicker
TO will result in larger voltage drop across TO and, hence,
higher energy carriers and will cause higher trap generation,
as will be explained later in Section III-F.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 7, JULY 2010
Fig. 14. Stress-accelerated room-temperature retention postcycling shows
higher charge loss at VG < 0 V indicative of SILC in TO. Negligible loss at
VG > 0 V highlights the integrity of BD. Devices have 4-nm TO and 12-nm
BD thickness and were initially programmed to VFB = 5.5 V.
The aforementioned discussion assumes trap generation in
SiO2 TO and not in the Al2 O3 BD during P/E cycling that is
responsible for enhanced postcycling retention loss for thicker
N+ SiN stacks. To verify this case, retention experiments were
carried out from excess electron programmed state under accelerated gate bias stress before and after P/E cycling for N2- and
N4-type SiN, as shown in Fig. 14. The stress bias applied during
retention is deliberately kept low (±6 V) to prevent appreciable
charge injection, leading to soft P/E. Positive VG stress during
retention will preferentially accelerate electron loss through the
BD, whereas a negative VG will enhance the tunnel out of
electrons through the TO. Retention loss due to the tunnel out
of electrons through the TO during VG < 0 stress significantly
increases after P/E cycling. For N2-type SiN, postcycling retention loss remains similar to precycling retention loss during
VG > 0 stress that ejects electrons through the BD. This result
clearly suggests trap generation in TO rather than in BD during
P/E cycling, resulting in increased SILC and enhanced charge
loss for thicker TO N+ SiN stacks. Although precycling charge
loss through BD increases at elevated temperature (increased
Poole–Frenkel component through preexisting Al2 O3 traps),
loss through TO still remains dominant, as shown in [30]. No
significant enhancement of charge loss through BD is observed
after cycling at elevated temperature and can be attributed to
negligible trap generation in the BD during cycling. Finally,
stress bias retention experiments for N4 (Si+ SiN) stacks show
slightly higher postcycling retention loss due to the tunnel out
of electrons through the TO during VG < 0 stress and similar
precycling and postcycling retention loss due to the tunnel out
of electrons through the BD during VG > 0 stress, as shown in
Fig. 14, RHS. However, the difference between precycling and
postcycling retention loss through the TO for VG < 0 stress is
much lower for N4 compared to N2 SiN. Because N4 stacks
show significant hole trapping, VG < 0 stress will move the
hole trap centroid toward the gate (away from channel) and will
reduce the effect of SILC-related loss of electrons through TO.
F. Physical Mechanism of Stack Degradation and Breakdown
It has been shown in previous sections that attempts to
achieve higher overall MW during P/E cycling by making either
SANDHYA et al.: P/E-CYCLING-ENDURANCE-INDUCED DEGRADATION IN SANOS MEMORIES
Fig. 15. Energy-band diagram of the SANOS stack (12 nm/6 nm/4 nm)
obtained from the Poisson solver during (a) program and (b) erase operations.
the starting program or starting erase levels more positive or
negative, respectively, lead to higher erase VFB degradation and
early stack breakdown. This case happens when P/E pulsewidth
or amplitude is increased (to increase charge fluence across
the stack and starting MW), although an increase in pulse
amplitude always results in more severe stack degradation.
For identical pulse duration and magnitude, positive gate pulse
during program results in early stack breakdown compared to
negative gate pulse during erase. Although Si+ SiN stacks show
lower erase VFB and overall MW degradation during cycling,
they sustain fewer P/E cycles before breakdown under larger
P/E biases and times. It has also been shown (see discussion
related to Figs. 4 and 11) that no significant trap generation and
trapping take place in the Al2 O3 BD during cycling. Therefore,
trap generation in CTF devices during P/E cycling must be
taking place in the TO and/or in the SiN charge trap layer.
Stack degradation has been shown to be fluence driven
(see Fig. 4 and related discussion); therefore, it is necessary
to identify various tunnel components in CTF stacks during
P/E operation. Fig. 15 illustrates energy-band diagrams of
SANOS gate stacks under program and erase. Neglecting hole
tunneling from n+ gate during program, charge flux across
the gate stack is due to electron tunneling through the TO
(designated as QIET ) and that through BD (QOEB ) [33]. Higher
dielectric constant of BD compared to TO results in lower
1555
electric field across BD. For most part of the program transient,
the magnitude of QOEB should be much lower than QIET ,
thereby making QIET the dominant component. During erase,
detrapped electrons from the SiN form major flux across TO
and are designated as QOET . The hole tunnel-in current (from
Si to SiN across TO) is likely to be much lower (unless very
high bias or long erase duration is used) due to higher valence
band barrier height and effective mass of holes. Although the
Al2 O3 electron barrier height is slightly lower than SiO2 [38],
the electron backinjection flux through the BD during erase,
i.e., QIEB can be assumed to be negligible as the erase level
does not increase with longer erase time [33], as shown in
Fig. 8. Because only a fraction of QIET gets trapped during
program, QOET consisting of detrapping of previously trapped
electrons will be much smaller than QIET . During program,
the injected electrons across TO (QIET ) can cause impact
ionization (I/I) in SiN, resulting in generation of hot holes
(HHG). Generated hot holes can subsequently cause defects in
SiO2 or SiN [39], [40]. During erase, electron flux across TO
(QOET ) can cause I/I in Si substrate and also result in HHG.
Injection of generated hot holes into the TO will be responsible
for defects generated in TO SiO2 bulk and Si/SiO2 interface.
During cycling, HHG caused by both QIET and QOET will
create defects. Although the Si bandgap is smaller than SiN,
QIET is much larger than QOET and likely explains why higher
device degradation is observed during program compared to
erase under identical pulse magnitude. Application of higher
VGP will impart higher electron energy and generate more
energetic hot holes due to I/I in SiN, further aggravating degradation. Moreover, HHG by QIET will be higher for Si+ SiN
due to its lower bandgap compared to N+ SiN and will create
higher trap generation and early breakdown in the former.1 It is
reasonable to assume that generated SiN traps are energetically
deeper, as electrons trapped in these defects are difficult to
erase [see Fig. 8(a) and related discussion]. Although larger trap
generation resulting in early breakdown of Si+ SiN stacks is
always observed, it is difficult to quantify such trap generation if
estimated from observed erase VFB degradation during cycling
due to large hole trapping in Si+ SiN stacks. It is important
to note that HHG followed by I/I due to QIET has important
implications on the use of high-k materials with lower bandgap
as trap layers [42]. Higher trap generation due to higher HHG
(because bandgap is smaller) can lead to early breakdown of
such stacks and require careful analysis.2
Furthermore, as previously mentioned, QOET will also cause
I/I and HHG in the Si substrate and trap generation in the SiO2
TO and Si/SiO2 interface. A signature of trap generation in the
SiO2 TO (more specifically at or close to Si/SiO2 interface)
is shown in Fig. 16, which compares the conductance–voltage
1 Alternatively, Q
IET can result in direct bond breakage under stress and
also result in gate stack breakdown. Si+ SiN has higher density of low-energy
Si-H bonds [41], which can easily be broken by ballistic electrons tunneling
into SiN, resulting in earlier breakdown relative to N+ SiN.
2 Note that HHG for a given Q
IET will be the largest for FG devices due to
the lowest bandgap of poly-Si charge storage layer. However, it is the presumed
trap generation due to HHG in the insulating charge trapping layer that limits
the maximum MW that can be endured for a certain amount of P/E cycles. Trap
generation in SiN or high-k trapping layer needs careful analysis.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 7, JULY 2010
Fig. 16. Increase in stack conductance (G) postcycling in N2 (LHS) and N4
(RHS) due to conduction aided by generated traps.
(G − VG ) characteristics measured before and after 104 P/E
cycles for N2 (N+ SiN) and N4 (Si+ SiN) stacks. For both
stacks, an increase in conductance after cycling indicates generated TO traps taking part in the conductance process [43].
However, larger change in conductance is shown for N2 compared to N4 stack, implying larger TO trap generation in the
former. This result is expected, because higher erase VFB
degradation for N2, particularly at longer P/E cycles, will result
in higher TO field during the start of erase. This result, in
turn, will impart more energy to QOET electrons and thereby
generate more energetic hot holes due to I/I in Si, and the
resulting TO degradation will be larger. Finally, significant HH
injection from Si to SiO2 TO can take place for very large
VGE , which will cause very early breakdown of these stacks,
as shown in Fig. 9. As an ending note, we wish to mention
that the stack degradation mechanism discussed in this section
is purely qualitative and will need development of quantitative
simulation models for verification, which is beyond the scope
of this paper.
IV. C ONCLUSION
In CTF memories (like SANOS), electron/hole capture and
emission efficiencies has determined the charge fluence through
the gate stack to obtain a particular MW during P/E operation,
which, in turn, is controlled by the magnitude and duration of
P/E pulses. Electron and hole trap properties have been strongly
influenced by the composition of the SiN trap layer. Therefore,
P/E-cycling-induced trap generation that leads to MW closure
and eventual stack breakdown has also been strongly dependent
on SiN composition. N+ SiN shows higher erase VFB (hence
MW) degradation, which is likely due to energetically deep
acceptor-like trap generation during P/E cycling followed by
electron trapping that are difficult to detrap. Si+ SiN shows
lower erase VFB degradation likely due to additional hole
trapping but also shows early stack breakdown (loss of programmability) due to larger generation of electron traps with
cycling.
Erase VFB degradation during cycling shows two distinct
mechanisms: 1) residual charge buildup due to incomplete erase
for cycling using short erase pulse and 2) stress-induced electron trap generation when cycling using long erase pulse. The
magnitude of trap generation is linked to charge fluence across
TO during cycling, because gate stacks cycled under similar
charge fluence show similar erase VFB degradation. Large MW
can be obtained by increasing the P/E pulsewidth or pulse amplitude to effectively increase charge fluence across the stack.
However, this case results in increased degradation and eventual
stack breakdown, and hence, fewer P/E cycles can be sustained
at higher MW. An electron-flux-induced anode hole generation
model qualitatively explains the observed degradation and its
dependence on several experimental factors during P/E cycling.
Postcycling retention characteristics suggest higher trap generation in TO and SiN than in BD, but this condition requires
further investigation. Application of higher P/E gate biases
further aggravates degradation by imparting higher energy to
the generated hot holes. Si+ SiN has decreased tolerance to
higher P/E biases due to its smaller bandgap and consequently
shows higher trap generation and early breakdown compared to
N+ SiN. Higher gate biases required for thicker TO for good
P/E speeds and MW also cause higher trap generation due to
higher energy associated with tunneling electrons that initiate
HHG, resulting in enhanced postcycling retention loss. Overall,
SiN-layer optimization, along with reliable TO and BD layers,
is very crucial to obtain CTF stacks that can reliably sustain
large MW during P/E operation.
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C. Sandhya (S’07) received the M.Tech. degree in
microelectronics and the Ph.D. degree in electrical
engineering from the Indian Institute of Technology Bombay, Mumbai, India, in 2006 and 2010,
respectively.
During her graduation, she received a Fellowship
for the Global Research Collaboration (GRC) from
the Semiconductor Research Corporation (SRC).
Since November 2009, she has been a Device Engineer with Samsung Semiconductor R&D Center,
South Korea. Her research interests include device
physics and flash memory optimization through device design, modeling,
reliability characterization, and simulation.
Apoorva B. Oak is currently working toward the
B.Tech. and M.Tech. degrees (dual-degree program)
in microelectronics in the Centre of Excellence in
Nanoelectronics and Department of Electrical Engineering, Indian Institute of Technology Bombay,
Mumbai, India, and will graduate in 2010.
His research interests include CTF memory characterization and simulation.
1558
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 7, JULY 2010
Nihit Chattar received the B.E. degree in electronics and telecommunication from the Institute of
Engineering and Technology, Indore, India, in 2007
and the M.Tech. degree in microelectronics from the
Indian Institute of Technology Bombay, Mumbai,
India, in 2009.
He is currently with the Centre of Excellence in
Nanoelectronics and Department of Electrical Engineering, Indian Institute of Technology Bombay,
Mumbai, India.
Udayan Ganguly received the Ph.D. degree from
Cornell University, Ithaca, NY, and the B.Tech. degree from the Indian Institute of Technology (IIT),
Madras, India.
He is currently a Device and Integration Engineer
with the Front-End Products Group, Applied Materials, Santa Clara, CA, focusing on the development
of applications for Applied front-end tools in flash
memory technologies.
C. Olsen, photograph and biography not available at the time of publication.
S. M. Seutter, photograph and biography not available at the time of
publication.
L. Date, photograph and biography not available at the time of publication.
R. Hung, photograph and biography not available at the time of publication.
Juzer Vasi (M’74–SM’96–F’04) received the
B.Tech. degree in electrical engineering from the
Indian Institute of Technology (IIT) Bombay,
Mumbai, India, in 1969 and the Ph.D. degree from
the Johns Hopkins University, Baltimore, MD,
in 1973.
He was with the Johns Hopkins University and
IIT Delhi, New Delhi, India, before moving to IIT
Bombay in 1981, where he is currently a Professor
with the Centre of Excellence in Nanoelectronics and
Department of Electrical Engineering. His research
interests include CMOS devices, technology, and design. He has worked on
MOS insulators, radiation effects in MOS devices, degradation and reliability
of MOS devices, modeling and simulation of MOS devices, and MOS-based
NVMs.
Dr. Vasi is a Fellow of the Indian National Academy of Engineering and
Institute of Electronics and Telecommunication Engineers (IETE). He was
the Editor of the IEEE TRANSACTIONS ON ELECTRON DEVICES FOR MOS
DEVICES AND TECHNOLOGY and a Distinguished Lecturer of the IEEE
Electron Devices Society.
Souvik Mahapatra (M’02–SM’07) received the
Ph.D. degree in electrical engineering from the Indian Institute of Technology (IIT) Bombay, Mumbai,
India, in 1999.
He was with Bell Laboratories, Murray Hill, NJ,
from 2000 to 2001. Since 2002, he has been with the
Centre of Excellence in Nanoelectronics and Department of Electrical Engineering, IIT Bombay, where
he is currently a Professor. He holds an honorary
graduate faculty position with Purdue University,
West Lafayette, IN. He has published more than 90
papers in peer-reviewed journals and conference proceedings, delivered invited
talks at leading international conferences in the U.S., Europe, and Asia Pacific,
including the IEEE International Electron Devices Meeting (IEDM), and served
as a Reviewer of several international journals and conferences. His research
interests include the characterization, modeling, and simulation of CMOS and
flash memory devices, and device reliability.
Dr. Mahapatra is a Distinguished Lecturer of the IEEE Electron Devices Society. He has delivered reliability tutorials at the IEEE International Reliability
Physics Symposium (IRPS).