IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 12, DECEMBER 2009
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Impact of SiN Composition Variation on
SANOS Memory Performance and Reliability
Under NAND (FN/FN) Operation
C. Sandhya, Student Member, IEEE, Apoorva B. Oak, Nihit Chattar, Ameya S. Joshi, Udayan Ganguly, C. Olsen,
S. M. Seutter, L. Date, R. Hung, Juzer Vasi, Fellow, IEEE, and Souvik Mahapatra, Senior Member, IEEE
Abstract—Despite significant advances in structure and material optimization, poor erase (E) speeds and high retention charge
loss remain the challenging issues for charge trap Flash (CTF)
memories. In this paper, the dependence of SANOS memory performance and reliability on the composition of silicon nitride (SiN)
layer is extensively studied. The effect of varying the Si:N ratio on
program (P)/E and retention characteristics is investigated. SiN
composition is shown to significantly alter the electron and hole
trap properties. Varying the SiN composition from N-rich (N+ )
to Si-rich (Si+ ) lowers electron trap depth but increases hole
trap depth, causing lower P state saturation but significant overerase, resulting in an enhanced memory window. During retention,
P state charge loss depends on thermal emission followed by the
tunneling out of electrons mostly through tunnel dielectric, which
becomes worse for Si+ SiN. Erase state charge loss mainly depends
on hole redistribution under the influence of internal electric fields,
which improves with Si+ SiN. This paper identifies several important performances versus reliability tradeoffs to be considered
during the optimization of SiN layer composition. It also explores
the option for CTF optimization through the engineering of SiN
stoichiometry for multilevel cell NAND Flash applications.
Index Terms—Charge trap Flash (CTF), program/erase (P/E)
window, retention, SANOS, silicon nitride (SiN), SONOS.
I. I NTRODUCTION
T
HE SURGING demand for data storage in portable electronics has fueled a tremendous growth of NAND Flash
memories in the recent years. As evident from the ITRS
roadmap, NAND Flash scaling is progressing at a much faster
rate than CMOS logic and is likely to hit the “red brick wall”
in the near future [1]. Scaling conventional floating gate (FG)
Flash beyond the 3X node is extremely challenging due to the
limitations of scaling the tunnel oxide (TO) below 7–8 nm, cell
to cell interference, and loss of control gate to FG coupling
[2]–[5]. Evolutionary memory technologies, such as charge trap
Flash (CTF) [2]–[5], and nanocrystal Flash [6] or revolution-
Manuscript received April 30, 2009; revised August 24, 2009. Current
version published November 20, 2009. This work was supported in part by
the Department of Information Technology, Government of India, through the
Center of Excellence in Nanoelectronics and in part by SRC (GRC). The review
of this paper was arranged by Editor J. Woo.
C. Sandhya, A. B. Oak, N. Chattar, A. S. Joshi, J. Vasi, and S. Mahapatra
are with the Center of Excellence in Nanoelectronics and the Department
of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai
400 076, India (e-mail: [email protected]).
U. Ganguly, C. Olsen, S. M. Seutter, L. Date, and R. Hung are with Applied
Materials, Santa Clara, CA 95054-3299 USA.
Digital Object Identifier 10.1109/TED.2009.2033313
ary technologies like ferroelectric random access memories
(RAMs) [3], phase change memories [3], magnetic RAM [7],
or resistive RAM [8] are the possible candidates to eventually
replace conventional FG memories. Among all possible alternatives, CTF is technologically the most mature for NAND Flash
applications. It also has benefit of being planar [4] and fully
CMOS compatible fabrication process. Other technologies require the introduction of complex materials and are subject
to difficulties in material integration and scaling. The discrete
trap-based charge storage enables TO scaling with improved
immunity to pinhole defects [9]. Significant research in performance enhancement through structure and material optimization has evolved CTF technology with excellent program/erase
(P/E) memory windows (MWs) and endurance capabilities.
However, poor E speeds and high retention charge loss remain
the challenging issues for CTF memories. Charge loss mechanisms from the P state have so far been fundamentally understood and successfully modeled, but the underlying charge loss
mechanisms in the E state are largely unexplored [38]–[41].
Modern CTF stacks replace deposited SiO2 with Al2 O3 as
the blocking dielectric (BD) [10]. The wider bandgap of Al2 O3
(compared to other high-κ dielectrics) restricts charge leakage
from silicon nitride (SiN) toward the gate during retention, and
its higher dielectric constant (κ ∼ 9) couples higher electric
fields to the tunnel dielectric, improving P/E speeds. A high
work function metal gate suppresses gate injection during E,
permitting wider MW [11]. To enable scaling, the SiO2 tunnel
layer is often replaced by a composite multilayered stack [12]–
[18]. The engineering of the tunnel dielectric with crested
[13], VARIOT [14], symmetric composite [15] tunnel barrier,
and double quantum-barrier structure [16] was also found to
improve performance. However, the use of thin multilayer
deposited tunnel dielectric may compromise the overall cell reliability, particularly for multilevel cell (MLC) operation which
requires high P/E voltages for large MW, resulting in degraded
P/E cycling endurance capability. Although blocking and tunnel
dielectric engineering provide some benefit, engineering the
charge trap layer itself would offer immense possibilities for
developing novel structures or engineered trap properties for
optimized memory performance. Therefore, engineering the
SiN charge trap layer is a promising strategy to enhance the
performance and reliability of CTF.
In an earlier work [19], it has been shown that the characteristics of nonstoichiometric SiN traps demonstrate a strong
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decrease in the trapped charge density when films become rich
in N–H bonds. It has also been shown [20], [21] that the Sirich (Si+ ) SiN has higher electron trap density at relatively
shallow energy levels, allowing them to get readily discharged
of the electrons during E operations [22]. In our earlier letter, it
has been demonstrated that Si+ SiN and N+ SiN show several
interesting tradeoffs in P/E windows, retention and endurance
characteristics from both P and E states [22]. Literature on the
chemical nature of traps in SiN [23]–[25] attempts to relate
distinct trap species for positive and negative traps. In contrast,
an amphoteric trap model attributes the same species serving to
trap both electron and holes [26]. Therefore, clarity in the relation of SiN composition to electron/hole trap properties to CTF
performance is essential for the realization of CTF technology.
Bandgap engineering with tapered SiN bandgap structure [27]
and composite NAN (N: nitride, A: Al2 O3 ) storage material in
an advanced TANOS stack [28] has demonstrated significant
performance improvements. Previously, we have shown that
a Si+ /N+ SiN bilayer separated by a controlled oxynitride
(SiON) interface in a SONOS stack provides comparable performance with simpler process integration [29]. Maximum MW
is achieved by placing the charge centroid close to the channel
but may compromise data retention by enhancing charge loss
through the tunnel dielectric [29]. These conflicting trends
require careful attention before establishing CTF as a viable
technology option.
Our earlier letter [22] briefly discussed the impact of SiN
composition on MW, retention loss, and cycling endurance
for SANOS gate stacks. This paper presents several new insights regarding the SiN material composition on electron/hole
trapping/detrapping characteristics in SANOS memories. First,
we aim at establishing the performance tradeoffs for a range
of trap layer compositions to understand the need for SiN
optimization. Charge trapping properties are shown to vary with
Si:N ratio of the SiN layer. This influences the magnitude of
stored charges in the P and E states and, hence, the overall
MW. Second, the dominant carrier conduction during charging/
discharging as a function of E bias is investigated. The location
of maximum charge trapping is also determined. In scaled
SANOS stacks, the role of interfaces on charge trapping characteristics is shown to be as significant as the bulk. Retention
during P and E states is shown to be strongly influenced by
SiN composition. The underlying charge loss mechanism from
the P and E states is systematically explored and found to be
radically different. The ability to modulate the performance and
reliability of CTF by tuning the SiN composition provides a
major opportunity for CTF optimization. From the aforementioned study, we derive useful insights that would help develop
optimized SiN charge storage layer for reliable MLC operation
of CTF memory.
II. D EVICE D ETAILS
SANOS capacitors, as schematically shown in Fig. 1, having n-substrate and p+ S/D diffusion ring (for providing the
minority carriers during inversion) are used in this paper. Gate
stacks are composed of rapid thermal oxidation (RTO) SiO2
TO of thickness 4–6 nm, LPCVD SiN charge storage layer of
Fig. 1. (a) Schematic and (b) energy band diagrams of SANOS capacitors
with p+ implants for supplying minority charge carriers. The devices have
an RTO TO of thickness 3–6 nm, a 6-nm-thick LPCVD SiN of varying
compositions, and 12–20-nm-thick CVD Al2 O3 as BD.
TABLE I
S PLIT TABLE FOR THE SANOS D EVICES
thickness 6 nm, CVD Al2 O3 BD of thickness 12–15 nm, and
n+ poly-Si gate. Table I summarizes the device details. The
composition of the SiN trap layer was controlled by varying
the Si2 H6 and NH3 gas flow ratio and LPCVD deposition
temperature. The SiN deposition temperature for sample N0
was 800 ◦ C, and samples N1–N4 were deposited at 650 ◦ C.
Fig. 2(a) shows the refractive index (RI) as a function of
LPCVD gas flow ratio for different SiN deposition
temperatures.1 Note that, for a given gas flow ratio, the obtained RI is strongly affected by the deposition temperature.
SiN films deposited at lower temperature (650 ◦ C) exhibit
a wide RI range as the gas flow ratio is varied. However, in
contrast, at higher deposition temperatures (800 ◦ C), lower RIs
are more easily attained. The SiN films used in this paper show
an RI of 1.97 (N-rich, henceforth referred to as N+ ) through
2.13 (Si-rich, referred to as Si+ ) and are tabulated in Table I.
The RI of stoichiometric SiN is known to be ∼2.01 [31]. Note
that Si, N, and H composition of SiN deposited by LPCVD
may vary with deposition temperature even at the same RI. For
1 RI measurements were done at 633 nm using a spectroscopic ellipsometer
on thicker (220 Å–240 Å) SiN films and verified across film thickness (data
not shown) for consistency. The measured RI was found to stabilize for film
thickness > 200 Å.
SANDHYA et al.: IMPACT OF SiN COMPOSITION VARIATION ON MEMORY PERFORMANCE AND RELIABILITY
Fig. 2. (a) RI versus Si2 H6 /NH3 gas flow ratio at deposition temperatures
of 650 ◦ C and 800 ◦ C. RI is measured for 49-point average at 633 nm.
(b) RBS/HFS to estimate Si, N, and H concentrations with deposition temperature in the same RI range as (a).
example, Fig. 2(b) shows the measured concentration of Si, N,
and H obtained using the Rutherford back scattering (RBS)/
hydrogen forward scattering (HFS) as a function of RI for
different LPCVD SiN deposition conditions. The measured Si,
N, and H concentrations show a systematic trend with deposition temperature in the specified RI range. The X-ray photoelectron spectroscopy characterization of the SiN splits used
(N1–N4) showed approximately 5% N-content change over
the stated RI range for 650 ◦ C films. RBS/HFS measurements
show 3%–4% higher H content at the expense of similarly
lower N% for 650 ◦ C films compared to 800 ◦ C at identical
RIs. This implies that higher deposition temperature reduces
H content and incorporates relatively larger N in the films. A
quantitative comparison shows that N2-type SiN has 3% more
Si, 3% less N, and comparable H compared to N0. The physical
characterization implies that it is possible to monotonically
vary the SiN composition by the gas flow ratio and deposition
temperature. We have chosen representative splits with a
wide composition variation to study its detailed impact on the
performance and reliability.
HFCV measurements at 1 MHz on capacitors having an area
of 100 × 100 μm were performed to determine the P, E, and
retention characteristics reported in this paper. The C–V curves
show negligible skew during the course of memory operation.
Hence, flatband voltage (VFB ) shifts are used to monitor the
memory operation of these devices. The initial VFB measured
for all fresh devices is in the range −0.1 to 0.2 V in the study.
III. P/E P ERFORMANCE
A. Constant-Voltage P/E Transients
Fig. 3 shows the P/E transients, measured at constant P/E
biases over different SiN compositions. P transients demonstrate higher saturation VFB for N+ SiN (N0, N1). In contrast,
the E transients of Si+ nitrides (N3, N4) are relatively faster
and saturate at lower E VFB values. Further improvement of
E saturation can be achieved using a p+ polysilicon gate to
suppress gate electron injection [32]. Similar SiN composition
dependence of P/E transients was reported on SONOS devices
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Fig. 3. P/E transients for different SiN compositions (N+ , N0 to Si+ , N4).
All devices have identical TO, SiN, and BD thickness.
Fig. 4. (Bars) P/E state VFB and (closed circles) MW for SiN composition
variations from (lower RI) N+ to (higher RI) Si+ . All devices have identical
stack thicknesses and were subject to P/E biases of +19 V/−19 V. RI values
are shown by open circles.
with HTO as the BD [29], [30]. It is of interest to note that,
from an MLC memory performance perspective, the overerase
capability of Si+ SiN can be leveraged to split the overall MW
between distinct quantized P and E states. This has the advantage of lower biases required for splitting a given MW between
P and E levels. Moreover, a split reduces the overall P and E
state charges within SiN and hence decreases internal electric
fields during retention. This is likely to improve the charge
loss during retention, resulting in a potential improvement of
memory reliability.
Fig. 4 shows the P and E windows measured at +19 V/
−19 V for different SiN compositions. Note that P level reduces while E level increases (in negative direction) as SiN
is made progressively Si+ . This emphasizes the importance of
overerasure on the overall MW. For example, when N4 (Si+ ) is
compared to N1 (N+ ) at identical P/E conditions, although the
P state level reduces by 14%, it is compensated by a remarkable
decrease in E state level, resulting in a 38% increase in the
overall window. A reduction in P state level is observed in Si+
SiN despite it being known to have a higher trap density [20].
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Fig. 5. VFB shifts due to ISPP for varying SiN compositions (N0–N4). The
gate pulses incremented at a 0.3-V step with constant pulsewidths of 200 μs.
This is attributed to the increased charge detrapping, owing to
shallower trap energy levels, resulting in net lower P saturation
level, as explained in [33]. Excellent correlation is observed between overerase capability and RI, which could be considered
as an indicator of the composition of films deposited at identical
temperatures (note that N1–N4 were deposited at 650 ◦ C, while
N0 was deposited at 800 ◦ C). Although N1 (RI = 1.97) and
N2 (RI = 2.006) have rather close RI values, RBS shows
progressively excess Si (N2 has ∼2% more Si and 1% less N
than N1), indicating significant impact of SiN composition on
P/E performance. The H and N content difference due to the
different deposition temperatures may also contribute to trap
layer properties, resulting in different P/E saturation levels with
varying SiN film composition.
B. Incremental Step Pulse P and E
The incremental step pulse programming (ISPP) [34] plots
for different SiN compositions are shown in Fig. 5. The programming pulsewidth was kept fixed at 200 μs, with 0.3-V
pulse increment steps. The plot represents clearer separation of
the P speed and saturation levels between different SiN films as
compared to Fig. 3. Note that N+ SiN shows faster programming and higher saturation level compared to Si+ SiN, and the
differences are more apparent at higher P VG . Conventionally,
ISPP is performed to tighten the threshold voltage (VT ) distribution between different P levels. However, splitting the MW
below 0-V VT would require tightened distribution between
the quantized E levels. This could potentially be achieved by
the incremental step pulse erasing (ISPE; similar to ISPP),
which also shows the relative dominance of different physical
processes during E, and is demonstrated as follows.
For the first time, we present the results of ISPE measured for
different SiN compositions. Fig. 6 shows the ISPE measured
at a fixed pulsewidth of 20 ms and a pulse step of 0.3 V.
The plot shows two sets of data: E done on fresh devices
(VFB ∼ 0 V) and that done after programming the devices to
VFB = 5.5 V. For E from VFB ∼ 0 V (negligible electrons in
SiN), no change in VFB is observed for lower E VG . For higher
E VG , N+ SiN shows soft programming (due to gate injection)
Fig. 6. VFB shifts due to ISPE for varying SiN compositions (N0–N4).
Devices were erased under two conditions: 1) Fresh and 2) programmed
devices; VFB = 5.5 V. The gate pulses are incremented at a 0.3-V step with
constant pulsewidths of 20 ms.
and then E as VG is increased further, while Si+ SiN shows
only E and no programming. Si+ SiN starts to E at relatively
lower VG compared to N+ SiN. E from VFB = 5.5 V (excess
electrons in SiN) shows two different slopes at lower and higher
E VG ’s, consistently for all SiN films. As VG is increased, the
E transients from VFB = 5.5 V merge to that from VFB ∼ 0 V
for all SiN films. This merging occurs at a relatively lower
VG for Si+ SiN when compared to N+ SiN. The overerase
capability (speed and VFB shift) progressively increases from
the most N+ SiN (N1) to the most Si+ SiN (N4) and is in
agreement with constant-voltage E transient trends shown in
Fig. 3. The two-slope ISPE characteristics demonstrate different physical regimes of charge conduction2 —electron back
tunneling to substrate at low E VG (only the state with excess
electrons show E) and hole trapping in SiN at higher E VG [32].
For N+ SiN erased from VFB = 5.5 V, the second phase of
hole tunneling sets in at very high electric fields, followed by
device breakdown as VFB becomes negative. This indicates E
dominated by electron detrapping rather than hole trapping, as
discussed in [35] for N+ SiN, reflecting significantly lower hole
trap density in N+ SiN relative to Si+ SiN. On the other hand,
E in Si+ SiN can be ascribed to both electron detrapping and
hole trapping, which also explain the relatively lower E VG and
overerase observed for these devices.
C. Determination of Charge Centroid
SiN charge density and charge centroid position are two
essential parameters that determine the final VFB and, hence,
the MW of the cell. The charge centroid estimation has earlier
been done for SONOS-type memories. The reported location
of charge trapping is debatable. It has been shown that charge
trapping mainly occurs at the top and bottom SiN interfaces
[36]. It has also been reported that the charge trapping is mainly
in the bulk SiN and the charge centroid lies at the center of
2 A close inspection of V
FB time transient data during erase (Fig. 3) also
shows two distinct slopes at short and long erase times, corresponding to the
relative dominance of different physical mechanisms.
SANDHYA et al.: IMPACT OF SiN COMPOSITION VARIATION ON MEMORY PERFORMANCE AND RELIABILITY
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Fig. 7. P/E transients at identical electric fields across the TO for varying TO
thickness splits. All devices have identical SiN and BD thicknesses.
the SiN layer [37]. The centroid extraction techniques are complicated and often require specific split design or complex experimental setups [37]. More importantly, the extent of charge
trapping at the SiN/Al2 O3 interface for SANOS stacks has
been largely unexplored. This section presents a simple method
used to determine the position of maximum charge trapping in
SANOS memories, once the saturation in programming level is
reached.
Fig. 7 shows the P/E transients taken at constant electric
fields across TO for devices with varying TO thicknesses. These
devices have 12-nm-thick BD and 6-nm N2-type (see Table I)
SiN trap layer. At the start of the P/E operation, the initial fields
were computed using [32]
Eox =
VG − VFB
.
xEOT
(1)
Carrier injection via tunneling through the TO from substrate to SiN and vice versa would depend on the applied
electric field. The P and E transients were measured at 12 and
−14 MV/cm, respectively. At these fields, the Fowler–
Nordheim tunneling of electrons from substrate into SiN and
back is the dominant charge injection mechanism. For identical
Eox fields over different oxide thicknesses, the amount of
charge injected into SiN would be the same, eventually leading
to the identical evolution of the charge centroid within the
SiN. This would then yield similar VFB shifts with time, all
other parameters (including BD thickness) being kept constant. The excellent correlation of both P and E transients
over various oxide thicknesses indicates the accuracy in Eox
computation.
Fig. 8(a) shows the programming transients for devices
with different Al2 O3 thicknesses, 6-nm-thick N2-type SiN,
and 4-nm-thick tunnel dielectric. P transients were measured
at identical Eox ’s of 10, 12, and 14 MV/cm, using (1), to
maintain identical charge injection conditions. The flatband
voltage VFB of a transistor is given by ΔVFB,sat = QN /Ceq ,
i.e., ΔVFB,sat = QN xeq /ε0 εox , where QN is the charge stored
in SiN, xeq = (xAlO εox /εAlO ) + (xc εox /εSiN ), and xc is the
Fig. 8. P/E transients for devices with varying BD thickness measured at
identical starting electric fields across TO. All devices have identical TO and
SiN thicknesses. For a given change of SiN charge during P/E, VFB shift is
proportional to the BD thickness, as evident from case 1.
position of charge centroid in the SiN at the end of P. Replots of Fig. 8(a) for three different cases are shown in
Fig. 8(b)–(d):
1) case 1 [Fig. 8(b)]: centroid at SiN/Al2 O3 interface with
xeq1 = xAlO εox /εAlO ;
2) case 2 [Fig. 8(c)]: centroid in the middle of nitride layer
with xeq2 = (xAlO εox /εAlO ) + (xSiN εox /2εSiN );
3) case 3 [Fig. 8(d)]: centroid at the SiN/SiO2 interface with
xeq3 = (xAlO εox /εAlO ) + (xSiN εox /εSiN ).
Scaling the transients with Al2 O3 thickness, as in case 1,
yields excellent match between the different P transients. The
transients would match only if the injected electrons were maximally trapped at the SiN/Al2 O3 interface, making VFB mostly
dependent on Al2 O3 thickness alone. Hence, this suggests
that the possible charge centroid location is at the SiN/Al2 O3
interface3 at least for N2-type SiN composition. The trap
density at the top interface is thence estimated to be Ntop =
(2.06 ± 0.04) × 1013 cm−2 , which is slightly higher compared
to the value (1.42 ± 0.09) × 1013 cm−2 ) specified in [36] for
a MONOS device. Similar splits can be designed and tested to
obtain the location of maximum charge trapping for other SiN
compositions.
3 We find that a linear relationship exists when ΔV
FB is plotted w.r.t. Al2 O3
thickness [36]. If trapping was to take place uniformly in the bulk Al2 O3 , the
dependence would be quadratic. This implies that the charge is indeed stored at
the SiN/Al2 O3 interface.
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Fig. 9. (a) Retention loss (25 ◦ C) from P and E states for different SiN
compositions (identical stack thicknesses). N1 cannot be erased to VFB < 0 V,
and hence, E state retention measurement is excluded. Note that the Y -axis
scales on graph for monitoring VFB shifts in the P and E states are different.
(b) Room temperature retention loss from the P and E states (identical starting
VFB ’s in each case) versus initial E state VFB for stacks having different SiN
compositions but identical thicknesses.
IV. I NTRINSIC R ETENTION P ERFORMANCE
Retention measurements were performed by monitoring VFB
shifts due to loss of electrons from the programmed state
and loss of holes from the overerased state as a function of
retention time (with all terminals grounded). All devices were
programmed and erased to evaluate retention loss under two
different conditions: 1) for devices with similar EOTs, identical
P/E levels to have identical internal electric fields in the TO
and BD during retention and 2) different P/E levels to estimate
retention loss under varying internal electric fields. This was
done to establish trends for examining the various charge loss
mechanisms.
Fig. 9(a) shows the SiN-composition-dependent retention
transients from both P and E states. Fig. 9(b) shows the trends,
with the VFB shifts measured at the end of 104 s. A strong
dependence of retention charge loss on the SiN composition
is observed. A progressive increase in electron loss from the
P state is observed as the SiN composition is varied from N+
(N1) to Si+ (N4), which is similar to [20]. The E state shows
the opposite trend with larger loss observed in relatively N+
Fig. 10. (a) Retention loss transients from the P state (starting VFB : 5.5 and
2.5 V) at different temperatures (25 ◦ C–180 ◦ C) for N2-type SiN. The P state
loss shows strong T dependence. The retention from VFB = 5.5 V at 180 ◦ C
is omitted as it was not possible to program the device to VFB = 5.5 V at high
temperatures. (b) Extracted activation energy (Ea ) of P state retention loss
for N+ to Si+ nitride compositions. The VFB shift is measured at the end of
retention time of 104 s.
SiN compared to Si+ SiN. The contrasting trends in retention
loss are shown in Fig. 9(b). Note that high overall MW obtained
for Si+ SiN (see Fig. 4) gets partially offset by the higher P state
retention loss observed in these devices.
A. Program State Retention Loss
Fig. 10(a) shows the impact of temperature on retention transients from two different P states for N2-type SiN. An increased
charge loss at high temperatures is consistently observed at
starting VFB ’s of 5.5 and 2.5 V, indicating thermal emission
(followed by tunneling, a temperature insensitive process) as
the charge loss mechanism at elevated temperatures. Fig. 10(b)
shows the activation energies for different SiN compositions
measured from the P state loss, computed from the Arrhenius
equation [38] tr = t0 eEa /kT , where tr is the retention time
associated with the VFB decay and Ea is the activation energy
related to the thermal emission process. Comparing charge loss
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Fig. 11. (a) Retention transients from the P state from VFB = 5.5 V and
VFB = 2.5 V for devices having different TO thicknesses and N2-type SiN.
(b) Retention transients from VFB = 2.5 V on an expanded scale.
from the P state indicates higher activation energy associated
with electron detrapping for the N+ SiN (N1: Ea = 1.88 eV;
N2: Ea = 1.38 eV) relative to Si+ N3-type SiN (Ea = 1.0 eV).
These values indicate a reduction in electron trap depth as
the SiN becomes Si+ . This is consistent with the existing
literature [20], which also attributes the increase in charge loss
to relatively shallower trap energy levels in Si+ SiN.
Fig. 11(a) shows the impact of TO thickness on the P state
retention at room temperature measured from two different
programmed levels of VFB = 5.5 and 2.5 V. Fig. 11(b) shows a
replot of retention from VFB = 2.5 V, on a finer scale. When the
internal electric fields are high (VFB = 5.5 V), the P state retention charge loss clearly worsens with decreasing TO thickness.
This indicates the charge loss mechanism to be detrapping,
followed by the tunneling of electrons primarily from SiN to
the substrate. On the other hand, no obvious dependence on
TO thickness is observed at VFB = 2.5 V, when the internal
electric fields are considerably lower across SiO2 . However, on
an expanded scale, a thinner TO (∼3 nm) continues to show
a retention loss (although the magnitude is smaller) with time.
However, in contrast, VFB increases slightly for a thicker TO,
suggesting net charge centroid movement toward TO. Note
that charge loss is significantly lower due to reduced tunnelout probability associated with thicker TO. Therefore, intrinsic
retention loss from the programmed state can be independently
compensated for by a thicker TO, as shown previously and also
discussed in [28].
Fig. 12(a) shows the charge loss after 103 s under varying
gate bias stress for different TO thicknesses at 25 ◦ C. A positive
gate bias stress would move the charge centroid toward the BD,
eventually resulting in charge loss by tunneling via the BD to
the gate. A negative gate bias stress, on the other hand, would
push the electrons toward the tunnel dielectric, accelerating the
tunneling component via the TO. Decreasing TO thicknesses
results in increased VFB shifts. Devices with 4-nm-thick TO,
Fig. 12. Accelerated retention charge loss under varying gate bias stress
for devices (a) with varying TO thicknesses at 25 ◦ C and (b) at different
temperatures.
used extensively in this paper, show significantly higher charge
loss through TO compared to BD. Fig. 12(b) shows the charge
loss observed under gate bias stress at different temperatures.
Room temperature (25 ◦ C) results show much larger VFB shift
with negative bias, suggesting retention loss to be primarily
through the TO and significantly lower through the BD. However, at elevated temperatures (125 ◦ C), an increased charge loss
is observed through the BD due to enhanced Poole–Frenkel
conduction [39]. However, the net charge loss is still significantly lower than the leakage through the TO.
B. E State Retention Loss
Fig. 9 shows that the SiN-composition-dependent trends in E
state retention loss are exactly opposite to those of the P state
retention (which was recently reported by us for the first time
[22]). To explore this further, Fig. 13 shows the E state retention
characteristics from different erased (VFB ) levels. All SiN
compositions (except N1, which is difficult to overerase) show
good E state retention at starting VFB = −1 V. A relatively
N+ SiN (N2), while showing E saturation at VFB = −2 V
(see Fig. 3) compared to relatively Si+ films (N3, N4), shows
higher retention decay from starting VFB = −2 V, while N3
and N4 continue to show excellent charge retention at VFB =
−2 V. However, significant retention decay for N3 and N4
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 12, DECEMBER 2009
Fig. 13. E state retention decay measured at different erased MWs (VFB ) for
devices with varying SiN compositions (N2, N3, and N4).
VFB = −2 V for an N2-type SiN is largely temperature independent in the measured temperature range of 25 ◦ C to 180 ◦ C.
This is in agreement with the reported literature that describes
the discharge rate of the excess hole state as temperature
independent [40], [41] and explains that their energy states are
too deep to be thermally activated [40]. Similar T independence
of retention loss has been observed for other Si+ SiN films.
Fig. 14(a) clearly shows the T independence of E state retention
loss to the strong T -activated retention loss from the P state, as
shown in Fig. 10.
Under the influence of lower internal fields during retention,
hole tunnel-out (from SiN to substrate) probability is lower
(compared to that for electrons) due to higher hole effective
mass, deeper trap energy levels, and higher barrier heights.
Fig. 14(b) shows that, for TO thickness > 3 nm (beyond the
direct tunneling limit), the VFB shifts during retention appear to
be insensitive to oxide thickness. Once again, Fig. 14(b) clearly
shows the TO thickness independence of E state retention loss
to the strong thickness dependence of P state retention loss (see
Fig. 11) and eliminates the possibility of charge loss via the
tunneling of holes from SiN to substrate for devices with thicker
TO. Since thermal emission of trapped holes is also ruled out
[see Fig. 14(a)], the results suggests hole redistribution within
the SiN layer under the influence of internal electric fields as
a possible cause of retention decay, which is similar to the
vertical and lateral charge redistributions reported for the excess
electron state [42].
V. C ONCLUSION
Fig. 14. (a) E state retention for devices with N2-type SiN with (a) varying
temperature and (b) varying TO thicknesses.
is observed at VFB = −3 V and VFB = −3.6 V, respectively,
close to their respective E saturation levels. This indicates
that, in addition to altering electron trap depth, as discussed
before, SiN composition also alters the hole trap depth. Making
SiN composition progressively Si-richer increases the hole trap
depth, which is opposite to the reduction in electron trap depth,
as discussed earlier. Fig. 13 shows that progressively Si+ SiN
shows excellent E state retention provided that the starting E
VFB is kept away from the E saturation level. Thus, the SiN
composition provides a very valuable engineering handle for
tuning the electron and hole trap properties to optimize memory
performance and intrinsic retention loss.
To understand the physical mechanism of E state retention
loss, Fig. 14(a) and (b) shows the impact of varying the temperature and TO thickness on the E state retention, respectively. Fig. 14(a) shows that the E state retention measured at
Engineering the SiN composition offers the possibility for
the optimization of CTF memory performance and reliability.
The trends are visibly reflected on MW, P/E speeds, and charge
retention characteristics. Progressively varying the SiN composition from N+ to Si+ increases overerase capability and hence
increases the overall MW. The lack of overerase in N+ SiN is
reflective of low hole trap density relative to Si+ SiN. The E
in N+ SiN is primarily due to electron detrapping, unlike that
in Si+ SiN which exhibits both electron detrapping and hole
trapping during E. The position of charge centroid at the end
of P operation was found to be located at the SiN/Al2 O3 interface. Contrasting trends in P and E state retentions have been
identified. The P state charge loss increases as SiN becomes
Si+ , while E state charge loss increases as SiN becomes N+ .
We have clearly demonstrated that SiN composition strongly
alters both electron and hole trap depths: The electron trap
depth reduces and the hole trap depth increases as SiN is varied
from N+ to Si+ . The P state charge loss is due to thermal detrapping followed by the tunneling of carriers primarily through
TO at lower temperatures and thermal detrapping followed
by tunneling via both TO and BD at elevated temperatures,
consistent with existing literature. Higher activation energy is
associated with electron detrapping in N+ SiN relative to Si+
SiN. The E state retention charge loss is strongly affected by
SiN composition and decreases as SiN becomes Si+ , in contrast
to that observed for P state loss, but is found to be independent
of temperature or TO thickness. The retention decay is hence
attributed to charge redistribution under the influence of internal
SANDHYA et al.: IMPACT OF SiN COMPOSITION VARIATION ON MEMORY PERFORMANCE AND RELIABILITY
electric fields within the SiN. Distinct tradeoffs between P and
E states necessitate the designing of optimal SiN composition,
which would provide efficient performance with acceptable
reliability. Thus, the use of a moderate Si+ SiN with thicker
reliable tunnel and BD is a promising approach to deliver
the performance and reliability requirements suitable for MLC
operation.
[20]
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C. Sandhya (S’07) received the M.Tech. degree in
microelectronics from the Indian Institute of Technology Bombay, Mumbai, India, in 2006, where she
is currently working toward the Ph.D. degree in
electrical engineering.
From July 2008 to October 2008, she was a
graduate student intern with Samsung Semiconductor R&D Center, Hwasung, Korea. Her research interests are in the field of CTF Flash optimization
through device characterization and understanding
the device physics through modeling, design, and
simulation.
Ms. Sandhya is a recipient of the SRC (GRC) fellowship.
Apoorva B. Oak is currently working toward the
B.Tech. and M.Tech. degrees (dual-degree program)
in microelectronics from the Department of Electrical Engineering, Indian Institute of Technology
Bombay, Mumbai, India, and will graduate in 2010.
His research interests include CTF memory characterization and simulation.
Nihit Chattar received the B.E. degree in electronics and telecommunication from the Institute of
Engineering and Technology, Indore, India, in 2007
and the M.Tech. degree in microelectronics from the
Indian Institute of Technology Bombay, Mumbai,
India, in 2009.
Ameya S. Joshi is currently working toward the
M.S. degree at the Indian Institute of Technology
Bombay, Mumbai, India, where he is currently working on the characterization and modeling of charge
trap Flash memories for his Master’s dissertation.
Udayan Ganguly received the B.Tech. degree from
the Indian Institute of Technology Madras, Chennai,
India, in 2000 and the Ph.D. degree from Cornell
University, Ithaca, NY, in 2006.
He is currently a Device and Integration Engineer
with the Front End Products Group, Applied Materials, Santa Clara, CA, focusing on the development
of applications for the company’s front-end tools in
Flash memory technologies.
C. Olsen, photograph and biography not available at the time of publication.
S. M. Seutter, photograph and biography not available at the time of
publication.
L. Date, photograph and biography not available at the time of publication.
R. Hung, photograph and biography not available at the time of publication.
Juzer Vasi (M’74–SM’96–F’04) received the
B.Tech. degree in electrical engineering from the
Indian Institute of Technology (IIT) Bombay,
Mumbai, India, in 1969 and the Ph.D. from the
Johns Hopkins University, Baltimore, MD, in 1973.
He was with the Johns Hopkins University and
IIT Delhi, New Delhi, India, before moving to IIT
Bombay in 1981, where he is currently a Professor.
His research interests are CMOS devices, technology, and design. He has worked on MOS insulators,
radiation effects in MOS devices, degradation and
reliability of MOS devices, modeling and simulation of MOS devices, and
MOS-based NVMs.
Dr. Vasi was the Editor of the IEEE T RANSACTIONS ON E LECTRON
D EVICES for MOS Devices and Technology and a Distinguished Lecturer of
the IEEE Electron Devices Society. He is a Fellow of the Indian National
Academy of Engineering and IETE.
Souvik Mahapatra (M’02–SM’07) received the
Ph.D. degree in electrical engineering from the
Indian Institute of Technology (IIT) Bombay,
Mumbai, India, in 1999.
He was with Bell Laboratories, Murray Hill, NJ,
from 2000 to 2001. Since 2002, he has been with the
Department of Electrical Engineering, IIT Bombay,
where he is currently a Professor. He holds an honorary graduate faculty position at Purdue University,
West Lafayette, IN. He has published more than
90 papers in peer-reviewed journals and conferences;
delivered invited talks at leading international conferences in the U.S., Europe,
and Asia Pacific, including IEEE IEDM; and served as a Reviewer of several
international journals and conferences. His research interests are the characterization, modeling, and simulation of CMOS and Flash memory devices, and
device reliability.
Dr. Mahapatra is a Distinguished Lecturer of IEEE EDS. He has delivered
reliability tutorials at the IEEE IRPS.