IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 2, FEBRUARY 2009
171
Effect of SiN on Performance and Reliability of
Charge Trap Flash (CTF) Under Fowler–Nordheim
Tunneling Program/Erase Operation
C. Sandhya, Student Member, IEEE, Udayan Ganguly, Nihit Chattar, Christopher Olsen, Sean M. Seutter,
Lucien Date, Raymond Hung, Juzer M. Vasi, Fellow, IEEE, and Souvik Mahapatra, Senior Member, IEEE
Abstract—Silicon-nitride trap layer stoichiometry in charge
trap flash (CTF) memory strongly impacts electron and hole
trap properties, memory performance, and reliability. Important
tradeoffs between program/erase (P/E) levels (memory window),
P- and E-state retention loss, and E-state window closure during
cycling are shown. Increasing the Si richness of the SiN layer improves memory window, cycling endurance, and E-state retention
loss but at the cost of higher P-state retention loss. The choice
of SiN stoichiometry to optimize CTF memory performance and
reliability is discussed.
Index Terms—Charge trap flash (CTF), cycling endurance,
program/erase (P/E) window, retention, SANOS, silicon nitride
(SiN), SONOS.
I. I NTRODUCTION
C
ONVENTIONAL floating-gate (FG) Flash devices suffer
from several scaling challenges beyond the 3× NAND
node [1]. Silicon nitride (SiN) storage-based charge trap flash
(CTF) memories have improved immunity to pinhole defects,
shown reduced cell-to-cell interference, and enhanced vertical
and planar scalability and conventional CMOS compatible fabrication process flow, making it one of the likely replacements
to FG technology [1]–[5]. 2-bit Multi-Level Cell (MLC) operation has been demonstrated for a TANOS gate-stack with
endurance issues (∼0.5 V erase VT shift after 103 cycles) [6].
In the recent past, engineering of SiN trap layer (SiN/SiON/SiN
[2], [3], graded SiN [4], and SiN/Al2 O3 /SiN [5]) has been
explored for optimizing memory performance and reliability.
Large memory window and better endurance (<0.25-V E-state
degradation after 104 cycles) have been shown, but retention
still remains an important concern. Improved retention may be
achieved by using a thicker or engineered tunnel oxide [7],
but not without issues of program/erase (P/E) speed reduction
or cycling endurance degradation, respectively. Therefore, the
Manuscript received November 7, 2008. First published December 31, 2008;
current version published January 28, 2009. IIT Bombay would like to acknowledge SRC (GRC) for financial support. The review of this letter was arranged
by Editor T. Wang.
C. Sandhya, N. Chattar, J. M. Vasi, and S. Mahapatra are with the Department of Electrical Engineering, Indian Institute of Technology Bombay,
Mumbai 400 076, India (e-mail: [email protected]; [email protected];
[email protected]; [email protected]).
U. Ganguly, C. Olsen, S. M. Seutter, L. Date, and R. Hung are with the Applied Materials, Santa Clara, CA 95054-3299 USA (e-mail: udayan_ganguly@
amat.com; [email protected]; [email protected]; lucien_date@
amat.com; [email protected]).
Digital Object Identifier 10.1109/LED.2008.2009552
choice of SiN composition is still a key design parameter
influencing CTF performance and reliability in single-layer
SiN or advanced SiN engineering (multilayer, graded, etc.)
approaches [2], [3]. While several earlier literatures have dealt
with the composition-dependent nature of traps in SiN [8], [9],
the fundamental influence of SiN composition on electrical trap
properties and, more importantly, on CTF performance and
reliability needs to be studied in detail.
This letter focuses on a systematic study of impact of SiN
trap layer composition on memory window, retention loss, and
cycling endurance for SANOS gate stacks. Si-to-N ratio of the
SiN layer explicitly controls electron and hole trap properties
and, therefore, the magnitude of stored charges in P and E states
and hence the overall memory window. Retention charge loss
from both P and E states and the memory-window closure due
to E-state degradation during P/E cycling also show systematic
dependence on the Si-to-N ratio of the SiN layer. These useful
insights would help develop optimized SiN charge storage layer
for reliable MLC operation of CTF memory.
II. R ESULTS AND D ISCUSSION
In this letter, large-area (100 × 100 μm2 ) n-substrate capacitors with p+ S/D diffusion and n+ poly-Si gate were used as
shown in the inset of Fig. 1. The gate stack consists of thermal
SiO2 tunnel oxide (40 Å), LPCVD SiN charge storage layer
(60 Å), and CVD Al2 O3 blocking dielectric (120 Å). The
properties of the SiN trap layer were controlled by varying
Si2 H6 and NH3 gas flow ratios and deposition temperature. SiN
films for samples D1 and D3–D6 were deposited at 800 ◦ C
and that for D2 and D7–D9 were deposited at 650 ◦ C. Such
deposition conditions are known to change the SiN composition
including the H-content [8]. Refractive indices1 (RI’s) of 1.97
(N-rich or N+ ) to 2.13 (Si-rich or Si+ ) were measured for
various SiN films.2 XPS measurement showed approximately
5% N-content change over the stated RI range for 650 ◦ C films.
RBS/HFS measurements show 3%–4% higher H content at the
expense of similarly lower N% for 650-◦ C films compared to
800 ◦ C at identical RI. Gate-stack EOT of 12.3 ± 0.3 nm was
measured for all splits. Flatband voltage (VFB ) shifts obtained
from 1-MHz HFCV measurements were used to determine P, E,
cycling endurance, and retention.
1 RI was measured at wavelength of 633 nm for thick films (thickness >
220 Å) for accuracy.
2 RI of stoichiometric SiN is ∼2.01 [8].
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Fig. 1. P/E transients for different nitride compositions (N+ , D2 and Si+ ,
D9). Si+ nitrides tend to break down earlier, and this limits the maximum
P level in these devices. On the other hand, N+ nitrides can be programmed
to much higher P levels but are limited in their E capability. Inset: Schematic of
SANOS capacitors with p+ implants for supplying minority charge carriers.
Fig. 1 shows the measured P and E transients for N+ (D2)
and Si+ (D9) stacks under identical P/E biases. N+ stacks
can be programmed to a high P level but have very low overerase capability. Si+ stacks exhibit lower P level (limited by
breakdown), although significant overerase is observed. Similar
Si+ - and N+ -dependent P/E results were previously reported
using SONOS devices with deposited HTO top oxide [2]. The
overall memory window and the RI data3 are also shown.
Good correlation is observed between overerase capability and
RI, which is an indicator of composition. The difference in E
performance between D1 (RI = 1.97), D3 (RI = 1.99), and
D7 (RI = 2.006), despite somewhat close RI values, is a
reflection of the progressively excess Si (RBS shows that D7 is
∼2% more Si-rich than D3, while D1 has 1% lower Si than D3),
indicating strong impact of SiN composition on the P/E performance. In addition, H- and N-content difference due to the
different deposition temperature may also contribute to the trap
layer properties. In this letter, we have chosen the E behavior
as an indicator of SiN composition to demonstrate remarkable
correlations with the other memory performance metrics, i.e.,
retention loss and endurance memory-window degradation.
From a memory performance perspective, the overerase capability of Si+ SiN can be leveraged to split the overall memory
window between P and E levels, which results in higher overall
window for identical P/E bias, as shown. Splitting a given total
memory window between P and E levels requires lower P/E
biases, which can potentially improve memory reliability. It
results in lower overall P-state charge, particularly important for
MLC operation, thereby reducing internal fields and potentially
reducing charge loss during retention.
Fig. 3 shows the measured VFB shifts due to loss of electrons from the programmed state and loss of holes from the
overerased state4 as a function of retention time (all terminals
grounded) on gate stacks having different SiN composition. All
devices were programmed and erased to identical P/E levels
to have identical internal electric fields in the tunnel oxide
3 RI, although not capable of providing a complete description of the SiN
film, is shown as a first-order guide to reflect the relative Si-to-N ratio.
4 The N-rich device (D2) cannot be overerased and, hence, does not show
retention loss from the E state.
IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 2, FEBRUARY 2009
Fig. 2. P/E state VFB and memory window for nitride composition variations
from N+ to Si+ as indicated by RI. Splits D2, D7, D8, and D9 were deposited
at 650 ◦ C, while splits D1, D3, D4, D5, and D6 were deposited at 800 ◦ C.
A 3%–4% higher H content is observed with corresponding decrease in N
concentration at lower deposition temperature of 650 ◦ C than at 800 ◦ C. Thus,
for nearly similar RI values, there exists a compositional difference which is
exhibited in terms of P and E levels (and, hence, the memory window) in the
different stacks. The P level corresponds to 40-ms, and E level corresponds to
400-ms accumulated pulsewidths.
and blocking dielectric during retention. As SiN composition
is varied from N+ to Si+ (at 650 ◦ C deposition temperature),
the electron loss from P state increases [9], [10], while interestingly, the loss of holes from E state reduces as shown. Fig. 3
shows that the retention charge loss from the P state increases
and correlates strongly with the increase (more negative) in E
saturation level, indicating a general performance tradeoff. The
increased retention loss from P state suggests reduction in electron trap depth [11] as the SiN is made Si+ . Indeed, Arrheniustype fitting of temperature-dependent retention measurements
(not explicitly shown in this letter) results in activation energies
(EA ) of 0.23 eV for device D1 (RI = 1.985) and 0.13 eV for
device D7 (RI = 2.006).5 Note that the compositions of D7
are further apart (3% higher Si, 3% lower N, and similar H
content) from that of D1 than the RI difference would suggest
due to the difference in deposition temperature as confirmed
by RBS/HFS. This suggests relatively deeper electron traps
in N+ SiN. The activation energy for N+ SiN is in close
agreement with published report [5]. Surprisingly, the increase
in E window level (see Fig. 2) and the reduced retention loss
from E state (see Fig. 3) suggest an increase in hole trap depth
as the SiN layer is made Si+ . The P- versus E-state retention
tradeoff with SiN composition presents the opportunity for
an optimized (moderately Si+ ) SiN with improving memory
window. Note that high overall memory window obtained for
Si+ SiN (see Fig. 2) is traded off by the higher P-state retention
loss observed in these devices. This retention loss can be
independently compensated for by a thicker tunnel oxide6 [5].
5 The activation energy of charge loss is influenced by emission from traps
among other processes. It is indicative of the contribution of relative trap depths
(but not a measure of the actual trap depths) in the two nitride types.
6 It has been found (by retention experiments under positive and negative gate
bias stress) that P-state electron loss takes place via the tunnel oxide. Retention
loss has been found to be negligible for devices having 60-Å tunnel oxide, not
explicitly shown in this letter. A thicker tunnel oxide implies lower P/E speed
unless large P/E biases are used, which, in turn, causes degradation of the tunnel
and/or blocking dielectric during cycling and enhances postcycling retention loss.
SANDHYA et al.: EFFECT OF SiN ON PERFORMANCE AND RELIABILITY OF CHARGE TRAP FLASH
173
the best P-state retention (N+ SiN) translates to the smallest
postcycling window—a challenge for MLC operation. Contrary
to P-state, the E-state retention improves with memory window
(more Si+ ) by adding a further tradeoff. Thus, moderate Si+
SiN with thicker reliable tunnel and blocking dielectrics is a
promising approach to deliver the performance and reliability
requirements for MLC operation.
R EFERENCES
Fig. 3. Retention loss from P and E states for different nitride compositions
(identical stack thickness). Note: D2 cannot be erased to VFB < 0 V, and
hence, E-state retention is measurement excluded. Inset: RT retention loss from
P state (identical starting VFB ) versus initial E state VFB for stacks having
different nitride compositions but identical thickness.
Fig. 4. P/E cycling endurance showing P- and E-state degradation for devices
having different nitride compositions but identical stack thickness. Inset: Degradation in E state during cycling versus initial E state VFB for different nitride
compositions.
III. C ONCLUSION
The impact of SiN composition on memory window, cycling
endurance, and charge retention of CTF memories is studied.
Making SiN from N+ to Si+ increases hole trap depth but
reduces electron trap depth, increases overerase capability, and
increases overall memory window by splitting between P and
E states, which is easier to control and requires lower P/E
bias. In addition to memory-window versus P-state retention
tradeoff, postcycling window closure strongly correlates with
memory window and improves as SiN is made Si+ . Indeed,
[1] K. Kim, “Technology for sub-50 nm DRAM and NAND Flash manufacturing,” in IEDM Tech. Dig., 2005, pp. 333–336.
[2] C. Sandhya, U. Ganguly, K. K. Singh, P. K. Singh, C. Olsen, S. Seutter,
G. Conti, K. Ahmed, N. Krishna, J. Vasi, and S. Mahapatra, “Nitride
engineering and the effect of interfaces on Charge Trap Flash performance
and reliability,” in Proc. Int. Reliab. Phys. Symp., 2008, pp. 406–412.
[3] C. Sandhya, U. Ganguly, K. K. Singh, C. Olsen, S. Seutter, G. Conti,
K. Ahmed, N. Krishna, J. Vasi, and S. Mahapatra, “The effect of band gap
engineering of the nitride storage node on performance and reliability of
Charge Trap Flash,” in Proc. Int. Symp. Phys. Fail. Anal. Integr. Circuits,
2008, pp. 224–230.
[4] H. C. Chien, C. H. Kao, W. Chang, and T. K. Tsai, “Two-bit SONOS type
Flash using a band engineering in the nitride layer,” Microelectron. Eng.,
vol. 80, no. 1, pp. 256–260, Jun. 2005.
[5] Z. L. Huo, J. Yang, S. Lim, S. Baik, J. Lee, J. H. Han, I. Yeo,
U. Chung, J. T. Moon, and B. Ryu, “Band engineered charge trap layer
for highly reliable MLC Flash memory,” in VLSI Symp. Tech. Dig., 2007,
pp. 138–139.
[6] D. Kwak, J. Park, K. Kim, Y. Yim, S. Ahn, Y. Park, J. Kim, W. Jeong,
J. Kim, M. Park, B. Yoo, S. Song, H. Kim, J. Sim, S. Kwon, B. Hwang,
H. Park, S. Kim, Y. Lee, H. Shin, N. Yim, K. Lee, M. Kim, Y. Lee, J. Park,
S. Park, J. Jung, and K. Kim, “Integration technology of 30 nm generation
multi-level NAND Flash for 64 Gb NAND Flash memory,” in VLSI Symp.
Tech. Dig., 2007, pp. 12–13.
[7] S. Y. Wang, H. T. Lue, E. K. Lai, L. W. Yang, T. Yang, K. C. Chen,
J. Gong, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Reliability and processing
effects of band-gap engineered SONOS (BE-SONOS) Flash memory,” in
Proc. Int. Reliab. Phys. Symp., 2007, pp. 171–176.
[8] J. Robertson and M. J. Powell, “Gap states in silicon nitride,” Appl. Phys.
Lett., vol. 44, no. 4, pp. 415–417, Feb. 1984.
[9] M. Peterson and Y. Roizin, “Density functional theory study of deep traps
in silicon nitride memories,” Appl. Phys. Lett., vol. 89, no. 5, pp. 053 5111–053 511-3, Aug. 2006.
[10] S. M. Sze, “Dielectric and polysilicon deposition, principles of chemical
vapor deposition,” in VLSI Technology, 2nd ed. New York: McGrawHill, 1988, ch. 6, p. 261.
[11] T. H. Kim, I. H. Park, J. D. Lee, H. C. Shin, and B. G. Park, “Electron
trap density distribution of Si-rich silicon nitride extracted using the modified negative charge decay model of silicon-oxide-nitride-oxide-silicon
structure at elevated temperatures,” App. Phys. Lett., vol. 89, no. 6,
pp. 63 508-1–63 508-3, Aug. 2006.
[12] S. J. Wrazien, Y. Zhao, J. D. Krayer, and M. H. White, “Characterization
of SONOS oxynitride nonvolatile semiconductor memory devices,” Solid
State Electron., vol. 47, no. 5, pp. 885–891, May 2003.
[13] A. Paul, C. Sridhar, S. Gedam, and S. Mahapatra, “Comprehensive simulation of program, erase and retention in charge trapping Flash memories,”
in IEDM Tech. Dig., 2006, pp. 393–396.