CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
SAiv1PLED DATA MODELS OF
il
VOLTAGE Iv1ULTIPLIERS
A thesis submitted in partial satisfaction of the
requirements for the degree of Master of Science in
Engineering
by
Edward Michael Skei
June, 1978
The Thesis of Edward Ivlichael Skei is approved:
California State University, Northridge
ii
ACKNOWLEDGErviENTS
The author wishes to thank Dr. Hashimoto and
Dr. Hriber for their help and encouragement, Semtech
Corporation for its support, and the author's family
for their help, encouragement, support and understanding.
iii
TABLE OF CONTENTS
iii
Acknowledgements
List of Figures
v
List of Symbols
vi
vii
Abstract
Chapter I, Introduction
1
Chapter II, Voltage !IIul tiplier Operation
4
Chapter III, The State Transition Equations
10
Chapter IV, Limitations of the Model
19
Chapter V, Z Transform of the State Transition
Equation
20
Chapter VI, Multiplier Transfer Functions
27
Chapter VII, The Output Capacitor
32
Chapter VIII, Closed Loop Multiplier Systems
36
Chapter IX, Conclusions
40
Bibliography
42
iv
TABLE OF FIGURES
Page
Figure 1a
1b
Figure 2a
2b
Figure .3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 1.3
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
lVtinimal voltage multiplier
Voltage doubler
Series multiplier
Parallel multiplier
Negative input
Zero input
Positive input
State variables of the series multiplier
Positive input at t=nTs
State equations of X' (nTs)
Negative input at t=(n+~)Ts
State equations of X((n+l)Ts)
The system matrices
Equations for X(OO)
Tridiagonal form for X(OO)
Solution for X(OO)
H1 (Z) ~nd H2 (Z) for unity capacitor
rat1o
H1 (Z) ~nd H2 (z) for optimum capacitor
rat1o
System model for the output capacitor
Closed loop multiplier system
Redrawn closed loop system
v
2
2
5
5
6
7
8
11
1.3
14
16
17
18
22
24
25
29
.30
.34
.37
.38
LIST OF SYMBOLS
A
B
c
c.l
co
D
G(s)
Hl
Hz
H3
H4
H5
IL
lVl
N
n
Q
r
t
'I' s
u
vs
X
X'
y
z
z
System matrix
System matrix
System matrix
ith capacitor
Output capacitor
System matrix
Linear transfer function
Z transfer function of the charge Q(Z)
Z transfer function of the voltage Vs(Z)
Z transfer function of the current IL(Z)
Z transfer function of the voltage Vs(Z)
~ transfer function of G(s)
Load current
General matrix
Number of multiplier capacitors
nth cycle
Charge due to the load
Reference input
Time
Sampling interval
Input vector
Voltage source
State vector
Transitional state vector
Output vector
Z transform variable
Z transform operator
vi
ABSTRACT
SAMPLED DATA MODELS OF
VOLTAGE mULTIPLIERS
by
Edward Wiichael Skei
Master of Science in Engineering
A method for developing sampled data models for
voltage multipliers using Z transform methods is developed.
The model is a Z transform transfer function relating the
output voltage of the multiplier to input voltage and the
load current.
The diodes of the multiplier are treated
as synchronous switches and capacitor voltages are chosen
as state variables.
A system of difference equations is
written in standard state variable form by considering
the operation of the multiplier over one state transition.
The solution is found by taking the Z transform of the
difference equations in the same manner that LaPlace
transforms are used in the solution of differential equations.
The resulting set of algebraic equations can be
solved using matrix techniques to find the desired Z
vii
'
transform transfer functions.
The transfer function of
the series multiplier is used to find the capacitor ratio
for optimum steady state performance with minimum total
capacitance.
The pole and zero locations of the transfer
functions for a number of series multipliers with unity
and optimum capacitor ratios are listed.
The usage of
the model in closed loop systems in conjunction with
continuous elements for compensation is discussed.
viii
'
CHAPTER I
INTRODUCTION
Sampled data techniques are usually used to analyze
digital or linear systems with digital computers as controllers.
These techniques are particularly useful in
the analysis of closed loop voltage multiplier systems
since the state of the multiplier changes at periodic
intervals which may be considered as sampling intervals.
This unique approach to model the voltage multiplier's
nonlinear network of diodes and capacitors provides the
first model that describes the multiplier's dynamic behavior.
Previous models, based on charge conservation,
have considered only the steady state response of voltage
multipliers to static load currents.
Voltage multipliers are used in power supplies to
generate a D.C. voltage from an A.C. voltage source.
The simplest forms of the voltage multiplier are the
single rectifier and capacitor shown in Figure la and
the voltage doubler shown in Figure lb.
These two forms
are incorporated in virtually all line operated electronic
equipment.
Multipliers of many stages are frequently
used in high voltage power supplies to reduce the size and
step-up ratio of the power transformer, or in lower voltage
1
2
Figure la.
Iilinimal voltage multiplier
vs
Figure lb.
Voltage doubler
3
cases to eliminate the transformer altogether.
Series elements are generally used in low voltage
power supplies for regulation, but at high output voltages
series regulators are impractical and other methods for
regulation are employed.
Television receivers require
12,000 volts to 30,000 volts to operate the picture tube.
The high voltage is generated by multiplying the output
of the horizontal oscillator transformer with a voltage
multiplier.
The output of the horizontal oscillator is
regulated and the performance of the high voltage power
supply depends directly on the performance of the voltage
multiplier.
For multipliers with few stages this method
of regulation frequently provides acceptable performance,
but the load regulation of voltage multipliers degrades
rapidly as the number of stages is increased.
The alter-
native to using arbitrarily large capacitors in the multiplier to provide regulation is to sense the output of the
multiplier and use gain and feedback to control the output
voltage.
Whenever feedback is used to alter the performance of
a system instability can result.
Methods for determining
the stability of closed loop continuous and sampled data
systems have been developed but before these methods may be
applied to closed loop systems using multipliers an accurate model for the voltage multiplier is necessary.
objective of this work is to derive such a model.
The
CHAPTER II
VOLTAGE MULTIPLIER OPERATION
Although a variety of voltage multiplier configurations are possible, two basic types are commonly used;
the series multiplier and the parallel multiplier.
Examples of these multiplier types are shown in Figure 2.
The series multiplier is usually used in high voltage
applications since the voltage stress on all but the output filter capacitor is either less than or equal to the
peak to peak input voltage.
Voltage multiplication for the series configuration
shown in Figure 2a is analyzed by assuming that the diodes
are ideal and operate as switches as shown in Figure J,
Figure 4, and Figure 5·
Figure J is the equivalent
circuit when the input attains its peak negative value
and charges the input capacitor
c7 .
The other capacitors
of the multiplier are shorted together in pairs as shown
in the figure.
Figure 4 is the equivalent circuit when
the input is at neither the positive nor the negative
peak.
Since none of the diodes are assumed to be con-
ducting for this input, all the switches are open.
Figure 5 is the equivalent circuit when the input is at
the positive peak, and the closed switches are again
4
5
Figure 2a.
Figure 2b.
Series multiplier
Parallel multiplier
6
Figure J.
Negative input
7
2V
s -
C
2
~2V
-
-
Figure 4.
2V
s
s
Zero input
8
2V
2V
2V
s -
8
+
_
cl
CJ
-:-l-2V
2
-
s
s -
Figure 5·
Positive input
9
shorting pairs of capacitors.
The periodic shorting
of the capacitors tends to equalize their voltages and
under conditions of no load the nominal capacitor voltages
shown in the figures satisfy Kirchoff's laws.
The figures also illustrate that the input voltage
wave form determines the circuit configuration.
If the
input wave form is a square wave then the circuit is
alternately that of Figure 3 and Figure 5·
If the input
is a sine wave the diodes are considered to conduct only
at the peaks and the circuit configuration is that of
Figure 4, and only momentarily in the configurations of
Figure 3 and Figure 5·
The circuit configurations that
result from other input wave forms or other multiplier
circuits are similarly determined by representing the
diodes as controlled switches.
Once the circuit config-
urations are determined state variables are assigned and
the state transition equations may be written.
CHAPTER III
THE STATE TRANSITION EQUATIONS
The series multiplier of Figure 2a was chosen to
illustrate the assignment of state variables and the
formulation of the state transition equations because
its static characteristics have previously been modeled
on the basis of charge conservation.
Not unexpectedly
the sampled data model predicts the same performance
under steady state conditions.
The input is an amplitude modulated sine wave, but
since the diodes are considered to conduct only during
the positive and negative peaks the sine wave may be
replaced by positive and negative Dirac impulse functions.
The period of the sine wave is the sampling interval Ts.
The positive impulses occur at t=nTs and the negative
impulses occur at t=(n+t)Ts·
The resulting circuit con-
figuration is shown in Figure 6.
The multiplier is con-
nected to the load and the output capacitor during the
positive input peak and a charge of Q(nTs) is transferred
from the multiplier to the output capacitor during the
instantaneous switch closure.
Q(nTs) will be treated
as a system input so that the output capacitor can be
modeled separately as a sample and hold device.
10
The
11
X
4
Figure 6.
State variables of the series multiplier.
12
other system input, the input voltage source, is connected
to the multiplier during both the positive and negative
input peaks implying a sampling rate twice as high as
A single sampling rate may be used to characterize the system if the magnitude of each negative peak
is assumed to be equal to the magnitude of the positive
peak that preceeds it.
The voltages of the A.C. leg capacitors shown in
Figure 6 are chosen as the state variables.
necessary to assign state variables to the
It is not
D.c.
leg ca-,
pacitors since they are periodically shorted to the
A.c.
leg capacitors and can be described in terms of the chosen
state variables.
The state of the system X(nTs) prior to the positive
input pulse is shown in Figure 7•
When t=nTs the
switches close, the input is at the positive peak, and
a charge Q(nT6
)
is delivered to the load by the series-
parallel capacitor network formed by the switch closures.
The resulting state X'(nTs) is easily found using
Kirchoff's laws and the resulting equations are shown
in Figure 8.
The output of the system Y(nTs) is the peak output
voltage of the multiplier and is the sum of the state
variables (the A.C. leg capacitor voltages) and the peak
input voltage V(nTs).
Thus the output Y(nTs) is simply
Y(nTs) = (l,l,l,l)X'(nTs) + V(nTs)
(III-1)
lJ
~&------~~
t=nT s
Q(nT
8
t=nT=--]_
Cz
t=nT s
+
~c
6
+
Figure 7•
~ositive
input at t=nT 8
)
14
Xi(nT 6
1
)
cz
X' (nT )
2
s
=
Xj(nT8
X4,(nT 8
c2 +c
0
)
)1
0
3
0
0
0
b_
0
0
Cz+C3
c4
C4+G5
0
I
I
Figure 8.
_l
c~~+c5
.,~6~.
Ct,+.._,7
lx1 CnT
8
Xz (nT8
-1
)1
0
cl
-1
)
0
C2+CJ
+
0
~
C '"
II
I x4
6"1""7:
-t
x3 (nT8 )
I
0
c4.;-c5
Ii
.. I
-1
C6+C7
I
I
I
(nT"'):
IQ(nTs)
-C6
I
C6·i-C7.
State equations of X'(nT 8
)
Vs(nTs)
...
15
At t=nTs all the switches open and remain open until
the negative peak input at t=(n+t)Ts as shown in Figure 9.
The circuit equations that result are shown in Figure 10.
The peak negative voltage has the same magnitude as the
positive peak that precedes it, V(nTs),
At t=(n+t)T!
the switches open again and one state transition has been
completed; the resulting state is X((n+1)Ts)•
The equations of Figure 8 and Figure 10 are written
in matrix notation with U(nTs), the input vector, representing the system inputs V(nTs) and Q(nTs):
X'(nTs) = A1X(nTs) + B1U(nTs)
X((n+1)Ts) = A 2 X'(nTs) + B2 U(nTs)
(III-2)
(III-3)
(III-4)
The indicated matrix multiplication is performed so
that the system may be characterized in the standard state
variable form:
= A2A1X(nTs)
+ (A2B1+B 2 )U(nTs)
Y(nTs) = C1A1X(nTs) + (C 1B1+D 1 )U(nTs)
(III-5)
X((n+l)Ts) = AX(nTs) + BU(nTs)
(III-7)
Y(nT s ) = CX(nT s ) + DU(nT s )
(III-8)
X((n+1)Ts)
(III-6)
or
The A, B, C, and D matrices are shown in Figure 11,
and the sampled data state variable formulation is complete.
16
Figure 9.
Negative input at
t=(n+~)T •
8
17
0
0
0
0
0
0
1
0
0
Figure 10.
0
State equations of X((n+1)T8
).
18
2
c2
1
C +C ( + C ·tC )
1 2
2 J
C2CJ
(c 1+c 2 )(c 2+cJ)
c 2c
2
(C 2+CJ)(CJ+c 4 )
_1_(--'2_ + _4_)
1
A
=
cz
c2
C3+C4C2+CJ
C4+C5
c 4 c~
0
(C4+C5)(c5+C6)
0
0
. 0
0
c4c5
(CJ+C4) (cli+C5)
0
c2
c2
_1_(-.:::..s._ + _6_)
C5+C6C4+C5
C6+C7
0
0
B
=
0
0
c
=
D
=
Figure 11.
1
The system matrices.
c6~
( C5+C6 }( C6+C7
0
CHAPTER IV
LIMITATIONS OF THE NlODEL
Very few assumptions were made in the development of
the state variable formulation, but the model is only
valid when the assumptions are justified.
The diodes
were considered to be ideal, and further, to conduct during every peak of the input wave form.
always the case.
This is not
Under conditions of little or no load
current the multiplier operates as a peak detector.
If
no load current is drawn from the multiplier reducing the
peak input voltage will not reduce the output voltage because none of the diodes are forward conducting, and the
system can not be characterized by a linear model.
To insure that the diodes will conduct on a cycle by
cycle basis a nominal operating condition of input voltage
and load current is assumed, and the model is valid for
small displacements from this operating point.
19
CHAPTER V
Z TRANSFOR!'Ji OF THE
STATE TRANSITION EQUATION
The formulation of the multiplier model in standard
state variable form is convenient because methods have
been developed to solve system equations in this form.
Since the system is represented as a sampled data system
the Z transform of the state equations is taken:
L
[X((n+l)Ts) = AX(nTs) + BU(nTs)l
~~(nTs) = CX(nTs) + DU(nTs~
(V-1)
(V-2)
or
ZX(Z) - ZX(O) = AX(Z) + BU(Z)
(V-3)
Y(Z) = CX(Z) + DU(Z)
(V-4)
The solution to these equations is found directly
using matrix algebra:
X(Z) = Z(ZI-A)- 1X(O) + (ZI-A)- 1BU(Z)
Y(Z) = CX(Z) + DU(Z)
(V-5)
(V-6)
X(O) is the initial state vector at t=O and causes
a transient term in the solution.
Since a transfer
function relationship between the input and output is
desired the system is assumed to be in equilibrium at
t=O so that X(O)=O.
Substituting the expression for
20
21
X(Z) into the expression for Y(Z) with X(O)=O:
Y(Z) = (C(ZI-A)- 1B+D)U(Z)
(V-7)
or
Y(Z)
= H(Z)U{Z)
(V-8)
The expression for Y(Z) is in the desired transfer
function form.
Although it is possible to find the gen-
eral transfer function H(Z) in terms of the Ci the equations become unwieldy for A matrices that are larger
than
JxJ.
The steady state solution in terms of the
c.
~
is not as difficult and is found by applying the Z transform final theorem to the expressions for X(Z) and Y(Z).
Step inputs for the load and input voltage are used with
magnitudes Q and Vs respectively, and have the following
Z transforms:
U(Z) =
(V-9)
Then using the Z transform final value theorem:
X(OO) =limit (Z-1)(ZI-A)- 1BU(Z)
(V-10)
Z+-1
or
Q
(I-A)X(CD) = B
(V-11)
vs
The formulation of equation (V-11) using the matrices developed in Chapter III is shown in Figure 12.
The solution for X(OO) is found by performing the indi-
- --------------
~--
---
-
--·
------------
-----·-~-------------
-
-~~~---
22
0
0
X (<DII
0
0
3
0
0
0
Figure 12.
Equations for X(OO).
1
,
I
lx .(co)l
•
1r
I
2J
cated subtraction along the main diagonal and cancelling
common multiplicative terms in the rows of (I-A) and B.
'I'he resulting form is nearly symmetrical and a single row
operation yields the symmetrical tridiagonal form shown
in Figure 1J.
The reduction to a symmetrical tridiagonal
form is useful because the inverse may be found by an
explicit process.
The tridiagonal form is decomposed
into the product of an upper triangular matrix with its
transpose.
The inverse of the triangular matrix is found
directly and the inverse of the original matrix is known
using the matrix identity of equation (V-12):
(V-12)
Cholesky's method gives the result shown in Figure 14
which may be checked by multiplication with the matrix in
Figure 1J.
The steady state output may now be found:
Y(OO) =limit (Z-1)(CX(Z) + DU(Z))
( V-13)
Z+1
Y(CO)
= CX(OO)
+ D
Q
(V-14)
~n
After performing the algebra indicated
equation
(V-14) the simple result of equation (V-15) is found:
Y(CO)
Q(1c
= 8Vs
~-----
--
+
1
+ 4 + ~ +
c c
2
J
4
1c
----~-~--
--
2c
2c
+
5
-------------------
+ 16)
6
-
c
7 (V- 15 )
---~---
24
?zcJ
Cz+C3
-c~c,_
C')+C-.
'-~
)
0
0
.::~.6
Cz+C3
c.,c, c 1,c.;
--'=--·l. . + -~
G2 +CJ c 4-1c
5
0
_::C4C5
C4+C5
0 xl(oo)l
01
Xz(co)l
C4+C5
CL!GS
c c
.
+ 5 6
C4+C5 C5+C6
ollx 1 (co}
0
0
lliX4(oo)!
-ctlc2
Figure 13.
II"
Ir(l
Cz
+ ..• +G )
"2 3
I
c.., -~ -c4
-(-.L-)
c 2 +C:) c 1,+c 5
0
c~
c6
- ( -~'--· + -----)
_2c 6c1
0
1
C6+~7
Clf+G.5
I
0
Tridiagonal form for X(CO).
C6+C7
IQ
lvs
-
-
-~-----
·-----
-----~
- -- -·----
--~-
-·-
--
--·--
-~-~-------~
-
-~
-----
..
25
It2~i fl tl
i
xl (co )I
i=l..Lci
.tl~.
X...,(CD)I
~-
=
X3(0.J)
l.J·~· t6~i
l.=""
I
l.
Figure -14.
-----~------
------
0
c4
0
•. (C +C + f"-..p;-)
c1
I
0
0
1
0
0
'
0
[J;
i=6'-'i
c2
-(l + c +c··;
2 3
l.
I1 ~6°1 j~6ti
7 1_
jx (o:>'!
' 4
I~=~ ~
i==6°i
I
o'
2
I
"4 '"'.5
3
c'l
c6
C6+C7
0
1
11
Solution for X(CO),
---------· -----
--------
2C6
-(·-;--- + -~)
C4+C5 C6-l "'7
-----
----------
Q
vs
26
This relationship was also established by
J. S. Brugler using a static model based on charge conservation.
He also showed that if the total capacitance
of the multiplier is constrained the optimum capacitor
ratio for maximum output voltage may be found by setting
Y(CO) =
Y(CO) =
c1
c2
(V-16)
which yields
(V-17)
The transfer functions for unity capacitor ratios
and optimum capacitor ratios may now be found.
CHAPTER VI
MULTIPLIER TRANSFER FUNCTIONS
Once the state transition equation has been derived
for a particular multiplier configuration the capacitor
values may be substituted in the system matrices and the
transfer functions evaluated using equation (V-7):
Y(Z)
=
(C(ZI-A)- 1B + D)U(Z)
(VI-1)
For multipliers with only a few stages the matrix
(ZI-A) may be evaluated using the adjoint and the determinant of (ZI-A), but the advantage of the state variable
formulation is the ease with which computers may be used
in the solution of the state equations.
A particularly
effective procedure for finding (ZI-A)- 1 is available in
the form of an algorithm and is outlined below.
The pro-
cedure is Fadeeva's Method and is often used in the proof
of the Cayley-Hamilton Theorem.
The inverse of a matrix is the adjoint of the matrix
divided by the determinant.
The determinant of the nxn
matrix (ZI-A) is a polynomial of degree n in Z:
(VI-2)
det ( ZI-A ) = Zn + d 1 Zn-1 + ••• + dn
The adjoint of (ZI-A) is a polynomial of degree n-1
in Z with nxn matrix coefficients Mi:
27
28
(VI-J)
The trace of a matrix is the sum of the elements
along the main diagonal and is used in the procedure to
find the coefficients di and Mi.
M1
Then
=I
(VI-4)
AM.l. + d.I
l.
i=1,2, ••• ,n
(VI-5)
i=1,2, ••• ,n-1
(VI-6)
(ZI-A)- 1
(VI-7)
The algorithm was used to find the transfer functions
for the series multiplier characterized in Chapter III.
The pole and zero locations and the mulplicative coefficients for several multiplier transfer functions with
unity capacitor ratio are listed in Figure 15.
Figure 16
lists the same information for several multipliers with
optimum capacitor ratios.
The number N listed in the
figures is the number of capacitors in the multiplier, not
counting the output capacitor.
The dominant pole of the transfer functions is the
pole closest to Z=1.
For every N the dominant pole of
the optimum capacitor ratio transfer function is smaller
in magnitude than the dominant pole of the unity capacitor
transfer function.
Thus the optimum capacitor ratio
yields a faster response and less steady state drop than
29
H1 (Z)
N
J
~
c1
H2 (Z)
zeros:
.ooo
·5
poles:
poles:
. 750
5
-2.0
~
zeros:
• 090
.J45
zeros:
-1.000
·750
·5
poles:
zeros:
-1.000
.250
·500
.J48
.905
poles:
.ooo
.J48
·905
7
.=b..2
c1
zeros:
.ooo
·5
.284
.611
·500
• 750
poles:
poles:
.188
.612
·950
9
=.l.!..Q
c1
zeros:
.031
.117
.472
. 755
poles:
.177
.413
·750
·970
zeros:
-1.000
.188
.612
·950
·5
zeros:
-1.000
.096
.146
.655
.854
poles:
. 000
. 177
• 413
·750
f
Figure 15.
970
H1 (Z) and H2 (Z) for unity capacitor ratio.
Figure 16.
H1 (Z) and H2 (Z) for optimum capacitor ratio.
31
the unity capacitor ratio.
As the number of stages is in-
creased the dominant pole increases in magnitude and the
response time increases, since adding stages to the multiplier also adds delay to the system.
Excessive delay has
an adverse effect on closed loop response, indicating that
the use of the optimum capacitor ratio and a minimum number
of stages will yield a faster closed loop response.
CHAPTER VII
THE OUTPUT CAPACITOR
The output capacitor is used to reduce the output
ripple voltage to acceptable limits.
Under steady state
conditions the charge the output capacitor delivers to the
load between the sampling instants is equal to the charge
Q the multiplier delivers to the output capacitor at the
sampling instants.
Thus for a constant load current IL:
(VII-1)
The steady state output ripple voltage Vr is found
using equation (VII-2):
=
ILTs
(VII-2)
co
The output capacitor operates as a sample and hold
device in the steady state, but unlike the zero order hold
encountered in sampled data systems the output capacitor
By assuming the output capa-
loads the system dynamics.
citor is suffiently large that inter-sample ripple may be
ignored the response of the complete system at the sampling instants may be found and the continuous output approximated using the zero order hold.
The output capacitor is considered as a single element system with inputs Q(nTs) and IL(nTs).
J2
The input
JJ
Q(nTs) is the charge delivered to the output capacitor by
the multiplier, and the output of the single element system is the same as the output of the multiplier, Y(nTs).
The system interconnection is shown in Figure 17.
At
t=nTs the switches close and the state vector X'(nTs) is
Q(nTs)
X' (nTs) = X(nTs) + -C__,.;;;;_
(VII-3)
0
This is also the output of the system, Y(nTs):
Y(nTs) = X(nTs) +
Q(nT )
C s
(VII-4)
0
At t=nT! the switches open and the load current
IL(nTs) remains connected to the output capacitor.
The
next state of the system X((n+l)Ts) may then be found:
X((n+l)T ) = X(nT ) +
s
s
Q(nT )
C s 0
(VII-.5)
As before Z transforms are taken and the initial
state of the system is set equal to zero so that the
transfer function of the system may be found:
(VII-6)
(VII-7)
As noted above Y(Z) and Q(Z) are exactly the same
variables used in the analysis of the multiplier.
If
the transfer function of the multiplier is written in
J4
t=~._------~------t,=_n_T~8
Figure 17.
zero
order
hold
System model for the output capacitor
35
the form
(VII-S)
then equation (VII-7) may be used to eliminate Q(Z) with
the result
(VII-9)
or
(VII-10)
This is the Z transform transfer function of the
complete open loop multiplier system.
This is a partie-
ularly convenient form since any of the transfer functions
in Figure 15 or Figure 16 may be used with equation
(VII-9) to determine the open loop response and the effect
of
c0
on the multiplier transfer function.
I•
,
CHAPTER VIII
CLOSED LOOP N1ULTIPLIER SYSTEMS
The Z trans£orm transfer £unction o£ the complete
multiplier system developed in Chapter VII gives the response of the multiplier at the sampling instants.
By
approximating the continuous output o£ the multiplier
using the zero order hold the methods developed for the
study of closed loop sampled data systems may be applied
directly using the multiplier as a block system element.
Figure 18 shows a typical closed loop regulator configuration.
The output o£ the zero order hold is sub-
tracted from the reference input r(s) resulting in an
error signal e(s).
G(s) represents the linear portion
o£ the system which ampli£ies the error signal and filters
the extraneous signals generated in the sampling process
and the intersample due to the load current.
I£ the
closed loop response is unsatisfactory, or if increased
loop gain is desired, G(s) may also contain elements for
cascade compensation.
To determine .the stability o£ the closed loop configuration the circuit is redrawn moving G(s) through the
summing junction.
The resulting configuration leaves
the circuit equations unchanged and is shown in Figure 19.
J6
37
e(s) ~-_,
G(s)
V6 (Z) ,-----...,
~
t=nT s
4 {z)
H
zero
order
hold
Figure 18.
Y(Z)
zero
order
hold
t=nT s
Closed loop multiplier system.
-~
38
Y ( Z )r-----.
zero
order
hold
G(s)
Figure 19.
zero
order
hold
Redrawn closed loop system
39
From Z transform theory the Z transform of the cascade
combination of the zero order hold and G(s) is
H (Z) = Z-1zQ.i§.l
z
5
(VIII-1)
s
G(s) is also now in cascade with the input r(s) and
the Z transform of the output of G(s), r(Z), is
r(Z)
=
(VIII-2)
Za(s)r(s)
The system output, Y(Z), may now be found using the
block diagram of Figure 19.
Y(Z)
=1
H (Z)
+ H
tz)H
4
H4(Z)
5
(Z) IL(Z) + 1 + H (Z)H (Z) r(Z)
4
5
(VIII-3)
The stability of the system depends on the location of
the poles of the transfer function.
The criterion for
stability in Z plane analysis is that all the poles must
lie within the unit circle defined by
Z
= e~·e
(VIII-4)
Assuming that the open loop system is stable the stability of the closed loop system depends on the location
of the zeros of
(VIII-5)
This stability equation is the central result of the
previous chapters and may be expressed in terms of the
open loop transfer functions and the output capacitor
ZH 2 (Z)H (Z)
5
(VIII-6)
CHAPTER IX
CONCLUSIONS
The sampled data voltage multiplier model provides
the designer sufficient information to predict the closed
loop behavior of multiplier systems.
Using the methods
described, a given configuration and input wave form may
be modeled by a system of difference equations in state
variable form.
The Z transform transfer function solution
is found using matrix algebra, a method best suited for
computers.
Computers may also be used to plot the root
locus of the closed loop multiplier system or to determine
the effectiveness of cascade compensators.
The model is superior to previous static models which
provide no information on the system dynamics.
The sam-
pled data model provides a complete description of the
system behavior for arbitrary inputs.
The model would
be further improved if the multiplier was analyzed using
two sampling rates since the voltage input is sampled at
twice the rate as the load current.
The assumption that
each negative input pulse has the same magnitude as the
positive pulse that precedes it adds delay to part of the
feedback signal in the closed loop configuration.
The
single sample rate model should predict a more potentially
40
41
unstable performance than is actually the case, which is a
desirable feature in a model.
The limitation of the model to small displacements
from an operating point is too restrictive.
For any par-
ticular case the range of the model can be expanded, since
to justify the model it is only necessary to show that the
diodes conduct on a cycle by cycle basis.
A stable closed
loop system will also provide a stable domain of attraction
for system states that are outside the range of the model.
42
BIBLIOGRAPHY
1.
Cadzow, J, A. Discrete-Time Systems. Englewood
Cliffs, N. J: Prentice-Hall, Inc., 1973·
2.
Kuo, B. c. Analysis and Synthesis of Sampled Data
Control Systems. Englewood Cliffs, N. J:
Prentice-Hall, Inc., 1963.
3·
Kuo, B. c. Discrete-Data Control Systems. Englewood
Cliffs, N. J: Prentice-Hall, Inc., 1970.
4.
Ogata, K. State Space Analysis of Control Systems.
Englewood Cliffs, N. J: Prentice-Hall, Inc.,
1967.
5·
Saucedo, R., and E. E. Schiring. Introduction to
Continuous and Digital Control Systems.
New York: Macmillan Publishing Co., Inc., 1968.
6.
Schwarz, H. R. Numerical Analysis of Symmetric
Matrices. Englewood Cliffs, N. J: PrenticeHall, Inc., 1973.
7•
Brugler, J. s. "Theoretical Performance of Voltage
Multiplier Circuits," IEEE Journal of Solid
State Circuits, Vol. SC-6, PP• 132-135,
June 1971.