DLD603/D
Rev. 0, Dec-2002
ECLinPS Plus™ Device Data
PUBLICATION ORDERING INFORMATION
GLOBAL Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: [email protected]
JAPAN: ON Semiconductor, Japan Customer Focus Center
4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031
Phone: 81-3-5740-2700
Email: [email protected]
N. American Technical Support: 800-282-9855 Toll Free USA/Canada
For additional information, please contact your local Sales
Representative
ECLinPS Plus™ Device Data
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and
do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed,
intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for
any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use
SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of
the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
ON Semiconductor Website: http://onsemi.com
DLD603/D
12/02
DLD603
REV 0
ECLinPS Plus Device Data
Advanced ECL in Picoseconds
DLD603/D
Rev. 0, Dec-2002
Formerly BR1513/D
 SCILLC, 2002
Previous Edition  2001
“All Rights Reserved”
ECLinPS, ECLinPS Lite, and ECLinPS Plus are trademarks of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: [email protected]
JAPAN: ON Semiconductor, Japan Customer Focus Center
2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850
Email: [email protected]
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
N. American Technical Support: 800-282-9855 Toll Free USA/Canada
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2
Table of Contents
Numeric Data Sheet Listing and
Selection Guide
Chapter 2: ECLinPS Plus Translators
Page
Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Page
Numeric Data Sheet Listing . . . . . . . . . . . . . . . . . . . . . . . . . 5
ECLinPS Plus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ECLinPS Plus Translators . . . . . . . . . . . . . . . . . . . . . . . 6
Low Voltage ECLinPS Plus . . . . . . . . . . . . . . . . . . . . . . . 6
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Clock/Data Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Clock/Data Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Flip-Flop/Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Line Receivers/Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Translators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 3: Low Voltage ECLinPS Plus
Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Chapter 4: Case Outlines and Package
Dimensions
Device Nomenclatures . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Case Outlines and Package Dimensions . . . . . . . . . . . 385
Chapter 5: Index
Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Chapter 1: ECLinPS Plus
Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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4
Numeric Data Sheet Listing
Chapter 1: ECLinPS Plus Data Sheets
Device
Function
Page
MC10EP01, MC100EP01 . . . . . . 3.3V / 5V ECL 4- Input OR/NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MC10EP05, MC100EP05 . . . . . . 3.3V / 5V ECL 2-Input Differential AND/NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MC10EP08, MC100EP08 . . . . . . 3.3V / 5V ECL 2-Input Differential XOR/XNOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MC10EP11, MC100EP11 . . . . . . 3.3V / 5V ECL 1:2 Differential Fanout Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MC100EP14 . . . . . . . . . . . . . . . . . 3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
MC10EP16, MC100EP16 . . . . . . 3.3V / 5V ECL Differential Receiver/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
MC100EP16F . . . . . . . . . . . . . . . . 3.3V / 5V ECL Differential Receiver/Driver With Reduced Output Swing . . . . . . . . . . . . . 45
MC10EP16T, MC100EP16T . . . 3.3V / 5V ECL Differential Receiver/Driver with Internal Termination . . . . . . . . . . . . . . . . 50
MC10EP16VA, MC100EP16VA . 3.3V / 5V ECL Differential Receiver/Driver with High Gain . . . . . . . . . . . . . . . . . . . . . . . . 56
MC100EP16VB . . . . . . . . . . . . . . 3.3V / 5V ECL Differential Receiver/Driver with High and Low Gain . . . . . . . . . . . . . . . . 62
MC100EP16VC . . . . . . . . . . . . . . 3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output . . . . . . . 67
MC100EP16VS . . . . . . . . . . . . . . 3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing . . . . . . . . . . . . . 74
MC100EP16VT . . . . . . . . . . . . . . 3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
and Internal Input Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
MC10EP17, MC100EP17 . . . . . . 3.3V / 5V ECL Quad Differential Driver/Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
MC10EP29, MC100EP29 . . . . . . 3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset . . . . . 96
MC10EP31, MC100EP31 . . . . . . 3.3V / 5V ECL D Flip-Flop with Set and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
MC10EP32, MC100EP32 . . . . . . 3.3V / 5V ECL 2 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
MC10EP33, MC100EP33 . . . . . . 3.3V / 5V ECL 4 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
MC10EP35, MC100EP35 . . . . . . 3.3V / 5V ECL JK Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
MC100EP40 . . . . . . . . . . . . . . . . . 3.3V / 5V ECL Differential Phase- Frequency Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
MC10EP51, MC100EP51 . . . . . . 3.3V / 5V ECL D Flip- Flop with Reset and Differential Clock . . . . . . . . . . . . . . . . . . . . . . . . 134
MC10EP52, MC100EP52 . . . . . . 3.3V / 5V ECL Differential Data and Clock D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
MC10EP56, MC100EP56 . . . . . . 3.3V / 5V ECL Dual Differential 2:1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
MC10EP57, MC100EP57 . . . . . . 3.3V / 5V ECL 4:1 Differential Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
MC10EP58, MC100EP58 . . . . . . 3.3V / 5V ECL 2:1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
MC10EP89 . . . . . . . . . . . . . . . . . . 3.3V / 5V ECL Coaxial Cable Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
MC10EP90, MC100EP90 . . . . . . - 3.3V / -5V Triple ECL Input to LVPECL/PECL Output Translator . . . . . . . . . . . . . . . . . . . . 172
MC10EP016, MC100EP016 . . . 3.3V / 5V ECL 8-Bit Synchronous Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
MC100EP016A . . . . . . . . . . . . . . 3.3V ECL 8-Bit Synchronous Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
MC10EP101, MC100EP101 . . . 3.3V / 5V ECL Quad 4-Input OR/NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
MC10EP105, MC100EP105 . . . 3.3V / 5V ECL Quad 2-Input Differential AND/NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
MC10EP116, MC100EP116 . . . . 3.3V / 5V Hex Differential Line Receiver/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
MC10EP131, MC100EP131 . . . 3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock . . . . . . . . . . . 216
MC10EP139, MC100EP139 . . . 3.3V / 5V ECL 2/4, 4/5/6 Clock Generation Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
MC100EP140 . . . . . . . . . . . . . . . . 3.3V ECL Phase- Frequency Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
MC10EP142, MC100EP142 . . . 3.3V / 5V ECL 9-Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
MC10EP195, MC100EP195 . . . 3.3V / 5V ECL Programmable Delay Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
MC100EP196 . . . . . . . . . . . . . . . . 3.3V ECL Programmable Delay Chip with FTUNE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
MC10EP445, MC100EP445 . . . 3.3V / 5V ECL 8-Bit Serial/Parallel Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
MC10EP446, MC100EP446 . . . 3.3V / 5V ECL 8-Bit Differential Parallel/Serial Converter . . . . . . . . . . . . . . . . . . . . . . . . . 281
MC10EP451, MC100EP451 . . . 3.3V / 5V ECL 6-Bit Differential Register with Master Reset . . . . . . . . . . . . . . . . . . . . . . 297
MC100EP809 . . . . . . . . . . . . . . . . 3.3V 1:9 Differential HSTL/PECL in, HSTL out Clock Driver with
LVTTL Clock Select and Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
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Numeric Data Sheet Listing (continued)
Chapter 2: ECLinPS Plus Translator Data Sheets
Device
Function
Page
MC10EPT20, MC100EPT20 . . . 3.3V LVTTL/LVCMOS to Differential LVPECL Translator . . . . . . . . . . . . . . . . . . . . . . . . . 310
MC100EPT21 . . . . . . . . . . . . . . . . 3.3V Differential LVPECL to LVTTL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
MC100EPT22 . . . . . . . . . . . . . . . . 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator . . . . . . . . . . . . . . . . . . . . 318
MC100EPT23 . . . . . . . . . . . . . . . . 3.3V Dual Differential LVPECL to LVTTL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
MC100EPT24 . . . . . . . . . . . . . . . . 3.3V LVTTL/LVCMOS to Differential LVECL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
MC100EPT25 . . . . . . . . . . . . . . . . -3.3V / -5V Differential ECL to +3.3V LVTTL Translator . . . . . . . . . . . . . . . . . . . . . . . . . 330
MC100EPT26 . . . . . . . . . . . . . . . . 3.3V 1:2 Fanout Differential LVPECL to LVTTL Translator . . . . . . . . . . . . . . . . . . . . . . . . . 334
MC100EPT622 . . . . . . . . . . . . . . 3.3V LVTTL/LVCMOS to LVPECL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Chapter 3: Low Voltage ECLinPS Plus Data Sheets
Device
Function
Page
MC10LVEP11, MC100LVEP11 . 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
MC100LVEP14 . . . . . . . . . . . . . . 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . 350
MC10LVEP16, MC100LVEP16 . 2.5V / 3.3V ECL Differential Receiver/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
MC100LVEP34 . . . . . . . . . . . . . . 2.5V / 3.3V ECL 2, 4, 8 Clock Generation Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
MC100LVEP111 . . . . . . . . . . . . . . 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver . . . . . . . . . . . . . . . . . . . . . . . 369
MC100LVEP210 . . . . . . . . . . . . . 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver . . . . . . . . . . . . . . . . . . . . . . 374
MC100EP210S . . . . . . . . . . . . . . 2.5V 1:5 Dual Differential LVDS Compatible Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
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Selection Guide
Gates
Function
Device
3.3V / 5V ECL 4- Input OR/NOR
3.3V / 5V ECL 2-Input Differential AND/NAND
3.3V / 5V ECL 2-Input Differential XOR/XNOR
3.3V / 5V ECL Quad 4-Input OR/NOR
3.3V / 5V ECL Quad 2-Input Differential AND/NAND
MC10EP01, MC100EP01
MC10EP05, MC100EP05
MC10EP08, MC100EP08
MC10EP101, MC100EP101
MC10EP105, MC100EP105
Page
10
16
22
197
203
Clock/Data Buffers
Function
Device
2.5V / 3.3V ECL 1:2 Differential Fanout Buffer
3.3V / 5V ECL 1:2 Differential Fanout Buffer
2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver
3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver
2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver
2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver
2.5V 1:5 Dual Differential LVDS Compatible Clock Driver
3.3V 1:9 Differential HSTL/PECL in, HSTL out Clock Driver with LVTTL
Clock Select and Enable
MC10LVEP11, MC100LVEP11
MC10EP11, MC100EP11
MC100LVEP14
MC100EP14
MC100LVEP111
MC100LVEP210
MC100EP210S
MC100EP809
Page
344
28
350
34
369
374
379
303
Clock/Data Dividers
Function
Device
3.3V / 5V ECL 2 Divider
3.3V / 5V ECL 4 Divider
2.5V / 3.3V ECL 2, 4, 8 Clock Generation Chip
3.3V / 5V ECL 2/4, 4/5/6 Clock Generation Chip
MC10EP32, MC100EP32
MC10EP33, MC100EP33
MC100LVEP34
MC10EP139, MC100EP139
Page
109
116
362
222
Flip-Flops/Registers
Function
Device
3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop with Set and
Reset
3.3V / 5V ECL D Flip-Flop with Set and Reset
3.3V / 5V ECL JK Flip-Flop
3.3V / 5V ECL D Flip- Flop with Reset and Differential Clock
3.3V / 5V ECL Differential Data and Clock D Flip-Flop
3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock
3.3V / 5V ECL 8-Bit Serial/Parallel Converter
3.3V / 5V ECL 8-Bit Differential Parallel/Serial Converter
3.3V / 5V ECL 6-Bit Differential Register with Master Reset
MC10EP29, MC100EP29
MC10EP31, MC100EP31
MC10EP35, MC100EP35
MC10EP51, MC100EP51
MC10EP52, MC100EP52
MC10EP131, MC100EP131
MC10EP445, MC100EP445
MC10EP446, MC100EP446
MC10EP451, MC100EP451
Page
96
103
123
134
140
216
266
281
297
Multiplexers
Function
Device
3.3V / 5V ECL Dual Differential 2:1 Multiplexer
3.3V / 5V ECL 4:1 Differential Multiplexer
3.3V / 5V ECL 2:1 Multiplexer
MC10EP56, MC100EP56
MC10EP57, MC100EP57
MC10EP58, MC100EP58
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Page
146
153
160
Selection Guide (continued)
Counters
Function
Device
3.3V / 5V ECL 8-Bit Synchronous Binary Up Counter
3.3V ECL 8-Bit Synchronous Binary Up Counter
MC10EP016, MC100EP016
MC100EP016A
Page
178
188
Shift Registers
Function
Device
3.3V / 5V ECL 9-Bit Shift Register
MC10EP142, MC100EP142
Page
234
Line Receivers/Drivers
Function
Device
2.5V / 3.3V ECL Differential Receiver/Driver
3.3V / 5V ECL Differential Receiver/Driver
3.3V / 5V ECL Differential Receiver/Driver with Reduced Output Swing
3.3V / 5V ECL Differential Receiver/Driver with Internal Termination
3.3V / 5V ECL Differential Receiver/Driver with High Gain
3.3V / 5V ECL Differential Receiver/Driver with High and Low Gain
3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable
Output
3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
and Internal Input Termination
3.3V / 5V ECL Quad Differential Driver/Receiver
3.3V / 5V Hex Differential Line Receiver/Driver
MC10LVEP16, MC100LVEP16
MC10EP16, MC100EP16
MC100EP16F
MC10EP16T, MC100EP16T
MC10EP16VA, MC100EP16VA
MC100EP16VB
MC100EP16VC
MC100EP16VS
MC100EP16VT
MC10EP17, MC100EP17
MC10EP116, MC100EP116
Page
356
39
45
50
56
62
67
74
82
90
209
Translators
Function
Device
3.3V LVTTL/LVCMOS to Differential LVPECL Translator
3.3V Differential LVPECL to LVTTL Translator
3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
3.3V Dual Differential LVPECL to LVTTL Translator
3.3V LVTTL/LVCMOS to Differential LVECL Translator
-3.3V / -5V Differential ECL to +3.3V LVTTL Translator
3.3V 1:2 Fanout Differential LVPECL to LVTTL Translator
- 3.3V / -5V Triple ECL Input to LVPECL/PECL Output Translator
3.3V LVTTL/LVCMOS to LVPECL Translator
MC10EPT20, MC100EPT20
MC100EPT21
MC100EPT22
MC100EPT23
MC100EPT24
MC100EPT25
MC100EPT26
MC10EP90, MC100EP90
MC100EPT622
Page
310
314
318
322
326
330
334
172
338
Miscellaneous
Function
Device
3.3V / 5V ECL Differential Phase- Frequency Detector
3.3V / 5V ECL Coaxial Cable Driver
3.3V ECL Phase- Frequency Detector
3.3V / 5V ECL Programmable Delay Chip
3.3V / 5V ECL Programmable Delay Chip with FTUNE
MC100EP40
MC10EP89
MC100EP140
MC10EP195, MC100EP195
MC100EP196
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8
Page
129
166
229
242
255
CHAPTER 1
ECLinPS Plus Data Sheets
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9
MC10EP01, MC100EP01
3.3V / 5VECL 4− Input
OR/NOR
The MC10EP01 is a 4- input OR/NOR gate. The device is
functionally equivalent to the EL01 device, LVEL01, and E101 (a
quad version). With AC performance much faster than the LVEL01
device, the EP01 is ideal for applications requiring the fastest AC
performance available.
The 100 Series contains temperature compensation.
• 230 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
•
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MARKING DIAGRAMS*
8
8
8
HEP01
ALYW
1
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
SO-8
D SUFFIX
CASE 751
1
1
8
8
8
1
TSSOP-8
DT SUFFIX
CASE 948R
KEP01
ALYW
KP01
ALYW
HP01
ALYW
1
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC10EP01D
SO-8
98 Units/Rail
MC10EP01DR2
SO-8
2500 Tape & Reel
MC100EP01D
SO-8
98 Units/Rail
MC100EP01DR2
SO-8
2500 Tape & Reel
MC10EP01DT
TSSOP-8
100 Units/Rail
MC10EP01DTR2
TSSOP-8
2500 Tape & Reel
MC100EP01DT
TSSOP-8
100 Units/Rail
MC100EP01DTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 4
10
2500 Tape & Reel
Publication Order Number:
MC10EP01/D
MC10EP01, MC100EP01
PIN DESCRIPTION
D0
D1
D2
D3
1
8
2
7
3
6
4
5
VCC
Q
PIN
FUNCTION
D0-D3
ECL Data Inputs
Q, Q
ECL Data Outputs
VCC
VEE
Positive Supply
Negative Supply
TRUTH TABLE
Q
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
D0*
D1*
D2*
D3*
Q
Q
L
H
X
X
X
H
L
X
H
X
X
H
L
X
X
H
X
H
L
X
X
X
H
H
L
H
H
H
H
H
H
L
L
L
L
L
*Pins will default LOW when left open.
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
115
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 SOIC
41 to 44
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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11
VI VCC
VI VEE
MC10EP01, MC100EP01
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
24
31
20
24
31
20
24
31
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2165
2240
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single-Ended)
1365
1690
1430
1755
1490
1815
mV
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC - 2.0 V.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
24
31
20
24
31
20
24
31
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 6)
3865
3940
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 6)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
6. All loading with 50 to VCC - 2.0 V.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 7)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
24
31
20
24
31
20
24
31
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8)
-1 135
-1060
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 8)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
0.5
150
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC.
8. All loading with 50 to VCC - 2.0 V.
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12
MC10EP01, MC100EP01
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 9)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
15
24
32
17
26
36
19
28
38
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 10)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 10)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
10. All loading with 50 to VCC - 2.0 V.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 11)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
15
24
32
17
26
36
19
28
38
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 12)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 12)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
12. All loading with 50 to VCC - 2.0 V.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 13)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
15
24
32
17
26
36
19
28
38
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 14)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 14)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
0.5
150
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
13. Input and output parameters vary 1:1 with VCC.
14. All loading with 50 to VCC - 2.0 V.
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13
MC10EP01, MC100EP01
AC CHARACTERISTICS VCC = 3.0 V to 5.5 V; VEE = 0 V or VCC = 0 V; VEE = -3.0 V to -5.5 V (Note 15)
-40 °C
Symbol
Min
Characteristic
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation
Delay
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
tr
tf
Output Rise/Fall Times
(20% - 80%)
25°C
Typ
Max
Min
>3
D to Q, Q
Q, Q
150
70
Typ
85°C
Max
Min
Typ
>3
260
330
0.2
<1
120
170
150
80
>3
270
330
0.2
<1
130
180
200
100
8
700
7
600
6
500
5
400
4
300
3
200
2
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
1
0
1000
2000
3000
4000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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14
5000
6000
GHz
350
ps
0.2
<1
ps
150
200
ps
ÉÉ
ÉÉ
(JITTER)
0
JITTEROUT (ps) (RMS)
VOUTpp (mV)
800
Unit
300
15. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC - 2.0 V.
100
Max
MC10EP01, MC100EP01
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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15
MC10EP05, MC100EP05
3.3V / 5VECL 2−Input
Differential AND/NAND
The MC10/100EP05 is a 2-input differential AND/NAND gate.
The device is functionally equivalent to the EL05 and LVEL05
devices. With AC performance much faster than the LVEL05 device,
the EP05 is ideal for applications requiring the fastest AC performance
available.
The 100 Series contains temperature compensation.
• 220 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
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MARKING DIAGRAMS*
8
8
8
1
SO-8
D SUFFIX
CASE 751
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
•
•
• Q Output Will Default LOW with Inputs Open or at VEE
HEP05
ALYW
1
KEP05
ALYW
1
8
8
8
1
TSSOP-8
DT SUFFIX
CASE 948R
HP05
ALYW
KP05
ALYW
1
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Package
Shipping
MC10EP05D
Device
SO-8
98 Units/Rail
MC10EP05DR2
SO-8
2500 Tape & Reel
MC100EP05D
SO-8
98 Units/Rail
MC100EP05DR2
SO-8
2500 Tape & Reel
MC10EP05DT
TSSOP-8
100 Units/Rail
MC10EP05DTR2
TSSOP-8
2500 Tape & Reel
MC100EP05DT
TSSOP-8
100 Units/Rail
MC100EP05DTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2001
April, 2001 - Rev. 4
16
2500 Tape & Reel
Publication Order Number:
MC10EP05/D
MC10EP05, MC100EP05
PIN DESCRIPTION
D0
D0
D1
1
8
2
7
6
3
VCC
Q
PIN
FUNCTION
D0*, D1*, D0**, D1**
ECL Data Inputs
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
Q
TRUTH TABLE
D1
4
5
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
D0
D1
D0
D1
Q
Q
L
L
H
H
L
H
L
H
H
H
L
L
H
L
H
L
L
L
L
H
H
H
H
L
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
137
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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17
VI VCC
VI VEE
MC10EP05, MC100EP05
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
24
29
20
24
29
20
24
29
mA
Output HIGH Voltage (Note 4)
2165
2240
2415
2230
2355
2480
2290
2415
2540
mV
VOL
VIH
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
Input HIGH Voltage (Single Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
1365
1690
1460
1755
1490
1815
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
150
150
D
0.5
0.5
0.5
µA
D -150
-150
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 ohms to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Input LOW Current
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
24
29
20
24
29
20
24
29
mA
Output HIGH Voltage (Note 7)
3865
3940
4115
3930
4055
4180
3990
4115
4240
mV
VOL
VIH
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
Input HIGH Voltage (Single Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
3065
3390
3130
3455
3190
3515
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
150
Input LOW Current
D
D
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 ohms to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
24
29
20
24
29
20
24
29
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 10)
-1 135
-1060
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
VIH
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
Input HIGH Voltage (Single Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
Input LOW Current
VEE+2.0
0.0
VEE+2.0
150
D
D
0.5
-150
0.0
VEE+2.0
150
0.5
-150
0.5
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 ohms to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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18
MC10EP05, MC100EP05
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
15
25
32
17
27
36
19
28
38
mA
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
1355
1675
1355
1675
1355
1675
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
150
150
D
0.5
0.5
0.5
µA
D -150
-150
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 ohms to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Input LOW Current
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
15
25
32
17
27
36
19
28
38
mA
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
VIH
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
Input HIGH Voltage (Single Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
3055
3375
3055
3375
3055
3375
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
150
Input LOW Current
D
D
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 ohms to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
15
25
32
17
27
36
19
28
38
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
VIH
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
Input LOW Current
VEE+2.0
0.0
VEE+2.0
150
D
D
0.5
-150
0.0
VEE+2.0
150
0.5
-150
0.5
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 ohms to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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19
MC10EP05, MC100EP05
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
Characteristic
Min
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
Typ
25°C
Max
Min
>3
Max
Min
>3
0.2
<1
800
1200
170
>3
270
0.2
<1
800
1200
210
Unit
GHz
ps
0.2
<1
ps
150
800
1200
mV
tr
Output Rise/Fall Times
Q
70
120
170
80
130
180
100
tf
(20% - 80%)
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
150
200
ps
150
220
900
9
800
8
700
7
600
6
500
5
JITTEROUT ps (RMS)
260
Max
320
150
210
Typ
260
VOUTpp (mV)
160
Typ
85°C
ÉÉ
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉ
ÇÇÇÇÇÇÇÇÇÇÇ
ÉÉÉÉÉÉÉÉ
ÇÇÇÇÇÇÇÇÇÇÇ
400
4
TBD
300
3
200
2
(JITTER)
1
100
TBD
0
0
1000
2000
3000
4000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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20
5000
6000
MC10EP05, MC100EP05
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices.)
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21
MC10EP08, MC100EP08
3.3V / 5VECL 2−Input
Differential XOR/XNOR
The MC10/100EP08 is a differential XOR/XNOR gate. The EP08 is
ideal for applications requiring the fastest AC performance available.
The 100 Series contains temperature compensation.
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• 250 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
MARKING DIAGRAMS*
8
8
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
8
1
SO-8
D SUFFIX
CASE 751
•
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
HEP08
ALYW
1
1
8
8
1
TSSOP-8
DT SUFFIX
CASE 948R
KEP08
ALYW
8
HP08
ALYW
KP08
ALYW
1
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
MC10EP08D
SO-8
98 Units/Rail
MC10EP08DR2
SO-8
2500 Tape & Reel
MC100EP08D
SO-8
98 Units/Rail
MC100EP08DR2
SO-8
2500 Tape & Reel
MC10EP08DT
TSSOP-8
100 Units/Rail
MC10EP08DTR2
TSSOP-8
2500 Tape & Reel
MC100EP08DT
TSSOP-8
100 Units/Rail
MC100EP08DTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2001
April, 2001 - Rev. 3
22
Shipping
2500 Tape & Reel
Publication Order Number:
MC10EP08/D
MC10EP08, MC100EP08
D0
1
8
2
D0
7
PIN DESCRIPTION
VCC
Q
PIN
FUNCTION
D0, D1, D0, D1
ECL Data Inputs
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
TRUTH TABLE
3
D1
6
4
D1
5
Q
VEE
D0*
D1*
D0**
D1**
Q
Q
L
L
H
H
L
H
L
H
H
H
L
L
H
L
H
L
L
H
H
L
H
L
L
H
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
135
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol
Parameter
Condition 1
VCC
VEE
PECL Mode Power Supply
NECL Mode Power Supply
VEE = 0 V
VCC = 0 V
VI
Input
PECL Mode In
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
TA
Tstg
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
θJC
θJA
Thermal Resistance (Junction to Case)
θJC
Tsol
Condition 2
Rating
Units
6
V
-6
V
6
-6
V
V
50
100
mA
mA
Operating Temperature Range
-40 to +85
°C
Storage Temperature Range
-65 to +150
°C
8 SOIC
8 SOIC
190
130
°C/W
°C/W
std bd
8 SOIC
41 to 44
°C/W
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
°C/W
Wave Solder
<2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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23
VI VCC
VI VEE
MC10EP08, MC100EP08
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
36
20
30
38
20
32
38
mA
Output HIGH Voltage (Note 4.)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
VIH
Output LOW Voltage (Note 4.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
Input HIGH Voltage (Single Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
1365
1690
1430
1755
1490
1815
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 5.)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
150
Input LOW Current
D
D
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 ohms to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6.)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
20
28
36
20
30
38
20
32
38
mA
Output HIGH Voltage (Note 7.)
3865
3940
4115
3930
4055
4180
3990
4115
4240
mV
VOL
VIH
Output LOW Voltage (Note 7.)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
Input HIGH Voltage (Single Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
3065
3390
3130
3455
3190
3515
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 8.)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
150
Input LOW Current
D
D
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 ohms to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
36
20
30
38
20
32
38
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 10.)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
VIH
Output LOW Voltage (Note 10.)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
Input HIGH Voltage (Single Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input HIGH Voltage Common Mode
Range (Differential) (Note 11.)
Input LOW Current
VEE+2.0
0.0
VEE+2.0
150
D
D
0.5
-150
0.0
VEE+2.0
150
0.5
-150
0.5
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 ohms to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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24
MC10EP08, MC100EP08
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
36
20
30
38
20
32
40
mA
Output HIGH Voltage (Note 13.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 13.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
1355
1675
1355
1675
1355
1675
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 14.)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
150
Input LOW Current
D
D
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 ohms to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
36
20
30
38
20
32
40
mA
Output HIGH Voltage (Note 16.)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
VIH
Output LOW Voltage (Note 16.)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
Input HIGH Voltage (Single Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
3055
3375
3055
3375
3055
3375
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 17.)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
150
Input LOW Current
D
D
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 ohms to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18.)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
20
28
36
20
30
38
20
32
40
mA
Output HIGH Voltage (Note 19.)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
VIH
Output LOW Voltage (Note 19.)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input HIGH Voltage Common Mode
Range (Differential) (Note 20.)
Input LOW Current
VEE+2.0
0.0
VEE+2.0
150
D
D
0.5
-150
0.0
VEE+2.0
150
0.5
-150
0.5
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 ohms to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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25
MC10EP08, MC100EP08
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21.)
-40 °C
Symbol
Characteristic
Min
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
Typ
25°C
Max
Min
>3
Typ
85°C
Max
Min
>3
Typ
Max
>3
Unit
GHz
ps
170
320
0.2
<1
ps
150
800
1200
mV
tr
Output Rise/Fall Times
Q, Q
70
120
170
80
130
180
100
tf
(20% - 80%)
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
150
200
ps
150
220
280
0.2
<1
800
1200
180
150
250
300
0.2
<1
800
1200
200
900
9
800
8
700
7
600
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
200
2
100
1
(JITTER)
0
0
1000
2000
JITTEROUT ps (RMS)
270
VOUTpp (mV)
D, D to Q, Q
3000
4000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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26
5000
6000
MC10EP08, MC100EP08
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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27
MC10EP11, MC100EP11
3.3V / 5VECL 1:2
Differential Fanout Buffer
The MC10/100EP11 is a differential 1:2 fanout buffer. The device is
pin and functionally equivalent to the LVEL11 device. With AC
performance much faster than the LVEL11 device, the EP11 is ideal
for applications requiring the fastest AC performance available.
The 100 Series contains temperature compensation.
• 220 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
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MARKING DIAGRAMS*
8
8
8
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
•
• Safety Clamp on Inputs
• Q Outputs Will Default LOW with Inputs Open or at VEE
1
SO-8
D SUFFIX
CASE 751
HEP11
ALYW
KEP11
ALYW
1
1
8
8
8
1
TSSOP-8
DT SUFFIX
CASE 948R
HP11
ALYW
1
H = MC10
K = MC100
A = Assembly Location
KP11
ALYW
1
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2001
April, 2001 - Rev. 4
28
Package
Shipping
MC10EP11D
SO-8
98 Units/Rail
MC10EP11DR2
SO-8
2500 Tape & Reel
MC100EP11D
SO-8
98 Units/Rail
MC100EP11DR2
SO-8
2500 Tape & Reel
MC10EP11DT
TSSOP-8
100 Units/Rail
MC10EP11DTR2
TSSOP-8
2500 Tape & Reel
MC100EP11DT
TSSOP-8
100 Units/Rail
MC100EP11DTR2
TSSOP-8
2500 Tape & Reel
Publication Order Number:
MC10EP11/D
MC10EP11, MC100EP11
Q0
Q0
1
8
2
PIN DESCRIPTION
VCC
7
D
PIN
FUNCTION
D*, D**
ECL Data Inputs
Q0, Q0, Q1, Q1
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
Q1
3
6
D
Q1
4
5
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
73
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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29
Condition 2
VI VCC
VI VEE
MC10EP11, MC100EP11
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
29
37
20
30
39
22
31
40
mA
Output HIGH Voltage (Note 4.)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
VIH
Output LOW Voltage (Note 4.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
Input HIGH Voltage (Single Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
1365
1690
1430
1755
1490
1815
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 5.)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
150
Input LOW Current
D
D
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 ohms to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6.)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
20
29
37
20
30
39
22
31
40
mA
Output HIGH Voltage (Note 7.)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
VIH
Output LOW Voltage (Note 7.)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
Input HIGH Voltage (Single Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
3065
3390
3130
3455
3190
3515
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 8.)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
150
Input LOW Current
D
D
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 ohms to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
29
37
20
30
39
22
31
40
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 10.)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
VIH
Output LOW Voltage (Note 10.)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
Input HIGH Voltage (Single Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input HIGH Voltage Common Mode
Range (Differential) (Note 11.)
Input LOW Current
VEE+2.0
0.0
VEE+2.0
150
D
D
0.5
-150
0.0
VEE+2.0
150
0.5
-150
0.5
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 ohms to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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30
MC10EP11, MC100EP11
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
35
44
26
35
44
26
35
44
mA
Output HIGH Voltage (Note 13.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 13.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
1355
1675
1355
1675
1355
1675
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 14.)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
150
Input LOW Current
D
D
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 ohms to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15.)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
26
35
44
26
35
44
26
35
44
mA
Output HIGH Voltage (Note 16.)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
VIH
Output LOW Voltage (Note 16.)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
Input HIGH Voltage (Single Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
3055
3375
3055
3375
3055
3375
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 17.)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
150
Input LOW Current
D
D
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 ohms to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
35
44
26
35
44
26
35
44
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 19.)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
VIH
Output LOW Voltage (Note 19.)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input HIGH Voltage Common Mode
Range (Differential) (Note 19.)
Input LOW Current
VEE+2.0
0.0
VEE+2.0
150
D
D
0.5
-150
0.0
VEE+2.0
150
0.5
-150
0.5
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 ohms to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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31
MC10EP11, MC100EP11
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21.)
-40 °C
Symbol
Characteristic
Min
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Within Device Skew
(Note 22.)
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
Typ
25°C
Max
Min
>3
Typ
85°C
Max
Min
>3
Typ
Max
>3
Unit
GHz
ps
CLK to Q, Q
140
Q0, Q1
150
200
250
10
160
220
270
15
15
.2
<1
800
1200
150
180
240
300
20
20
25
ps
.2
<1
.2
<1
ps
800
1200
800
1200
mV
150
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
ÉÉ
100
1
(JITTER)
0
0
1000
2000
3000
4000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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32
JITTEROUT ps (RMS)
VOUTpp (mV)
tr
Output Rise/Fall Times
Q, Q
70
120
170
80
130
180
100
150
200
ps
tf
(20% - 80%)
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
5000
6000
MC10EP11, MC100EP11
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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33
MC100EP14
3.3V / 5V1:5 Differential
ECL/PECL/HSTL Clock Driver
The MC100EP14 is a low skew 1- to- 5 differential driver, designed with
clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
single- ended (if the VBB output is used). HSTL inputs can be used when
the LVEP14 is operating under PECL conditions.
The EP14 specifically guarantees low output- to- output skew. Optimal
design, layout, and processing minimize skew within a device and from
device to device.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated even if only one output is
being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.
The MC100EP14, as with most other ECL devices, can be operated
from a positive VCC supply in PECL mode. This allows the EP14 to be
used for high performance clock distribution in 5.0 V systems.
Designers can take advantage of the EP14’s performance to distribute
low skew clocks across the backplane or the board.
•
•
•
•
•
•
•
•
400 ps Typical Propagation Delay
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MARKING
DIAGRAM*
20
20
100
1
EP14
TSSOP-20
DT SUFFIX
CASE 948E
A
L
Y
W
ALYW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
100 ps Device-to-Device Skew
25 ps Within Device Skew
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
ORDERING INFORMATION
PECL and HSTL Mode: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
 Semiconductor Components Industries, LLC, 2001
June, 2001 - Rev. 2
Device
34
Package
Shipping
MC100EP14DT
TSSOP
75 Units/Tray
MC100EP14DTR2
TSSOP
2500 Tape & Reel
Publication Order Number:
MC100EP14/D
MC100EP14
VCC
EN
VCC
CLK1
CLK1
VBB
CLK0
CLK0
CLK_SEL
VEE
20
19
18
17
16
15
14
13
12
11
1
0
D
Q
1
2
3
4
5
6
7
8
9
10
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram
PIN DESCRIPTION
PIN
FUNCTION
FUNCTION TABLE
CLK0*, CLK0**
ECL/PECL/HSTL CLK Input
CLK1*, CLK1**
ECL/PECL/HSTL CLK Input
Q0:4, Q0:4
ECL/PECL Outputs
CLK_SEL*
ECL/PECL Active Clock Select Input
EN*
ECL Sync Enable
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
CLK0
CLK1
CLK_SEL
EN
Q
L
H
X
X
X
X
X
L
H
X
L
L
H
H
X
L
L
L
L
H
L
H
L
H
L*
* On next negative transition of CLK0 or CLK1
* Pins will default low when left open.
** Pins will default to VCC/2 when left open.
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index
> 2 kV
> 100 V
> 2 kV
Level 1
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
357
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
http://onsemi.com
35
MC100EP14
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
6
V
-6
V
6
-6
V
V
50
100
mA
mA
± 0.5
mA
-40 to +85
°C
VCC
VEE
PECL Mode Power Supply
NECL Mode Power Supply
VEE = 0 V
VCC = 0 V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
IBB
TA
VBB Sink/Source
Operating Temperature Range
Tstg
θJA
Storage Temperature Range
-65 to +150
°C
20 TSSOP
20 TSSOP
140
100
°C/W
°C/W
20 TSSOP
23 to 41
°C/W
265
°C
Thermal Resistance (Junction to Ambient)
VI VCC
VI VEE
0 LFPM
500 LFPM
θJC
Thermal Resistance (Junction to Case)
std bd
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
55
65
75
58
68
78
62
72
82
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 4)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 4)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
VBB
Input LOW Voltage (Single Ended)
1355
1675
1355
1675
1355
1675
mV
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
1.2
3.3
1.2
3.3
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
1875
1.2
1875
150
D
D
0.5
-150
1875
150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 ohms to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
55
65
75
58
68
78
62
72
82
mA
Output HIGH Voltage (Note 7)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
VIH
Output LOW Voltage (Note 7)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
Input HIGH Voltage (Single Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
VBB
Input LOW Voltage (Single Ended)
3055
3375
3055
3375
3055
3375
mV
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
5.0
1.2
5.0
1.2
5.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
3575
1.2
150
D
D
0.5
-150
3575
150
0.5
-150
0.5
-150
3575
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 ohms to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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36
MC100EP14
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
55
65
75
58
68
78
62
72
82
mA
Output HIGH Voltage (Note 10)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 10)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Reference Voltage
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IEE
Power Supply Current
VOH
-1425
VEE+1.2
0.0
-1425
VEE+1.2
150
CLK
CLK
0.5
-150
0.0
-1425
VEE+1.2
150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 ohms to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
fmaxLVPECL
/HSTL
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH
tPHL
Propagation Delay to
Output Differential
tskew
Within-Device Skew
Device-to-Device Skew
(Note 13)
ts
th
Setup Time to CLK
Hold Time
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
VPP
Minimum Input Swing
tr/tf
Output Rise/Fall Time
(20%-80%)
Min
Typ
Max
Min
>2
275
EN to CLK
EN to CLK
25°C
100
200
Typ
85°C
Max
Min
>2
330
400
25
100
35
125
50
140
275
100
200
0.2
<1
150
800
1200
140
180
240
37
Max
>2
375
450
30
150
45
175
50
140
400
100
200
0.2
<1
150
800
1200
145
200
270
Unit
GHz
475
600
ps
40
175
50
200
ps
50
140
ps
0.2
<1
ps
150
800
1200
mV
150
225
300
ps
12. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
13. Skew is measured between outputs under identical transitions.
http://onsemi.com
Typ
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
ÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉ
ÉÉ
(JITTER)
100
1
0
0
1000
2000
3000
4000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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38
JITTEROUT ps (RMS)
VOUTpp (mV)
MC100EP14
MC10EP16, MC100EP16
3.3V / 5VECL Differential
Receiver/Driver
The EP16 is a world-class differential receiver/driver. The device is
functionally equivalent to the EL16 and LVEL16 devices with higher
performance capabilities. With output transition times significantly
faster than the EL16 and LVEL16, the EP16 is ideally suited for
interfacing with high frequency sources.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Under open input conditions (pulled to VEE) internal input clamps
will force the Q output LOW.
The 100 Series contains temperature compensation.
• 220 ps Typical Propagation Delay
• Maximum Frequency > 4 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
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MARKING DIAGRAMS*
8
8
8
HEP16
ALYW
1
SO-8
D SUFFIX
CASE 751
1
1
8
8
1
TSSOP-8
DT SUFFIX
CASE 948R
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
8
KP16
ALYW
HP16
ALYW
1
1
H = MC10
K = MC100
A = Assembly Location
•
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
• VBB Output
KEP16
ALYW
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Package
Shipping
MC10EP16D
Device
SO-8
98 Units/Rail
MC10EP16DR2
SO-8
2500 Tape & Reel
MC100EP16D
SO-8
98 Units/Rail
MC100EP16DR2
SO-8
2500 Tape & Reel
MC10EP16DT
TSSOP-8
100 Units/Rail
MC10EP16DTR2
TSSOP-8
2500 Tape & Reel
MC100EP16DT
TSSOP-8
100 Units/Rail
MC100EP16DTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2001
April, 2001 - Rev. 3
39
2500 Tape & Reel
Publication Order Number:
MC10EP16/D
MC10EP16, MC100EP16
NC
1
8
VCC
D
2
7
Q
D
3
6
Q
VBB
4
5
PIN DESCRIPTION
PIN
FUNCTION
D*, D**
Q, Q
VBB
VCC
VEE
NC
ECL Data Inputs
ECL Data Outputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
167
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
Input
PECL Mode In
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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40
VI VCC
VI VEE
MC10EP16, MC100EP16
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
24
31
20
24
31
20
24
32
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 4.)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
VIH
Output LOW Voltage (Note 4.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
Input HIGH Voltage (Single Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
VBB
Input LOW Voltage (Single Ended)
1365
1690
1430
1755
1490
1815
mV
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5.)
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
1890
2.0
1955
150
Input LOW Current
D
D
2015
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 ohms to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
24
31
20
24
31
20
24
32
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 7.)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
VIH
Output LOW Voltage (Note 7.)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
Input HIGH Voltage (Single Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
VBB
Input LOW Voltage (Single Ended)
3065
3390
3130
3455
3190
3515
mV
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8.)
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
3590
2.0
3655
150
Input LOW Current
D
D
3715
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 ohms to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
24
31
20
24
31
20
24
32
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 10.)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
VIH
Output LOW Voltage (Note 10.)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
Input HIGH Voltage (Single Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
VBB
Input LOW Voltage (Single Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
-1 185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11.)
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
-1410
VEE+2.0
0.0
150
D
D
0.5
-150
-1345
VEE+2.0
0.0
150
0.5
-150
-1285
VEE+2.0
0.5
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 ohms to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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41
MC10EP16, MC100EP16
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
17
25
36
17
25
36
22
26
38
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 13.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 13.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
VBB
Input LOW Voltage (Single Ended)
1355
1675
1355
1675
1355
1675
mV
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14.)
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
1875
2.0
1875
150
Input LOW Current
D
D
1875
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 ohms to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
17
25
36
17
25
36
22
26
38
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 16.)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
VIH
Output LOW Voltage (Note 16.)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
Input HIGH Voltage (Single Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
VBB
Input LOW Voltage (Single Ended)
3055
3375
3055
3375
3055
3375
mV
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17.)
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
3575
2.0
3575
150
Input LOW Current
D
D
3575
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 ohms to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
17
25
36
17
25
36
22
26
38
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 19.)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
VIH
Output LOW Voltage (Note 19.)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
VBB
Input LOW Voltage (Single Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20.)
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
-1425
VEE+2.0
0.0
150
D
D
0.5
-150
-1425
VEE+2.0
0.0
150
0.5
-150
-1425
VEE+2.0
0.5
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 ohms to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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42
MC10EP16, MC100EP16
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21.)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Min
Typ
25°C
Max
Min
>4
150
Max
Min
>4
220
280
Duty Cycle Skew (Note 22.)
5.0
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Q, Q
Typ
85°C
150
Typ
Max
>4
220
280
20
5.0
0.2
<1
150
800
1200
70
120
170
160
Unit
GHz
240
300
ps
20
5.0
20
ps
0.2
<1
0.2
<1
ps
150
800
1200
150
800
1200
mV
80
130
180
100
150
200
ps
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
800
VOUTpp (mV)
700
Measured
Simulated
600
7
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
É
É
200
2
100
1
(JITTER)
0
0
1000
2000
JITTEROUT ps (RMS)
8
3000
4000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
http://onsemi.com
43
5000
6000
MC10EP16, MC100EP16
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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44
MC100EP16F
3.3V / 5VECL Differential
Receiver/Driver With
Reduced Output Swing
The MC100EP16F is a differential receiver/driver. The device is
functionally equivalent to the EP16 device with higher performance
capabilities. With reduced output swings, rise/fall transition times are
significantly faster than on the EP16. The EP16F is ideally suited for
interfacing with high frequency sources.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
•
•
•
•
•
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MARKING
DIAGRAMS*
8
SO-8
D SUFFIX
CASE 751
8
1
KEP60
ALYW
1
100 ps Typical Rise and Fall Time
8
Max Frequency >4 GHz Typical
TSSOP-8
DT SUFFIX
CASE 948R
8
1
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0V
with VEE = -3.0 V to -5.5 V
Open Input Default State
HKP60
ALYW
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
•
• Safety Clamp on Inputs
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
 Semiconductor Components Industries, LLC, 2001
April, 2001 - Rev. 1
45
Device
Package
Shipping
MC100EP16FD
SO-8
98 Units/Rail
MC100EP16FDR2
SO-8
2500 Tape & Reel
MC100EP16FDT
TSSOP-8
100 Units/Rail
MC100EP16FDTR2
TSSOP-8 2500 Tape & Reel
Publication Order Number:
MC100EP16F/D
MC100EP16F
NC
D
D
1
8
2
7
3
6
PIN DESCRIPTION
VCC
Q
Q
PIN
FUNCTION
D*, D**
ECL Data Inputs
Q, Q
ECL Data Outputs
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
NC
No Connect
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
VBB
4
5
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
139
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Parameter
Symbol
Condition 1
VCC
PECL Mode Power Supply
VEE = 0 V
VEE
NECL Mode Power Supply
VCC = 0 V
VI
PECL
C Mode
ode Input
u Voltage
o age
VEE = 0 V
VCC = 0 V
NECL Mode Input Voltage
Condition 2
VI VCC
VI VEE
Continuous
Surge
Rating
Units
6
V
-6
V
6
V
-6
V
50
100
mA
mA
± 0.5
mA
Iout
Output Current
IBB
VBB Sink/Source
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44 ± 5%
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44 ± 5%
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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46
MC100EP16F
DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
28
35
25
31
38
26
33
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 4.)
1575
1690
1775
1575
1690
1775
1575
1690
1775
mV
VIH
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single Ended)
(Note 5.)
1490
1675
1490
1675
1490
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 6.)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
1875
2.0
1875
150
D
D
0.5
-150
1875
150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 ohms to VCC-2.0 volts.
5. Not recommended for single ended operation when using an EP16F to drive another EP16F. VOL has reduced output swing and may not
meet the VIL specification over temperature.
6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 7.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
28
35
25
31
38
26
33
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8.)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 8.)
3275
3390
3475
3275
3390
3475
3275
3390
3475
mV
VIH
Input HIGH Voltage (Single Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single Ended)
(Note 9.)
3190
3375
3190
3375
3190
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 10.)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
3575
2.0
150
D
D
0.5
-150
3575
150
0.5
-150
0.5
-150
3575
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
8. All loading with 50 ohms to VCC-2.0 volts.
9. Not recommended for single ended operation when using an EP16F to drive another EP16F. VOL has reduced output swing and may not
meet the VIL specification over temperature.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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47
MC100EP16F
DC CHARACTERISTICS, NECL VCC = 0V; VEE = -5.5V to -3.0V (Note 11.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
28
35
25
31
38
26
33
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 12.)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 12.)
-1725
-1610
-1525
-1725
-1610
-1525
-1725
-1610
-1525
mV
VIH
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single Ended)
(Note 13.)
-1810
-1625
-1810
-1625
-1810
-1625
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14.)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
-1425
VEE+2.0
0.0
-1425
VEE+2.0
150
D
D
0.5
-150
0.0
-1425
VEE+2.0
150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC.
12. All loading with 50 ohms to VCC-2.0 volts.
13. Not recommended for single ended operation when using an EP16F to drive another EP16F. VOL has reduced output swing and may not
meet the VIL specification over temperature.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0V; VEE = -3.0V to -5.5V or VCC = 3.0V to 5.5V; VEE = 0V (Note 15.)
-40 °C
Symbol
Characteristic
fmax
Maximum Toggle Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to Output Differential
tSKEW
Min
Typ
25°C
Max
Min
>4
170
Typ
85°C
Max
Min
>4
210
250
Duty Cycle Skew
5.0
tJITTER
Cycle-to-Cycle Jitter (RMS)
(See Figure 2. Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
Max
>4
220
260
20
5.0
0.2
<1
800
1200
GHz
300
ps
20
5.0
20
ps
0.2
<1
0.2
<1
ps
800
1200
150
800
1200
mV
tr
Output Rise/Fall Times
Q
70
85
110
80
100
120
90
tf
(20% - 80%)
15. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
110
130
ps
http://onsemi.com
48
150
200
Unit
250
150
180
Typ
MC100EP16F
800
VOUTpp (mV)
700
Measured
7
Simulated
600
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
200
2
100
1
É
É
(JITTER)
0
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 2. Fmax/JITTER
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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49
JITTEROUT ps (RMS)
8
MC10EP16T, MC100EP16T
3.3V / 5VECL Differential
Receiver/Driver with
Internal Termination
The EP16T is a world-class differential receiver/driver. The device
is functionally equivalent to the EP16 with internal termination
resistors. A 50 resistor is connected from the D input to the VT pin
and from the D input to the VT pin. Tie the VT and VT pins to VTT
supply (VCC - 2 V) for parallel termination or connect VT and VT
pins for 100 input series termination.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
The 100 Series contains temperature compensation.
• 220 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
•
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Internal 50 Termination Resistors
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MARKING DIAGRAMS*
8
8
8
1
SO-8
D SUFFIX
CASE 751
HEP61
ALYW
1
1
8
8
1
TSSOP-8
DT SUFFIX
CASE 948R
KEP61
ALYW
8
HP61
ALYW
1
H = MC10
K = MC100
A = Assembly Location
KP61
ALYW
1
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Package
Shipping
MC10EP16TD
Device
SO-8
98 Units/Rail
MC10EP16TDR2
SO-8
2500 Tape & Reel
MC100EP16TD
SO-8
98 Units/Rail
MC100EP16TDR2
SO-8
2500 Tape & Reel
MC10EP16TDT
TSSOP-8
100 Units/Rail
MC10EP16TDTR2
TSSOP-8
2500 Tape & Reel
MC100EP16TDT
TSSOP-8
100 Units/Rail
MC100EP16TDTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 3
50
2500 Tape & Reel
Publication Order Number:
MC10EP16T/D
MC10EP16T, MC100EP16T
VT
1
8
VCC
50 D
D
PIN DESCRIPTION
2
7
3
Q
PIN
FUNCTION
6
Q
D, D
Q, Q
VCC
VEE
VT
VT
ECL Data Inputs
ECL Data Outputs
Positive Supply
Negative Supply
50 Termination Resistor to D
50 Termination Resistor to D
5
VEE
50 VT
4
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL-94 V-0 @ 0.125 in
Transistor Count
167
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
6
V
-6
V
6
-6
V
V
50
100
mA
mA
VCC
PECL Mode Power Supply
VEE = 0 V
VEE
NECL Mode Power Supply
VCC = 0 V
VI
Input
PECL Mode In
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
8 TSSOP
41 to 44
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
http://onsemi.com
51
VI VCC
VI VEE
MC10EP16T, MC100EP16T
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
16
23
31
16
23
31
16
23
31
mA
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
VIH
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
VIHCMR
Input LOW Voltage (Single-Ended)
1365
1690
1430
1755
1490
1815
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
2.0
3.3
2.0
3.3
2.0
3.3
V
RT
IIH
Internal Termination Resistor
43
57
43
57
43
Input HIGH Current
50
150
150
57
150
µA
IIL
Input LOW Current
-150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
16
23
31
16
23
31
16
23
31
mA
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
VIH
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
VIHCMR
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
2.0
5.0
2.0
5.0
2.0
5.0
V
RT
IIH
Internal Termination Resistor
43
57
43
57
43
Input HIGH Current
50
150
150
57
150
µA
IIL
Input LOW Current
-150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
16
23
31
16
23
31
16
23
31
mA
Output HIGH Voltage (Note 10)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
VIH
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
VIHCMR
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
0.0
V
RT
IIH
Internal Termination Resistor
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
VEE+2.0
0.0
43
57
Input HIGH Current
150
VEE+2.0
43
50
0.0
57
150
VEE+2.0
43
57
150
µA
IIL
Input LOW Current
-150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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52
MC10EP16T, MC100EP16T
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
18
25
35
20
27
37
22
29
39
mA
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
VIHCMR
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
2.0
3.3
2.0
3.3
2.0
3.3
V
RT
IIH
Internal Termination Resistor
43
57
43
57
43
Input HIGH Current
50
150
150
57
150
µA
IIL
Input LOW Current
-150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
18
25
35
20
27
37
22
29
39
mA
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
VIH
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
VIHCMR
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
2.0
5.0
2.0
5.0
2.0
5.0
V
RT
IIH
Internal Termination Resistor
43
57
43
57
43
Input HIGH Current
50
150
150
57
150
µA
IIL
Input LOW Current
-150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
18
25
35
20
27
37
22
29
39
mA
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
VIH
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
VIHCMR
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
0.0
V
RT
IIH
Internal Termination Resistor
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
VEE+2.0
0.0
43
57
Input HIGH Current
150
VEE+2.0
43
50
0.0
57
150
VEE+2.0
43
57
150
µA
IIL
Input LOW Current
-150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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53
MC10EP16T, MC100EP16T
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
Characteristic
Min
fmax
Maximum Frequency
(See Figure 2 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Typ
25°C
Max
Min
>3
150
Typ
Max
Min
>3
230
300
Duty Cycle Skew (Note 22)
5.0
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2 Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Q, Q
85°C
150
Typ
Max
>3
240
300
20
5.0
0.2
<1
150
800
1200
70
120
170
200
Unit
GHz
275
350
ps
20
5.0
20
ps
0.2
<1
0.2
<1
ps
150
800
1200
150
800
1200
mV
80
130
180
100
140
200
ps
900
9
800
8
700
7
600
6
500
5
JITTEROUT ps (RMS)
VOUTpp (mV)
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
400
4
300
3
200
2
(JITTER)
100
1
0
0
500
1000
1500
2000
2500
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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54
3000
3500
4000
MC10EP16T, MC100EP16T
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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55
MC10EP16VA, MC100EP16VA
3.3V / 5VECL Differential
Receiver/Driver with High
Gain
The EP16VA is a world-class differential receiver/driver. The
device is functionally equivalent to the EP16 and LVEP16 devices but
with high gain output. QHG and QHG outputs have a DC gain several
times larger than the DC gain of an EP16.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Under open input conditions (pulled to VEE) internal input clamps
will force the QHG output LOW.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
The 100 Series contains temperature compensation.
•
•
•
•
•
•
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MARKING DIAGRAMS*
1
SO-8
D SUFFIX
CASE 751
Gain > 200
20 mV Minimum Input Voltage Swing
HEP64
ALYW
8
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
KP64
ALYW
HP64
ALYW
1
1
1
H = MC10
K = MC100
A = Assembly Location
Maximum Frequency > 3 GHz Typical
KEP64
ALYW
1
1
8
8
TSSOP-8
DT SUFFIX
CASE 948R
270 ps Typical Propagation Delay
8
8
8
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
•
• VBB Output
ORDERING INFORMATION
Package
Shipping
MC10EP16VAD
Device
SO-8
98 Units/Rail
MC10EP16VADR2
SO-8
2500 Tape & Reel
MC100EP16VAD
SO-8
98 Units/Rail
MC100EP16VADR2
SO-8
2500 Tape & Reel
MC10EP16VADT
TSSOP-8
100 Units/Rail
MC10EP16VADTR2
TSSOP-8 2500 Tape & Reel
MC100EP16VADT
TSSOP-8
100 Units/Rail
MC100EP16VADTR2 TSSOP-8 2500 Tape & Reel
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 4
56
Publication Order Number:
MC10EP16VA/D
MC10EP16VA, MC100EP16VA
NC
1
VCC
8
PIN DESCRIPTION
D
D
VBB
2
7
QHG
QHG
6
3
4
5
PIN
FUNCTION
D*, D*
ECL Data Inputs
QHG, QHG
ECL High Gain Data Outputs
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
NC
No Connect
* Pins will default LOW when left open.
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL-94 V-0 @ 0.125 in
Transistor Count
167
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
VI
NECL Mode Power Supply
-6
V
PECL
C Mode
ode Input
u Voltage
o age
VCC = 0 V
VEE = 0 V
6
V
NECL Mode Input Voltage
VCC = 0 V
Output Current
Iout
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
θJA
Thermal Resistance (Junction-to-Ambient)
θJC
Thermal Resistance (Junction-to-Case)
θJA
Thermal Resistance (Junction-to-Ambient)
θJC
Thermal Resistance (Junction-to-Case)
VI VCC
VI VEE
-6
V
Continuous
50
mA
Surge
100
mA
± 0.5
mA
-40 to +85
°C
-65 to +150
°C
190
°C/W
8 SOIC
130
°C/W
8 SOIC
41 to 44
°C/W
8 TSSOP
185
°C/W
8 TSSOP
140
°C/W
8 TSSOP
41 to 44
°C/W
265
°C
0 LFPM
8 SOIC
500 LFPM
std bd
0 LFPM
500 LFPM
std bd
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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57
MC10EP16VA, MC100EP16VA
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
31
22
30
38
24
32
40
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 4)
2165
2240
2415
2230
2355
2480
2290
2415
2540
mV
VOL
VIH
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
1365
1690
1460
1755
1490
1815
mV
Output Voltage Reference
1750
1950
1825
2025
1850
2050
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
1850
2.0
1925
150
1950
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
31
22
30
38
24
32
40
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 7)
3865
3940
4115
3930
4055
4180
3990
4115
4240
mV
VOL
VIH
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
Output Voltage Reference
3450
3650
3525
3725
3550
3750
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
3550
2.0
3625
150
3650
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
31
22
30
38
24
32
40
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 10)
-1 135
-1060
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
VIH
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
Output Voltage Reference
-1550
-1350
-1475
-1275
-1450
-1250
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
-1450
VEE+2.0
0.0
VEE+2.0
150
0.5
-1375
0.0
VEE+2.0
150
0.5
-1350
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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58
MC10EP16VA, MC100EP16VA
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
36
22
30
38
24
32
40
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
Output Voltage Reference
1550
1950
1725
1925
1700
1900
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
1850
2.0
1825
150
1800
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
36
22
30
38
24
32
40
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
VIH
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
Output Voltage Reference
3450
3650
3425
3625
3400
3600
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
3550
2.0
3525
150
3500
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
36
22
30
38
24
32
40
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
VIH
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
Output Voltage Reference
-1550
-1350
-1575
-1375
-1600
-1400
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
-1450
VEE+2.0
0.0
VEE+2.0
150
0.5
-1475
0.0
VEE+2.0
150
0.5
-1500
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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59
MC10EP16VA, MC100EP16VA
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 2 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Min
Typ
25°C
Max
Min
Typ
>3
200
Max
Min
>3
260
320
Duty Cycle Skew (Note 22)
5.0
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2 Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
(See Figure 3)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Q, Q
85°C
220
Typ
Max
>3
270
340
20
5.0
0.2
<1
20
800
1200
70
110
170
250
Unit
GHz
320
390
ps
20
5.0
20
ps
0.2
<1
0.2
<1
ps
20
800
1200
20
800
1200
mV
80
110
180
80
120
200
ps
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
(JITTER)
1
100
0
0
1000
2000
3000
4000
5000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
800
700
VOUTpp (mV)
600
500
400
300
200
100
0
20
15
10
5
VINpp (mV)
Figure 3. Gain vs. Input Voltage (50 MHz)
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60
JITTEROUT ps (RMS)
VOUTpp (mV)
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
0
MC10EP16VA, MC100EP16VA
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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61
MC100EP16VB
3.3V / 5VECL Differential
Receiver/Driver with High
and Low Gain
The EP16VB is a world-class differential receiver/driver. The
device is functionally equivalent to the EP16 and LVEP16 devices but
with both high and low gain outputs. QHG and QHG outputs have a DC
gain several times larger than the DC gain of an EP16. Q output is
provided for feedback purposes.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
The 100 Series contains temperature compensation.
•
•
•
•
•
•
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MARKING DIAGRAMS*
8
8
1
SO-8
D SUFFIX
CASE 751
KEP65
ALYW
1
8
8
1
300 ps Typical Propagation Delay
KP65
ALYW
TSSOP-8
DT SUFFIX
CASE 948R
Gain > 200
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
VBB Output
K
A
L
Y
W
1
= MC100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 1
62
Device
Package
Shipping
MC100EP16VBD
SO- 8
98 Units/Rail
MC100EP16VBDR2
SO- 8
2500 Tape & Reel
MC100EP16VBDT
TSSOP- 8
100 Units/Rail
MC100EP16VBDTR2
TSSOP- 8 2500 Tape & Reel
Publication Order Number:
MC100EP16VB/D
MC100EP16VB
Q
1
VCC
8
PIN DESCRIPTION
D
D
VBB
2
7
QHG
QHG
6
3
4
5
PIN
FUNCTION
D*, D*
ECL Data Inputs
Q
ECL Data Output
QHG, QHG
ECL High Gain Data Outputs
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of DryPack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL-94 V-0 @ 0.125 in
Transistor Count
167
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Rating
Units
6
V
-6
V
6
V
-6
V
Continuous
50
mA
Surge
100
mA
± 0.5
mA
-40 to +85
°C
VCC
PECL Mode Power Supply
VEE = 0 V
VEE
NECL Mode Power Supply
VCC = 0 V
VI
PECL
C Mode
ode Input
u Voltage
o age
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Output Current
Iout
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
θJA
Thermal Resistance (Junction-to-Ambient)
θJC
Thermal Resistance (Junction-to-Case)
θJA
Thermal Resistance (Junction-to-Ambient)
θJC
Thermal Resistance (Junction-to-Case)
Condition 2
VI VCC
VI VEE
-65 to +150
°C
190
°C/W
8 SOIC
130
°C/W
8 SOIC
41 to 44
°C/W
8 TSSOP
185
°C/W
8 TSSOP
140
°C/W
8 TSSOP
41 to 44
°C/W
265
°C
0 LFPM
8 SOIC
500 LFPM
std bd
0 LFPM
500 LFPM
std bd
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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63
MC100EP16VB
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
24
34
44
26
36
46
28
38
48
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 4)
2125
2250
2375
2100
2230
2350
2100
2220
2350
mV
VOL
VIH
Output LOW Voltage (Note 4)
1305
1430
1555
1305
1400
1555
1305
1380
1555
mV
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
Output Voltage Reference
1760
1960
1720
1920
1690
1890
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
1860
2.0
1820
150
1790
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
24
34
44
26
36
46
28
38
48
mA
Output HIGH Voltage (Note 7)
3825
3950
4075
3800
3930
4050
3800
3920
4050
mV
VOL
VIH
Output LOW Voltage (Note 7)
3005
3130
3255
3005
3100
3255
3005
3080
3255
mV
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
Output Voltage Reference
3460
3660
3420
3620
3390
3590
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
3560
2.0
3520
150
3490
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
Symbol
Characteristic
Min
-40 °C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
24
34
44
26
36
46
28
38
48
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 10)
-1 175
-1050
-925
-1200
-1070
-950
-1200
-1080
-950
mV
VOL
VIH
Output LOW Voltage (Note 10)
-1995
-1870
-1745
-1995
-1900
-1745
-1995
-1920
-1745
mV
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
Output Voltage Reference
-1540
-1340
-1580
-1380
-1610
-1410
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
-1440
VEE+2.0
0.0
VEE+2.0
150
0.5
-1480
0.0
VEE+2.0
150
0.5
-1510
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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64
MC100EP16VB
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
Min
fmax
Maximum Frequency
(See Figure 2 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay
(Differential) Q
(Differential) QHG, QHG
(Single-Ended) Q
(Single-Ended) QHG, QHG
tSKEW
Typ
25°C
Max
Min
>3
200
200
250
250
85°C
Typ
Max
Min
Typ
>3
275
280
325
330
350
350
400
400
Duty Cycle Skew (Note 13)
5.0
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2 Fmax/JITTER)
VPP
Input Voltage Swing
tr
tf
Output Rise/Fall Times
(20% - 80%)
250
250
300
300
Max
>3
300
300
350
350
400
400
450
450
20
5.0
0.2
<1
275
275
325
325
Unit
GHz
310
320
360
370
425
425
475
475
ps
20
5.0
20
ps
0.2
<1
0.2
<1
ps
(Differential) HG
(Differential) Q
25
150
800
800
1200
1200
25
150
800
800
1200
1200
25
150
800
800
1200
1200
mV
Q
QHG, QHG
200
70
270
130
400
220
220
80
300
150
420
240
250
100
310
170
450
270
ps
900
9
800
8
700
7
600
6
500
5
JITTEROUT ps (RMS)
VOUTpp (mV)
12. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
13. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
ÉÉ
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
400
4
300
3
200
2
100
1
0
0
500
1000
1500
2000
2500
3000
3500
4000
FREQUENCY (MHz)
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
100
1
JITTEROUT ps (RMS)
VOUTpp (mV)
Figure 2. Fmax/Jitter for QHG, QHG Output
900
ÉÉ
ÉÉÉÉ ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
0
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
Figure 3. Fmax/Jitter for Q Output
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65
3500
4000
MC100EP16VB
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices.)
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66
MC100EP16VC
3.3V / 5VECL Differential
Receiver/Driver with High
Gain and Enable Output
The EP16VC is a world-class differential receiver/driver. The
device is functionally equivalent to the EP16 and LVEP16 devices but
with high gain and enable output.
The EP16VC provides an EN input which is synchronized with the
data input (D) signal in a way that provides glitchless gating of the
QHG and QHG outputs.
When the EN signal is LOW, the input is passed to the outputs and
the data output equals the data input. When the data input is HIGH and
EN goes HIGH, it will force the QHG LOW and the QHG HIGH on the
next negative transition of the data input. If the data input is LOW
when the EN goes HIGH, the next data transition to a HIGH is ignored
and QHG remains LOW and QHG remains HIGH. The next positive
transition of the data input is not passed on to the data outputs under
these conditions. The QHG and QHG outputs remain in their disabled
state as long as the EN input is held HIGH. The EN input has no
influence on the Q output and the data input is passed on (inverted) to
this output whether EN is HIGH or LOW. This configuration is ideal
for crystal oscillator applications where the oscillator can be free
running and gated on and off synchronously without adding extra
counts to the output.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
•
•
•
•
•
310 ps Typical Prop Delay Q, 380 ps Typical Prop Delay QHG, QHG
Gain > 200
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
•
• QHG Output Will Default LOW with D Inputs Open or at VEE
• VBB Output
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MARKING DIAGRAMS*
8
8
KEP66
ALYW
1
SO-8
D SUFFIX
CASE 751
1
8
8
KP66
ALYW
1
TSSOP-8
DT SUFFIX
CASE 948R
1
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC100EP16VCD
SO-8
98 Units/Rail
MC100EP16VCDR2
SO-8
2500 Tape & Reel
MC100EP16VCDT
TSSOP-8
100 Units/Rail
MC100EP16VCDTR2 TSSOP-8 2500 Tape & Reel
 Semiconductor Components Industries, LLC, 2002
September, 2002- Rev. 1
67
Publication Order Number:
MC100EP16VC/D
MC100EP16VC
Q
D
VBB
1
8
2
7
6
3
LEN
VBB
EN
Q
PIN DESCRIPTION
QHG
QHG
OE
LATCH
4
VCC
5
D
VEE
PIN
FUNCTION
D*
ECL Data Input
Q
ECL Data Output
QHG, QHG
ECL High Gain Data Outputs
EN*
ECL Enable Input
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 SOIC
41 to 44
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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68
VI VCC
VI VEE
MC100EP16VC
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
Symbol
IEE
Characteristic
Power Supply Current
Min
-40 °C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
25
36
45
30
40
50
32
42
52
Unit
mA
VOH
VOL
Output HIGH Voltage (Note 4)
2105
2230
2355
2105
2230
2355
2105
2230
2355
mV
Output LOW Voltage (Note 4)
1305
1430
1555
1305
1430
1555
1305
1430
1555
mV
VIH
VIL
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
VIHCMR
Output Voltage Reference
1725
1925
1700
1900
1675
1875
mV
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
A
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
1825
2.0
1800
150
Input LOW Current
D
1775
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Symbol
IEE
VOH
Characteristic
Power Supply Current
Min
25
36
45
30
40
50
32
42
52
Unit
mA
Output HIGH Voltage (Note 7)
3805
3930
4055
3805
3930
4055
3805
3930
4055
mV
VOL
VIH
Output LOW Voltage (Note 7)
3005
3130
3255
3005
3130
3255
3005
3130
3255
mV
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
Output Voltage Reference
3425
3625
3400
3600
3375
3575
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
A
3525
2.0
3500
150
Input LOW Current
D
3475
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
Min
-40 °C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
25
36
45
30
40
50
32
42
52
Unit
mA
Output HIGH Voltage (Note 10)
-1 195
-1070
-945
-1 195
-1070
-945
-1 195
-1070
-945
mV
Output LOW Voltage (Note 10)
-1995
-1870
-1745
-1995
-1870
-1745
-1995
-1870
-1745
mV
VIH
VIL
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
VIHCMR
Output Voltage Reference
-1575
-1375
-1600
-1400
-1625
-1425
mV
0.0
V
IIH
IIL
Input HIGH Current
150
A
Symbol
IEE
Characteristic
Power Supply Current
VOH
VOL
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
Input LOW Current
-1475
VEE+2.0
0.0
VEE+2.0
150
D
0.5
-1500
0.0
VEE+2.0
150
0.50
-1525
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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69
MC100EP16VC
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 12)
-40 °C
Symbol
Min
Characteristic
Typ
25°C
Max
Min
>3
Typ
85°C
Max
Min
>3
Typ
Max
fmax
Maximum Frequency
(See Figure 2 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay
(Differential) Q
(Differential) QHG, QHG
(Single-Ended) Q
(Single-Ended) QHG, QHG
200
250
250
300
280
360
330
410
tS
Setup Time
EN = L to D
EN =H to D
50
100
tH
Hold Time
EN = L to D
EN =H to D
100
50
tSKEW
Duty Cycle Skew (Note 13)
5.0
20
5.0
20
5.0
20
ps
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2 Fmax/JITTER)
0.2
<1
0.2
<1
0.2
<1
ps
VPP
Input Voltage Swing
tr
tf
Output Rise/Fall Times
(20% - 80%)
350
450
400
500
250
300
300
350
310
380
360
430
15
60
50
100
50
15
100
50
>3
Unit
400
500
450
550
GHz
275
325
325
375
340
430
390
480
425
525
475
575
ps
5
40
50
100
18
10
ps
40
20
100
50
5
20
ps
(Differential) HG
(Differential) Q
25
150
800
800
1200
1200
25
150
800
800
1200
1200
25
150
800
800
1200
1200
mV
Q
QHG, QHG
200
70
300
130
400
220
250
80
350
150
450
240
250
100
350
170
500
270
ps
12. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
13. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
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70
MC100EP16VC
900
9
800
8
700
7
600
6
500
5
JITTEROUT ps (RMS)
VOUTpp (mV)
Single-Ended Input
ÉÉ
ÉÉÉÉ
ÉÉ
ÉÉÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
400
4
300
3
200
2
100
1
0
0
500
1000
1500
2000
2500
3000
3500
4000
FREQUENCY (MHz)
900
9
800
8
700
7
600
6
500
5
JITTEROUT ps (RMS)
VOUTpp (mV)
Figure 2. Fmax/Jitter for QHG, QHG Output
ÉÉÉÉÉÉÉ
ÉÉ
ÉÉÉÉÉÉÉ
ÉÉ
ÉÉÉÉÉÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
400
4
300
3
200
2
100
1
0
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
Figure 3. Fmax/Jitter for Q Output
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71
3500
4000
MC100EP16VC
900
9
800
8
700
7
600
6
500
5
JITTEROUT ps (RMS)
VOUTpp (mV)
Differential Inputs
ÉÉ
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
400
4
300
3
200
2
100
1
0
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
900
9
800
8
700
7
600
6
500
5
JITTEROUT ps (RMS)
VOUTpp (mV)
Figure 4. Fmax/Jitter for QHG, QHG Output
ÉÉÉÉÉ
ÉÉ
ÉÉÉÉÉ
ÉÉ
ÉÉÉÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
400
4
300
3
200
2
100
1
0
0
500
1000
1500
2000
FREQUENCY (MHz)
Figure 5. Fmax/Jitter for Q Output
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72
2500
3000
MC100EP16VC
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices.)
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73
MC100EP16VS
3.3V / 5VECL Differential
Receiver/Driver with
Variable Output Swing
The MC100EP16VS is a differential receiver with variable output
amplitude. The device is functionally equivalent to the 100EP16 with
an input pin that controls the amplitude of the outputs.
The VCTRL input pin controls the output amplitude of the EP16VS
and is referenced to VCC. (See Figure 5.) The operational range of the
VCTRL input is from ≤ VBB (max output amplitude) to VCC (min
output amplitude). (See Figure 4.) A variable resistor between the VCC
and VBB pins, with the wiper driving VCTRL, can control the output
amplitude. Typical application circuits and a VCTRL Voltage vs.
Output Amplitude graph are described in this data sheet. When left
open, the VCTRL pin will be internally pulled down to VEE and operate
as a standard EP16, with 100% output amplitude.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
•
•
•
•
•
•
•
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MARKING
DIAGRAMS*
8
SO-8
D SUFFIX
CASE 751
8
1
1
8
TSSOP-8
DT SUFFIX
CASE 948R
8
1
KP62
ALYW
1
10
220 ps Propagation Delay
Maximum Frequency > 4 GHz Typical (See Graph)
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
Q Output Will Default LOW with Inputs Open or at VEE
KEP62
ALYW
1
K
A
L
Y
W
QFN-10
MP SUFFIX
CASE 485C
10
1
KP62
ALYW
= MC100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
 Semiconductor Components Industries, LLC, 2002
January, 2002 - Rev. 2
74
Device
Package
Shipping
MC100EP16VSD
SO-8
98 Units/Rail
MC100EP16VSDR2
SO-8
2500 Tape & Reel
MC100EP16VSDT
TSSOP
100 Units/Rail
MC100EP16VSDTR2
TSSOP
2500 Tape & Reel
MC100EP16VSMP
QFN
124 Units/Rail
MC100EP16VSMPR2
QFN
3000 Tape & Reel
Publication Order Number:
MC100EP16VS/D
MC100EP16VS
VCTRL
D
D
VBB
1
8
2
VCC
7
3
1
10 VCC
D
2
9
Q
D
3
8
Q
VBB
4
7
VEE
NC
5
6
NC
Q
6
4
VCTRL
Q
5
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
Figure 2. 10-Lead QFN Pinout (Top View)
PIN DESCRIPTION
PIN
FUNCTION
8 LD
10 LD
D*, D**
ECL Data Inputs
2, 3
2, 3
Q, Q
ECL Data Outputs
6, 7
8, 9
VCTRL*
Output Swing Control
1
1
VBB
Reference Voltage Output
4
4
VCC
Positive Supply
8
10
VEE
Negative Supply
5
7
NC
No Connect
5, 6
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index
> 4 kV
> 200 V
> 2 kV
Level 1
UL-94 code V-0 A 1/8″
28 to 34
Transistor Count
140 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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75
MC100EP16VS
MAXIMUM RATINGS (Note 2)
Symbol
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
8 TSSOP
41 to 44 ± 5%
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
10 QFN
10 QFN
40
20
°C/W
°C/W
10 QFN
3.3
°C/W
VI ≤ VCC
VI ≥ VEE
θJC
Thermal Resistance (Junction-to-Case)
std bd
2. Maximum Ratings are those values beyond which device damage may occur.
DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
IEE
Power Supply Current
VOH
Output HIGH Voltage (Max Swing)
(Note 4)
VCC ≥ VCTRL ≥ VEE
VOL
Output LOW Voltage (Max Swing)
(Note 4)
VCTRL ≤ VBB
Min
Typ
30
36
2155
Max
Min
Typ
38
42
31
2405
2155
1605
1355
85°C
Max
Typ
40
44
32
2405
2155
1490
See
Fig.3
2105
2230
1520
1605
1355
See
Fig.3
Max
Unit
48
mA
2405
mV
2355
2095
2420
2075
1675
1490
2005
1805
2220
2345
2065
2420
2075
1675
1490
2005
1805
D, D Input HIGH Voltage (Single-Ended)
2075
VIL
D, D Input LOW Voltage (Single-Ended)
1490
VBB
Output Voltage Reference
1805
VCTRL
Input Voltage (VCTRL)
VEE
VCC
VEE
VCC
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
2.0
2.9
2.0
2.9
IIH
Input HIGH Current
IIL
Input LOW Current
1905
150
0.5
-150
1905
1605
2190
2315
2420
mV
1675
mV
2005
mV
VEE
VCC
mV
2.0
2.9
V
150
µA
150
0.5
-150
1520
See
Fig.3
VIH
D
D
Min
mV
1355
VCC ≥ VCTRL > VBB
VCTRL = VCC (Min Swing)
25°C
0.5
-150
1905
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 Ω to VCC-2.0 volts. VOH does not change with VCTRL. VOL changes with VCTRL. VCTRL is referenced to VCC.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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76
MC100EP16VS
DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 7)
VCC > VCTRL > VEE
VOL
Output LOW Voltage (Max Swing)
(Note 7)
VCTRL ≤ VBB
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
36
42
31
38
44
32
40
48
mA
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
3055
3190
3305
3055
3220
3305
3055
3220
3305
mV
VCC ≥ VCTRL > VBB
VCTRL = VCC (Min Swing)
25°C
See
Fig.3
3805
3930
See
Fig.3
4055
3795
3920
See
Fig.3
4045
3765
3890
4015
VIH
D, D Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
D, D Input LOW Voltage (Single-Ended)
3190
3375
3190
3375
3190
3375
mV
VCTRL
Input Voltage (VCTRL)
VEE
VCC
VEE
VCC
VEE
VCC
mV
VBB
Output Voltage Reference
3505
3705
3505
3705
3505
3705
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
4.6
2.0
4.6
2.0
4.6
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
3605
2.0
3605
150
D
D
3605
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 Ω to VCC-2.0 volts. VOH does not change with VCTRL. VOL changes with VCTRL. VCTRL is referenced to VCC.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 10)
VCC > VCTRL > VEE
VOL
Output LOW Voltage (Max Swing)
(Note 10)
VCTRL ≤ VBB
25°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
36
42
31
38
44
32
40
48
mA
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
-1945
-1810
-1695
-1945
-1780
-1695
-1945
-1780
-1695
mV
VCC ≥ VCTRL > VBB
See
Fig.3
VCTRL = VCC (Min Swing)
-1 195
VIH
D, D Input HIGH Voltage (Single- Ended)
-1225
VIL
D, D Input LOW Voltage (Single- Ended)
-1810
VBB
Output Voltage Reference
-1525
VCTRL
Input Voltage (VCTRL)
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
IIH
Input HIGH Current
IIL
Input LOW Current
-1070
-1425
VEE
VEE+2.0
See
Fig.3
-945
-1205
-880
-1225
-1625
-1810
-1325
-1525
VCC
VEE
-0.4
0.5
-150
-1080
-1425
VEE+2.0
150
D
D
85°C
See
Fig.3
-955
-1235
-880
-1225
-1625
-1810
-1325
-1525
VCC
VEE
-0.4
-1425
VEE+2.0
150
0.5
-150
-1 110
0.5
-150
-985
-880
mV
-1625
mV
-1325
mV
VCC
mV
-0.4
V
150
µA
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 Ω to VCC-2.0 volts. VOH does not change with VCTRL. VOL changes with VCTRL. VCTRL is referenced to VCC.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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77
MC100EP16VS
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
>4
fmax
Maximum Toggle Frequency
(See Figure 7. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to Output Differential
Max Swing
Min Swing
tSKEW
Max
Min
>4
Typ
Max
>4
Unit
GHz
ps
220
150
280
210
Duty Cycle Skew (Note 13)
5.0
tJITTER
Cycle-to-Cycle Jitter
(See Figure 7. Fmax/JITTER)
VPP
Input Voltage Swing (Differential) (Note 14)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Max Swing Q
Min Swing
Typ
85°C
150
90
150
90
220
150
280
210
20
5.0
0.2
<1
150
800
1200
70
30
120
80
170
130
160
100
240
160
300
220
20
5.0
20
ps
0.2
<1
0.2
<1
ps
150
800
1200
150
800
1200
mV
80
20
130
70
180
120
100
20
150
70
200
120
ps
12. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC-2.0 V.
13. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
14. VPP(min) is minimum input swing for which AC parameters are guaranteed.
100
90
80
VSWING (%)
70
60
50
40
30
20
10
0
0.0
0.5
1.0
VOLTS (V)
Figure 3. VCC - VCTRL (pin #1)
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78
1.5
2.0
VPK- PK
MC100EP16VS
VOH
Min Swing
Max Swing
VOL
0.0
0.5
1.0
1.3
1.5
2.0
VOLTS (V)
Figure 4. VCC - VCTRL
VCTRL
+
1
8
VCC
(10)
VCTRL
D
2
VSWING
(pk-pk)
7
Q
(9)
D
3
6
Q
(8)
VBB
4
5
VEE
(7)
50 50 VCC-2 V
Figure 5. Voltage Source Implementation for 8 Ld Package
10 Ld Package Pins in ( )
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79
MC100EP16VS
+5 V
1
8
VCC
(10)
VCTRL
D
2
VSWING
(pk-pk)
7
Q
(9)
D
3
6
Q
(8)
VBB
4
470 470 5
VEE
(7)
1000
10
900
9
800
2.00 V Below VCC
8
700
7
1.25 V Below VCC
600
6
1.00 V Below VCC
500
5
0.75 V Below VCC
400
4
300
3
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
200
0.25 V Below VCC
100
(JITTER)
2
1
0
0
500
1000
1500
2000
2500
FREQUENCY (MHz)
Figure 7. Fmax/Jitter
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80
3000
3500
4000
JITTEROUT ps (RMS)
VOUTpp (mV)
Figure 6. Alternative Implementation for 8 Ld Package
10 Ld Package Pins in ( )
É
É
MC100EP16VS
Q
D
Driver
Device
Receiver
Device
D
Q
50 Ω
50 Ω
VTT
VTT = VCC - 2.0 V
Figure 8. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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81
MC100EP16VT
3.3V / 5VECL Differential
Receiver/Driver with
Variable Output Swing and
Internal Input Termination
The MC100EP16VT is a differential receiver functionally equivalent
to the 100EP16 with input pins controlling the amplitude of the outputs
(pin 1) and providing an internal termination network (pin 4).
The VCTRL input pin controls the output amplitude of the EP16VT
and is referenced to VCC. (See Figure 4.) The operational range of the
VCTRL input is from VBB (a supply at VCC-1.42 V, maximum
output amplitude) to VCC (minimum output amplitude). VBB is an
externally supplied voltage equal to VCC-1.42 V (See Figures 2 and
3). A variable resistor between VCC and VBB, with the wiper driving
VCTRL, can control the output amplitude. Typical application circuits
and a VCTRL Voltage vs. Output Amplitude graph are described in this
data sheet. When left open, the VCTRL pin will be internally pulled
down to VEE and operate as a standard EP16, with 100% output
amplitude.
The VTT input pin offers an internal termination network for a 50 ohm
line impedance environment, shown in Figure 1. For further reference,
see Application Note AND8020, Termination of ECL Logic Devices.
Input considerations are required for D and D under no signal conditions
to prevent instability.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
•
•
•
•
•
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MARKING
DIAGRAMS*
8
SO-8
D SUFFIX
CASE 751
8
1
KEP63
ALYW
1
8
TSSOP-8
DT SUFFIX
CASE 948R
8
1
KP63
ALYW
1
K
A
L
Y
W
= MC100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
220 ps Propagation Delay
Maximum Frequency > 4 GHz Typical (See Graph)
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
ORDERING INFORMATION
•
• 50 Internal Termination Resistor
Device
Package
Shipping
MC100EP16VTD
SO-8
98 Units/Rail
MC100EP16VTDR2
SO-8
2500 Tape & Reel
MC100EP16VTDT
TSSOP-8
100 Units/Rail
MC100EP16VTDTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2001
April, 2001 - Rev. 1
82
2500 Tape & Reel
Publication Order Number:
MC100EP16VT/D
MC100EP16VT
VCTRL
D
1
8
2
7
PIN DESCRIPTION
VCC
Q
50 D
3
6
Q
50 VTT
4
5
VEE
PIN
FUNCTION
D, D
ECL Data Inputs
Q, Q
ECL Data Outputs
VCTRL*
Output Swing Control
VTT
Termination Supply
VCC
Positive Supply
VEE
Negative Supply
* Pin will default LOW when left open.
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
140 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44 ± 5%
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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83
VI VCC
VI VEE
MC100EP16VT
DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
-40 °C
Symbol
Characteristic
IEE
Power Supply Current
VOH
Output HIGH Voltage (Max Swing)
(Note 4.)
VCC VCTRL VEE
VOL
Output LOW Voltage (Max Swing)
(Note 4.)
VCTRL VBB
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
36
42
31
38
44
32
40
48
mA
2405
2155
2405
2155
2405
mV
1605
1355
1605
1355
2155
mV
1355
VCC VCTRL > VBB
VCTRL = VCC (Min Swing)
25°C
1490
See
Fig.2
2105
2230
1520
See
Fig.2
2355
2095
2220
1520
1605
See
Fig.2
2345
2065
2190
2315
VIH
D, D Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
D, D Input LOW Voltage (Single Ended)
1490
1675
1490
1675
1490
1675
mV
VCTRL
Input Voltage (VCTRL)
VEE
VCC
VEE
VCC
VEE
VCC
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5.)
2.0
2.9
2.0
2.9
2.0
2.9
V
IIH
Input HIGH Current
150
µA
(VTT Open)
150
150
IIL
Input LOW Current
(VTT Open) -150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 ohms to VCC-2.0 volts. VOH does not change with VCTRL. VOL changes with VCTRL. VCTRL is referenced to VCC.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6.)
-40 °C
Symbol
Characteristic
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 7.)
VCC > VCTRL > VEE
VOL
Output LOW Voltage (Max Swing)
(Note 7.)
VCTRL VBB
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
36
42
31
38
44
32
40
48
mA
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
3055
3190
3305
3055
3220
3305
3055
3220
3305
mV
VCC VCTRL > VBB
VCTRL = VCC (Min Swing)
25°C
See
Fig.2
3805
3930
See
Fig.2
4055
3795
3920
See
Fig.2
4045
3765
3890
4015
VIH
D, D Input HIGH Voltage (Single Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
D, D Input LOW Voltage (Single Ended)
3190
3375
3190
3375
3190
3375
mV
VCTRL
Input Voltage (VCTRL)
VEE
VCC
VEE
VCC
VEE
VCC
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8.)
2.0
4.6
2.0
4.6
2.0
4.6
V
IIH
Input HIGH Current
150
µA
(VTT Open)
150
150
IIL
Input LOW Current
(VTT Open) -150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 ohms to VCC-2.0 volts. VOH does not change with VCTRL. VOL changes with VCTRL. VCTRL is referenced to VCC.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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84
MC100EP16VT
DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9.)
-40 °C
Symbol
Characteristic
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 10.)
VCC > VCTRL > VEE
VOL
Output LOW Voltage (Max Swing)
(Note 10.)
VCTRL VBB
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
36
42
31
38
44
32
40
48
mA
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
-1945
-1810
-1695
-1945
-1780
-1695
-1945
-1780
-1695
mV
VCC VCTRL > VBB
See
Fig.2
VCTRL = VCC (Min Swing)
-1 195
VIH
D, D Input HIGH Voltage (Single Ended)
VIL
D, D Input LOW Voltage (Single Ended)
VCTRL
Input Voltage (VCTRL)
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11.)
IIH
Input HIGH Current
See
Fig.2
-1070
-945
-1205
-1225
-880
-1810
-1625
VEE
VCC
VEE+2.0
-955
-1235
-1225
-880
-1225
-880
mV
-1810
-1625
-1810
-1625
mV
VEE
VCC
VEE
VCC
mV
-0.4
V
150
µA
-0.4
(VTT Open)
-1080
See
Fig.2
VEE+2.0
-0.4
150
-1 110
VEE+2.0
150
-985
IIL
Input LOW Current
(VTT Open) -150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 ohms to VCC-2.0 volts. VOH does not change with VCTRL. VOL changes with VCTRL. VCTRL is referenced to VCC.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 12.)
-40 °C
Symbol
Characteristic
Min
fmax
Maximum Toggle Frequency
(See Figure 8. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to Output Differential
Max Swing
Min Swing
tSKEW
Typ
25°C
Max
Min
>4
85°C
Max
Min
>4
Typ
Max
>4
Unit
GHz
ps
300
250
350
300
Duty Cycle Skew (Note 13.)
5.0
tJITTER
Cycle-to-Cycle Jitter
(See Figure 8. Fmax/JITTER)
VPP
Input Voltage Swing (Differential) (Note 14.)
tr, tf
Output Rise/Fall Times
(20% - 80%)
Max Swing Q
Min Swing
Typ
250
200
250
200
300
250
350
300
20
5.0
0.2
<1
150
800
1200
70
30
120
80
170
130
250
200
300
250
350
300
20
5.0
20
ps
0.2
<1
0.2
<1
ps
150
800
1200
150
800
1200
mV
80
20
130
70
180
120
100
20
150
70
200
120
ps
12. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
13. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
14. VPP(min) is minimum input swing for which AC parameters are guaranteed.
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85
MC100EP16VT
100
90
OUTPUT SWING (%)
80
70
60
50
40
30
20
10
0
0.0
0.5
1.0
VOLTS (V)
1.42
VBB
1.5
2.0
VPK- PK
Figure 2. VCC - VCTRL (pin #1)
VOH
Min Swing
Max Swing
VOL
0.0
0.5
1.0
VOLTS (V)
Figure 3. VCC - VCTRL
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86
1.42
VBB
1.5
2.0
MC100EP16VT
VCTRL +
1
8
VCC
VCTRL
2
D
7
Q*
50 D
*See Figure 9.
3
6
Q*
5
VEE
50 VTT
4
Figure 4. Voltage Source Implementation, VCTRL Pin 1
VCC
1
8
VCC
VCTRL
VBB
D
2
7
Q*
50 D
*See Figure 9.
3
6
Q*
5
VEE
50 VEE
VTT
4
Figure 5. Alternative Implementations, VCTRL Pin 1
VCTRL +
1
8
VCC
VCTRL
D
2
7
Q*
50 D
*See Figure 9.
3
6
Q*
5
VEE
50 VCC-2 V
4
VTT
Figure 6. Standard Termination Method, VTT Pin 4
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87
MC100EP16VT
VCTRL +
1
8
VCC
VCTRL
D
2
7
Q*
50 D
*See Figure 9.
3
6
Q*
5
VEE
50 VCC
RT
5.0 V
112 3.3 V
46 4
VTT
RT
VEE
1000
10
900
9
VOUTpp (mV)
800
2.00 V Below VCC
8
700
7
1.25 V Below VCC
600
6
1.00 V Below VCC
500
5
0.75 V Below VCC
400
4
300
3
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
200
0.25 V Below VCC
100
(JITTER)
2
1
0
0
500
1000
1500
2000
2500
FREQUENCY (MHz)
Figure 8. Fmax/Jitter
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88
3000
3500
4000
JITTEROUT ps (RMS)
Figure 7. Alternate “Y” Termination Method, VTT Pin 4
É
É
É
MC100EP16VT
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 9. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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89
MC10EP17, MC100EP17
3.3V / 5VECL Quad
Differential Driver/Receiver
The MC10/100EP17 is a 4-bit differential line receiver based on the
EP16 device. The >3.0 GHz maximum frequency provided by the high
frequency outputs makes the device ideal for buffering of very high
speed oscillators.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The design incorporates two stages of gain, internal to the device,
making it an excellent choice for use in high bandwidth amplifier
applications.
Inputs of unused gates can be left open and will not affect the
operation of the rest of the device. All VCC and VEE pins must be
externally connected to power supply to guarantee proper operation.
The 100 Series contains temperature compensation.
• 220 ps Typical Propagation Delay
• Maximum Frequency >3.0 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
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MARKING
DIAGRAMS*
20
20
XXXX
EP17
ALYW
1
TSSOP-20
DT SUFFIX
CASE 948E
1
20
20
MCXXXEP17
AWLYYWW
1
SO-20
DW SUFFIX
CASE 751D
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
XXXX
XXX
A
L,
WL
Y, YY
W, WW
•
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
• VBB Output
1
= MC10 or 100
= 10 or 100
= Assembly Location
= Assembly Lot
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 4
90
Package
Shipping
MC10EP17DT
TSSOP-20
75 Units/Rail
MC10EP17DTR2
TSSOP-20 2500 Tape & Reel
MC100EP17DT
TSSOP-20
MC100EP17DTR2
TSSOP-20 2500 Tape & Reel
75 Units/Rail
MC10EP17DW
SO-20
38 Units/Rail
MC10EP17DWR2
SO-20
1000 Tape & Reel
MC100EP17DW
SO-20
38 Units/Rail
MC100EP17DWR2
SO-20
1000 Tape & Reel
Publication Order Number:
MC10EP17/D
MC10EP17, MC100EP17
VCC
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
VEE
20
19
18
17
16
15
14
13
12
11
PIN DESCRIPTION
PIN
FUNCTION
D[0:3]*, D[0:3]*
ECL Differential Data Inputs
Q[0:3], Q[0:3]
ECL Differential Data Outputs
VBB
VCC
Reference Voltage Output
VEE
Negative Supply
Positive Supply
* Pins will default LOW when left open.
1
2
3
4
5
6
7
8
9
10
VCC
D0
D0
D1
D1
D2
D2
D3
D3
VBB
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL94 V-0 @ 0.125 in
Transistor Count
259 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
140
100
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
20 TSSOP
23 to 41
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
20 SOIC
20 SOIC
90
60
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
20 SOIC
30 to 35
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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91
VI VCC
VI VEE
MC10EP17, MC100EP17
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
Symbol
IEE
Characteristic
Power Supply Current
Min
-40 °C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
42
50
65
44
52
66
46
54
68
Unit
mA
VOH
VOL
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
VIL
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
Input LOW Voltage (Single-Ended)
365
1690
1430
1755
1490
1815
mV
VBB
VIHCMR
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
A
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
Input LOW Current
1890
2.0
1955
150
2015
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
Symbol
IEE
Characteristic
Power Supply Current
Min
-40 °C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
42
50
65
44
52
66
46
54
68
Unit
mA
VOH
VOL
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
VIL
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
VBB
VIHCMR
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
A
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
Input LOW Current
3590
2.0
3655
150
3715
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
Min
-40 °C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
42
50
65
44
52
66
46
54
68
Unit
mA
Output HIGH Voltage (Note 10)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
VIL
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VBB
VIHCMR
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
-1 185
mV
0.0
V
IIH
IIL
Input HIGH Current
150
A
Symbol
IEE
Characteristic
Power Supply Current
VOH
VOL
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
Input LOW Current
-1410
VEE+2.0
0.0
VEE+2.0
150
0.5
-1345
0.0
VEE+2.0
150
0.5
-1285
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP17, MC100EP17
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
Symbol
IEE
Characteristic
Power Supply Current
Min
-40 °C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
47
55
63
50
58
66
54
62
70
Unit
mA
VOH
VOL
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
VIL
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
VIHCMR
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
A
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
Input LOW Current
1875
2.0
1875
150
1875
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
Symbol
IEE
Characteristic
Power Supply Current
Min
-40 °C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
47
55
63
50
58
66
54
62
70
Unit
mA
VOH
VOL
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
VIL
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
VIHCMR
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
5.0
2.0
5.0
2.0
5.0
V
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
3575
2.0
3575
3575
IIH
Input HIGH Current
150
150
150
A
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18)
Min
-40 °C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
47
55
63
50
58
66
54
62
70
Unit
mA
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
VIL
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
VIHCMR
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
0.0
V
Symbol
IEE
Characteristic
Power Supply Current
VOH
VOL
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
-1425
VEE+2.0
0.0
-1425
VEE+2.0
0.0
-1425
VEE+2.0
IIH
Input HIGH Current
150
150
150
A
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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93
MC10EP17, MC100EP17
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
Min
Characteristic
fmax
Maximum Frequency
(See Figure 2 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to Output Differential
10 Series
100 Series
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2 Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Typ
25°C
Max
Min
>3
Q, Q
Typ
85°C
Max
Min
Typ
>3
>3
200
220
275
300
.2
<1
150
800
1200
100
160
220
150
180
220
250
300
320
.2
<1
150
800
1200
100
170
230
200
200
260
290
350
360
.2
<1
ps
150
800
1200
mV
120
190
250
ps
8
700
7
600
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
200
2
100
1
(JITTER)
0
2000
JITTEROUT ps (RMS)
VOUTpp (mV)
800
1000
Unit
GHz
ps
125
150
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
0
Max
3000
4000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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94
5000
6000
MC10EP17, MC100EP17
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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95
MC10EP29, MC100EP29
3.3V / 5VECL Dual
Differential Data and Clock
D Flip−Flop With Set and
Reset
The MC10/100EP29 is a dual master-slave flip-flop. The device
features fully differential Data and Clock inputs as well as outputs.
The MC10/100EP29 is functionally equivalent to the
MC10/100EL29. Data enters the master latch when the clock is LOW
and transfers to the slave upon a positive transition on the clock input.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open the D input will pull down to VEE and the D input will
bias around VCC/2. The outputs will go to a defined state, however the
state will be random based on how the flip flop powers up.
Both flip flops feature asynchronous, overriding Set and Reset
inputs. Note that the Set and Reset inputs cannot both be HIGH
simultaneously.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
• Maximum Frequency > 3 GHz Typical
• 500 ps Typical Propagation Delays
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
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MARKING
DIAGRAM*
20
20
xxx
EP29
ALYW
1
TSSOP-20
DT SUFFIX
CASE 948E
xxx
A
L
Y
W
1
= MC10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
with VEE = 0 V
Device
• NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
•
• Safety Clamp on Inputs
Package
Shipping
MC10EP29DT
TSSOP-20
75 Units/Rail
MC10EP29DTR2
TSSOP-20
2500 Tape & Reel
MC100EP29DT
TSSOP-20
75 Units/Rail
MC100EP29DTR2 TSSOP-20
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 2
96
2500 Tape & Reel
Publication Order Number:
MC10EP29/D
MC10EP29, MC100EP29
VCC
20
R0
S0
Q0
Q0
Q1
Q1
S1
R1
19
18
17
16
15
14
13
12
Q
S
R
S
Q
Q
D
1
2
D0
D0
R
Q
CLK
CLK
3
VEE
11
4
5
6
D
7
9
8
10
VBB CLK0 CLK0 CLK1 CLK1
D1
D1
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
VCC
Figure 4. 20-Lead Pinout (Top View) and Logic Diagram
PIN DESCRIPTION
TRUTH TABLE
PIN
FUNCTION
D0*, D0*; D1*, D1*
ECL Differential Data Inputs
R0*, R1*
ECL Reset Inputs
CLK0*, CLK0*
ECL Differential Clock Inputs
CLK1*, CLK1*
ECL Differential Clock Inputs
S0*, S1*
ECL Set Inputs
Q0, Q0; Q1, Q1
ECL Differential Data Outputs
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
R
S
D
CLK
Q
Q
L
L
H
L
H
L
L
L
H
H
L
H
X
X
X
Z
Z
X
X
X
L
H
L
H
Undef
H
L
H
L
Undef
Z = LOW to HIGH Transition
X = Don’t Care
* Pins will default LOW when left open.
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 2 kV
> 200 V
> 2 kV
Level 1
UL 94 V-0 @ 0.125 in
383 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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97
MC10EP29, MC100EP29
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
140
100
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
20 TSSOP
23 to 41
°C/W
265
°C
VI VCC
VI VEE
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
35
46
55
37
48
57
40
49
60
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
1690
1460
1755
1490
1815
mV
1990
1855
2055
1915
2115
mV
3.3
2.0
3.3
2.0
3.3
V
150
A
VIL
Input LOW Voltage (Single-Ended)
1365
VBB
Output Voltage Reference
1790
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
IIH
Input HIGH Current
IIL
Input LOW Current
1890
2.0
150
0.5
1955
150
0.5
0.5
2015
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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98
MC10EP29, MC100EP29
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
35
46
55
37
48
57
40
49
60
mA
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IEE
Power Supply Current
VOH
3590
2.0
3655
150
3715
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
35
46
55
37
48
57
40
49
60
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 10)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VBB
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
-1 185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
Input HIGH Current
150
A
-1410
VEE+2.0
0.0
150
-1345
VEE+2.0
0.0
150
-1285
VEE+2.0
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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99
MC10EP29, MC100EP29
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
35
46
55
37
48
57
40
49
60
mA
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IEE
Power Supply Current
VOH
1875
2.0
1875
150
1875
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
35
46
55
37
48
57
40
49
60
mA
VOH
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
3575
2.0
150
3575
150
3575
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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100
MC10EP29, MC100EP29
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
35
46
55
37
48
57
40
49
60
mA
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
0.0
V
IIH
Input HIGH Current
150
A
IEE
Power Supply Current
VOH
-1425
VEE+2.0
0.0
-1425
VEE+2.0
0.0
150
-1425
VEE+2.0
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
Characteristic
Min
fmax
Maximum Frequency
(See Figure 5 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tS
tH
Typ
300
275
300
380
380
400
Setup Time
Hold Time
100
100
tRR/tRR2
Set/Reset Recovery
tPW
Minimum Pulse Width
Set, Reset
Cycle-to-Cycle Jitter
(See Figure 5 Fmax/JITTER)
VPP
Input Voltage Swing (Note 22)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Max
Min
> 3.0
CLK
S
R
tJITTER
25°C
Q, Q
Typ
85°C
Max
350
300
325
420
400
420
20
20
100
100
150
80
500
300
450
475
500
.2
<1
150
800
1200
100
180
250
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Typ
Max
> 3.0
500
500
525
Unit
GHz
400
350
375
470
450
470
20
20
100
100
20
20
ps
150
80
150
80
ps
500
300
500
300
ps
.2
<1
150
800
1200
150
210
300
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
22. VPP(min) is the minimum input swing for which AC parameters are guaranteed.
101
Min
> 3.0
550
550
575
ps
.2
<1
ps
150
800
1200
mV
175
230
325
ps
900
9
800
8
700
7
600
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
200
2
(JITTER)
100
1
0
0
1000
2000
3000
4000
5000
FREQUENCY (MHz)
Figure 5. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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102
JITTEROUT ps (RMS)
VOUTpp (mV)
MC10EP29, MC100EP29
MC10EP31, MC100EP31
3.3V / 5VECL D Flip−Flop
with Set and Reset
The MC10/100EP31 is a D flip-flop with set and reset. The device
is pin and functionally equivalent to the EL31 and LVEL31 devices.
With AC performance much faster than the EL31 and LVEL31
devices, the EP31 is ideal for applications requiring the fastest AC
performance available. Both set and reset inputs are asynchronous,
level triggered signals. Data enters the master portion of the flip-flop
when CLK is low and is transferred to the slave, and thus the outputs,
upon a positive transition of the CLK.
The 100 Series contains temperature compensation.
• 340 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
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MARKING DIAGRAMS*
HEP31
ALYW
1
SO-8
D SUFFIX
CASE 751
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
8
8
8
1
1
8
8
1
•
• Q Output Will Default LOW with Inputs Open or at VEE
TSSOP-8
DT SUFFIX
CASE 948R
KEP31
ALYW
8
HP31
ALYW
1
KP31
ALYW
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Package
Shipping
MC10EP31D
Device
SO-8
98 Units/Rail
MC10EP31DR2
SO-8
2500 Tape & Reel
MC100EP31D
SO-8
98 Units/Rail
MC100EP31DR2
SO-8
2500 Tape & Reel
MC10EP31DT
TSSOP-8
100 Units/Rail
MC10EP31DTR2
TSSOP-8
2500 Tape & Reel
MC100EP31DT
TSSOP-8
100 Units/Rail
MC100EP31DTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2001
April, 2001 - Rev. 5
103
2500 Tape & Reel
Publication Order Number:
MC10EP31/D
MC10EP31, MC100EP31
PIN DESCRIPTION
SET
1
8
VCC
S
D
2
7
D
Q
Flip Flop
CLK
3
6
Q
PIN
FUNCTION
CLK*
ECL Clock Inputs
Reset*
ECL Asynchronous Reset
Set*
ECL Asynchronous Set
D*
ECL Data Input
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
R
TRUTH TABLE
RESET
4
5
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
D
SET
RESET
CLK
Q
L
H
X
X
X
L
L
H
L
H
L
L
L
H
H
Z
Z
X
X
X
L
H
H
L
UNDEF
Z = LOW to HIGH Transition
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
75 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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104
Condition 2
VI VCC
VI VEE
MC10EP31, MC100EP31
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
34
44
26
35
45
28
37
47
mA
Output HIGH Voltage (Note 4.)
2165
2240
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single Ended)
1365
1690
1430
1755
1490
1815
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IEE
Power Supply Current
VOH
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 ohms to VCC-2.0 volts.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5.)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
26
34
44
26
35
45
28
37
47
mA
VOH
Output HIGH Voltage (Note 6.)
3865
3940
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 6.)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single Ended)
3065
3390
3130
3455
3190
3515
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
6. All loading with 50 ohms to VCC-2.0 volts.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 7.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
34
44
26
35
45
28
37
47
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8.)
-1 135
-1060
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 8.)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
0.5
150
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC.
8. All loading with 50 ohms to VCC-2.0 volts.
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105
MC10EP31, MC100EP31
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 9.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
34
44
26
35
45
28
37
47
mA
Output HIGH Voltage (Note 10.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 10.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single Ended)
1355
1675
1355
1675
1355
1675
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IEE
Power Supply Current
VOH
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
10. All loading with 50 ohms to VCC-2.0 volts.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 11.)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
26
34
44
26
35
45
28
37
47
mA
VOH
Output HIGH Voltage (Note 12.)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 12.)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single Ended)
3055
3375
3055
3375
3055
3375
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
12. All loading with 50 ohms to VCC-2.0 volts.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 13.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
34
44
26
35
45
28
37
47
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 14.)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 14.)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
0.5
150
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
13. Input and output parameters vary 1:1 with VCC.
14. All loading with 50 ohms to VCC-2.0 volts.
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106
MC10EP31, MC100EP31
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 15.)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
Min
Typ
25°C
Max
Min
>3
Typ
85°C
Max
Min
Typ
>3
Max
>3
Unit
GHz
ps
CLK to Q, Q
S, R to Q, Q
250
300
330
380
400
450
270
330
340
400
410
470
300
360
370
430
440
500
tRR
Set/Reset Recovery
225
225
225
ps
tS
tH
Setup Time
Hold Time
100
150
100
150
100
150
ps
tPW
Minimum Pulse width
ps
SET, RESET
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Q, Q
550
50
450
550
0.2
<1
120
180
60
450
550
0.2
<1
130
200
450
70
0.2
<1
ps
150
220
ps
1100
11
1000
10
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
JITTEROUT ps (RMS)
VOUTpp (mV)
15. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
100
1
(JITTER)
0
0
1000
2000
3000
4000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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107
5000
6000
MC10EP31, MC100EP31
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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108
MC10EP32, MC100EP32
3.3V / 5VECL 2 Divider
The MC10/100EP32 is an integrated 2 divider with differential
CLK inputs.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flops will attain a random state; the
reset allows for the synchronization of multiple EP32’s in a system.
The 100 Series contains temperature compensation.
• 350 ps Typical Propagation Delay
• Maximum Frequency > 4 GHz Typical (See Graph)
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
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MARKING DIAGRAMS*
8
1
SO-8
D SUFFIX
CASE 751
HEP32
ALYW
1
1
TSSOP-8
DT SUFFIX
CASE 948R
KEP32
ALYW
1
8
8
•
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
8
8
8
HP32
ALYW
1
KP32
ALYW
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
MC10EP32D
SO-8
98 Units/Rail
MC10EP32DR2
SO-8
2500 Tape & Reel
MC100EP32D
SO-8
98 Units/Rail
MC100EP32DR2
SO-8
2500 Tape & Reel
MC10EP32DT
TSSOP-8
100 Units/Rail
MC10EP32DTR2
TSSOP-8
2500 Tape & Reel
MC100EP32DT
TSSOP-8
100 Units/Rail
MC100EP32DTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 5
109
Shipping
2500 Tape & Reel
Publication Order Number:
MC10EP32/D
MC10EP32, MC100EP32
PIN DESCRIPTION
RESET
1
8
VCC
R
CLK
2
7
Q
2
CLK
3
6
PIN
FUNCTION
CLK*, CLK*
ECL Clock Inputs
Reset*
ECL Asynchronous Reset
VBB
Reference Voltage Output
Q, Q
ECL Data Outputs
VCC
VEE
Positive Supply
Negative Supply
* Pins will default LOW when left open.
Q
TRUTH TABLE
VBB
4
5
CLK
CLK
RESET
Q
Q
X
Z
X
Z
Z
L
L
F
H
F
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 2 Function
CLK
tRR
RESET
Q
Figure 2. Timing Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 4 kV
> 200 V
> 2 kV
Level 1
UL-94 V-0 @ 0.125 in
78 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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110
MC10EP32, MC100EP32
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 SOIC
41 to 44
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 TSSOP
41 to 44
°C/W
265
°C
VI VCC
VI VEE
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
30
37
23
30
37
23
30
37
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single-Ended)
1365
1690
1430
1755
1490
1815
mV
VBB
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
1890
2.0
150
1955
150
2015
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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111
MC10EP32, MC100EP32
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
30
37
23
30
37
23
30
37
mA
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
Symbol
Characteristic
IEE
Power Supply Current
VOH
3590
2.0
3655
150
3715
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
30
37
23
30
37
23
30
37
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 10)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VBB
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
-1 185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
Input HIGH Current
150
A
-1410
VEE+2.0
0.0
150
-1345
VEE+2.0
0.0
150
-1285
VEE+2.0
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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112
MC10EP32, MC100EP32
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
30
37
23
30
37
26
33
40
mA
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
Symbol
Characteristic
IEE
Power Supply Current
VOH
1875
2.0
1875
150
1875
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
30
37
23
30
37
26
33
40
mA
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
Symbol
Characteristic
IEE
Power Supply Current
VOH
3575
2.0
150
3575
150
3575
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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113
MC10EP32, MC100EP32
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
30
37
23
30
37
26
33
40
mA
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
0.0
V
IIH
Input HIGH Current
150
A
Symbol
Characteristic
IEE
Power Supply Current
VOH
-1425
VEE+2.0
0.0
-1425
VEE+2.0
150
0.0
-1425
VEE+2.0
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
VOPP
Min
Characteristic
Output Voltage Amplitude
(See Figure 3)
fin < 3.5 GHz
fin < 4.0 GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
10 Series
100 Series
tRR
Set/Reset Recovery
tPW
Minimum Pulse width
tJITTER
Cycle-to-Cycle Jitter
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
mV
700
500
700
500
700
500
ps
CLK to Q, Q
RESET to Q, Q
RESET to Q, Q
RESET
Q, Q
250
220
320
330
290
400
200
420
390
480
270
250
320
350
300
400
175
200
550
475
0.2
<1
150
800
50
100
450
390
480
320
320
375
400
380
450
175
200
175
ps
550
475
550
475
ps
0.2
<1
0.2
<1
ps
1200
150
800
1200
150
800
1200
mV
150
70
120
170
70
130
200
ps
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
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114
480
460
525
MC10EP32, MC100EP32
900
VOPP, OUTPUT VOLTAGE (mV)
800
700
600
500
400
300
200
100
0
0
500
1000 1500
2000 2500
3000 3500
4000 4500
5000
fin, INPUT FREQUENCY (MHz)
Figure 3. Input Frequency (fin) versus Output Voltage (VOPP)
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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115
MC10EP33, MC100EP33
3.3V / 5VECL 4 Divider
The MC10/100EP33 is an integrated 4 divider. The differential
clock inputs.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flops will attain a random state; the
reset allows for the synchronization of multiple EP33’s in a system.
The 100 Series contains temperature compensation.
• 320 ps Propagation Delay
• Maximum Frequency > 4 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
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MARKING DIAGRAMS*
8
HEP33
ALYW
1
SO-8
D SUFFIX
CASE 751
1
1
•
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
• VBB Output
TSSOP-8
DT SUFFIX
CASE 948R
KEP33
ALYW
1
8
8
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
8
8
8
KP33
ALYW
HP33
ALYW
1
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Package
Shipping
MC10EP33D
Device
SO-8
98 Units/Rail
MC10EP33DR2
SO-8
2500 Tape & Reel
MC100EP33D
SO-8
98 Units/Rail
MC100EP33DR2
SO-8
2500 Tape & Reel
MC10EP33DT
TSSOP-8
100 Units/Rail
MC10EP33DTR2
TSSOP-8
2500 Tape & Reel
MC100EP33DT
TSSOP-8
100 Units/Rail
MC100EP33DTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 5
116
2500 Tape & Reel
Publication Order Number:
MC10EP33/D
MC10EP33, MC100EP33
PIN DESCRIPTION
FUNCTION
PIN
RESET
1
8
VCC
R
CLK
2
7
Q
4
CLK
3
6
Q
CLK*, CLK*
ECL Clock Inputs
Reset*
ECL Asynchronous Reset
VBB
Reference Voltage Output
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
TRUTH TABLE
VBB
4
5
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
CLK
CLK
RESET
Q
Q
X
Z
X
Z
Z
L
L
F
H
F
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 4 Function
CLK
tRR
RESET
Q
Figure 2. Timing Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
NA
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 4 kV
> 200 V
> 2 kV
Level 1
UL-94 V-0 @ 0.125 in
91 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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117
MC10EP33, MC100EP33
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 SOIC
41 to 44
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 TSSOP
41 to 44
°C/W
265
°C
VI VCC
VI VEE
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
18
26
34
18
26
34
18
26
34
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single-Ended)
1365
1690
1430
1755
1490
1815
mV
VBB
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
1890
2.0
150
1955
150
2015
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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118
MC10EP33, MC100EP33
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
18
26
34
18
26
34
18
26
34
mA
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
Symbol
Characteristic
IEE
Power Supply Current
VOH
3590
2.0
3655
150
3715
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
18
26
34
18
26
34
18
26
34
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 10)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VBB
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
-1 185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
Input HIGH Current
150
A
-1410
VEE+2.0
0.0
150
-1345
VEE+2.0
0.0
150
-1285
VEE+2.0
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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119
MC10EP33, MC100EP33
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
28
33
24
30
36
25
31
37
mA
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
Symbol
Characteristic
IEE
Power Supply Current
VOH
1875
2.0
1875
150
1875
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
28
33
24
30
36
25
31
37
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
3575
2.0
150
3575
150
3575
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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120
MC10EP33, MC100EP33
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
28
33
24
30
36
25
31
37
mA
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
0.0
V
IIH
Input HIGH Current
150
A
Symbol
Characteristic
IEE
Power Supply Current
VOH
-1425
VEE+2.0
0.0
-1425
VEE+2.0
150
0.0
-1425
VEE+2.0
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
VOPP
Min
Characteristic
Output Voltage Amplitude
(See Figure 3)
fin < 4.0 GHz
fin < 4.5 GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
CLK/Q
RESET/Q
tRR
Set/Rest Recovery
tPW
Minimum Pulse width
tJITTER
Cycle-to-Cycle Jitter
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(20% - 80%)
RESET
Q, Q
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
mV
700
600
300
370
380
420
150
700
600
440
470
300
370
380
420
100
200
550
480
0.2
<1
150
800
90
170
700
600
440
470
320
400
400
450
100
200
100
ps
550
480
550
480
ps
0.2
<1
0.2
<1
ps
1200
150
800
1200
150
800
1200
mV
200
100
180
250
120
200
280
ps
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
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121
460
500
ps
MC10EP33, MC100EP33
900
VOPP, OUTPUT VOLTAGE (mV)
800
700
600
500
400
300
200
100
0
0
500
1000 1500
2000 2500
3000 3500
4000 4500
5000
fin, INPUT FREQUENCY (MHz)
Figure 3. Input Frequency (fin) versus Output Voltage (VOPP)
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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122
MC10EP35, MC100EP35
3.3V / 5VECL JK Flip−Flop
The MC10/100EP35 is a higher speed/low voltage version of the
EL35 JK flip-flop. The J/K data enters the master portion of the
flip-flop when the clock is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the clock. The reset pin is
asynchronous and is activated with a logic HIGH.
The 100 Series contains temperature compensation.
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• 410 ps Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
MARKING DIAGRAMS*
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
8
8
8
HEP35
ALYW
1
•
• Q Output Will Default LOW with Inputs Open or at VEE
SO-8
D SUFFIX
CASE 751
1
1
8
8
8
KP35
ALYW
HP35
ALYW
1
TSSOP-8
DT SUFFIX
CASE 948R
KEP35
ALYW
1
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC10EP35D
SO-8
98 Units/Rail
MC10EP35DR2
SO-8
2500 Tape & Reel
MC100EP35D
SO-8
98 Units/Rail
MC100EP35DR2
SO-8
2500 Tape & Reel
MC10EP35DT
TSSOP-8
100 Units/Rail
MC10EP35DTR2
TSSOP-8
2500 Tape & Reel
MC100EP35DT
TSSOP-8
100 Units/Rail
MC100EP35DTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2001
April, 2001 - Rev. 3
123
2500 Tape & Reel
Publication Order Number:
MC10EP35/D
MC10EP35, MC100EP35
PIN DESCRIPTION
J
K
1
8
J
2
7
K
VCC
Q
Flip Flop
CLK
3
6
PIN
FUNCTION
CLK*
ECL Clock Inputs
J*, K*
ECL Signal Inputs
RESET*
ECL Asynchronous Reset
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
Q
TRUTH TABLE
R
RESET
4
5
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
J
K
RESET
CLK
Qn+1
L
L
H
H
X
L
H
L
H
X
L
L
L
L
H
Z
Z
Z
Z
X
Qn
L
H
Qn
L
Z = LOW to HIGH Transition
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
77 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
6
V
-6
V
6
-6
V
V
50
100
mA
mA
-40 to +85
°C
VCC
PECL Mode Power Supply
VEE = 0 V
VEE
NECL Mode Power Supply
VCC = 0 V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
Iout
Output Current
VEE = 0 V
VCC = 0 V
Continuous
Surge
TA
Operating Temperature Range
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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124
VI VCC
VI VEE
MC10EP35, MC100EP35
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
40
50
30
40
50
30
40
50
mA
Output HIGH Voltage (Note 4.)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single Ended)
1365
1690
1460
1755
1490
1815
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IEE
Power Supply Current
VOH
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 ohms to VCC-2.0 volts.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
40
50
30
40
50
30
40
50
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 6.)
3865
3940
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 6.)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single Ended)
3065
3390
3130
3455
3190
3515
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
6. All loading with 50 ohms to VCC-2.0 volts.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 7.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
40
50
30
40
50
30
40
50
mA
Output HIGH Voltage (Note 8.)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 8.)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IEE
Power Supply Current
VOH
150
0.5
150
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC.
8. All loading with 50 ohms to VCC-2.0 volts.
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125
MC10EP35, MC100EP35
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 9.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
40
50
30
40
50
30
40
50
mA
Output HIGH Voltage (Note 10.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 10.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single Ended)
1355
1675
1355
1675
1355
1675
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IEE
Power Supply Current
VOH
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
10. All loading with 50 ohms to VCC-2.0 volts.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 11.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
40
50
30
40
50
30
40
50
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 12.)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 12.)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single Ended)
3055
3375
3055
3375
3055
3375
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
12. All loading with 50 ohms to VCC-2.0 volts.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 13.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
40
50
30
40
50
30
40
50
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 14.)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 14.)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
0.5
150
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
13. Input and output parameters vary 1:1 with VCC.
14. All loading with 50 ohms to VCC-2.0 volts.
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126
MC10EP35, MC100EP35
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 15.)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tRR
Min
Typ
25°C
Max
Min
>3
Typ
85°C
Max
Min
Typ
>3
>3
400
Reset Recovery
150
tS
tH
Setup Time
Hold Time
tPW
Minimum Pulse width
R, CLK to Q, Q
GHz
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
tr
tf
Output Rise/Fall Times
(20% - 80%)
480
330
410
80
150
150
150
50
50
550
400
490
340
420
500
90
150
100
ps
150
150
50
50
150
150
80
80
ps
550
400
550
400
ps
RESET
Q, Q
70
0.2
<1
120
170
80
0.2
<1
130
180
100
0.2
<1
ps
150
200
ps
900
9
800
8
700
7
600
6
500
5
400
4
300
3
ÉÉ
ÉÉ
2
200
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
(JITTER)
100
1
0
1000
2000
3000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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127
JITTEROUT ps (RMS)
15. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
VOUTpp (mV)
Unit
ps
320
0
Max
4000
5000
MC10EP35, MC100EP35
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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128
MC100EP40
3.3V / 5VECL Differential
Phase− Frequency Detector
The MC100EP40 is a three- state phase- frequency detector
intended for phase-locked loop applications which require a minimum
amount of phase and frequency difference at lock. Advanced design
significantly reduces the dead zone of the detector. For proper
operation, the input edge rate of the R and V inputs should be less than
5 ns. The device is designed to work with a 3.3 V / 5 V power supply.
When Reference (R) and Feedback (FB) inputs are unequal in
frequency and/or phase the differential UP (U) and DOWN (D)
outputs will provide pulse streams which when subtracted and
integrated provide an error voltage for control of a VCO.
When Reference (R) and Feedback (FB) inputs are 80 ps or less in
phase difference, the Phase Lock Detect pin will indicate lock by a
high state (VOH). The VTX (VTR, VTR, VTFB, VTFB) pins offer an
internal termination network for 50 line impedance environment
shown in Figure 2. An external sinking supply of VCC-2 V is required
on VTX pin(s). If you short the two differential VTR and VTR (or VTFB
and VTFB) together, you provide a 100 termination resistance that is
compatible with LVDS signal receiver termination. For more
information on termination of logic devices, see AND8020.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
For more information on Phase Lock Loop operation, refer to
AND8040.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
•
•
•
•
•
•
•
•
•
Maximum Frequency > 2 GHz Typical
Fully Differential
Advanced High Band Output Swing of 400 mV
Theoretical Gain = 1.11
Trise 97 ps Typical, Ffall 70 ps Typical
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
50 Internal Termination Resistor
 Semiconductor Components Industries, LLC, 2002
October, 2002 - Rev. 7
http://onsemi.com
MARKING
DIAGRAM
20
20
100
EP40
ALYW
1
TSSOP-20
DT SUFFIX
CASE 948E
A
L
Y
W
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
MC100EP40DT
Package
Shipping
TSSOP-20
75 Units/Rail
MC100EP40DTR2 TSSOP-20
129
2500 Tape & Reel
Publication Order Number:
MC100EP40/D
MC100EP40
VCC PLD VCC
20
1
19
2
18
3
D
D
U
U
VCC
NC
VEE
17
16
15
14
13
12
11
4
VEE VTFB VTFB FB
5
6
7
FB
R
R
9
8
PIN DESCRIPTION
10
VTR VTR VBB
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View)
PIN
FUNCTION
U, U
ECL Up Differential Outputs
D, D
ECL Down Differential Outputs
FB, FB
ECL Feedback Differential Inputs
R, R
ECL Reference Differential Inputs
PLD
ECL Phase Lock Detect Function
VTR
ECL Internal Termination for R
VTR
ECL Internal Termination for R
VTFB
ECL Internal Termination for FB
VTFB
ECL Internal Termination for FB
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
NC
No Connect
VTR
50 U
C
A
A
R
R
U
U
A
C
S
50 U
FF
Reset
A
R
VTR
C
Reset
D
B
D
VTFB
Reset
50 (V) FB
FB
R
B
D
FF
S
B
50 Reset
B
D
D
VTFB
VBB
Figure 2. Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 4 kV
> 400 V
> 2 kV
Level 1
UL 94 V-0 @ 0.125 in
699 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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130
D
D
MC100EP40
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
140
100
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
20 TSSOP
23 to 41
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
VI VCC
VI VEE
2. Maximum Ratings are those values beyond which device damage may occur.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
100
128
160
100
130
160
110
140
170
mA
U, U, B, B
2225
2350
2475
2275
2400
2525
2300
2425
2550
mV
1775
1355
1900
1480
2025
1605
1800
1355
1925
1480
2050
1605
1825
1355
1950
1480
2075
1605
mV
PLD
Characteristic
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
VOL
Output LOW Voltage (Note 4)
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
1875
2.0
150
-150
1875
150
-150
-150
1875
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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131
MC100EP40
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 7)
100
128
160
100
130
160
110
140
170
mA
VOH
Output HIGH Voltage (Note 8)
3925
4050
4175
3975
4100
4225
4000
4125
4250
mV
VOL
Output LOW Voltage (Note 8)
3475
3055
3600
3180
3725
3305
3500
3055
3625
3180
3750
3305
3525
3055
3650
3180
3775
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode Range (Differential) (Note 9)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
U, U, B, B
PLD
3575
2.0
3575
150
-150
3575
150
-150
A
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
7. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal protection at elevated temperatures. Recommend
VCC-V EE operation at 3.3 V.
8. All loading with 50 to VCC-2.0 volts.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 10)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 11)
100
128
160
100
130
160
110
140
170
mA
VOH
Output HIGH Voltage (Note 12)
-1075
-950
-825
-1025
-900
-775
-1000
-875
-750
mV
VOL
Output LOW Voltage (Note 12)
U, U, B, B
PLD
-1525
-1945
-1400
-1820
-1275
-1695
-1500
-1945
-1375
-1820
-1250
-1945
-1475
-1945
-1350
-1820
-1225
-1945
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 13)
0.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
Symbol
Characteristic
mV
-1425
VEE+2.0
0.0
VEE+2.0
150
-150
-1425
0.0
VEE+2.0
150
-150
-1425
-150
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
10. Input and output parameters vary 1:1 with VCC.
11. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal protection at elevated temperatures. Recommend
VCC-V EE operation at 3.3 V.
12. All loading with 50 to VCC-2.0 volts.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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132
MC100EP40
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 14)
-40 °C
Symbol
Min
Characteristic
fmax
Maximum Frequency
(See Figure 3. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tJITTER
Cycle-to-Cycle Jitter
(See Figure 3. Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(20% - 80%)
25°C
Typ
Max
Min
>2
FB to D/U
R to D/U
Q, Q
400
Typ
85°C
Max
Min
Typ
>2
525
700
0.2
<1
150
800
1200
60
85
130
410
>2
550
750
0.2
<1
150
800
1200
75
110
150
450
ps
0.2
<1
ps
150
800
1200
mV
80
120
160
ps
700
7
600
6
500
5
400
4
300
3
200
2
ÏÏ
ÏÏ
1
(JITTER)
0
500
1000
1500
2000
2500
3000
3500
FREQUENCY (MHz)
Figure 3. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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133
JITTEROUT ps (RMS)
VOUTpp (mV)
8
0
GHz
775
800
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
Unit
575
14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
100
Max
MC10EP51, MC100EP51
3.3V / 5VECL D Flip− Flop
with Reset and Differential
Clock
The MC10/100EP51 is a differential clock D flip-flop with reset.
The device is functionally equivalent to the EL51 and LVEL51
devices.
The reset input is an asynchronous, level triggered signal. Data
enters the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition
of the clock. The differential clock inputs of the EP51 allow the device
to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability
under open input conditions. When left open, the CLK input will be
pulled down to VEE and the CLK input will be biased at VCC/2.
The 100 Series contains temperature compensation.
• 350 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
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MARKING DIAGRAMS*
8
8
8
HEP51
ALYW
1
SO-8
D SUFFIX
CASE 751
1
1
8
8
1
TSSOP-8
DT SUFFIX
CASE 948R
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
8
KP51
ALYW
HP51
ALYW
1
1
H = MC10
K = MC100
A = Assembly Location
•
• Safety Clamp on Inputs
KEP51
ALYW
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC10EP51D
SO-8
98 Units/Rail
MC10EP51DR2
SO-8
2500 Tape & Reel
MC100EP51D
SO-8
98 Units/Rail
MC100EP51DR2
SO-8
2500 Tape & Reel
MC10EP51DT
TSSOP-8
100 Units/Rail
MC10EP51DTR2
TSSOP-8
2500 Tape & Reel
MC100EP51DT
TSSOP-8
100 Units/Rail
MC100EP51DTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2001
April, 2001 - Rev. 3
134
2500 Tape & Reel
Publication Order Number:
MC10EP51/D
MC10EP51, MC100EP51
PIN DESCRIPTION
RESET
1
8
PIN
VCC
R
D
2
7
D
Q
Flip-Flop
CLK
3
6
Q
FUNCTION
CLK*, CLK*
ECL Clock Inputs
Reset*
ECL Asynchronous Reset
D*
ECL Data Input
Q, Q
ECL Data Outputs
VCC
VEE
Positive Supply
Negative Supply
* Pins will default LOW when left open.
TRUTH TABLE
CLK
4
5
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
Q
L
H
L
CLK
Z
Z
X
R
L
L
H
D
L
H
X
VEE
Z = LOW to HIGH Transition
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
165 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
6
V
-6
V
6
-6
V
V
50
100
mA
mA
VCC
PECL Mode Power Supply
VEE = 0 V
VEE
NECL Mode Power Supply
VCC = 0 V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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VI VCC
VI VEE
MC10EP51, MC100EP51
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
34
44
26
35
45
28
37
47
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 4.)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
VIH
Output LOW Voltage (Note 4.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
Input HIGH Voltage (Single Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
1365
1690
1430
1755
1490
1815
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 5.)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 ohms to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
34
44
26
35
45
28
37
47
mA
Output HIGH Voltage (Note 7.)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
VIH
Output LOW Voltage (Note 7.)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
Input HIGH Voltage (Single Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
3065
3390
3130
3455
3190
3515
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 8.)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
Input LOW Current
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 ohms to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9.)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
26
34
44
26
35
45
28
37
47
mA
Output HIGH Voltage (Note 10.)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
VIH
Output LOW Voltage (Note 10.)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
Input HIGH Voltage (Single Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input HIGH Voltage Common Mode
Range (Differential) (Note 11.)
Input LOW Current
VEE+2.0
0.0
VEE+2.0
150
0.5
0.0
VEE+2.0
150
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 ohms to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP51, MC100EP51
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
34
44
26
35
45
28
37
47
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 13.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 13.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
1355
1675
1355
1675
1355
1675
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 14.)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 ohms to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
34
44
26
35
45
28
37
47
mA
Output HIGH Voltage (Note 16.)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
VIH
Output LOW Voltage (Note 16.)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
Input HIGH Voltage (Single Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
3055
3375
3055
3375
3055
3375
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 17.)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
Input LOW Current
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 ohms to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18.)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
26
34
44
26
35
45
28
37
47
mA
Output HIGH Voltage (Note 19.)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
VIH
Output LOW Voltage (Note 19.)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input HIGH Voltage Common Mode
Range (Differential) (Note 20.)
Input LOW Current
VEE+2.0
0.0
VEE+2.0
150
0.5
0.0
VEE+2.0
150
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 ohms to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP51, MC100EP51
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21.)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
>3
Typ
85°C
Max
Min
>3
Typ
Max
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to Output Differential
CLK, CLK to Q, Q
10
100
250
275
300
340
350
425
270
300
320
375
370
450
300
350
350
425
420
500
RESET to Q, Q
300
380
450
325
400
475
350
425
500
Reset Recovery
150
150
tS
tH
Setup Time
Hold Time
100
100
100
100
tPW
Minimum Pulse Width
500
150
ps
80
40
100
100
ps
440
500
ps
RESET
500
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
440
.2
<1
.2
<1
tr
Output Rise/Fall Times
Q, Q
tf
(20% - 80%)
70
120
170
80
130
180
100
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
1100
11
Measured
Simulated
VOUTpp (mV)
900
10
9
800
8
700
7
600
6
500
5
ÉÉ
ÉÉ
400
4
300
3
ÉÉÉÉÉ
ÉÉÉÉÉ
200
2
100
0
1000
JITTEROUT ps (RMS)
1000
0
GHz
ps
tRR
tJITTER
>3
Unit
1
(JITTER)
2000
3000
4000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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138
5000
6000
440
.2
<1
150
200
ps
ps
MC10EP51, MC100EP51
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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139
MC10EP52, MC100EP52
3.3V / 5VECL Differential
Data and Clock D Flip−Flop
The MC10EP/100EP52 is a differential data, differential clock D
flip- flop. The device is pin and functionally equivalent to the EL52 device.
Data enters the master portion of the flip-flop when the clock is
LOW and is transferred to the slave, and thus the outputs, upon a
positive transition of the clock. The differential clock inputs of the
EP52 allow the device to also be used as a negative edge triggered
device.
The EP52 employs input clamping circuitry so that under open input
conditions (pulled down to VEE) the outputs of the device will remain
stable.
The 100 Series contains temperature compensation.
•
•
•
•
•
•
•
330 ps Typical Propagation Delay
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MARKING DIAGRAMS*
8
8
8
HEP52
ALYW
1
SO-8
D SUFFIX
CASE 751
1
KEP52
ALYW
1
Maximum Frequency > 4 GHz Typical
8
PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V
8
8
NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V
1
TSSOP-8
DT SUFFIX
CASE 948R
Open Input Default State
Safety Clamp on Inputs
KP52
ALYW
HP52
ALYW
1
1
Q Output Will Default LOW with Inputs Open or at VEE
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2001
April, 2001 - Rev. 2
140
Package
Shipping
MC10EP52D
SO-8
98 Units/Rail
MC10EP52DR2
SO-8
2500 Tape & Reel
MC100EP52D
SO-8
98 Units/Rail
MC100EP52DR2
SO-8
2500 Tape & Reel
MC10EP52DT
TSSOP-8
100 Units/Rail
MC10EP52DTR2
TSSOP-8
2500 Tape & Reel
MC100EP52DT
TSSOP-8
100 Units/Rail
MC100EP52DTR2
TSSOP-8
2500 Tape & Reel
Publication Order Number:
MC10EP52/D
MC10EP52, MC100EP52
PIN DESCRIPTION
D
D
1
8
D
2
7
VCC
Q
Flip-Flop
CLK
3
6
Q
FUNCTION
PIN
CLK*, CLK*
ECL Clock Inputs
D*, D*
ECL Data Input
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
TRUTH TABLE
CLK
4
5
VEE
Figure 4. 8-Lead Pinout (Top View) and Logic Diagram
D
CLK
Q
L
H
Z
Z
L
H
Z = LOW to HIGH Transition
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
155 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
6
V
-6
V
6
-6
V
V
50
100
mA
mA
± 0.5
mA
-40 to +85
°C
VCC
PECL Mode Power Supply
VEE = 0 V
VEE
NECL Mode Power Supply
VCC = 0 V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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141
VI VCC
VI VEE
MC10EP52, MC100EP52
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
34
44
26
35
45
28
37
47
mA
Output HIGH Voltage (Note 4.)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
VIH
Output LOW Voltage (Note 4.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
Input HIGH Voltage (Single Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
1365
1690
1430
1755
1490
1815
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 5.)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
Input LOW Current
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 ohms to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6.)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
26
34
44
26
35
45
28
37
47
mA
Output HIGH Voltage (Note 7.)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
VIH
Output LOW Voltage (Note 7.)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
Input HIGH Voltage (Single Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
3065
3390
3130
3455
3190
3515
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 8.)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 ohms to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
34
44
26
35
45
28
37
47
mA
Output HIGH Voltage (Note 10.)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
Output LOW Voltage (Note 10.)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
Input HIGH Voltage (Single Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
VIHCMR
Input LOW Voltage (Single Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
0.0
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
VOL
VIH
Input HIGH Voltage Common Mode
Range (Differential) (Note 11.)
Input LOW Current
VEE+2.0
0.0
VEE+2.0
150
0.5
0.0
VEE+2.0
150
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 ohms to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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142
MC10EP52, MC100EP52
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
34
44
26
35
45
28
37
47
mA
Output HIGH Voltage (Note 13.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
Output LOW Voltage (Note 13.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single Ended)
1355
1675
1355
1675
1355
1675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14.)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IEE
Power Supply Current
VOH
VOL
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 ohms to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
34
44
26
35
45
28
37
47
mA
Output HIGH Voltage (Note 16.)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
Output LOW Voltage (Note 16.)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single Ended)
3055
3375
3055
3375
3055
3375
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17.)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IEE
Power Supply Current
VOH
VOL
150
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 ohms to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
26
34
44
26
35
45
28
37
47
mA
Output HIGH Voltage (Note 19.)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
Output LOW Voltage (Note 19.)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20.)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IEE
Power Supply Current
VOH
VOL
VEE+2.0
0.0
VEE+2.0
150
0.5
0.0
VEE+2.0
150
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 ohms to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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143
MC10EP52, MC100EP52
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21.)
-40 °C
Symbol
Characteristic
Min
fmax
Maximum Toggle
Frequency (See Figure 5. Fmax/Jitter)
tPLH,
tPHL
Propagation Delay to
Output Differential
25°C
Typ
Max
Min
>4
Typ
85°C
Max
Min
>4
Typ
Max
>4
Unit
GHz
ps
CLK, CLK->Q, Q
tS
tH
Setup Time
Hold Time
tJITTER
Cycle-to-Cycle Jitter
(See Figure 5. Fmax/Jitter)
VPP
Input Voltage Swing (Diff.)
250
300
350
280
50
0
330
380
310
50
0
1200
ps
150
800
1200
mV
tr
Output Rise/Fall Times
tf
(20% - 80%)
Q, Q
70
110
170
80
120
180
90
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
130
200
150
.2
<1
800
1200
ps
1000
10
900
9
800
8
700
7
600
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
ÉÉ
200
100
2
1
(JITTER)
0
0
1000
2000
3000
4000
FREQUENCY (MHz)
Figure 5. Fmax/Jitter
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144
ps
JITTEROUT ps (RMS)
800
50
0
<1
VOUTpp (mV)
<1
410
.2
150
.2
360
5000
6000
MC10EP52, MC100EP52
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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145
MC10EP56, MC100EP56
3.3V / 5VECL Dual
Differential 2:1 Multiplexer
The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or other skew sensitive signals. Multiple VBB pins are
provided.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The device features both individual and common select inputs to
address both data path and random logic applications.
The 100 Series contains temperature compensation.
• 360 ps Typical Propagation Delays
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
•
•
•
•
•
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MARKING
DIAGRAMS*
20
20
xxxx
EP56
ALYW
1
TSSOP-20
DT SUFFIX
CASE 948E
1
20
20
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
MC100EP56
AWLYYWW
1
SO-20
DW SUFFIX
CASE 751D
1
Safety Clamp on Inputs
Separate and Common Select
Q Output Will Default LOW with Inputs Open or at VEE
VBB Outputs
xxx
A
L, WL
Y, YY
W, WW
=
=
=
=
=
MC10 or 100
Assembly Location
Wafer Lot
Year
Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 10
146
Package
Shipping
MC10EP56DT
TSSOP-20
75 Units/Rail
MC10EP56DTR2
TSSOP-20
2500 Tape & Reel
MC100EP56DT
TSSOP-20
75 Units/Rail
MC100EP56DTR2
TSSOP-20
2500 Tape & Reel
MC100EP56DW
SO-20
38 Units/Rail
MC100EP56DWR2
SO-20
1000 Tape & Reel
Publication Order Number:
MC10EP56/D
MC10EP56, MC100EP56
Q0
Q0
SEL0
20
19
18
17
1
1
D0a
COM_SEL
VCC
PIN DESCRIPTION
SEL1
VCC
Q1
Q1
VEE
D0a* - D1a*
16
15
14
13
12
11
D0a* - D1a*
ECL Input Data a Invert
D0b* - D1b*
ECL Input Data b
D0b* - D1b*
ECL Input Data b Invert
0
2
3
1
4
D0a VBBO D0b
5
D0b
6
0
7
8
9
D1a D1a VBB1 D1b
10
D1b
PIN
FUNCTION
ECL Input Data a
SEL0* - SEL1*
ECL Indiv. Select Input
COM_SEL*
ECL Common Select Input
VBB0,VBB1
Q0 - Q1
ECL True Outputs
Q0 - Q1
ECL Inverted Outputs
VCC
VEE
Positive Supply
Output Reference Voltage
Negative Supply
* Pins will default LOW when left open.
TRUTH TABLE
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
SEL0
SEL1
COM_SEL
Q0,
Q0
Q1,
Q1
X
L
L
H
H
X
L
H
H
L
H
L
L
L
L
a
b
b
a
a
a
b
a
a
b
Figure 1. 20-Lead Package (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 2 kV
> 200 V
> 2 kV
Level 1
UL 94 V-0 @ 0.125 in
140 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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147
MC10EP56, MC100EP56
MAXIMUM RATINGS (Note 2)
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
140
100
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
20 TSSOP
23 to 41
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
20 SOIC
20 SOIC
90
60
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
20 SOIC
33 to 35
°C/W
265
°C
Symbol
Condition 1
Condition 2
VI VCC
VI VEE
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
50
61
75
50
63
75
55
65
78
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single-Ended)
1365
1690
1460
1755
1490
1815
mV
VBB
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
1890
2.0
150
1955
150
2015
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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148
MC10EP56, MC100EP56
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
50
61
75
50
63
75
55
65
78
mA
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IEE
Power Supply Current
VOH
3590
2.0
3655
150
3715
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
50
61
75
50
63
75
55
65
78
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 10)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VBB
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
-1 185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
Input HIGH Current
150
A
-1410
VEE+2.0
0.0
150
-1345
VEE+2.0
0.0
150
-1285
VEE+2.0
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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149
MC10EP56, MC100EP56
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
50
61
75
50
63
77
55
66
80
mA
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IEE
Power Supply Current
VOH
1875
2.0
1875
150
1875
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
50
61
75
50
63
77
55
66
80
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
3575
2.0
150
3575
150
3575
IIL
Input LOW Current
0.5
0.5
0.50
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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150
MC10EP56, MC100EP56
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
50
61
75
50
63
77
55
66
80
mA
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
0.0
V
IIH
Input HIGH Current
150
A
IEE
Power Supply Current
VOH
-1425
VEE+2.0
0.0
-1425
VEE+2.0
150
0.0
-1425
VEE+2.0
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 2 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
Min
Typ
25°C
Max
Min
>3
Typ
85°C
Max
Min
>3
Typ
Max
>3
Unit
GHz
ps
D to Q, Q
SEL to Q, Q
COM_SEL to Q, Q
250
250
250
340
340
350
450
450
450
270
270
270
360
340
360
470
470
470
300
300
300
400
400
400
500
500
500
tSKEW
Within-Device Skew (Note 22)
Device to Device Skew
50
100
200
50
100
200
50
100
200
ps
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2 Fmax/JITTER)
0.2
<1
0.2
<1
0.2
<1
ps
VPP
Input Voltage Swing (Differential)
150
800
1200
150
800
1200
150
800
1200
mV
tr
tf
Output Rise/Fall Times
(20% - 80%)
70
120
170
80
130
180
100
150
230
ps
Q, Q
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
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151
1000
10
900
9
800
8
700
7
600
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
200
2
(JITTER)
100
1
ÉÉ
ÉÉ
0
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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152
JITTEROUT ps (RMS)
VOUTpp (mV)
MC10EP56, MC100EP56
MC10EP57, MC100EP57
3.3V / 5VECL 4:1
Differential Multiplexer
The MC10/100EP57 is a fully differential 4:1 multiplexer. By
leaving the SEL1 line open (pulled LOW via the input pulldown
resistors) the device can also be used as a differential 2:1 multiplexer
with SEL0 input selecting between D0 and D1. The fully differential
architecture of the EP57 makes it ideal for use in low skew
applications such as clock distribution.
The SEL1 is the most significant select line. The binary number
applied to the select inputs will select the same numbered data input
(i.e., 00 selects D0).
Multiple VBB outputs are provided. The VBB pin, an internally
generated voltage supply, is available to this device only. For
single- ended input conditions, the unused differential input is
connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 F capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, VBB should be left open.
The 100 Series contains temperature compensation.
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MARKING
DIAGRAM
20
20
xxx
EP57
ALYW
1
TSSOP-20
DT SUFFIX
CASE 948E
xxx
A
L
Y
W
• 375 ps Typical Propagation Delays
• Maximum Frequency > 2 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
1
= MC10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
•
•
•
•
•
*For additional information, see Application Note
AND8002/D
with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output will default LOW with inputs open or at VEE
ORDERING INFORMATION
VBB Outputs
Useful as Either 4:1 or 2:1 Multiplexer
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 8
Device
153
Package
Shipping
MC10EP57DT
TSSOP- 20
75 Units/Rail
MC10EP57DTR2
TSSOP- 20
2500 Tape & Reel
MC100EP57DT
TSSOP- 20
75 Units/Rail
MC100EP57DTR2
TSSOP- 20
2500 Tape & Reel
Publication Order Number:
MC10EP57/D
MC10EP57, MC100EP57
VCC
SEL1
SEL0
VCC
Q
Q
VCC
20
19
18
17
16
15
14
13
12
11
VBB1
VBB2
VEE
4:1
1
2
3
4
5
6
7
8
9
10
VCC
D0
D0
D1
D1
D2
D2
D3
D3
VEE
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 20-Lead Package (Top View) and Logic Diagram
PIN DESCRIPTION
FUNCTION TABLE
FUNCTION
PIN
D0-3*, D0-3*
ECL Diff. Data Inputs
SEL0*, 1*
ECL Mux Select Inputs
VBB1, VBB2
ECL Reference Output Voltage
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
SEL1
SEL0
DATA OUT
L
L
H
H
L
H
L
H
D0, D0
D1, D1
D2, D2
D3, D3
* Pins will default LOW when left open.
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 4 kV
> 100 V
> 2 kV
Level 1
UL 94 V-0 @ 0.125 in
584 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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154
MC10EP57, MC100EP57
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
140
100
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
20 TSSOP
23 to 41
°C/W
265
°C
VI VCC
VI VEE
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
52
65
40
52
65
40
52
65
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single-Ended)
1365
1690
1460
1755
1490
1815
mV
VBB
Output Voltage Reference
1735
1935
1800
2000
1860
2060
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
1835
2.0
150
1900
150
1960
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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155
MC10EP57, MC100EP57
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
52
65
40
52
65
40
52
65
mA
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3435
3635
3500
3700
3560
3760
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IEE
Power Supply Current
VOH
3535
2.0
3600
150
3660
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
52
65
40
52
65
40
52
65
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 10)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VBB
Output Voltage Reference
-1565
-1365
-1500
-1300
-1440
-1240
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
Input HIGH Current
150
A
-1465
VEE+2.0
0.0
150
-1400
VEE+2.0
0.0
150
-1340
VEE+2.0
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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156
MC10EP57, MC100EP57
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
52
65
40
52
65
40
52
65
mA
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IEE
Power Supply Current
VOH
1875
2.0
1875
150
1875
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
52
65
40
52
65
40
52
65
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
3575
2.0
150
3575
150
3575
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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157
MC10EP57, MC100EP57
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
52
65
40
52
65
40
52
65
mA
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
0.0
V
IIH
Input HIGH Current
150
A
IEE
Power Supply Current
VOH
-1425
VEE+2.0
0.0
-1425
VEE+2.0
150
0.0
-1425
VEE+2.0
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
Min
Device to Device Skew (Note 22)
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Max
Min
>3
Typ
85°C
Max
Min
>3
Typ
Max
>3
Unit
GHz
ps
D to Q, Q
COM_SEL, SEL to Q, Q
tSKEW
Typ
25°C
250
300
350
400
450
500
275
320
375
420
200
Q, Q
0.2
<1
150
800
1200
70
120
170
475
520
320
320
420
450
200
520
575
200
ps
0.2
<1
ps
0.2
<1
150
800
1200
150
800
1200
mV
70
140
200
70
150
220
ps
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
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158
10
900
9
800
8
700
7
600
6
500
5
400
4
VOUTpp (mV)
1000
300
ÉÉ
ÉÉ
3
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
2
200
100
0
0
1000
2000
1
(JITTER)
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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159
JITTEROUT ps (RMS)
MC10EP57, MC100EP57
MC10EP58, MC100EP58
3.3V / 5VECL 2:1 Multiplexer
The MC10/100EP58 is a 2:1 multiplexer. The device is pin and
functionally equivalent to the EL58 and LVEL58 devices.
The 100 Series contains temperature compensation.
• 310 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
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MARKING DIAGRAMS*
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
•
• Q Output Will Default LOW with Inputs Open or at VEE
8
8
8
HEP58
ALYW
1
SO-8
D SUFFIX
CASE 751
1
1
8
8
8
HP58
ALYW
1
TSSOP-8
DT SUFFIX
CASE 948R
KEP58
ALYW
1
KP58
ALYW
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2001
June, 2001 - Rev. 4
160
Package
Shipping
MC10EP58D
SO-8
98 Units/Rail
MC10EP58DR2
SO-8
2500 Tape & Reel
MC100EP58D
SO-8
98 Units/Rail
MC100EP58DR2
SO-8
2500 Tape & Reel
MC10EP58DT
TSSOP-8
100 Units/Rail
MC10EP58DTR2
TSSOP-8
2500 Tape & Reel
MC100EP58DT
TSSOP-8
100 Units/Rail
MC100EP58DTR2
TSSOP-8
2500 Tape & Reel
Publication Order Number:
MC10EP58/D
MC10EP58, MC100EP58
PIN DESCRIPTION
NC
Da
1
8
2
7
1
VCC
3
6
0
FUNCTION
Da*, Db*
ECL Data Inputs
SEL*
ECL Select Inputs
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
NC
No Connect
Q
MUX
Db
PIN
Q
* Pins will default LOW when left open.
SEL
4
5
VEE
TRUTH TABLE
SEL
Data
H
L
a
b
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
41 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
Input
PECL Mode In
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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161
VI VCC
VI VEE
MC10EP58, MC100EP58
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
37
20
30
39
22
31
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4.)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single Ended)
1365
1690
1460
1755
1490
1815
mV
IIH
Input HIGH Current
150
µA
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 ohms to VCC-2.0 volts.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
37
20
30
39
22
31
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 6.)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 6.)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single Ended)
3065
3390
3130
3455
3190
3515
mV
IIH
Input HIGH Current
150
µA
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
6. All loading with 50 ohms to VCC-2.0 volts.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 7.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
37
20
30
39
22
31
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8.)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 8.)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
IIH
Input HIGH Current
150
µA
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC.
8. All loading with 50 ohms to VCC-2.0 volts.
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162
MC10EP58, MC100EP58
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 9.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
37
20
31
39
25
33
42
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 10.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 10.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single Ended)
1355
1675
1355
1675
1355
1675
mV
IIH
Input HIGH Current
150
µA
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
10. All loading with 50 ohms to VCC-2.0 volts.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 11.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
37
20
31
39
25
33
42
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 12.)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 12.)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single Ended)
3055
3375
3055
3375
3055
3375
mV
IIH
Input HIGH Current
150
µA
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
12. All loading with 50 ohms to VCC-2.0 volts.
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 13.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
37
20
31
39
25
33
42
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 14.)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 14.)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
IIH
Input HIGH Current
150
µA
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
13. Input and output parameters vary 1:1 with VCC.
14. All loading with 50 ohms to VCC-2.0 volts.
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163
MC10EP58, MC100EP58
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 15.)
-40 °C
Symbol
Characteristic
Min
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
25°C
Typ
Max
Min
>3
Typ
85°C
Max
Min
>3
Typ
Max
>3
Unit
GHz
ps
200
0.2
<2
ps
150
800
1200
mV
tr
Output Rise/Fall Times
Q, Q
70
120
170
80
130
180
100
tf
(20% - 80%)
15. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
150
200
ps
150
280
380
0.2
<2
800
1200
210
150
310
410
0.2
<2
800
1200
220
1000
10
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
100
ÉÉ
ÉÉ
ÉÉ
(JITTER)
1
0
0
1000
2000
3000
4000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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164
JITTEROUT ps (RMS)
420
VOUTpp (mV)
340
D to Q,Q
SEL to Q,Q
5000
6000
MC10EP58, MC100EP58
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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165
MC10EP89
3.3V / 5VECL Coaxial
Cable Driver
The MC10EP89 is a differential fanout gate specifically designed to
drive coaxial cables. The device is especially useful in digital video
broadcasting applications; for this application, since the system is
polarity free, each output can be used as an independent driver. The
driver produces swings 70% larger than a standard ECL output. When
driving a coaxial cable, proper termination is required at both ends of
the line to minimize signal loss. The 1.6 V (5 V) and 1.4 V (3.3 V)
swing allow for termination at both ends of the cable, while
maintaining a 800 mV (5 V) and 700 mV (3.3 V) swing at the
receiving end of the cable. Because of the larger output swings, the
device cannot be terminated into the standard VCC-2.0 V. All of the
DC parameters are tested with a 50 Ω to VCC-3.0 V load. The driver
accepts a standard differential ECL input and can run off of the digital
video broadcast standard -5.0 V supply.
•
•
•
•
•
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MARKING
DIAGRAMS*
8
SO-8
D SUFFIX
CASE 751
8
1
1
8
310 ps Typical Propagation Delay
TSSOP-8
DT SUFFIX
CASE 948R
8
Maximum Frequency > 2 GHz Typical
HEP89
ALYW
1
HP89
ALYW
1
1.6 V (5 V) and 1.4 V (3.3 V) VOUTpp Swing
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
•
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 5
166
Package
Shipping
MC10EP89D
SO-8
98 Units/Rail
MC10EP89DR2
SO-8
2500 Tape & Reel
MC10EP89DT
TSSOP-8
100 Units/Rail
MC10EP89DTR2
TSSOP-8
2500 Tape & Reel
Publication Order Number:
MC10EP89/D
MC10EP89
Q0
Q0
1
8
2
7
PIN DESCRIPTION
VCC
D
PIN
FUNCTION
D*, D*
ECL Data Inputs
Q0, Q1, Q0, Q1
ECL Data Outputs
VCC
VEE
Positive Supply
Negative Supply
* Pins will default LOW when left open.
Q1
3
6
D
Q1
4
5
VEE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL-94 V-0 @ 0.125 in
Transistor Count
152 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
8 TSSOP
41 to 44
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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167
VI VCC
VI VEE
MC10EP89
DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
22
28
34
24
32
38
28
34
40
mA
VOH
Output HIGH Voltage (Note 4)
2080
2180
2280
2150
2250
2350
2225
2325
2425
mV
VOL
Output LOW Voltage (Note 4)
620
720
820
630
730
830
670
770
870
mV
VIH
Input HIGH Voltage (Single-Ended)
2070
2410
2170
2490
2240
2580
mV
VIL
Input LOW Voltage (Single-Ended)
1350
1800
1350
1820
1350
1855
mV
2.0
3.3
2.0
3.3
2.0
3.3
V
150
µA
VIHCMR Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
IIH
Input HIGH Current
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC.
4. All loading with 50 to VCC-3.0 volts.
5. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal.
DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
27
34
41
30
37
44
32
39
46
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 7)
3780
3880
3980
3850
3950
4050
3925
4025
4125
mV
VOL
Output LOW Voltage (Note 7)
2075
2225
2375
2060
2210
2360
2090
2240
2390
mV
VIH
Input HIGH Voltage (Single-Ended)
3770
4110
3870
4190
3940
4280
mV
VIL
Input LOW Voltage (Single-Ended)
3050
3500
3050
3520
3050
3555
mV
2.0
5.0
2.0
5.0
2.0
5.0
V
150
µA
VIHCMR Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
IIH
Input HIGH Current
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC.
7. All loading with 50 to VCC-3.0 volts.
8. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal.
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168
MC10EP89
DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.3 V (Note 9)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
22
28
34
24
32
38
28
34
40
mA
VOH
Output HIGH Voltage (Note 10)
-1220
-1 120
-1020
-1 150
-1050
-950
-1075
-975
-875
mV
VOL
Output LOW Voltage (Note 10)
-2680
-2580
-2480
-2670
-2570
-2470
-2630
-2530
-2430
mV
VIH
Input HIGH Voltage (Single-Ended)
-1230
-890
-1 130
-810
-1060
-720
mV
VIL
Input LOW Voltage (Single-Ended)
-1950
-1500
-1950
-1480
-1950
-1445
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
Input HIGH Current
150
µA
-1.3
0.0
-1.3
0.0
150
-1.3
150
IIL
Input LOW Current
D
0.5
0.5
0.5
µA
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-3.0 volts.
11. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal.
DC CHARACTERISTICS, NECL VCC = 0V, VEE = -5.2 (Note 12)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
25
32
39
28
35
42
31
38
45
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 13)
-1220
-1 120
-1020
-1 150
-1050
-950
-1075
-975
-875
mV
VOL
Output LOW Voltage (Note 13)
-2950
-2800
-2650
-2950
-2850
-2650
-2950
-2800
-2650
mV
VIH
Input HIGH Voltage (Single-Ended)
-1230
-890
-1 130
-810
-1060
-720
mV
VIL
Input LOW Voltage (Single-Ended)
-1950
-1500
-1950
-1480
-1950
-1445
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
0.0
V
IIH
Input HIGH Current
150
µA
-3.2
0.0
150
-3.2
0.0
150
-3.2
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC.
13. All loading with 50 to VCC-3.0 volts.
14. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal.
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169
MC10EP89
AC CHARACTERISTICS VCC = 0V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
fmax
Maximum Toggle
(See Figure 2 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Min
25°C
Typ
Max
Min
>2
220
Typ
Max
Min
Typ
>2
280
340
Within Device Skew
Q, Q
Device to Device Skew (Note 16)
5.0
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2 Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Q, Q
85°C
250
>2
310
370
20
120
5.0
.5
<1
150
800
1200
175
250
325
270
ps
20
120
5.0
20
120
ps
.5
<1
.5
<1
ps
150
800
1200
150
800
1200
mV
200
275
350
225
295
375
ps
9
1400
7
1200
6
3.3 V
1000
5
800
4
600
3
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
ÉÉ
400
2
(JITTER)
200
1
0
2000
3000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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170
JITTEROUT ps (RMS)
VOUTpp (mV)
8
5V
1000
GHz
390
1800
0
Unit
330
15. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-3.0 V.
16. Skew is measured between outputs under identical transitions.
1600
Max
4000
5000
MC10EP89
DC BLOCKING CAPACITORS
75 Ω
75 Ω COAX
0.1 µF
75Ω
EP89
75 Ω
150 Ω
150 Ω
75 Ω COAX
0.1 µF
VEE
Cable Driver Termination Configuration
Q
D
Receiver
Device
Driver
Device
D
Q
50 50 V TT
V TT = V CC - 3.0 V
Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
Figure 3. Termination Configurations
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171
75 Ω
MC10EP90, MC100EP90
− 3.3V / −5VTriple ECL Input
to LVPECL/PECL Output
Translator
The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL
translator. The device receives differential LVECL or ECL signals and
translates them to differential LVPECL or PECL output signals.
A VBB output is provided for interfacing with Single- Ended LVECL
or ECL signals at the input. If a Single- Ended input is to be used the
VBB output should be connected to the D input. The active signal would
then drive the D input. When used the VBB output should be bypassed
to ground by a 0.01 F capacitor. The VBB output is designed to act as
the switching reference for the EP90 under Single- Ended input
switching conditions, as a result this pin can only source/sink up to 0.5
mA of current.
To accomplish the level translation the EP90 requires three power
rails. The VCC supply should be connected to the positive supply, and
the VEE connected to the negative supply.
The 100 Series contains temperature compensation.
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MARKING
DIAGRAM*
20
1
1
xxx
A
L
Y
W
• 260 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• Voltage Supplies VCC = 3.0 V to 5.5 V, VEE = -3.0 V to -5.5 V,
•
•
•
•
•
GND = 0 V
Open Input Default State
XXXX
EP90
ALYW
TSSOP-20
DT SUFFIX
CASE 948E
20
= MC10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
Safety Clamp on Inputs
Fully Differential Design
Q Output Will Default LOW with Inputs Open or at VEE
VBB Output
ORDERING INFORMATION
Device
Package
MC10EP90DT
TSSOP-20
75 Units/Rail
MC10EP90DTR2
TSSOP-20
2500 Tape & Reel
MC100EP90DT
TSSOP-20
75 Units/Rail
MC100EP90DTR2 TSSOP-20
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 3
172
Shipping
2500 Tape & Reel
Publication Order Number:
MC10EP90/D
MC10EP90, MC100EP90
VCC
Q0
Q0
GND
Q1
Q1
GND
Q2
Q2
VCC
20
19
18
17
16
15
14
13
12
11
PIN DESCRIPTION
PIN
FUNCTION
Q(0:2), Q(0:2)
Differential LVPECL or PECL Outputs
D(0:2)*, D(0:2)* Differential LVECL or ECL Inputs
LVPECL/
PECL
LVPECL/
PECL
ECL
LVPECL/
PECL
ECL
ECL
VCC
Positive Supply
GND
Ground
VEE
Negative Supply
VBB
Output Reference Supply
* Pins will default LOW when left open.
FUNCTION TABLE
1
2
3
4
5
6
7
8
9
10
VCC
D0
D0
VBB
D1
D1
VBB
D2
D2
VEE
Warning: All VCC, VEE and GND pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. 20-Lead TSSOP (Top View) and Logic Diagram
Function
VCC
GND
VEE
-5V ECL to 5V PECL
5V
0V
-5 V
-5V ECL to 3.3V PECL
3.3 V
0V
-5 V
-3.3V ECL to 5V PECL
5V
0V
-3.3 V
-3.3V ECL to 3.3V PECL
3.3 V
0V
-3.3 V
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
350 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
6
V
-6
V
6
-6
V
V
50
100
mA
mA
± 0.5
mA
-40 to +85
°C
VCC
PECL Mode Power Supply
GND = 0 V
VEE
NECL Mode Power Supply
GND = 0 V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
GND = 0 V
GND = 0 V
Iout
Output Current
Continuous
Surge
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
140
100
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
20 TSSOP
23 to 41
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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173
VI VCC
VI VEE
MC10EP90, MC100EP90
10EP DC CHARACTERISTICS VCC = 3.3 V, VEE = -5.5 V to -3.0 V; GND = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
5
13
20
5
13
20
5
13
20
mA
ICC
Positive Power Supply Current
43
55
67
43
55
67
43
55
67
mA
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VBB
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
-1 185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
0.0
V
IIH
Input HIGH Current
150
A
-1410
VEE+2.0
0.0
-1345
VEE+2.0
150
0.0
-1285
VEE+2.0
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal.
10EP DC CHARACTERISTICS VCC = 5.0 V, VEE = -5.5 V to -3.0 V; GND = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
5
13
20
5
13
20
5
13
20
mA
ICC
Positive Power Supply Current
43
55
67
43
55
67
43
55
67
mA
VOH
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1690
-1870
-1545
-1810
-1485
mV
VBB
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
-1 185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
0.0
V
IIH
Input HIGH Current
150
A
-1410
VEE+2.0
0.0
150
-1345
VEE+2.0
0.0
150
-1285
VEE+2.0
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC.
7. All loading with 50 to VCC - 2.0 volts.
8. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal.
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174
MC10EP90, MC100EP90
100EP DC CHARACTERISTICS VCC = 3.3 V, VEE = -5.5 V to -3.0 V; GND = 0 V (Note 9)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
5
13
20
5
13
20
5
13
20
mA
ICC
Positive Power Supply Current
45
58
70
50
62
75
53
65
78
mA
VOH
Output HIGH Voltage (Note 10)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 10)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
Input HIGH Current
150
A
-1425
VEE+2.0
0.0
-1425
VEE+2.0
150
0.0
-1425
VEE+2.0
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal.
100EP DC CHARACTERISTICS VCC = 5.0 V, VEE = -5.5 V to -3.0 V; GND = 0 V (Note 12)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
5
13
20
5
13
20
5
13
20
mA
ICC
Positive Power Supply Current
45
58
70
50
62
75
53
65
78
mA
VOH
Output HIGH Voltage (Note 13)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 13)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
0.0
V
IIH
Input HIGH Current
150
A
-1425
VEE+2.0
0.0
150
-1425
VEE+2.0
0.0
150
-1425
VEE+2.0
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC.
13. All loading with 50 to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.. The VIHCMR range is referenced to the most positive side of the differential input
signal.
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175
MC10EP90, MC100EP90
AC CHARACTERISTICS VEE = -3.0 V to -5.5 V; VCC = 3.0 V to 5.5 V; GND = 0 V (Note 15)
-40 °C
Symbol
Min
Characteristic
fmax
Maximum Frequency
(See Figure 2 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Duty Cycle Skew (Note 16)
Typ
25°C
Max
Min
>3
170
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2 Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(20% - 80%)
310
5.0
20
200
Min
Typ
0.2
<1
150
800
1200
70
120
170
Max
>3
260
340
5.0
20
80
140
Q, Q
Max
>3
240
Within Device Skew
Q, Q
Device to Device Skew (Note 16)
Typ
85°C
230
300
370
ps
5.0
20
ps
80
140
0.2
<1
150
800
1200
80
130
180
Unit
GHz
80
140
0.2
<1
ps
150
800
1200
mV
100
150
230
ps
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
100
(JITTER)
1
0
0
1000
2000
3000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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176
JITTEROUT ps (RMS)
VOUTpp (mV)
15. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
16. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
4000
5000
MC10EP90, MC100EP90
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices.)
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177
MC10EP016, MC100EP016
3.3V / 5VECL 8−Bit
Synchronous Binary
Up Counter
The MC10/100EP016 is a high-speed synchronous, presettable,
cascadeable 8-bit binary counter. Architecture and operation are the
same as the MC10E016 in the ECLinPS family.
The counter features internal feedback to TC gated by the TCLD
(Terminal Count Load) pin. When TCLD is LOW (or left open, in
which case it is pulled LOW by the internal pulldowns), the TC
feedback is disabled, and counting proceeds continuously, with TC
going LOW to indicate an all-one state. When TCLD is HIGH, the TC
feedback causes the counter to automatically reload upon TC = LOW,
thus functioning as a programmable counter. The Qn outputs do not
need to be terminated for the count function to operate properly. To
minimize noise and power, unused Q outputs should be left
unterminated.
COUT and COUT provide differential outputs from a single,
non-cascaded counter or divider application. COUT and COUT
should not be used in cascade configuration. Only TC should be used
for a counter or divider cascade chain output.
A differential clock input has also been added to improve
performance.
The 100 Series contains temperature compensation.
• 500 ps Typical Propagation Delay
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
•
•
•
•
•
•
•
•
•
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
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MARKING
DIAGRAM*
MCxxx
EP016
AWLYYWW
LQFP-32
FA SUFFIX
CASE 873A
32
1
xxx
A
WL
YY
WW
= 10 OR 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Safety Clamp on Inputs
Package
Shipping
MC10EP016FA
LQFP-32
250 Units/Tray
MC10EP016FAR2
LQFP-32 2000 Tape & Reel
8-Bit
MC100EP016FA
LQFP-32
Differential Clock Input
MC100EP016FAR2
LQFP-32 2000 Tape & Reel
Internal TC Feedback (Gated)
Addition of COUT and COUT
250 Units/Tray
VBB Output
Fully Synchronous Counting and TC Generation
Asynchronous Master Reset
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 10
178
Publication Order Number:
MC10EP016/D
MC10EP016, MC100EP016
VBB CLK CLK P0
24
23
22
21
P1
P2
P3
P4
20
19
18
17
PIN DESCRIPTION
25
PE
16
P5
PIN
FUNCTION
P0-P7*
ECL Parallel Data (Preset) Inputs
CE
26
15
P6
Q0-Q7
ECL Data Outputs
MR
27
14
P7
CE*
ECL Count Enable Control Input
VEE
28
Q0
29
MC10EP016
MC100EP016
13
VCC
12
TC
PE*
ECL Parallel Load Enable Control Input
MR*
ECL Master Reset
CLK*, CLK*
ECL Differential Clock
TC
ECL Terminal Count Output
Q1
30
11
COUT
Q2
31
10
TCLD*
COUT COUT, COUT
VCC
32
9
1
2
3
4
5
6
7
VEE
8
ECL TC-Load Control Input
ECL Differential Output
VCC
VEE
Positive Supply
Negative Supply
VBB
Reference Voltage Output
* Pins will default LOW when left open.
VCC Q3
Q4
Q5
Q6
Q7 TCLD VCC
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
FUNCTION TABLES
CE
PE
X
L
L
H
X
X
L
H
H
H
X
X
TCLD MR
X
L
H
X
X
X
CLK
L
L
L
L
L
H
Z
Z
Z
Z
ZZ
X
FUNCTION
Load Parallel (Pn to Qn)
Continuous Count
Count; Load Parallel on TC = LOW
Hold
Masters Respond, Slaves Hold
Reset (Qn : = LOW, TC : = HIGH)
ZZ = Clock Pulse (High-to-Low)
Z = Clock Pulse (Low-to-High)
FUNCTION TABLE
Function
PE
CE
MR
TCLD
CLK
P7-P4
P3
P2
P1
P0
Q7-Q4
Q3
Q2
Q1
Q0
TC
COUT
COUT
Load Count
L
H
H
H
H
X
L
L
L
L
L
L
L
L
L
X
L
L
L
L
Z
Z
Z
Z
Z
H
X
X
X
X
H
X
X
X
X
H
X
X
X
X
L
X
X
X
X
L
X
X
X
X
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
L
H
H
H
H
L
H
L
L
L
H
L
Load Hold
L
H
H
X
H
H
L
L
L
X
X
X
Z
Z
Z
H
X
X
H
X
X
H
X
X
L
X
X
L
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
Load on
Terminal
Count
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
Z
Z
Z
Z
Z
Z
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
L
L
H
H
H
H
L
H
L
H
L
H
L
H
H
L
H
H
H
H
H
L
H
H
H
L
L
H
L
L
L
Reset
X
X
H
X
X
X
X
X
X
X
L
L
L
L
L
H
H
L
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179
MC10EP016, MC100EP016
Q1
Q0
Q7
PE
TCLD
Q0M
MASTER Q0M SLAVE
CE
Q0
CE
CE Q
Q1 0
Q2
Q3
Q4
Q5 Q
6
BIT 1
BIT 0
P0
P1
BIT 7
P7
MR
CLK
BITS 2-6
CLK
TC
5
VBB
VEE
COUT
COUT
Note that this diagram is provided for understanding of logic operation only.
It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.
Figure 2. 8-BIT Binary Counter Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
Flammability Rating
> 2 kV
> 100 V
> 2 kV
Level 2
Oxygen Index: 28 to 34
Transistor Count
UL 94 V-0 @ 0.125 in
897 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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180
MC10EP016, MC100EP016
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
VCC
VEE
PECL Mode Power Supply
NECL Mode Power Supply
VEE = 0 V
VCC = 0 V
VI
Input
PECL Mode In
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
IBB
TA
VBB Sink/Source
Operating Temperature Range
Tstg
θJA
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
Condition 2
θJC
Thermal Resistance (Junction-to-Case)
std bd
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
Units
6
V
-6
V
6
-6
V
V
50
100
mA
mA
± 0.5
mA
-40 to +85
°C
VI VCC
VI VEE
0 LFPM
500 LFPM
Rating
-65 to +150
°C
32 LQFP
32 LQFP
80
55
°C/W
°C/W
32 LQFP
12 to 17
°C/W
265
°C
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Typ
Max
Unit
IEE
VOH
Power Supply Current
120
160
200
120
160
200
120
160
200
mA
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
VIH
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
1365
1690
1460
1755
1490
1815
mV
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
Min
Typ
Max
Min
Typ
Max
Min
1890
2.0
1955
150
0.5
2015
150
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current (Note 7)
120
160
200
120
160
200
120
160
200
mA
Output HIGH Voltage (Note 8)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
VIH
Output LOW Voltage (Note 8)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 9)
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
3590
2.0
150
0.5
3655
150
0.5
0.5
3715
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
8. All loading with 50 to VCC-2.0 volts.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP016, MC100EP016
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 10)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current (Note 11)
120
160
200
120
160
200
120
160
200
mA
Output HIGH Voltage (Note 12)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
VIH
Output LOW Voltage (Note 12)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
-1 185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 13)
0.0
V
-1410
VEE+2.0
0.0
-1345
VEE+2.0
0.0
-1285
VEE+2.0
IIH
Input HIGH Current
150
150
150
µA
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
10. Input and output parameters vary 1:1 with VCC.
11. Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
12. All loading with 50 to VCC-2.0 volts.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 14)
Symbol
Characteristic
Min
-40 °C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
IEE
VOH
Power Supply Current
120
160
200
120
160
200
120
160
200
mA
Output HIGH Voltage (Note 15)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 15)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 16)
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
1875
2.0
1875
150
0.5
1875
150
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
14. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
15. All loading with 50 to VCC-2.0 volts.
16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 17)
-40 °C
Symbol
Characteristic
25°C
85°C
Typ
Max
Unit
IEE
VOH
Power Supply Current (Note 18)
120
160
200
120
160
200
120
160
200
mA
Output HIGH Voltage (Note 19)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
VIH
Output LOW Voltage (Note 19)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
Min
Typ
Max
Min
Typ
Max
Min
3575
2.0
150
0.5
3575
150
0.5
0.5
3575
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
17. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
18. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP016, MC100EP016
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 21)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
120
160
200
120
160
200
120
160
200
mA
IEE
VOH
Power Supply Current (Note 22)
Output HIGH Voltage (Note 23)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
VIH
Output LOW Voltage (Note 23)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 24)
0.0
V
IIH
IIL
Input HIGH Current
150
µA
-1425
VEE+2.0
0.0
-1425
VEE+2.0
0.0
150
Input LOW Current
0.5
-1425
VEE+2.0
150
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
21. Input and output parameters vary 1:1 with VCC.
22. Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
23. All loading with 50 to VCC-2.0 volts.
24. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VEE = -3.0 V to -5.5 V; VCC = 0 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 25)
-40 °C
Symbol
fCOUNT
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
Maximum Frequency
>1
> 800
Q, TC
COUT/COUT
tPLH
tPHL
Propagation Delay (10)
(10)
(10)
(10)
(10)
(10)
(100)
(100)
(100)
(100)
(100)
(100)
tS
>1
> 800
350
400
400
350
450
400
400
450
400
450
450
500
500
500
500
450
550
500
550
590
550
590
600
640
-50
300
300
300
100
500
500
500
-50
300
300
300
100
500
500
500
300
300
350
250
400
300
350
400
350
400
400
450
460
400
420
350
470
400
500
550
500
550
550
600
Setup Time
Pn
CE
PE
TCLD
100
500
500
500
tH
Hold Time
Pn
CE
PE
TCLD
100
500
500
500
tJITTER
Clock Random Jitter
(RMS >1000 Waveforms)
tRR
Reset Recovery Time
200
80
200
80
200
80
ps
tPW
Minimum Pulse Width CLK, MR
550
300
550
300
550
300
ps
150
250
8.5
400
450
400
400
450
450
480
520
480
520
530
570
560
580
550
510
600
560
630
670
630
670
680
720
-50
300
300
300
100
500
500
500
-50
300
300
300
ps
-50
300
300
300
100
500
500
500
-50
300
300
300
ps
2.5
650
600
600
550
700
650
700
750
700
750
800
850
GHz
MHz
CLK to Q
MR to Q
CLK to TC
MR to TC
CLK to COUT
MR to COUT
CLK to Q
MR to Q
CLK to TC
MR to TC
CLK to COUT
MR to COUT
2.6
600
500
550
450
650
550
650
700
650
700
750
800
>1
> 800
8.0
tr
Output Rise/Fall Times
120
210
320
120
220
320
tf
20% - 80%
25. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
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2.5
700
700
700
600
800
700
780
820
780
820
880
920
8.0
450
ps
ps
ps
MC10EP016, MC100EP016
Applications Information
Cascading Multiple EP016 Devices
For applications which call for larger than 8-bit counters
multiple EP016s can be tied together to achieve very wide
bit width counters. The active low terminal count (TC)
output and count enable input (CE) greatly facilitate the
cascading of EP016 devices. Two EP016s can be cascaded
without the need for external gating, however for counters
wider than 16 bits external OR gates are necessary for
cascade implementations.
Figure 3 below pictorially illustrates the cascading of 4
EP016s to build a 32-bit high frequency counter. Note the
EP01 gates used to OR the terminal count outputs of the
lower order EP016s to control the counting operation of the
higher order bits. When the terminal count of the preceding
device (or devices) goes low (the counter reaches an all 1s
state) the more significant EP016 is set in its count mode and
will count one binary digit upon the next positive clock
transition. In addition, the preceding devices will also count
one bit thus sending their terminal count outputs back to a
high state disabling the count operation of the more
significant counters and placing them back into hold modes.
Therefore, for an EP016 in the chain to count, all of the lower
order terminal count outputs must be in the low state. The bit
width of the counter can be increased or decreased by simply
adding or subtracting EP016 devices from Figure 3 and
maintaining the logic pattern illustrated in the same figure.
The maximum frequency of operation for a cascaded
counter chain is set by the propagation delay of the TC output,
the necessary setup time of the CE input, and the propagation
delay through the OR gate controlling it (for 16- bit counters
the limitation is only the TC propagation delay and the CE
setup time). Figure 3 shows EP01 gates used to control the
count enable inputs, however, if the frequency of operation is
slow enough, a LVECL OR gate can be used. Using the worst
case guarantees for these parameters.
LOAD
Q0 to Q7
LO
CE
PE
EP016
LSB
CLK
CLK
TC
Q0 to Q7
PE
CE
PE
CE
EP016
CLK
CLK
CE
EP016
CLK
CLK
TC
PE
EP016
MSB
CLK
CLK
TC
TC
EP01
EP01
P0 to P7
Q0 to Q7
Q0 to Q7
P0 to P7
P0 to P7
P0 to P7
CLK
CLK
Figure 3. 32-Bit Cascaded EP016 Counter
TCLD pin (load on terminal count) when asserted reloads the
data present at the parallel input pin (Pn’s) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 4
below illustrates the input conditions necessary for utilizing
the EP016 as a programmable divider set up to divide by 113.
Note that this assumes the trace delay between the TC
outputs and the CE inputs are negligible. If this is not the
case estimates of these delays need to be added to the
calculations.
Programmable Divider
The EP016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider. The
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184
MC10EP016, MC100EP016
Applications Information (continued)
H
L
L
P7 P6 P5
H
PE
L
CE
H
L
H
H
H
H
P4
P3
P2 P1 P0
Table 1. Preset Values for Various Divide Ratios
Ratio
P7
P6
P5
P4
P3
P2
P1
P0
2
3
4
5
•
•
112
113
114
•
•
254
255
256
H
H
H
H
•
•
H
H
H
•
•
L
L
L
H
H
H
H
•
•
L
L
L
•
•
L
L
L
H
H
H
H
•
•
L
L
L
•
•
L
L
L
H
H
H
H
•
•
H
L
L
•
•
L
L
L
H
H
H
H
•
•
L
H
H
•
•
L
L
L
H
H
H
L
•
•
L
H
H
•
•
L
L
L
H
L
L
H
•
•
L
H
H
•
•
H
L
L
L
H
L
H
•
•
L
H
L
•
•
L
H
L
TC
TCLD
COUT
CLK
CLK
Q7 Q6 Q5
COUT
Q4 Q3 Q2 Q1 Q0
Figure 4. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
Pn’s = 256 - 113 = 8F16 = 1000 1111
where:
P0 = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure 4
will result in the waveforms of Figure 5. Note that the TC
output is used as the divide output and the pulse duration is
equal to a full clock period. For even divide ratios, twice the
desired divide ratio can be loaded into the EP016 and the TC
output can feed the clock input of a toggle flip flop to create
a signal divided as desired with a 50% duty cycle.
Load
1001 0000
Preset Data Inputs
Divide
de
A single EP016 can be used to divide by any ratio from 2
to 256 inclusive. If divide ratios of greater than 256 are
needed multiple EP016s can be cascaded in a manner similar
to that already discussed. When EP016s are cascaded to
build larger dividers the TCLD pin will no longer provide a
means for loading on terminal count. Because one does not
want to reload the counters until all of the devices in the
chain have reached terminal count, external gating of the TC
pins must be used for multiple EP016 divider chains.
1001 0001
1111 1100
•••
1111 1101
1111 1110
1111 1111
CLK
•••
PE
•••
TC
DIVIDE BY 113
Figure 5. Divide by 113 EP016 Programmable Divider Waveforms
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185
Load
MC10EP016, MC100EP016
Applications Information (continued)
EP01
Q0 to Q7
LO
CE
PE
EP016
LSB
CLK
CLK
TC
Q0 to Q7
CE
Q0 to Q7
PE
CE
EP016
CLK
CLK
PE
CE
EP016
CLK
CLK
TC
PE
EP016
MSB
CLK
CLK
TC
EP01
P0 to P7
Q0 to Q7
TC
EP01
P0 to P7
P0 to P7
P0 to P7
CLK
CLK
Figure 6. 32-Bit Cascaded EP016 Programmable Divider
Maximizing EP016 Count Frequency
Figure 6 shows a typical block diagram of a 32-bit divider
chain. Once again to maximize the frequency of operation
EP01 OR gates were used. For lower frequency applications
a slower OR gate could replace the EP01. Note that for a
16-bit divider the OR function feeding the PE (program
enable) input CANNOT be replaced by a wire OR tie as the
TC output of the least significant EP016 must also feed the
CE input of the most significant EP016. If the two TC
outputs were OR tied the cascaded count operation would
not operate properly. Because in the cascaded form the PE
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.
The EP016 device produces 9 fast transitioning
single-ended outputs, thus VCC noise can become
significant in situations where all of the outputs switch
simultaneously in the same direction. This VCC noise can
negatively impact the maximum frequency of operation of
the device. Since the device does not need to have the Q
outputs terminated to count properly, it is recommended that
if the outputs are not going to be used in the rest of the system
they should be left unterminated. In addition, if only a subset
of the Q outputs are used in the system only those outputs
should be terminated. Not terminating the unused outputs
will not only cut down the VCC noise generated but will also
save in total system power dissipation. Following these
guidelines will allow designers to either be more aggressive
in their designs or provide them with an extra margin to the
published data book specifications.
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186
MC10EP016, MC100EP016
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 VTT
VTT = VCC - 2.0 V
Figure 7. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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187
MC100EP016A
3.3 VECL 8−Bit
Synchronous Binary
Up Counter
The MC100EP016A is a high-speed synchronous, presettable,
cascadeable 8-bit binary counter. Architecture and operation are the
same as the ECLinPS family MC100E016 with higher operating
speed.
The counter features internal feedback to TC gated by the TCLD
(Terminal Count Load) pin. When TCLD is LOW (or left open, in
which case it is pulled LOW by the internal pulldowns), the TC
feedback is disabled, and counting proceeds continuously, with TC
going LOW to indicate an all-one state. When TCLD is HIGH, the TC
feedback causes the counter to automatically reload upon TC = LOW,
thus functioning as a programmable counter. The Qn outputs do not
need to be terminated for the count function to operate properly. To
minimize noise and power, unused Q outputs should be left
unterminated.
COUT and COUT provide differential outputs from a single,
non-cascaded counter or divider application. COUT and COUT
should not be used in cascade configuration. Only TC should be used
for a counter or divider cascade chain output.
A differential clock input has also been added to improve
performance.
The 100 Series contains temperature compensation.
• 550 ps Typical Propagation Delay
• Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016
• PECL Mode Operating Range: VCC = 3.0 V to 3.6 V
with VEE = 0 V
MARKING
DIAGRAM*
LQFP-32
FA SUFFIX
CASE 873A
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
MC100EP016AFA
with VEE = -3.0 V to -3.6 V
Open Input Default State
MC100
EP016A
AWLYYWW
32
Device
• NECL Mode Operating Range: VCC = 0 V
•
•
•
•
•
•
•
•
•
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Package
Shipping
LQFP-32
250 Units/Tray
MC100EP016AFAR2 LQFP-32
2000/Tape & Reel
Safety Clamp on Clock Inputs
Internal TC Feedback (Gated)
Addition of COUT and COUT
8-Bit
Differential Clock Input
VBB Output
Fully Synchronous Counting and TC Generation
Asynchronous Master Reset
 Semiconductor Components Industries, LLC, 2002
September 2002 - Rev. 3
188
Publication Order Number:
MC100EP016A/D
MC100EP016A
VBB CLK CLK P0
24
23
22
21
P1
P2
P3
P4
20
19
18
17
PIN DESCRIPTION
25
PE
16
P5
PIN
FUNCTION
P0-P7*
ECL Parallel Data (Preset) Inputs
CE
26
15
P6
Q0-Q7
ECL Data Outputs
MR
27
14
P7
CE*
ECL Count Enable Control Input
VEE
28
Q0
29
MC100EP016A
13
VCC
12
TC
PE*
ECL Parallel Load Enable Control Input
MR*
ECL Master Reset
CLK*, CLK*
ECL Differential Clock
TC
ECL Terminal Count Output
Q1
30
11
COUT
Q2
31
10
TCLD*
COUT COUT, COUT
VCC
32
9
1
2
3
4
5
6
7
VEE
8
ECL TC-Load Control Input
ECL Differential Output
VCC
VEE
Positive Supply
Negative Supply
VBB
Reference Voltage Output
* Pins will default LOW when left open.
VCC Q3
Q4
Q5
Q6
Q7 TCLD VCC
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
FUNCTION TABLES
CE
PE
X
L
L
H
X
X
L
H
H
H
X
X
TCLD MR
X
L
H
X
X
X
CLK
L
L
L
L
L
H
Z
Z
Z
Z
ZZ
X
FUNCTION
Load Parallel (Pn to Qn)
Continuous Count
Count; Load Parallel on TC = LOW
Hold
Masters Respond, Slaves Hold
Reset (Qn : = LOW, TC : = HIGH)
ZZ = Clock Pulse (High-to-Low)
Z = Clock Pulse (Low-to-High)
FUNCTION TABLE
Function
PE
CE
MR
TCLD
CLK
P7-P4
P3
P2
P1
P0
Q7-Q4
Q3
Q2
Q1
Q0
TC
COUT
COUT
Load Count
L
H
H
H
H
X
L
L
L
L
L
L
L
L
L
X
L
L
L
L
Z
Z
Z
Z
Z
H
X
X
X
X
H
X
X
X
X
H
X
X
X
X
L
X
X
X
X
L
X
X
X
X
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
L
H
H
H
H
L
H
L
L
L
H
L
Load Hold
L
H
H
X
H
H
L
L
L
X
X
X
Z
Z
Z
H
X
X
H
X
X
H
X
X
L
X
X
L
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
Load on
Terminal
Count
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
Z
Z
Z
Z
Z
Z
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
L
L
H
H
H
H
L
H
L
H
L
H
L
H
H
L
H
H
H
H
H
L
H
H
H
L
L
H
L
L
L
Reset
X
X
H
X
X
X
X
X
X
X
L
L
L
L
L
H
H
L
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189
MC100EP016A
Q1
Q0
Q7
PE
TCLD
Q0M
MASTER Q0M SLAVE
CE
Q0
CE
CE Q
Q1 0
Q2
Q3
Q4
Q5 Q
6
BIT 1
BIT 0
P0
P1
BIT 7
P7
MR
CLK
BITS 2-6
CLK
TC
5
VBB
VEE
COUT
COUT
Note that this diagram is provided for understanding of logic operation only.
It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.
Figure 2. 8-BIT Binary Counter Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
Flammability Rating
> 2 kV
> 100 V
> 2 kV
Level 2
Oxygen Index: 28 to 34
Transistor Count
UL 94 V-0 @ 0.125 in
1226 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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190
MC100EP016A
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
VEE
PECL Mode Power Supply
NECL Mode Power Supply
VEE = 0 V
VCC = 0 V
6
V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
TA
VBB Sink/Source
Operating Temperature Range
± 0.5
mA
Tstg
JA
Storage Temperature Range
-65 to +150
-40 to +70
°C
°C
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
74
61
°C/W
°C/W
JC
Thermal Resistance (Junction to Case)
std bd
32 LQFP
12 to 17
°C/W
265
°C
VI VCC
VI VEE
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
Symbol
IEE
Characteristic
Power Supply Current
Min
-40 °C
Typ
Max
Min
25°C
Typ
Max
Min
70°C
Typ
Max
130
170
210
130
177
210
130
180
210
Unit
mA
VOH
VOL
Output HIGH Voltage (Note 4)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
Output LOW Voltage (Note 4)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
VIL
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
Input LOW Voltage (Single Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
VIHCMR
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
A
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
Input LOW Current
1875
2.0
1875
150
1875
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V.
4. All loading with 50 ohms to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.6 V to -3.0 V (Note 6)
-40 °C
25°C
70°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
130
170
210
130
177
210
130
180
210
mA
Output HIGH Voltage (Note 7)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
VIH
Output LOW Voltage (Note 7)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
VBB
Input LOW Voltage (Single Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
0.0
V
IIH
IIL
Input HIGH Current
150
A
Symbol
Characteristic
IEE
VOH
Power Supply Current
Input LOW Current
-1425
VEE+2.0
0.0
VEE+2.0
150
0.5
-1425
0.0
VEE+2.0
150
0.5
-1425
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC.
7. All loading with 50 ohms to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC100EP016A
AC CHARACTERISTICS VEE = -3.0 V to -3.6 V; VCC = 0 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 9)
-40 °C
Symbol
fCOUNT
Min
Characteristic
Maximum Frequency
Count & Division Modes
Q, TC, COUT/COUT
Typ
25°C
Max
Min
Typ
70°C
Max
Min
Typ
Max
Unit
GHz
1.3
1.5
CLK to Q
MR to Q
CLK to TC
MR to TC
CLK to COUT/COUT
MR to COUT/COUT
350
400
350
400
475
450
511
550
511
555
705
720
1.4
400
400
400
400
500
500
550
570
550
570
745
760
1.3
480
450
480
520
550
570
610
630
610
635
825
830
Propagation Delay
tS
Setup Time
P0
P1 to P4
P5 to P7
CE
PE
TCLD
400
300
250
500
500
550
240
140
80
320
315
355
400
300
250
500
500
550
240
135
65
330
320
365
400
300
250
500
500
550
245
125
55
340
325
380
ps
tH
Hold Time
P0
P1 to P4
P5 to P7
CE
PE
TCLD
100
50
150
600
625
525
-145
-160
-105
380
465
320
100
50
150
600
625
525
-155
-170
-1 10
410
500
325
100
50
150
600
625
525
-170
-180
-1 15
450
535
340
ps
tJITTER
Clock Random Jitter
(RMS, 1000 Waveforms)
tRR
Reset Recovery Time
400
195
400
205
400
220
ps
tPW
Minimum Pulse Width CLK
Minimum Pulse Width MR
550
550
365
380
550
550
365
380
550
550
370
380
ps
tr, tf
Output Rise/Fall Times
20% - 80%
90
180
100
190
125
215
8.5
320
2.5
700
750
700
750
900
900
1.1
tPLH
tPHL
2.6
650
700
650
700
850
850
1.2
8.0
320
9. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
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192
2.5
780
820
780
820
1000
950
8.0
450
ps
ps
ps
MC100EP016A
Applications Information
Cascading Multiple EP016A Devices
For applications which call for larger than 8-bit counters
multiple EP016As can be tied together to achieve very wide
bit width counters. The active low terminal count (TC)
output and count enable input (CE) greatly facilitate the
cascading of EP016A devices. Two EP016As can be
cascaded without the need for external gating, however for
counters wider than 16 bits external OR gates are necessary
for cascade implementations.
Figure 3 below pictorially illustrates the cascading of 4
EP016As to build a 32-bit high frequency counter. Note the
EP01 gates used to OR the terminal count outputs of the
lower order EP016As to control the counting operation of
the higher order bits. When the terminal count of the
preceding device (or devices) goes low (the counter reaches
an all 1s state) the more significant EP016A is set in its count
mode and will count one binary digit upon the next positive
clock transition. In addition, the preceding devices will also
count one bit thus sending their terminal count outputs back
to a high state disabling the count operation of the more
significant counters and placing them back into hold modes.
Therefore, for an EP016A in the chain to count, all of the
lower order terminal count outputs must be in the low state.
The bit width of the counter can be increased or decreased
by simply adding or subtracting EP016A devices from
Figure 3 and maintaining the logic pattern illustrated in the
same figure.
The maximum frequency of operation for a cascaded
counter chain is set by the propagation delay of the TC output,
the necessary setup time of the CE input, and the propagation
delay through the OR gate controlling it (for 16- bit counters
the limitation is only the TC propagation delay and the CE
setup time). Figure 3 shows EP01 gates used to control the
count enable inputs, however, if the frequency of operation is
slow enough, a LVECL OR gate can be used. Using the worst
case guarantees for these parameters.
LOAD
Q0 to Q7
LO
CE
PE
EP016
LSB
CLK
CLK
TC
Q0 to Q7
CE
CE
PE
EP016
CLK
CLK
CE
PE
EP016
CLK
CLK
TC
PE
EP016
MSB
CLK
CLK
TC
TC
EP01
EP01
P0 to P7
Q0 to Q7
Q0 to Q7
P0 to P7
P0 to P7
P0 to P7
CLK
CLK
Figure 3. 32-Bit Cascaded EP016A Counter
TCLD pin (load on terminal count) when asserted reloads the
data present at the parallel input pin (Pn’s) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 4
below illustrates the input conditions necessary for utilizing
the EP016A as a programmable divider set up to divide by
113.
Note that this assumes the trace delay between the TC
outputs and the CE inputs are negligible. If this is not the
case estimates of these delays need to be added to the
calculations.
Programmable Divider
The EP016A has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider. The
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193
MC100EP016A
Applications Information (continued)
H
L
L
P7 P6 P5
H
PE
L
CE
H
L
H
H
H
H
P4
P3
P2 P1 P0
Table 1. Preset Values for Various Divide Ratios
Ratio
P7
P6
P5
P4
P3
P2
P1
P0
2
3
4
5
•
•
112
113
114
•
•
254
255
256
H
H
H
H
•
•
H
H
H
•
•
L
L
L
H
H
H
H
•
•
L
L
L
•
•
L
L
L
H
H
H
H
•
•
L
L
L
•
•
L
L
L
H
H
H
H
•
•
H
L
L
•
•
L
L
L
H
H
H
H
•
•
L
H
H
•
•
L
L
L
H
H
H
L
•
•
L
H
H
•
•
L
L
L
H
L
L
H
•
•
L
H
H
•
•
H
L
L
L
H
L
H
•
•
L
H
L
•
•
L
H
L
TC
TCLD
COUT
CLK
CLK
Q7 Q6 Q5
COUT
Q4 Q3 Q2 Q1 Q0
Figure 4. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
Pn’s = 256 - 113 = 8F16 = 1000 1111
where:
P0 = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure 4
will result in the waveforms of Figure 5. Note that the TC
output is used as the divide output and the pulse duration is
equal to a full clock period. For even divide ratios, twice the
desired divide ratio can be loaded into the EP016A and the
TC output can feed the clock input of a toggle flip flop to
create a signal divided as desired with a 50% duty cycle.
Load
1001 0000
Preset Data Inputs
Divide
de
A single EP016A can be used to divide by any ratio from
2 to 256 inclusive. If divide ratios of greater than 256 are
needed multiple EP016As can be cascaded in a manner
similar to that already discussed. When EP016As are
cascaded to build larger dividers the TCLD pin will no
longer provide a means for loading on terminal count.
Because one does not want to reload the counters until all of
the devices in the chain have reached terminal count,
external gating of the TC pins must be used for multiple
EP016A divider chains.
1001 0001
1111 1100
•••
1111 1101
1111 1110
1111 1111
CLK
•••
PE
•••
TC
DIVIDE BY 113
Figure 5. Divide by 113 EP016A Programmable Divider Waveforms
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194
Load
MC100EP016A
Applications Information (continued)
EP01
Q0 to Q7
LO
CE
PE
EP016
LSB
CLK
CLK
TC
Q0 to Q7
CE
Q0 to Q7
PE
CE
EP016
CLK
CLK
PE
CE
EP016
CLK
CLK
TC
PE
EP016
MSB
CLK
CLK
TC
EP01
P0 to P7
Q0 to Q7
TC
EP01
P0 to P7
P0 to P7
P0 to P7
CLK
CLK
Figure 6. 32-Bit Cascaded EP016A Programmable Divider
Maximizing EP016A Count Frequency
Figure 6 shows a typical block diagram of a 32-bit divider
chain. Once again to maximize the frequency of operation
EP01 OR gates were used. For lower frequency applications
a slower OR gate could replace the EP01. Note that for a
16-bit divider the OR function feeding the PE (program
enable) input CANNOT be replaced by a wire OR tie as the
TC output of the least significant EP016A must also feed the
CE input of the most significant EP016A. If the two TC
outputs were OR tied the cascaded count operation would
not operate properly. Because in the cascaded form the PE
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.
The EP016A device produces 9 fast transitioning single
ended outputs, thus VCC noise can become significant in
situations where all of the outputs switch simultaneously in
the same direction. This VCC noise can negatively impact
the maximum frequency of operation of the device. Since
the device does not need to have the Q outputs terminated to
count properly, it is recommended that if the outputs are not
going to be used in the rest of the system they should be left
unterminated. In addition, if only a subset of the Q outputs
are used in the system only those outputs should be
terminated. Not terminating the unused outputs will not only
cut down the VCC noise generated but will also save in total
system power dissipation. Following these guidelines will
allow designers to either be more aggressive in their designs
or provide them with an extra margin to the published data
book specifications.
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195
MC100EP016A
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 7. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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196
MC10EP101, MC100EP101
3.3V / 5VECL Quad 4−Input
OR/NOR
The MC10/100EP101 is a Quad 4-input OR/NOR gate. The device
is functionally equivalent to the E101. With AC performance faster
than the E101 device, the EP101 is ideal for applications requiring the
fastest AC performance available.
The 100 Series contains temperature compensation.
http://onsemi.com
MARKING
DIAGRAM*
• 250 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
•
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
LQFP-32
FA SUFFIX
CASE 873A
MCXXX
EP016
AWLYYWW
32
xxx
A
WL
YY
WW
1
=10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2002
May, 2002 - Rev. 6
197
Package
Shipping
MC10EP101FA
LQFP-32
250 Units/Tray
MC10EP101FAR2
LQFP-32
2000 Tape & Reel
MC100EP101FA
LQFP-32
250 Units/Tray
MC100EP101FAR2
LQFP-32
2000 Tape & Reel
Publication Order Number:
MC10EP101/D
MC10EP101, MC100EP101
D0d D1a D1b D1c D1d D2a D2b D2c
24
23
22
21
20
19
18
D0a
D0b
D0c
17
Q0
Q0
D0d
D0c
25
16
D2d
D0b
26
15
D3a
D1a
D0a
27
14
D3b
D1b
Q1
28
13
D1c
VEE
VCC
Q1
Q0
29
12
D3c
Q0
30
11
D3d
VCC
31
10
VEE
VCC
32
9
NC
MC10EP101
MC100EP101
1
2
3
4
5
6
7
D1d
D2a
D2b
Q2
D2c
D2d
Q2
8
D3a
VCC Q1
Q1
Q2
Q2
Q3
Q3
D3b
D3c
Q3 VCC
Q3
D3d
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
VEE
Figure 1. 32-Lead LQFP Pinout (Top View)
Figure 2. Logic Diagram
PIN DESCRIPTION
PIN
FUNCTION
D0a*-D3d*
ECL Data Inputs
Q0-Q3, Q0-Q3
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
NC
No Connect
TRUTH TABLE
* Pins will default LOW when left open.
Dna
Dnb
Dnc
Dnd
Qn
Qn
L
H
X
X
X
H
L
X
H
X
X
H
L
X
X
H
X
H
L
X
X
X
H
H
L
H
H
H
H
H
H
L
L
L
L
L
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
> 4 kV
> 100 V
> 2 kV
Level 2
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8″
28 to 34
Transistor Count
173 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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198
MC10EP101, MC100EP101
MAXIMUM RATINGS (Note 2)
Symbol
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
VI ≤ VCC
VI ≤ VEE
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
57
75
45
58
75
45
59
75
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single-Ended)
1365
1690
1460
1755
1490
1815
mV
IIH
Input HIGH Current
150
µA
150
150
IIL
Input LOW Current
-150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 Ω to VCC-2.0 volts.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
57
75
45
58
75
45
59
75
mA
Output HIGH Voltage (Note 6)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 6)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
IIH
Input HIGH Current
150
µA
IEE
Power Supply Current
VOH
150
150
IIL
Input LOW Current
-150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
6. All loading with 50 Ω to VCC-2.0 volts.
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199
MC10EP101, MC100EP101
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 7)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
57
75
45
58
75
45
59
75
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 8)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
IIH
Input HIGH Current
150
µA
150
150
IIL
Input LOW Current
-150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC.
8. All loading with 50 Ω to VCC-2.0 volts.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 9)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
50
63
80
55
67
85
60
70
88
mA
VOH
Output HIGH Voltage (Note 10)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 10)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
-150
150
-150
µA
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
10. All loading with 50 Ω to VCC-2.0 volts.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 11)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
50
63
80
55
67
85
60
70
88
mA
Output HIGH Voltage (Note 12)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note12)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IEE
Power Supply Current
VOH
150
-150
150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
12. All loading with 50 Ω to VCC-2.0 volts.
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200
MC10EP101, MC100EP101
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 13)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
50
63
80
55
67
85
60
70
88
mA
Output HIGH Voltage (Note 14)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 14)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
IIH
Input HIGH Current
150
µA
IEE
Power Supply Current
VOH
150
150
IIL
Input LOW Current
-150
-150
-150
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
13. Input and output parameters vary 1:1 with VCC.
14. All loading with 50 Ω to VCC-2.0 volts.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 15)
-40 °C
Characteristic
fmax
Maximum Frequency
(See Figure 3. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay
tSKEW
tJITTER
Min
Typ
25°C
Max
Min
>3
D to Q, Q
10
100
Typ
85°C
Max
Min
>3
325
380
Within Device Skew
Q, Q
Device to Device Skew (Note 16)
15
Cycle-to-Cycle Jitter
(See Figure 3. Fmax/JITTER)
0.2
>3
125
180
150
200
250
300
370
400
50
200
20
<1
0.2
170
250
VOUTpp (mV)
GHz
420
450
50
200
20
50
200
ps
<1
0.2
<1
ps
190
250
ps
150
1000
10
900
9
800
8
700
7
600
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
ÉÉ
2
(JITTER)
100
1
0
1000
Unit
300
320
tr
Output Rise/Fall Times
Q, Q
100
150
200
120
170
220
tf
(20% - 80%)
15. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC-2.0 V.
16. Skew is measured between outputs under identical transitions.
0
Max
ps
225
280
200
Typ
2000
3000
FREQUENCY (MHz)
Figure 3. Fmax/Jitter
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201
JITTEROUT ps (RMS)
Symbol
4000
5000
MC10EP101, MC100EP101
Q
D
Driver
Device
Receiver
Device
D
Q
50 Ω
50 Ω
VTT
VTT = VCC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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202
MC10EP105, MC100EP105
3.3V / 5VECL Quad 2−Input
Differential AND/NAND
The MC10/100EP105 is a quad 2-input differential AND/NAND
gate. Each gate is functionally equivalent to the EP05 and LVEL05
devices. With AC performance much faster than the LVEL05 device,
the EP105 is ideal for applications requiring the fastest AC
performance available.
The 100 Series contains temperature compensation.
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MARKING
DIAGRAM*
• 275 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
MCxxx
EP105
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
AWLYYWW
LQFP-32
FA SUFFIX
CASE 873A
•
• Safety Clamp on Inputs
xxx
A
WL
YY
WW
32
1
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 8
203
Package
Shipping
MC10EP105FA
LQFP-32
250 Units/Tray
MC10EP105FAR2
LQFP-32
2000 Tape & Reel
MC100EP105FA
LQFP-32
250 Units/Tray
MC100EP105FAR2
LQFP-32
2000 Tape & Reel
Publication Order Number:
MC10EP105/D
MC10EP105, MC100EP105
D0b D1a D1a D1b D1b D2a D2a D2b
24
23
22
21
20
19
18
D0a
17
25
16
D2b
D0a
26
15
D3a
D1a
D0a
27
14
D3a
D1a
D1b
VEE
28
13
VCC
Q0
29
12
D3b
D2a
D2a
D2b
D2b
Q0
30
11
D3b
VCC
31
10
VEE
VCC
32
9
NC
1
2
3
4
5
6
7
8
Q0
D0b
D0b
MC10EP105
MC100EP105
Q0
D0a
D0b
Q1
Q1
D1b
Q2
Q2
D3a
Q3
D3a
D3b
Q3
D3b
VCC Q1
Q1
Q2
Q2
Q3
Q3 VCC
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
VEE
Figure 1. 32-Lead LQFP Pinout (Top View)
Figure 2. Logic Diagram
PIN DESCRIPTION
PIN
TRUTH TABLE
FUNCTION
Dna*, Dnb*, Dna*, Dnb*
ECL Data Inputs
Qn, Qn
ECL Data Outputs
VCC
Positive Supply
VEE
NC
Negative Supply
No Connect
Dna
Dnb
Dna
L
L
H
H
L
H
L
H
H
H
L
L
Dnb
Qn
Qn
H
L
H
L
L
L
L
H
H
H
H
L
* Pins will default LOW when left open.
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 100 V
> 2 kV
Oxygen Index: 28 to 34
UL-94 V-0 @ 0.125 in
Moisture Sensitivity (Note 1)
Flammability Rating
Level 2
Transistor Count
444 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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204
MC10EP105, MC100EP105
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Units
VCC
VEE
PECL Mode Power Supply
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
Iout
Output Current
IBB
TA
VBB Sink/Source
Operating Temperature Range
Tstg
θJA
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
θJC
Tsol
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
NECL Mode Power Supply
VEE = 0 V
VCC = 0 V
Rating
6
V
-6
V
6
-6
V
V
50
100
mA
mA
± 0.5
mA
-40 to +85
°C
-65 to +150
°C
VI ≤ VCC
VI ≥ VEE
VEE = 0 V
VCC = 0 V
Continuous
Surge
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
58
75
45
59
75
45
60
75
mA
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
Input LOW Voltage (Single-Ended)
1365
1690
1460
1755
1490
1815
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
2.0
3.3
2.0
3.3
2.0
3.3
V
150
µA
IEE
VOH
Power Supply Current
VOL
VIH
VIL
VIHCMR
IIH
IIL
Input HIGH Current
Input LOW Current
150
0.5
150
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 Ω to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
58
75
45
59
75
45
60
75
mA
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
2.0
5.0
2.0
5.0
2.0
5.0
V
150
µA
IEE
VOH
Power Supply Current
VOL
VIH
VIL
VIHCMR
IIH
IIL
Input HIGH Current
Input LOW Current
150
0.5
150
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 Ω to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP105, MC100EP105
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
58
75
45
59
75
45
60
75
mA
Output HIGH Voltage (Note 10)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
VIH
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
VIHCMR
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
0.0
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
Input LOW Current
VEE+2.0
0.0
VEE+2.0
150
0.5
0.0
VEE+2.0
150
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 Ω to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
45
59
75
45
62
75
45
64
75
mA
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
VIHCMR
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
150
0.5
150
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 Ω to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
59
75
45
62
75
45
64
75
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
VIH
Output LOW Voltage (Note16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
VIHCMR
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
150
0.5
150
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 Ω to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP105, MC100EP105
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
59
75
45
62
75
45
64
75
mA
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
VIHCMR
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
0.0
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
VOL
VIH
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
VEE+2.0
0.0
VEE+2.0
0.0
150
Input LOW Current
0.5
VEE+2.0
150
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 Ω to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 3 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Min
Typ
25°C
Max
Min
>3
85°C
Max
Min
Typ
>3
325
Within Device Skew
Device to Device Skew (Note 22)
10
tJITTER
Cycle-to-Cycle Jitter
(See Figure 3 Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
275
350
50
10
0.2
<1
800
1200
GHz
375
ps
50
15
50
ps
0.2
<1
0.2
<1
ps
800
1200
150
800
1200
mV
tr
Output Rise/Fall Times
Q
100
150
200
120
170
220
tf
(20% - 80%)
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC-2.0 V.
22. Skew is measured between outputs under identical transitions.
150
200
250
ps
150
225
Unit
300
150
200
Max
>3
1000
10
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
100
0
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
ÉÉ
2
(JITTER)
0
1000
2000
3000
FREQUENCY (MHz)
Figure 3. Fmax/Jitter
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207
JITTEROUT ps (RMS)
250
VOUTpp (mV)
175
Typ
1
4000
5000
MC10EP105, MC100EP105
Q
D
Driver
Device
Receiver
Device
D
Q
50 Ω
50 Ω
VTT
VTT = VCC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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208
MC10EP116, MC100EP116
3.3V / 5VHex Differential
Line Receiver/Driver
The MC10EP116/100EP116 is a 6-bit differential line receiver
based on the EP16 device. The 3.0 GHz bandwidth provided by the
high frequency outputs makes the device ideal for buffering of very
high speed oscillators.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The design incorporates two stages of gain, internal to the device,
making it an excellent choice for use in high bandwidth amplifier
applications.
The differential inputs have internal clamp structures which will
force the Q output of a gate in an open input condition to go to a LOW
state. Thus, inputs of unused gates can be left open and will not affect
the operation of the rest of the device. Note that the input clamp will
take affect only if both inputs fall 2.5 V below VCC.
The 100 Series contains temperature compensation.
• 260 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
•
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
• VBB Output
September, 2002 - Rev. 8
MARKING
DIAGRAM*
MCxxx
EP116
LQFP-32
FA SUFFIX
CASE 873A
AWLYYWW
32
1
xxx
A
WL
YY
WW
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
 Semiconductor Components Industries, LLC, 2002
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209
ORDERING INFORMATION
Device
Package
Shipping
MC10EP116FA
LQFP-32
250 Units/Tray
MC10EP116FAR2
LQFP-32
2000 Tape & Reel
MC100EP116FA
LQFP-32
250 Units/Tray
MC100EP116FAR2
LQFP-32
2000 Tape & Reel
Publication Order Number:
MC10EP116/D
MC10EP116, MC100EP116
D4
24
D5
23
D5 Q5 Q5 Q4 Q4 VCC
22
21
20
19
18
17
D0
Q0
D0
Q0
D4
25
16
VCC
D3
26
15
Q3
D1
Q1
D3
27
14
Q3
D1
Q1
VEE
28
13
VCC
D2
29
12
VCC
D2
Q2
D2
30
11
Q2
D2
Q2
D1
31
10
Q2
D1
32
9
D3
Q3
D3
Q3
D4
Q4
D4
Q4
D5
Q5
D5
Q5
MC10EP116
MC100EP116
1
2
D0
3
4
5
6
7
VCC
8
D0 VBB Q0 Q0 Q1 Q1 VEE
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
PIN DESCRIPTION
PIN
FUNCTION
D[0:5]*, D[0:5]*
ECL Differential Data Inputs
Q[0:5], Q[0:5]
ECL Differential Data Outputs
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
VBB
VEE
Figure 2. Logic Diagram
* Pins will default LOW when left open.
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
Flammability Rating
> 2 kV
> 100 V
> 2 kV
Level 2
Oxygen Index: 28 to 34
Transistor Count
UL-94 V-0 @ 0.125 in
729 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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210
MC10EP116, MC100EP116
MAXIMUM RATINGS (Note 2)
Symbol
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
265
°C
VI ≤ VCC
VI ≥ VEE
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
60
75
90
60
80
95
60
85
95
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single-Ended)
1365
1690
1460
1755
1490
1815
mV
VBB
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
µA
1890
2.0
150
1955
150
2015
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 Ω to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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211
MC10EP116, MC100EP116
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
60
75
90
60
80
95
60
85
95
mA
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
µA
IEE
Power Supply Current
VOH
3590
2.0
3655
150
3715
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 Ω to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
60
75
90
60
80
95
60
85
95
mA
VOH
Output HIGH Voltage (Note 10)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VBB
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
-1 185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
Input HIGH Current
150
µA
-1410
VEE+2.0
0.0
150
-1345
VEE+2.0
0.0
150
-1285
VEE+2.0
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 Ω to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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212
MC10EP116, MC100EP116
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
60
75
90
60
80
95
60
85
95
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1490
1675
1490
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
µA
1875
2.0
1875
150
1875
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 Ω to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
60
75
90
60
80
95
60
85
95
mA
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3790
3375
3190
3375
3190
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
µA
IEE
Power Supply Current
VOH
3575
2.0
150
3575
150
3575
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 Ω to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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213
MC10EP116, MC100EP116
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
60
75
90
60
80
95
60
85
95
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
0.0
V
IIH
Input HIGH Current
150
µA
-1425
VEE+2.0
0.0
-1425
VEE+2.0
150
0.0
-1425
VEE+2.0
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 Ω to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 3 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Duty Cycle Skew (Note 22)
tSKEW
Within Device Skew
Device to Device Skew (Note 22)
tJITTER
Cycle-to-Cycle Jitter
(See Figure 3 Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Min
Typ
25°C
Max
Min
>3
160
Typ
Max
Min
>3
250
340
5.0
20
160
0.2
<1
150
800
1200
90
150
220
Typ
Max
>3
260
340
5.0
20
100
180
Q, Q
85°C
190
Unit
GHz
300
380
ps
5.0
20
ps
100
190
ps
0.2
<1
ps
100
180
0.2
<1
150
800
1200
150
800
1200
mV
90
160
240
90
160
250
ps
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC-2.0 V.
22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
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214
900
9
800
8
700
7
600
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
200
2
100
1
(JITTER)
0
0
1000
2000
3000
4000
5000
FREQUENCY (MHz)
Figure 3. Fmax/Jitter
Q
D
Driver
Device
Receiver
Device
D
Q
50 Ω
50 Ω
VTT
VTT = VCC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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215
JITTEROUT ps (RMS)
VOUTpp (mV)
MC10EP116, MC100EP116
MC10EP131, MC100EP131
3.3V / 5VECL Quad D
Flip−Flop with Set, Reset,
and Differential Clock
The MC10/100EP131 is a Quad Master-slaved D flip-flop with
common set and separate resets. The device is an expansion of the
E131 with differential common clock and individual clock enables.
With AC performance faster than the E131 device, the EP131 is ideal
for applications requiring the fastest AC performance available.
Each flip-flop may be clocked separately by holding Common
Clock (CC) LOW and CC HIGH, then using the differential Clock
Enable inputs for clocking (C0- 3, C0- 3).
Common clocking is achieved by holding the differential inputs
C0- 3 LOW and C0- 3 HIGH while using the differential Common
Clock (CC) to clock all four flip-flops. When left floating open, any
differential input will disable operation due to input pulldown resistors
forcing an output default state.
Individual asynchronous resets (R0- 3) and an asynchronous set
(SET) are provided.
Data enters the master when both CC and C0- 3 are LOW, and
transfers to the slave when either CC or C0- 3 (or both) go HIGH.
The 100 Series contains temperature compensation.
•
•
•
•
•
•
•
460 ps Typical Propagation Delay
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MARKING
DIAGRAM*
MCXXX
EP131
LQFP-32
FA SUFFIX
CASE 873A
AWLYYWW
32
1
XXX = 10 or 100
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
*For additional information, see Application Note
AND8002/D
Maximum Frequency > 3 GHz Typical
Differential Individual and Common Clocks
Individual Asynchronous Resets
Asynchronous Set
ORDERING INFORMATION
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
Device
•
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
 Semiconductor Components Industries, LLC, 2002
May, 2002 - Rev. 6
216
Package
Shipping
MC10EP131FA
LQFP-32
250 Units/Tray
MC10EP131FAR2
LQFP-32
2000 Tape & Reel
MC100EP131FA
LQFP-32
250 Units/Tray
MC100EP131FAR2 LQFP-32
2000 Tape & Reel
Publication Order Number:
MC10EP131/D
MC10EP131, MC100EP131
Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0
S
D
D3
24
VCC
23
22
21
20
19
18
17
16
25
VCC
C3
C3
C3
26
15
R0
C3
27
14
D0
VEE
28
13
VCC
D2
D3
29
12
C0
R3
30
11
C0
C2
C2
SET
31
10
R1
D2
32
32-Lead LQFP Pinout
(Top View)
9
1
2
3
4
5
6
7
ECL Separate Clock Inputs
CC*, CC*
ECL Common Clock Inputs
Q
Q2
Q
Q1
Q
Q1
Q
Q0
Q
Q0
R1
R
C1
C1
D
S
R0
R0- 3*
ECL Asynchronous Reset
SET*
ECL Asynchronous Set
Q0- 3, Q0- 3
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
R
C0
C0
D0
D
S
VEE
* Pins will default LOW when left open.
Figure 2. Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
Flammability Rating
Q2
R
D1
C0- 3*, C0- 3*
Q
S
D
CC
CC
PIN DESCRIPTION
FUNCTION
Q3
R2
Figure 1. 32-Lead LQFP Pinout (Top View)
ECL Data Inputs
Q
R
R3
R2 C2 C2 CC CC C1 C1 D1
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
PIN
Q3
VEE SET
8
D0- 3*
Q
> 2 kV
> 100 V
> 2 kV
Level 2
Oxygen Index: 28 to 34
Transistor Count
UL 94 V-0 @ 0.125 in
935 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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217
MC10EP131, MC100EP131
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
6
V
-6
V
6
-6
V
V
50
100
mA
mA
± 0.5
mA
VCC
PECL Mode Power Supply
VEE = 0 V
VEE
NECL Mode Power Supply
VCC = 0 V
VI
Input
PECL Mode In
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
IBB
VBB Sink/Source
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
265
°C
VI ≤ VCC
VI ≥ VEE
Tsol
Wave Solder
> 2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
70
95
120
70
95
120
70
95
120
mA
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single-Ended)
1365
1690
1460
1755
1490
1815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
µA
IEE
Power Supply Current
VOH
VOL
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 Ω to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
70
95
120
70
95
120
70
95
120
mA
VOH
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
µA
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 Ω to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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218
MC10EP131, MC100EP131
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
70
95
120
70
95
120
70
95
120
mA
VOH
Output HIGH Voltage (Note 10)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
Input HIGH Current
150
µA
VEE+2.0
0.0
VEE+2.0
150
0.0
VEE+2.0
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 Ω to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
70
95
120
75
97
120
80
105
130
mA
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
µA
IEE
Power Supply Current
VOH
VOL
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 Ω to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
70
95
120
75
97
120
80
105
130
mA
VOH
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
µA
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 Ω to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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219
MC10EP131, MC100EP131
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
70
95
120
75
97
120
80
105
130
mA
VOH
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
0.0
V
IIH
Input HIGH Current
150
µA
VEE+2.0
0.0
VEE+2.0
0.0
150
VEE+2.0
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 Ω to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
Characteristic
Min
fmax
Maximum Frequency
(See Figure 3. Frequency vs. VOUTpp
and JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tRR
tS
tH
tPW
Minimum Pulse Rate
tJITTER
Cycle-to-Cycle Jitter
(See Figure 3. Frequency vs. VOUTpp
and JITTER)
C0- 3
CC
R0- 3
SET
Typ
Max
Min
>3
320
320
320
300
450
450
430
430
Set/R0-3 Recovery
290
Setup Time
Hold Time
120
550
400
SET, R0- 3
25°C
Typ
Max
460
500
480
460
210
290
80
120
550
400
520
520
520
550
<1
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Typ
Max
>3
Unit
GHz
450
450
450
400
560
560
560
530
210
350
280
ps
80
120
80
ps
550
400
0.2
580
600
580
580
<1
tr
Output Rise/Fall Times
Q, Q
110
180
250
125
200
275
tf
(20% - 80%)
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC-2.0 V.
220
Min
>3
380
400
380
380
0.2
85°C
150
650
650
700
650
ps
0.2
<1
ps
230
300
ps
800
8
700
7
600
6
500
5
400
4
300
3
200
2
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
100
1
(JITTER)
0
0
1000
2000
JITTEROUT ps (RMS)
VOUTpp (mV)
MC10EP131, MC100EP131
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 3. Frequency vs. VOUTpp and JITTER
Q
D
Driver
Device
Receiver
Device
D
Q
50 Ω
50 Ω
VTT
VTT = VCC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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221
MC10EP139, MC100EP139
3.3V / 5VECL ÷2/4, ÷4/5/6
Clock Generation Chip
The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single- ended ECL or, if positive power supplies are used,
LVPECL input signals. In addition, by using the VBB output, a sinusoidal
source can be AC coupled into the device. If a single- ended input is to be
used, the VBB output should be connected to the CLK input and bypassed
to ground via a 0.01 F capacitor.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen with
an asynchronous control. The internal enable flip- flop is clocked on the
falling edge of the input clock, therefore, all associated specification
limits are referenced to the negative edge of the clock input.
Upon startup, the internal flip- flops will attain a random state;
therefore, for systems which utilize multiple EP139s, the master reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EP139, the MR pin need not be exercised as the
internal divider design ensures synchronization between the ÷2/4 and the
÷4/5/6 outputs of a single device. All VCC and VEE pins must be
externally connected to power supply to guarantee proper operation.
The 100 Series contains temperature compensation.
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MARKING
DIAGRAMS*
20
20
TSSOP-20
DT SUFFIX
CASE 948E
•
•
•
•
•
•
20
1
SO-20
DW SUFFIX
CASE 751D
1
HEP
KEP
XXX
A
L,WL
Y, YY
W, WW
= MC10EP
= MC100EP
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Synchronous Enable/Disable
Device
Master Reset for Synchronization of Multiple Chips
VBB Output
September, 2002 - Rev. 3
MCXXXEP139
AWLYYWW
*For additional information, see Application Note
AND8002/D
Safety Clamp on Inputs
 Semiconductor Components Industries, LLC, 2002
1
20
• Maximum Frequency >1.0 GHz Typical
• 50 ps Output-to-Output Skew
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
HEP or KEP
139
ALYW
1
222
Package
Shipping
MC10EP139DT
TSSOP-20
75 Units/Rail
MC10EP139DTR2
TSSOP-20 2500 Tape & Reel
MC100EP139DT
TSSOP-20
MC100EP139DTR2
TSSOP-20 2500 Tape & Reel
75 Units/Rail
MC10EP139DW
SO-20
38 Units/Rail
MC10EP139DWR2
SO-20
1000 Tape & Reel
MC100EP139DW
SO-20
38 Units/Rail
MC100EP139DWR2
SO-20
1000 Tape & Reel
Publication Order Number:
MC10EP139/D
MC10EP139, MC100EP139
Q1
Q1
Q2
Q2
Q3
Q3
VEE
20
19
18
17
16
15
14
13
12
11
1
2
3
4
VCC
EN
CLK
5
6
CLK VBB
7
8
9
10
MR
VCC
DIVSELa
Q0
DIVSELb1
Q0
DIVSELb0
VCC
PIN DESCRIPTION
FUNCTION
PIN
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View)
CLK*, CLK*
ECL Diff Clock Inputs
EN*
ECL Sync Enable
MR*
ECL Master Reset
VBB
Q0, Q1, Q0, Q1
ECL Diff ÷2/4 Outputs
Q2, Q3, Q2, Q3
ECL Diff ÷4/5/6 Outputs
ECL Reference Output
DIVSELa*
ECL Freq. Select Input 2/4
DIVSELb0*
ECL Freq. Select Input 4/5/6
DIVSELb1*
ECL Freq. Select Input 4/5/6
VCC
VEE
ECL Positive Supply
*
ECL Negative Supply
Pins will default low when left open.
DIVSELa
Q0
CLK
÷2/4
CLK
R
Q0
Q1
Q1
Q2
EN
÷4/5/6
R
MR
DIVSELb0
DIVSELb1
Q2
Q3
Q3
VEE
Figure 2. Logic Diagram
FUNCTION TABLES
CLK
EN
MR
Z
ZZ
X
L
H
X
L
L
H
FUNCTION
Divide
Hold Q0:3
Reset Q0:3
Z = Low-to-High Transition
ZZ = High-to-Low Transition
DIVSELa
L
H
Q0:1 OUTPUTS
Divide by 2
Divide by 4
DIVSELb0 DIVSELb1
L
H
L
H
L
L
H
H
Q2:3 OUTPUTS
Divide by 4
Divide by 6
Divide by 5
Divide by 5
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MC10EP139, MC100EP139
CLK
Q (÷2)
Q (÷4)
Q (÷5)
Q (÷6)
Figure 3. Timing Diagram
CLK
tRR
RESET
Q (÷n)
Figure 4. Timing Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
758 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
VCC
VEE
PECL Mode Power Supply
NECL Mode Power Supply
VEE = 0 V
VCC = 0 V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
IBB
TA
VBB Sink/Source
Operating Temperature Range
Tstg
JA
Storage Temperature Range
-65 to +150
°C
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
140
100
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
20 TSSOP
23 to 41
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
20 SOIC
20 SOIC
90
60
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
20 SOIC
33 to 35
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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224
VI VCC
VI VEE
6
V
-6
V
6
-6
V
V
50
100
mA
mA
± 0.5
mA
-40 to +85
°C
MC10EP139, MC100EP139
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
65
82
105
65
83
105
65
84
105
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
VIH
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
1365
1690
1460
1755
1490
1815
mV
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
A
Input LOW Current
1890
2.0
1955
150
2015
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
65
82
105
65
83
105
65
84
105
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
VIH
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
A
Input LOW Current
3590
2.0
3655
150
3715
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
65
82
105
65
83
105
65
84
105
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 10)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
VIH
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
-1 185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
IIL
Input HIGH Current
150
A
Input LOW Current
-1410
VEE+2.0
0.0
VEE+2.0
150
0.5
-1345
0.0
VEE+2.0
150
0.5
-1285
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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225
MC10EP139, MC100EP139
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
70
83
100
70
87
105
75
90
110
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
A
Input LOW Current
1875
2.0
1875
150
1875
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
70
85
100
70
90
105
75
95
110
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
VIH
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
5.0
2.0
5.0
2.0
5.0
V
3575
2.0
3575
3575
IIH
Input HIGH Current
150
150
150
A
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
70
85
100
70
90
105
75
95
110
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
VIH
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
0.0
V
-1425
VEE+2.0
0.0
-1425
VEE+2.0
0.0
-1425
VEE+2.0
IIH
Input HIGH Current
150
150
150
A
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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226
MC10EP139, MC100EP139
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
>1
Typ
85°C
Max
Min
Max
Maximum Frequency
(See Figure 5 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay
tRR
Reset Recovery
ts
Setup Time
th
Hold Time
tPW
Minimum Pulse Width
tSKEW
Within Device Skew
Q, Q
Device-to-Device Skew (Note 22)
50
200
100
300
50
200
100
300
50
200
100
300
ps
tJITTER
Cycle-to-Cycle Jitter
(See Figure 5 Fmax/JITTER)
0.2
<1
0.2
<1
0.2
<1
ps
VPP
Input Voltage Swing (Differential)
150
800
1200
150
800
1200
150
800
1200
mV
tr
tf
Output Rise/Fall Times
(20% - 80%)
110
180
250
125
190
275
150
215
300
ps
550
700
700
800
200
EN, CLK
DIVSEL, CLK
600
700
750
850
100
200
200
400
120
180
CLK, EN
CLK, DIVSEL
100
200
50
140
MR
550
450
Q, Q
800
900
>1
Unit
fmax
CLK, Q (Diff)
MR, Q
>1
Typ
900
1000
GHz
675
800
825
950
975
1100
ps
100
200
100
ps
200
400
120
180
200
400
120
180
ps
100
200
50
140
100
200
50
140
ps
550
450
550
450
ps
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
800
8
4
5
7
2
600
6
6
500
5
JITTEROUT ps (RMS)
VOUTpp (mV)
700
ÉÉ
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
400
4
300
3
200
2
(JITTER)
100
0
1100
1
1200
1300
1400
1500
1600
1700
FREQUENCY (MHz)
Figure 5. Fmax/Jitter
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227
1800
1900
2000
MC10EP139, MC100EP139
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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228
MC100EP140
3.3VECL Phase− Frequency
Detector
The MC100EP140 is a three state phase frequency- detector intended for
phase- locked loop applications which require a minimum amount of phase
and frequency difference at lock. Since the part is designed with fully
differential internal gates, the noise is reduced throughout the circuit,
especially at high speeds. The basic operation of a Phase/Frequency
Detector (PFD) is to “compare” an incoming signal (feedback) to a set
reference signal. When the Reference (R) and Feedback (FB) inputs are
unequal in frequency and/or phase, the differential UP (U) and DOWN
(D) outputs will provide pulse streams which, when subtracted and
integrated, provide an error voltage for control of a VCO. Detector
states of operation are shown in the Figure 2 and the State Table.
The device is packaged in a small outline, surface mount 8-lead
SOIC package. The typical output amplitude of the EP140 is 400 mV,
allowing faster switching time and greater bandwidth. For proper
operation, the input edge rate of the R and FB inputs should be less
than 5 ns.
More information on Phase Lock Loop operation and application can
be found in AND8040.
The pinout is shown in Figure 1, the logic diagram in Figure 3, and
the typical termination in Figure 5.
•
•
•
•
•
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MARKING
DIAGRAM
8
SO-8
D SUFFIX
CASE 751
8
1
KP140
ALYW
1
KP = MC100EP
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
500 ps Typical Propagation Delay
Maximum Frequency > 2.1 GHz Typical
Fully Differential Internally
Advanced High Band Output Swing of 400 mV
ORDERING INFORMATION
Transfer Gain: 1.0 mV/Degree at 1.4 GHz
1.2 mV/Degree at 1.0 GHz
Rise and Fall Time: 100 ps Typical
Device
•
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: VCC = 3.0 V to 3.6 V
Package
Shipping
MC100EP140D
SO-8
98 Units/Rail
MC100EP140DR2
SO-8
2500 Units/Reel
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -3.6 V
• Open Input Default State
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 5
229
Publication Order Number:
MC100EP140/D
MC100EP140
VCC
R
FB
VEE
8
7
6
5
1
2
3
4
U
U
D
D
PIN DESCRIPTION
PIN
FUNCTION
D, D
Differential Down Outputs
U, U
Differential Up Outputs
R*
ECL Reference Input
FB*
ECL Feedback Input
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
Figure 1. 8-Lead Pinout (Top View)
STATE TABLE
R
R
1
FB
PHASE
DETECTOR
STATE
2
Pump
Down
U= L
D=H
3
Pump
Up
U=L
D=L
FB
R
L
L
L
L
H
L
H
1-2
H
L
L
L
2
L
L
L
L
2
L
L
L
L
2-3
H
L
H
L
3-2
H
H
L
L
2
L
L
L
L
C
A
U
U
C
U
FF
A
R
C
Reset
D
VEE
B
D
Reset
FB
R
B
D
PUMP UP
2-3-2
A
S
U
L
U=H
D=L
U
Reset
FB
2-1
FB
A
R
OUTPUT
PUMP DOWN
2-1-2
2
Figure 2. Phase Detector Logic Model
R
INPUT
D
FF
S
Reset
B
D
B
D
Figure 3. Logic Diagram
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230
D
D
MC100EP140
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
37.5 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL-94 V-0 @ 0.125 in
Transistor Count
457 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
8 SOIC
41 to 44
°C/W
265
°C
VI VCC
VI VEE
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
55
70
85
60
74
90
63
78
93
mA
VOH
Output HIGH Voltage (Note 4)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 4)
1755
1880
2005
1755
1880
2005
1755
1880
2005
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
IIH
Input HIGH Current
150
µA
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V.
4. All loading with 50 to VCC-2.0 volts.
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231
MC100EP140
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.6 V to -3.0 V (Note 5)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
55
70
85
60
74
90
63
78
93
mA
Output HIGH Voltage (Note 6)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 6)
-1545
-1420
-1295
-1545
-1420
-1295
-1545
-1420
-1295
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
IIH
Input HIGH Current
150
µA
IEE
Power Supply Current
VOH
150
150
IIL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Input and output parameters vary 1:1 with VCC.
6. All loading with 50 to VCC-2.0 volts.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 7)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 4 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tJITTER
Cycle-to-Cycle Jitter
(See Figure 4 Fmax/JITTER)
VPP
Input Voltage Swing
tr
tf
Output Rise/Fall Times
(20% - 80%)
Min
Typ
25°C
Max
Min
>2
R to U, FB to D
FB to U, R to D
300
400
Q, Q
Typ
85°C
Max
Min
>2
450
600
6002
800
.2
<1
400
800
1200
50
90
180
325
450
Typ
>2
475
650
625
850
.2
<1
400
800
1200
60
100
200
350
500
6
500
5
400
4
300
3
ps
.2
<1
ps
400
800
1200
mV
70
120
220
ps
ÏÏ
ÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
2
(JITTER)
100
1
0
0
400
800
1200
1600
FREQUENCY (MHz)
Figure 4. Fmax/Jitter
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232
2000
2400
GHz
650
900
JITTEROUT ps (RMS)
VOUTpp (mV)
600
Unit
500
700
7. Measured using a 750 mV VPP pk-pk, 50% duty cycle, clock source. All loading with 50 to VCC-2.0 V.
200
Max
MC100EP140
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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233
MC10EP142, MC100EP142
3.3V / 5VECL 9−Bit Shift
Register
The MC10EP/100EP142 is a 9-bit shift register, designed with
byte-parity applications in mind. The E142 performs serial/parallel in
and serial/parallel out, shifting in one direction. The nine inputs
D0 - D8 accept parallel input data, while S-IN accepts serial input
data. The Qn outputs do not need to be terminated for the shift
operation to function. To minimize noise and power, any Q output not
used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes
of operation - SHIFT and LOAD. The shift direction is from bit 0 to
bit 8. Input data is accepted by the registers a set-up time before the
positive going edge of CLK0 or CLK1; shifting is also accomplished
on the positive clock edge. A HIGH on the Master Reset pin (MR)
asynchronously resets all the resisters to zero.
The 100 Series contains temperature compensation.
•
•
•
•
•
•
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MARKING
DIAGRAM*
LQFP-32
FA SUFFIX
CASE 873A
MCxxx
EP142
AWLYYWW
32
1
>3 GHz Minimum Shift Frequency
xxx
A
WL
YY
WW
9-Bit for Byte-Parity Applications
Asynchronous Master Reset
Dual Clocks
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, refer to Application Note
AND8002/D
•
• Safety Clamp on Inputs
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 8
234
Package
Shipping
MC10EP142FA
LQFP-32
250 Units/Tray
MC10EP142FAR2
LQFP-32
2000/Tape & Reel
MC100EP142FA
LQFP-32
250 Units/Tray
MC100EP142FAR2
LQFP-32
2000/Tape & Reel
Publication Order Number:
MC10EP142/D
D7
D8
Q8
Q7
Q7
Q6
Q5
VCC
MC10EP142, MC100EP142
24
23
22
21
20
19
18
17
PIN DESCRIPTION
25
16
PIN
FUNCTION
D6
VEE
D0* - D8*
ECL Parallel Data Inputs
D5
26
15
Q4
S-IN*, S-IN**
ECL Differential Serial Data Input
D4
27
14
Q3
SEL*
ECL Mode Select Input
13
VCC
CLK0*, CLK1*,
CLK0**, CLK1**
ECL Differential Clock Inputs
12
Q2
MR*
ECL Master Reset
Q0 - Q8
ECL Data Outputs
Q7
ECL Data Output
VCC
Positive Supply
VEE
28
D3
29
D2
30
11
Q1
D1
31
10
Q0
VCC
32
9
MR
7
8
SEL
6
CLK1
5
CLK1
4
CLK0
3
CLK0
2
S-IN
D0
1
S-IN
MC10EP142
MC100EP142
VEE
Negative Supply
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
Warning: All VCC and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
TRUTH TABLE
Function*
SEL
S-IN
MR
CLK0
CLK1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Load
L
X
L
Z
Z
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Shift
H
L
L
Z
Z
L
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
H
H
L
Z
Z
H
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
X
X
H
Z
Z
L
L
L
L
L
L
L
L
L
L
Reset
* All functions are accomplished on the positive edge of CLK0 or CLK1.
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235
MC10EP142, MC100EP142
S-IN
S-IN
1
D0
0
Q
Q0
1
0
D
Q
Q1
D1
1
0
D
Q
Q2
D2
D3
1
0
D
Q
Q3
1
0
D
Q
Q4
D4
D5
1
0
D
Q
Q5
D
Q
Q6
D
Q
Q7
Q
Q7
Q
Q8
1
D8
D
D6
0
D7
1
0
1
0
D
SEL
MR
CLK0
VCC
CLK0
VEE
CLK1
CLK1
Figure 2. Logic Diagram
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236
MC10EP142, MC100EP142
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
37.5 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity (Note 1)
Level 2
Flammability Rating
Oxygen Index: 28 to 34
UL-94 V-0 @ 0.125 in
Transistor Count
405 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
-8
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
265
°C
VI VCC
VI VEE
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
105
125
145
105
125
145
105
125
145
mA
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single-Ended)
1365
1690
1460
1755
1490
1815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
CLK0, CLK1, D, S-IN
CLK0, CLK1, D, S-IN
150
150
µA
0.5
-150
0.5
-150
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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237
MC10EP142, MC100EP142
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 7)
105
125
145
105
125
145
105
125
145
mA
VOH
Output HIGH Voltage (Note 8)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 8)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 9)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
CLK0, CLK1, D, S-IN
CLK0, CLK1, D, S-IN
150
150
µA
0.5
-150
0.5
-150
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
8. All loading with 50 to VCC-2.0 volts.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 10)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 11)
105
125
145
105
125
145
105
125
145
mA
VOH
Output HIGH Voltage (Note 12)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 12)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 13)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
CLK0, CLK1, D, S-IN
CLK0, CLK1, D, S-IN
VEE+2.0
0.0
VEE+2.0
150
0.0
VEE+2.0
150
µA
0.5
-150
0.5
-150
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
10. Input and output parameters vary 1:1 with VCC.
11. Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
12. All loading with 50 to VCC-2.0 volts.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP142, MC100EP142
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 14)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
105
125
145
105
130
150
105
130
150
mA
VOH
Output HIGH Voltage (Note 15)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 15)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 16)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
CLK0, CLK1, D, S-IN
CLK0, CLK1, D, S-IN
150
150
µA
0.5
-150
0.5
-150
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
14. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
15. All loading with 50 to VCC-2.0 volts.
16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 17)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 18)
105
125
145
105
130
150
105
130
150
mA
VOH
Output HIGH Voltage (Note 19)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 19)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
CLK0, CLK1, D, S-IN
CLK0, CLK1, D, S-IN
150
150
µA
0.5
-150
0.5
-150
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
17. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
18. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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239
MC10EP142, MC100EP142
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 21)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 22)
105
125
145
105
130
150
105
130
150
mA
VOH
Output HIGH Voltage (Note 23)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 23)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 24)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
CLK0, CLK1, D, S-IN
CLK0, CLK1, D, S-IN
VEE+2.0
0.0
VEE+2.0
0.0
150
VEE+2.0
150
µA
0.5
-150
0.5
-150
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
21. Input and output parameters vary 1:1 with VCC.
22. Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
23. All loading with 50 to VCC-2.0 volts.
24. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC= 3.0 V to 5.5 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -3.0 V to -5.5 V (Note 25)
-40 °C
Symbol
Characteristic
fSHIFT
Max. Shift Frequency
tPLH
tPHL
Propagation Delay to Output
ts
Setup Time
th
Min
Typ
25°C
Max
Min
Typ
3.0
> 3.4
550
550
675
675
85°C
Max
Min
Typ
Max
GHz
ps
Clk
MR
500
500
625
625
750
750
D
SEL
50
100
-50
50
50
100
D
SEL
100
50
50
-50
100
50
800
800
575
575
700
700
-50
50
50
100
-50
50
50
-50
100
50
50
-50
825
825
ps
Hold Time
tSKEW
Within-Device Skew (Note 26)
Duty Cycle Skew (Note 27)
tJITTER
Cycle-to-Cycle Jitter
(See Figure 3 Fmax/JITTER)
tr
tf
Rise/Fall Times
(20 - 80%)
Unit
ps
Q, Q
110
50
5.0
100
20
50
5.0
100
20
50
5.0
100
20
ps
1
2
1
2
1
2
ps
180
250
190
275
215
300
ps
125
150
25. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
26. Within-device skew is defined as identical transitions on similar paths through a device.
27. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
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240
900
9
800
8
700
7
600
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
200
2
100
1
0
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 3. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices.)
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241
JITTEROUT ps (RMS)
VOUTpp (mV)
MC10EP142, MC100EP142
MC10EP195, MC100EP195
3.3V / 5VECL
Programmable Delay Chip
The MC10/100EP195 is a programmable delay chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 2. The delay increment
of the EP195 has a digitally selectable resolution of about 10 ps and a
range of up to 10.2 ns. The required delay is selected by the 10 data select
inputs D[0:9] which are latched on chip by a high signal on the latch
enable (LEN) control. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in Table 1
and Figure 3.
Because the EP195 is designed using a chain of multiplexers it has a
fixed minimum delay of 2.2 ns. An additional pin D10 is provided for
cascading multiple PDCs for increased programmable range. The cascade
logic allows full control of multiple PDCs.
Select input pins D0- D10 may be threshold controlled by combinations
of interconnects between VEF (pin 7) and VCF (pin 8) for CMOS, ECL, or
TTL level signals. For CMOS input levels, leave VCF and VEF open. For
ECL operation, short VCF and VEF (pins 7 and 8). For TTL level
operation, connect a 1.5 V supply reference to VCF and leave open VEF
pin. The 1.5 V reference voltage to VCF pin can be accomplished by
placing a 1.5 k or 500 resistor between VCF and VEE for 3.3 V or 5.0
V power supplies, respectively.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
•
•
•
•
•
•
•
•
•
•
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MARKING
DIAGRAM*
MCXXX
EP195
LQFP-32
FA SUFFIX
CASE 873A
AWLYYWW
32
1
XXX
A
WL
YY
WW
= 10 OR 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
Maximum Frequency > 2.5 GHz Typical
MC10EP195FA
LQFP-32
250 Units/Tray
Programmable Range: 2.2 ns to 12.2 ns
MC10EP195FAR2
LQFP-32
2000 Tape & Reel
10 ps Increments
MC100EP195FA
LQFP-32
250 Units/Tray
MC100EP195FAR2
LQFP-32
2000 Tape & Reel
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
A Logic High on the EN Pin Will Force Q to Logic Low
D[0:10] Can Accept Either ECL, CMOS, or TTL Inputs
VBB Output Reference Voltage
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 9
242
Publication Order Number:
MC10EP195/D
MC10EP195, MC100EP195
VEE D0 VCC Q
24
23
22
PIN DESCRIPTION
Q VCC VCC NC
21
20
19
18
17
PIN
FUNCTION
IN*, IN*
ECL Signal Input
D1
25
16
EN
EN*
ECL Input Enable
D2
26
15
CASCADE
D[0:10]*
CMOS, ECL, or TTL Select Inputs
D3
27
14
CASCADE
VEE
28
D4
29
D5
Q, Q
ECL Signal Output
LEN*
ECL Latch Enable
13
VCC
SETMIN*†
ECL Minimum Delay Set
12
SETMAX
SETMAX*
ECL Maximum Delay Set
30
11
SETMIN
ECL Cascade Signal
D6
31
10
CASCADE,
CASCADE
LEN
D7
32
9
MC10EP195
MC100EP195
1
D8
2
3
4
5
D9 D10 IN
6
7
VEE
8
IN VBB VEF VCF
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
VBB
VCC
Positive Supply
Output Reference Voltage
VEE
Negative Supply
VCF
CMOS, ECL, or TTL Input Select
VEF
ECL Reference Mode Connection
NC
No Connect
* Pins will default LOW when left open.
† SETMIN will override SETMAX if both are high.
Figure 1. 32-Lead LQFP Pinout (Top View)
TRUTH TABLE
EN
L
Q = IN
EN
H
Q Logic Low
LEN
L
Pass Through D[0:10]
LEN
H
Latch D[0:10]
SETMIN
L
Normal Mode
SETMIN
H
Min Delay Path
SETMAX
L
Normal Mode
SETMAX
H
Max Delay Path
VCF
VEF Pin***
ECL Mode
VCF
No Connect
CMOS Mode
VCF
1.5 V
TTL Mode**
** For TTL Mode, connect appropriate resistor between VCF and VEE pin.
*** Short VCF (pin 8) and VEF (pin 7).
Resistor Value
Power Supply
1.5 k
3.3 V
500 5.0 V
DATA INPUT OPERATING VOLTAGE TABLE
POWER
SUPPLY
(VCC, VEE)
DATA SELECT INPUTS (D [0:10])
CMOS
TTL
PECL
NECL
PECL
N/A
NECL
N/A
N/A
N/A
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243
Q
1
*GD = (GATE DELAY) APPROXIMATELY 10 ps DELAY PER GATE
(MINIMUM FIXED DELAY APPROX. 2.2 ns)
D9
D8
1
512
1
GD*
1
D7
1
D6
1
D5
D4
10 BIT LATCH
1
1
Table 1. THEORETICAL DELAY VALUES
1
D3
D10
CASCADE
CASCADE
D2
1
Latch
1
D0
D10
1
D1
1
VEE
VCF
VEF
SET MIN
SET MAX
VBB
EN
IN
IN
LEN
1
GD*
0
2
GD*
0
4
GD*
0
8
GD*
0
16
GD*
0
32
GD*
0
64
GD*
0
128
GD*
0
256
GD*
0
0
1
GD*
0
Q
MC10EP195, MC100EP195
Figure 2. Logic Diagram
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244
D(9:0) Value
Delay Value
Comment
0000000000
0 ps
(SET MIN)
0000000001
10 ps
0000000010
20 ps
0000000011
30 ps
0000000100
40 ps
0000000101
50 ps
0000000110
60 ps
0000000111
70 ps
0000001000
80 ps
0000010000
160 ps
0000100000
320 ps
0001000000
640 ps
0010000000
1280 ps
0100000000
2560 ps
1000000000
5120 ps
1111111111
10230 ps
XXXXXXXXXX
10240 ps
(SET MAX)
MC10EP195, MC100EP195
14000
13000
12000
85 °C
11000
25 °C
VCC = 0 V
VEE = -3.3 V
10000
- 40 °C
DELAY ( ps)
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
0
100
200
300
400
500
600
700
800
Decimal Value of Select Inputs (D[9:0])
Figure 3. Measured Delay vs. Select Inputs
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
Flammability Rating
> 2 kV
> 100 V
> 2 kV
Level 2
Oxygen Index: 28 to 34
Transistor Count
UL 94 V-0 @ 0.125 in
1217 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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245
900
1000
MC10EP195, MC100EP195
MAXIMUM RATINGS (Note 2)
Symbol
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
265
°C
VI ≤ VCC
VI ≥ VEE
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
110
145
175
120
150
180
120
150
180
mA
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
PECL
CMOS
TTL
2090
2415
2155
1815
2000
2480
2215
2540
1365
1690
1430
1755
1485
400
1490
1815
IEE
Power Supply Current
VOH
VIL
Input LOW Voltage (Single-Ended)
PECL
CMOS
TTL
mV
mV
VBB
Output Voltage Reference
1790
1890
1990
1855
1955
2055
1915
2015
2115
mV
VCF
Input Select
1610
1710
1810
1620
1718
1820
1625
1725
1825
mV
VEF
Mode Connection
1920
2020
2120
1980
2080
2180
2030
2130
2230
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
2.0
150
IN
IN
0.5
-150
150
0.5
-150
0.5
-150
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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246
MC10EP195, MC100EP195
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 7)
110
145
175
120
150
180
120
150
180
mA
VOH
Output HIGH Voltage (Note 8)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 8)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
PECL
CMOS
TTL
3790
4115
3855
2750
2000
4180
3915
4240
3065
3390
3130
3455
2250
400
3190
3515
3690
3555
3755
3615
VIL
Input LOW Voltage (Single-Ended)
PECL
CMOS
TTL
mV
mV
VBB
Output Voltage Reference
3490
3590
VCF
Input Select
TBD
mV
VEF
Mode Connection
TBD
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 9)
IIH
Input HIGH Current
IIL
Input LOW Current
2.0
5.0
3655
2.0
5.0
150
IN
IN
3715
2.0
150
0.5
-150
0.5
-150
3815
mV
5.0
V
150
A
A
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) > 3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at ≤ 3.8 V.
8. All loading with 50 to VCC-2.0 volts.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 10)
-40 °C
Symbol
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 11)
110
145
175
120
150
180
120
150
180
mA
VOH
Output HIGH Voltage (Note 12)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 12)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
NECL
-1210
-885
-1 145
-820
-1085
-760
Input LOW Voltage (Single-Ended)
NECL
-1935
-1610
-1870
-1545
-1810
-1485
VBB
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
VCF
Input Select
VEF
Mode Connection
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 13)
IIH
Input HIGH Current
IIL
Input LOW Current
VIL
Characteristic
25°C
mV
mV
-1410
-1345
-1285
-1 185
TBD
mV
TBD
VEE+2.0
0.0
VEE+2.0
150
IN
IN
0.5
-150
mV
0.0
VEE+2.0
150
0.5
-150
mV
0.5
-150
0.0
V
150
A
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
10. Input and output parameters vary 1:1 with VCC.
11. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) > 3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at ≤ 3.8 V.
12. All loading with 50 to VCC-2.0 volts.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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247
MC10EP195, MC100EP195
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 14)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
100
135
160
110
140
170
110
145
175
mA
Output HIGH Voltage (Note 15)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 15)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
2075
2420
2075
1815
2000
2420
2075
2420
1355
1675
1490
1675
1485
400
1490
1675
VIL
Input HIGH Voltage (Single-Ended)
PECL
CMOS
TTL
Input LOW Voltage (Single-Ended)
PECL
CMOS
TTL
mV
mV
VBB
VCF
Output Voltage Reference
1775
1875
1975
1775
1875
1975
1775
1875
1975
mV
Input Select
1610
1720
1825
1610
1720
1825
1610
1720
1825
mV
VEF
VIHCMR
Mode Connection
1900
2000
2100
1900
2000
2100
1900
2000
2100
mV
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
A
Input HIGH Voltage Common Mode
Range (Differential) (Note 16)
Input LOW Current
2.0
150
IN
IN
0.5
-150
150
0.5
-150
A
0.5
-150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
14. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
15. All loading with 50 to VCC-2.0 volts.
16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 17)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current (Note 18)
100
135
160
110
140
170
110
145
175
mA
Output HIGH Voltage (Note 19)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
VIH
Output LOW Voltage (Note 19)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
3775
4120
3775
2750
2000
4120
3775
4120
3790
3375
3190
3375
2250
400
3190
3375
3675
3475
3675
3475
VIL
Input HIGH Voltage (Single-Ended)
PECL
CMOS
TTL
Input LOW Voltage (Single-Ended)
PECL
CMOS
TTL
VBB
VCF
Output Voltage Reference
VEF
VIHCMR
Mode Connection
IIH
IIL
Input HIGH Current
mV
mV
3475
3575
Input Select
3575
3675
TBD
2.0
5.0
2.0
150
IN
IN
0.5
-150
mV
5.0
2.0
150
0.5
-150
mV
mV
TBD
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
Input LOW Current
3575
0.5
-150
5.0
V
150
A
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
17. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
18. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) > 3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at ≤ 3.8 V.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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248
MC10EP195, MC100EP195
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 21)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
100
135
160
110
140
170
110
145
175
mA
IEE
Power Supply Current (Note 22)
VOH
Output HIGH Voltage (Note 23)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 23)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
NECL
-1225
-880
-1225
-880
-1225
-880
Input LOW Voltage (Single-Ended)
NECL
-1945
-1625
-1945
-1625
-1945
-1625
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
VCF
Input Select
TBD
mV
VEF
Mode Connection
TBD
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 24)
IIH
Input HIGH Current
IIL
Input LOW Current
VIL
mV
mV
-1425
VEE+2.0
0.0
VEE+2.0
150
IN
IN
0.5
-150
-1425
0.0
VEE+2.0
150
0.5
-150
-1425
0.5
-150
-1325
mV
0.0
V
150
A
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
21. Input and output parameters vary 1:1 with VCC.
22. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) > 3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at ≤ 3.8 V.
23. All loading with 50 to VCC-2.0 volts.
24. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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249
MC10EP195, MC100EP195
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 25)
-40 °C
Symbol
Characteristic
Min
Typ
Max
fmax
Maximum Frequency
(See Figure 4. Fmax/JITTER)
tPLH
tPHL
Propagation Delay
IN to Q; D(0-10) = 0
IN to Q; D(0-10) = 1023
EN to Q; D(0-10) = 0
D0 to CASCADE
1650
9500
1600
300
2050
11500
2150
420
tRANGE
Programmable Range
tPD (max) - tPD (min)
7850
9450
t
25°C
Min
2.5
Typ
2450
13500
2600
500
1800
10000
1800
350
2200
12200
2300
450
8200
10000
Typ
Max
2.5
Unit
GHz
2600
14000
2800
550
1950
10800
2000
425
2350
13300
2500
525
8850
10950
2750
15800
3000
625
ps
Step Delay (Note 26)
ps
13
27
44
90
130
312
590
1100
2250
4500
14
30
47
97
140
335
650
1180
2400
4800
Linearity
TBD
tSKEW
Duty Cycle Skew (Note 27)
tPHL-t PLH
TBD
tR
Min
2.5
Lin
th
Max
ps
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
ts
85°C
41
100
145
360
690
1300
2650
5300
ps
Setup Time
ps
D to LEN
D to IN (Note 28)
EN to IN (Note 29)
200
300
300
0
140
150
200
300
300
0
160
170
200
300
300
0
180
180
LEN to D
IN to EN (Note 30)
200
400
60
250
200
400
100
280
200
400
80
300
400
350
TBD
250
200
Hold Time
ps
Release Time
ps
EN to IN (Note 31)
SET MAX to LEN
SET MIN to LEN
tjit
Cycle-to-Cycle Jitter
(See Figure 4. Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Time
20-80% (Q)
20-80% (CASCADE)
400
350
200
275
0.2
<1
150
800
1200
100
100
180
180
250
250
400
350
0.2
<1
150
800
1200
150
150
210
210
300
300
300
225
0.2
<1
ps
150
800
1200
mV
175
175
230
230
325
325
ps
25. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
26. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
27. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
28. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
29. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
±75 mV to that IN/IN transition.
30. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than ±75 mV to that IN/IN transition.
31. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
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250
900
9
800
8
700
7
600
6
500
5
400
4
300
3
JITTEROUT ps (RMS)
VOUTpp (mV)
MC10EP195, MC100EP195
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
200
2
(JITTER)
100
1
0
0
1000
2000
FREQUENCY (MHz)
3000
Figure 4. Fmax/Jitter
Cascading Multiple EP195s
To increase the programmable range of the EP195, internal
cascade circuitry has been included. This circuitry allows for the
cascading of multiple EP195s without the need for any external
gating. Furthermore, this capability requires only one more
address line per added E195. Obviously, cascading multiple
programmable delay chips will result in a larger programmable
range: however, this increase is at the expense of a longer
minimum delay.
Figure 5 illustrates the interconnect scheme for cascading two
EP195s. As can be seen, this scheme can easily be expanded for
larger EP195 chains. The D10 input of the EP195 is the cascade
control pin. With the interconnect scheme of Figure 5 when D10
is asserted, it signals the need for a larger programmable range
than is achievable with a single device. The A11 address can be
added to generate a cascade output for the next EP195. For a
2- device configuration, A11 is not required.
Need if Chip #3 is used
ADDRESS BUS
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7
D6
D5
D4
VEE
D3
D2
D7
D1
D6
D5
D4
VEE
D3
D2
D1
D8
VEE
D8
VEE
D9
D0
D9
D0
D10
D10
VCC
EP195
IN
Q
IN
Q
IN
VCC
EP195
Q
INPUT
OUTPUT
NC
EN
CASCADE
VCF
CASCADE
NC
VCC
VCC
VCC
VEF
SETMAX
VCC
CHIP #1
SETMIN
VBB
VEE
CASCADE
CASCADE
VCC
SETMAX
LEN
VEE
VCF
SETMIN
VEF
VCC
EN
CHIP #2
VBB
Q
LEN
IN
Figure 5. Cascading Interconnect Architecture
all of the latches of chip #2 will be reset and the device will be
set at its minimum delay.
Chip #1, on the other hand, will have both SET MIN and
SET MAX deasserted so that its delay will be controlled
entirely by the address bus A0—A9. If the delay needed is
greater than can be achieved with 1023 gate delays
An expansion of the latch section of the block diagram is
pictured in Figure 6. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D10 of
chip #1 in Figure 5 is low the cascade output will also be low
while the cascade bar output will be a logical high. In this
condition the SET MIN pin of chip #2 will be asserted and thus
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251
MC10EP195, MC100EP195
(1111111111 on the A0—A9 address bus) D10 will be asserted
to signal the need to cascade the delay to the next EP195
device. When D10 is asserted, the SET MIN pin of chip #2 will
be deasserted and SET MAX pin asserted resulting in the
device delay to be the maximum delay. Figure 7 shows the
delay time of two EP195 chips in cascade.
To expand this cascading scheme to more devices, one simply
needs to connect the D10 pin from the next chip to the address
bus and CASCADE outputs to the next chip in the same manner
as pictured in Figure 5. The only addition to the logic is the
increase of one line to the address bus for cascade control of the
second programmable delay chip.
TO SELECT MULTIPLEXERS
SET
MIN
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
D8 Q8
D9 Q9
LEN
LEN
LEN
LEN
LEN
LEN
LEN
LEN
LEN
LEN
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
SET
MAX
Figure 6. Expansion of the Latch Section of the EP195 Block Diagram
VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2
INPUT FOR CHIP #1
Total
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Delay Value
Delay Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 ps
4400 ps
1
10 ps
0
0
0
0
0
0
0
0
0
4410 ps
1
0
20 ps
0
0
0
0
0
0
0
0
4420 ps
0
1
1
30 ps
0
0
0
0
0
0
0
4430 ps
0
1
0
0
40 ps
0
0
0
0
0
0
4440 ps
0
0
1
0
1
50 ps
0
0
0
0
0
4450 ps
0
0
0
1
1
0
60 ps
0
0
0
0
4460 ps
0
0
0
0
1
1
1
70 ps
0
0
0
4470 ps
0
0
0
0
1
0
0
0
80 ps
0
0
4480 ps
0
0
0
0
1
0
0
0
0
160 ps
0
4560 ps
0
0
0
0
1
0
0
0
0
0
220 ps
4720 ps
0
0
0
0
1
0
0
0
0
0
0
640 ps
5040 ps
0
0
0
1
0
0
0
0
0
0
0
1280 ps
5680 ps
0
0
1
0
0
0
0
0
0
0
0
2560 ps
6960 ps
0
1
0
0
0
0
0
0
0
0
0
5120 ps
9520 ps
0
1
1
1
1
1
1
1
1
1
1
10230 ps
14630 ps
Delay Value
Delay Value
VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2
INPUT FOR CHIP #1
Total
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
0
0
0
0
0
10240 ps
14640 ps
1
0
0
0
0
0
0
0
0
0
1
10250 ps
14650 ps
1
0
0
0
0
0
0
0
0
1
0
10260 ps
14660 ps
1
0
0
0
0
0
0
0
0
1
1
10270 ps
14670 ps
1
0
0
0
0
0
0
0
1
0
0
10280 ps
14680 ps
1
0
0
0
0
0
0
0
1
0
1
10290 ps
14690 ps
1
0
0
0
0
0
0
0
1
1
0
10300 ps
14700 ps
1
0
0
0
0
0
0
0
1
1
1
10310 ps
14710 ps
1
0
0
0
0
0
0
1
0
0
0
10320 ps
14720 ps
1
0
0
0
0
0
1
0
0
0
0
10400 ps
14800 ps
1
0
0
0
0
1
0
0
0
0
0
10560 ps
14960 ps
1
0
0
0
1
0
0
0
0
0
0
10880 ps
15280 ps
1
0
0
1
0
0
0
0
0
0
0
11520 ps
15920 ps
1
0
1
0
0
0
0
0
0
0
0
12800 ps
17200 ps
1
1
0
0
0
0
0
0
0
0
0
15360 ps
19760 ps
1
1
1
1
1
1
1
1
1
1
1
20470 ps
24870 ps
Figure 7. Delay Value of Two EP195 Cascaded
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252
MC10EP195, MC100EP195
Multi-Channel Deskewing
The most practical application for EP195 is in multiple
channel delay matching. Slight differences in impedance and
cable length can create large timing skews within a high- speed
system. To deskew multiple signal channels, each channel can
be sent through each EP195 as shown in Figure 8. One signal
channel can be used as reference and the other EP195s can be
used to adjust the delay to eliminate the timing skews. Nearly
any high- speed system can be fine- tuned (as small as 10 ps)
to reduce the skew to extremely tight tolerances.
EP195
IN
IN
Q
Q
#1
EP195
IN
IN
Q
Q
#2
EP195
IN
IN
Q
Q
#N
Control
Logic
Digital
Data
Figure 8. Multiple Channel Deskewing Diagram
Measure Unknown High Speed Device Delays
EP195s provide a possible solution to measure the
unknown delay of a device with a high degree of precision.
By combining two EP195s and EP31 as shown in Figure 9,
the delay can be measured. The first EP195 can be set to
SETMIN and its output is used to drive the unknown delay
device, which in turn drives the input of a D flip-flop of
EP31. The second EP195 is triggered along with the first
EP195 and its output provides a clock signal for EP31. The
programmed delay of the second EP195 is varied to detect
the output edge from the unknown delay device.
If the programmed delay through the second EP195 is too
long, the flip- flop output will be at logic high. On the other
hand, if the programmed delay through the second EP195 is
too short, the flip- flop output will be at a logic low. If the
programmed delay is correctly fine- tuned in the second
EP195, the flip- flop will bounce between logic high and logic
low. The digital code in the second EP195 can be directly
correlated into an accurate device delay.
EP195
CLOCK
IN
IN
CLOCK
Q
Q
Unknown Delay
Device
#1
D
Q
EP31
CLK
EP195
IN
IN
Q
Q
#2
Control
Logic
Figure 9. Multiple Channel Deskewing Diagram
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253
Q
MC10EP195, MC100EP195
Q
D
Driver
Device
Receiver
Device
D
Q
50 50 VTT
VTT = VCC - 2.0 V
Figure 10. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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254
MC100EP196
3.3VECL Programmable
Delay Chip with FTUNE
The MC100EP196 is a programmable delay chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides
programmably variable delay of a differential ECL input signal. It has
similar architecture to the EP195 with the added feature of further
tuneability in delay using the FTUNE pin. The FTUNE input takes an
analog voltage from VCC to VEE to fine tune the output delay from 0 to
60 ps.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 2. The delay
increment of the EP196 has a digitally selectable resolution of about
10 ps and a range of up to 10 ns. The required delay is selected by the
10 programmable data select inputs D[0:9] which are latched on chip
by a high signal on the latch enable (LEN) control. Delays are set by
programming values of 0000000000 to 1111111111 on the D0 (LSB)
through D9 (MSB) as shown in Table 1.
Because the EP196 is designed using a chain of multiplexers, it has a
fixed minimum delay of 2.4 ns. An additional pin, D10, is provided for
cascading multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs.
Select input pins, D0- D10, may be threshold controlled by
combinations of interconnects between VEF (pin 7) and VCF (pin 8)
for LVCMOS, ECL, or LVTTL level signals. LVTTL and LVCMOS
operation is available in PECL mode only. For LVCMOS input levels,
leave VCF and VEF open. For ECL operation, short VCF and VEF (pins
7 and 8). For LVTTL level operation, connect a 1.5 V supply reference
to VCF and leave open VEF pin. The 1.5 V reference voltage to VCF pin
can be accomplished by placing a 2.2 k resistor between VCF and
VEE for 3.3 V power supply.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
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MARKING
DIAGRAM*
MC100
EP196
LQFP-32
FA SUFFIX
CASE 873A
AWLYYWW
32
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, refer to Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC100EP196FA
LQFP-32
250 Units/Tray
MC100EP196FAR2
LQFP-32
2000/Tape & Reel
• Maximum Frequency > 1.2 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 3.6 V
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
•
•
•
•
•
with VEE = -3.0 V to -3.6 V
Open Input Default State
Safety Clamp on Inputs
A Logic High on the EN Pin Will Force Q to Logic Low
D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
VBB Output Reference Voltage
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 8
255
Publication Order Number:
MC100EP196/D
MC100EP196
VEE D0 VCC Q
24
23
22
21
20
19
18
17
FUNCTION
IN*, IN*
ECL Signal Input
EN*
ECL Input Enable
15
CASCADE
D[0:10]*
LVCMOS, ECL, or LVTTL Select Inputs
14
CASCADE
25
16
D2
26
D3
27
28
PIN
EN
D1
VEE
PIN DESCRIPTION
Q VCC VCC FTUNE
Q, Q
ECL Signal Output
LEN*
ECL Latch Enable Input
13
VCC
SETMIN*†
ECL Minimum Delay Set Input
D4
29
12
SETMAX
SETMAX*
ECL Maximum Delay Set Input
D5
30
11
SETMIN
ECL Cascade Signal Output
D6
31
10
CASCADE,
CASCADE
LEN
32
9
VBB
VCC
Output Reference Voltage
D7
Positive Supply
VEE
Negative Supply
VCF
LVCMOS, ECL, or LVTTL
Input Select Input
VEF
ECL Reference Mode Connection
FTUNE*
Fine Tuning Input
MC100EP196
1
D8
2
3
4
5
D9 D10 IN
6
7
VEE
8
IN VBB VEF VCF
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
* Pins will default LOW (VEE) when left open.
†SETMIN will override SETMAX if both pins are high.
Figure 1. 32-Lead LQFP Pinout (Top View)
TRUTH TABLE
L*
EN
Q = IN
EN
H
Q Logic Low
LEN
L*
Pass Through D[0:10]
LEN
H
Latch D[0:10]
SETMIN
L*
Normal Mode
SETMIN
H
Min Delay Path
SETMAX
L*
Normal Mode
SETMAX
H
Max Delay Path
VCF
VEF Pin**
ECL Mode
VCF
No Connect
LVCMOS Mode
VCF
1.5 V 100 mV
LVTTL Mode***
*
Internal pulldown will provide logic low if pin left unconnected.
**
Short VCF (pin 8) and VEF (pin 7).
*** For LVTTL Mode, if no external voltage can be provided, the
reference voltage can be provided by connecting the appropriate
resistor between VCF and VEE pins.
Power Supply
Resistor Value
5% (Tolerance)
3.3 V
2.2 k
DATA INPUT OPERATING VOLTAGE TABLE
POWER
SUPPLY
(VCC, VEE)
LVCMOS
LVTTL
PECL
NECL
PECL
N/A
NECL
N/A
N/A
N/A
DATA SELECT INPUTS (D [0:10])
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Q
Table 1. Theoretical Delta Delay Values
1
0
Q
MC100EP196
D7
1
D6
128
GD*
1
D4
10 BIT LATCH
D5
64
GD*
1
32
GD*
1
1
Delay Value
Comment
0000000000
0 ps
(SET MIN)
0000000001
10 ps
0000000010
20 ps
0000000011
30 ps
0000000100
40 ps
0000000101
50 ps
0000000110
60 ps
0000000111
70 ps
1
Latch
D0
D10
D1
CASCADE
D2
CASCADE
8
GD*
1
4
GD*
1
2
GD*
1
VEE
VCF
VEF
SET MIN
SET MAX
VBB
EN
LEN
1
GD*
IN
0000001000
80 ps
0000010000
160 ps
0000100000
320 ps
0001000000
640 ps
0010000000
1280 ps
0100000000
2560 ps
1000000000
5120 ps
1111111111
10230 ps
XXXXXXXXXX
10240 ps
(SET MAX)
Table 2. Typical FTUNE Delay Pin
D3
16
GD*
(FIXED MINIMUM DELAY APPROX. 2.4 ns)
*GD = (GATE DELAY) APPROXIMATELY 10 ps DELAY PER GATE
D9
D8
1
256
GD*
0
0
0
0
0
0
0
0
0
IN
FTUNE
D(9:0) Value
1
D10
512
1
GD*
0
1
GD*
(does not include fixed minimum delay)
Figure 2. Logic Diagram
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Input Range
Output Range
VCC-V EE (V)
0 - 60 (ps)
MC100EP196
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
Flammability Rating
> 2 kV
> 100 V
> 2 kV
Level 2
Oxygen Index: 28 to 34
Transistor Count
UL 94 V-0 @ 0.125 in″
1237 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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MC100EP196
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
VI ≤ VCC
VI ≥ VEE
2. Maximum Ratings are those values beyond which device damage may occur.
DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
100
125
160
110
130
170
110
135
175
mA
VOH
Output HIGH Voltage (Note 4)
2155
2300
2405
2155
2300
2405
2155
2300
2405
mV
VOL
Output LOW Voltage (Note 4)
1355
1520
1605
1355
1500
1605
1355
1485
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
PECL
LVCMOS
LVTTL
2075
2000
2000
2420
3300
3300
2075
2000
2000
2420
3300
3300
2075
2000
2000
2420
3300
3300
Input LOW Voltage (Single-Ended)
PECL
LVCMOS
LVTTL
1355
0
0
1675
800
800
1355
0
0
1675
800
800
1355
0
0
1675
800
800
VBB
Output Voltage Reference
1775
1875
1975
1775
1875
1975
1775
1875
1975
mV
VCF
LVTTL Mode Input Detect Voltage
@ IVCF = 700 A
1.4
1.5
1.6
1.4
1.5
1.6
1.4
1.5
1.6
V
VEF
Reference Voltage for
ECL Mode Connection
1900
1960
2050
1875
1953
2050
1850
1945
2050
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current (PECL)
IN, IN, EN, LEN, SETMIN, SETMAX
VIL
mV
mV
2.0
A
150
IIHH
FTUNE Input High Current @ VCC
50
IIL
Input LOW Current (PECL)
IN, IN, EN, LEN, SETMIN, SETMAX
0.5
IILL
FTUNE Input LOW Current @VEE
-10
87
150
150
50
84
150
0.5
0
10
-10
150
50
82
150
A
0.5
0
10
-10
A
0
10
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC100EP196
DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.3 V (Note 6)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
100
125
160
110
130
170
110
135
175
mA
VOH
Output HIGH Voltage (Note 7)
-1 145
-1000
-895
-1 145
-1000
-895
-1 145
-1000
-895
mV
VOL
Output LOW Voltage (Note 7)
-1945
-1780
-1695
-1945
-1800
-1695
-1945
-1815
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
NECL
-1225
-880
-1225
-880
-1225
-880
Input LOW Voltage (Single-Ended)
NECL
-1945
-1625
-1945
-1625
-1945
-1625
VBB
Output Voltage Reference
-1525
-1425
-1325
-1525
-1425
-1325
-1525
-1425
-1325
mV
VEF
Reference Voltage for ECL Mode
Connection
-1400
-1340
-1250
-1425
-1347
-1250
-1450
-1355
-1250
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
0
V
IIH
Input HIGH Current
IN, IN, EN, LEN, SETMIN, SETMAX
VIL
mV
mV
VEE+2.0
VEE+2.0
0
VEE+2.0
A
150
IIHH
FTUNE Input High Current @ VCC
50
IIL
Input LOW Current
IN, IN, EN, LEN, SETMIN, SETMAX
0.5
FTUNE Input LOW Current @ VEE
-10
IILL
0
87
150
150
50
84
150
150
50
82
150
A
A
0.5
0
10
-10
0.5
0
10
-10
0
10
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V.
7. All loading with 50 to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC100EP196
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 9)
-40 °C
Symbol
Min
Characteristic
25°C
Typ
Max
Min
Max
Min
1.2
Typ
Max
fmax
Maximum Frequency
tPLH
tPHL
Propagation Delay
IN to Q; D(0-9) = 0
IN to Q; D(0-9) = 1023
EN to Q; D(0-9) = 0
D10 to CASCADE
1810
9500
1780
350
2210
11496
2277
450
2610
13500
2780
550
1960
10000
1930
380
2360
12258
2430
477
2760
14000
2930
580
2180
10955
2150
420
2580
13454
2650
520
2980
15955
3150
620
tRANGE
Programmable Range
{D(0-9) = HI} - {D(0-9) = LO}
8600
9285
10000
9200
9897
10700
9900
10875
12000
90
245
530
1060
2160
4335
7
23
39
58
137
293
590
1158
2317
4647
100
260
560
1130
2290
4590
11
30
48
67
149
313
629
1237
2472
4955
90
270
600
1200
2450
4935
13
32
53
73
154
337
681
1353
2712
5440
t
1.2
Typ
85°C
1.2
ps
ps
ps
185
335
650
1265
2490
5010
200
370
710
1355
2680
5385
Mono
Monotonicity (Note 11)
9
10
11
tSKEW
Duty Cycle Skew (Note 12)
|tPHL-t PLH|
20
22
27
th
tR
GHz
Step Delay (Note 10)
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
ts
Unit
225
410
770
1520
3015
6015
ps
ps
Setup Time
ps
D to LEN
D to IN (Note 13)
EN to IN (Note 14)
150
100
150
-10
-130
-105
150
100
150
-70
-150
-120
150
100
150
-70
-165
-140
LEN to D
IN to EN (Note 15)
225
450
170
275
200
450
70
305
200
450
60
325
EN to IN (Note 16)
SET MAX to LEN
SET MIN to LEN
150
400
300
-105
70
165
150
400
350
-120
110
180
150
400
350
-140
160
205
Hold Time
ps
Release Time
ps
tjit
Random Clock Jitter
@ 1.2 GHz, SETMAX Delay
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Time
20-80% (Q)
20-80% (CASCADE)
3
3
3
ps
150
800
1200
150
800
1200
150
800
1200
85
100
110
150
130
200
95
110
120
160
145
210
110
125
135
175
160
225
mV
ps
9. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
10. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
11. The monotonicity indicates the increased delay value for each binary count increment on the control inputs D(0-9).
12. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
13. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
14. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
VCC - 1425 mV to that IN/IN transition.
15. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than VCC - 1425 mV to that IN/IN transition.
16. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
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MC100EP196
Using the FTUNE Analog Input
The analog FTUNE pin on the EP196 device is intended to
add more delay in a tunable gate to enhance the 10 ps resolution
capabilities of the fully digital EP196. The level of resolution
obtained is dependent on the voltage applied to the FTUNE pin.
To provide this further level of resolution, the FTUNE pin
must be capable of adjusting the additional delay finer than the
10 ps digital resolution (See Logic Diagram). This requirement
is easily achieved because a 60 ps additional delay can be
obtained over the entire FTUNE voltage range (See Figure 3).
This extra analog range ensures that the FTUNE pin will be
capable even under worst case conditions of covering a digital
resolution. Typically, the analog input will be driven by an
external DAC to provide a digital control with very fine analog
output steps. The final resolution of the device will be dependent
on the width of the DAC chosen.
To determine the voltage range necessary for the FTUNE
input, Figure 3 should be used. There are numerous voltage
ranges which can be used to cover a given delay range; users are
given the flexibility to determine which one best fits their
designs.
90
80
VCC = 0 V
VEE = -3.3 V
25°C
70
-40 °C
DELAY (ps)
60
50
40
30
20
85°C
10
0
-10
-3.3 -2.97 -2.64 -2.31
VEE
-1.98 -1.65 -1.32 -0.99
-0.66 -0.33
FTUNE VOLTAGE (V)
Figure 3. Typical EP196 Delay versus FTUNE Voltage
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0
VCC
MC100EP196
Cascading Multiple EP196s
To increase the programmable range of the EP196,
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP196s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E196.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range; however, this
increase is at the expense of a longer minimum delay.
Figure 4 illustrates the interconnect scheme for cascading
two EP196s. As can be seen, this scheme can easily be
expanded for larger EP196 chains. The D10 input of the
EP196 is the cascade control pin. With the interconnect
scheme of Figure 4 when D10 is asserted, it signals the need
for a larger programmable range than is achievable with a
single device. The A11 address can be added to generate a
cascade output for the next EP196. For a 2-device
configuration, A11 is not required.
ADDRESS BUS
Need if Chip #3 is used
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7
D6
D5
D4
VEE
D3
D2
D6
D5
D4
VEE
D3
D2
D1
VEE
D8
VEE
D9
D0
D9
D0
D10
D10
VCC
EP196
IN
VCC
EP196
Q
IN
Q
IN
Q
OUTPUT
IN
CHIP #2
Q
CHIP #1
FTUNE
EN
CASCADE
EN
LEN
VEE
CASCADE
VCF
VCC
FTUNE
VCF
SETMAX
VCC
SETMIN
VEF
LEN
VCC
VEE
VEF
CASCADE
VCC
CASCADE
VBB
VCC
VCC
SETMAX
VBB
SETMIN
INPUT
D7
D1
D8
DAC
Figure 4. Cascading Interconnect Architecture
chip #2 will be deasserted and the SETMAX pin asserted,
resulting in the device delay to be the maximum delay.
Figure 6 shows the delay time of two EP196 chips in
cascade.
To expand this cascading scheme to more devices, one
simply needs to connect the D10 pin from the next chip to
the address bus and CASCADE outputs to the next chip in
the same manner as pictured in Figure 4. The only addition
to the logic is the increase of one line to the address bus for
cascade control of the second programmable delay chip.
Furthermore, to fully utilize EP196, the FTUNE pin can
be used for additional delay and for finer resolution than 10
ps. As shown in Figure 3, an analog voltage input from DAC
can adjust the FTUNE pin with an extra 60 ps of delay for
each chip.
An expansion of the latch section of the block diagram is
pictured in Figure 5. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D10
of chip #1 in Figure 4 is low, the cascade output will also be
low while the cascade bar output will be a logical high. In
this condition, the SETMIN pin of chip #2 will be asserted
and thus all of the latches of chip #2 will be reset and the
device will be set at its minimum delay.
Chip #1, on the other hand, will have both SETMIN and
SETMAX deasserted so that its delay will be controlled
entirely by the address bus A0-A9. If the delay needed is
greater than can be achieved with 1023 gate delays
(1111111111 on the A0-A9 address bus), D10 will be
asserted to signal the need to cascade the delay to the next
EP196 device. When D10 is asserted, the SETMIN pin of
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MC100EP196
TO SELECT MULTIPLEXERS
SET
MIN
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
D8 Q8
D9 Q9
LEN
LEN
LEN
LEN
LEN
LEN
LEN
LEN
LEN
LEN
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
SET
MAX
Figure 5. Expansion of the Latch Section of the EP196 Block Diagram
VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2
INPUT FOR CHIP #1
Total
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Delay Value
Delay Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 ps
4400 ps
1
10 ps
0
0
0
0
0
0
0
0
0
4410 ps
1
0
20 ps
0
0
0
0
0
0
0
0
4420 ps
0
1
1
30 ps
0
0
0
0
0
0
0
4430 ps
0
1
0
0
40 ps
0
0
0
0
0
0
4440 ps
0
0
1
0
1
50 ps
0
0
0
0
0
4450 ps
0
0
0
1
1
0
60 ps
0
0
0
0
4460 ps
0
0
0
0
1
1
1
70 ps
0
0
0
4470 ps
0
0
0
0
1
0
0
0
80 ps
0
0
4480 ps
0
0
0
0
1
0
0
0
0
160 ps
0
4560 ps
0
0
0
0
1
0
0
0
0
0
320 ps
4720 ps
0
0
0
0
1
0
0
0
0
0
0
640 ps
5040 ps
0
0
0
1
0
0
0
0
0
0
0
1280 ps
5680 ps
0
0
1
0
0
0
0
0
0
0
0
2560 ps
6960 ps
0
1
0
0
0
0
0
0
0
0
0
5120 ps
9520 ps
0
1
1
1
1
1
1
1
1
1
1
10230 ps
14630 ps
Delay Value
Delay Value
VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2
INPUT FOR CHIP #1
Total
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
0
0
0
0
0
10240 ps
14640 ps
1
0
0
0
0
0
0
0
0
0
1
10250 ps
14650 ps
1
0
0
0
0
0
0
0
0
1
0
10260 ps
14660 ps
1
0
0
0
0
0
0
0
0
1
1
10270 ps
14670 ps
1
0
0
0
0
0
0
0
1
0
0
10280 ps
14680 ps
1
0
0
0
0
0
0
0
1
0
1
10290 ps
14690 ps
1
0
0
0
0
0
0
0
1
1
0
10300 ps
14700 ps
1
0
0
0
0
0
0
0
1
1
1
10310 ps
14710 ps
1
0
0
0
0
0
0
1
0
0
0
10320 ps
14720 ps
1
0
0
0
0
0
1
0
0
0
0
10400 ps
14800 ps
1
0
0
0
0
1
0
0
0
0
0
10560 ps
14960 ps
1
0
0
0
1
0
0
0
0
0
0
10880 ps
15280 ps
1
0
0
1
0
0
0
0
0
0
0
11520 ps
15920 ps
1
0
1
0
0
0
0
0
0
0
0
12800 ps
17200 ps
1
1
0
0
0
0
0
0
0
0
0
15360 ps
19760 ps
1
1
1
1
1
1
1
1
1
1
1
20470 ps
24870 ps
Figure 6. Cascaded Delay Value of Two EP196s
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MC100EP196
Multi-Channel Deskewing
The most practical application for EP196 is in multiple
channel delay matching. Slight differences in impedance
and cable length can create large timing skews within a
high-speed system. To deskew multiple signal channels,
each channel can be sent through each EP196 as shown in
Figure 7. One signal channel can be used as reference and the
other EP196s can be used to adjust the delay to eliminate the
timing skews. Nearly any high-speed system can be fine
tuned (as small as 10 ps) to reduce the skew to extremely
tight tolerances using the available FTUNE pin.
EP196
IN
IN
Q
Q
#1
EP196
IN
IN
Q
Q
#2
EP196
IN
IN
Q
Q
#N
Control
Logic
Digital
Data
DAC
Figure 7. Multiple Channel Deskewing Diagram
Q
D
Driver
Device
Receiver
Device
D
Q
50 50 VTT
VTT = VCC - 2.0 V
Figure 8. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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MC10EP445, MC100EP445
3.3V/5VECL 8−Bit
Serial/Parallel Converter
The MC10/100EP445 is an integrated 8–bit differential serial to
parallel data converter with asynchronous data synchronization. The
device has two modes of operation. CKSEL HIGH mode is designed
to operate NRZ data rates of up to 3.3 Gb/s, while CKSEL LOW mode
is designed to operate at twice the internal clock data rate of up to
5.0 Gb/s. The conversion sequence was chosen to convert the first
serial bit to Q0, the second bit to Q1, etc. Two selectable differential
serial inputs, which are selected by SINSEL, provide this device with
loop-back testing capability. The MC10/100EP445 has a SYNC pin
which, when held high for at least two consecutive clock cycles, will
swallow one bit of data shifting the start of the conversion data from
Dn to Dn+1. Each additional shift requires an additional pulse to be
applied to the SYNC pin.
Control pins are provided to reset and disable internal clock
circuitry. Additionally, VBB pin is provided for single-ended input
condition.
The 100 Series contains temperature compensation.
•
•
•
•
•
•
•
•
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MARKING
DIAGRAM*
LQFP-32
FA SUFFIX
CASE 873A
32
1
XXX
A
WL
YY
WW
300 ps Propagation Delay
5.0 Gb/s Typical Data Rate for CLKSEL LOW Mode
Differential Clock and Serial Inputs
MCXXX
EP445
AWLYYWW
= 10 OR 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
VBB Output for Single-Ended Input Applications
Asynchronous Data Synchronization (SYNC)
Asynchronous Master Reset (RESET)
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
ORDERING INFORMATION
Device
•
• CLK ENABLE Immune to Runt Pulse Generation
 Semiconductor Components Industries, LLC, 2002
November, 2002 - Rev. 7
266
Package
Shipping
MC10EP445FA
LQFP-32
250 Units/Tray
MC10EP445FAR2
LQFP-32
2000/Tape & Reel
MC100EP445FA
LQFP-32
250 Units/Tray
MC100EP445FAR2
LQFP-32
2000/Tape & Reel
Publication Order Number:
MC10EP445/D
VCC
Q2
Q1
VCC
Q0
PCLK
PCLK
VCC
MC10EP445, MC100EP445
PIN DESCRIPTION
24
23
22
21
20
19
18
17
PIN
FUNCTION
SINSEL
25
16
VEE
SINA*, SINA*
ECL Differential Serial Data Input A
SINB
26
15
Q3
SINB*, SINB*
ECL Differential Serial Data Input B
SINSEL*
ECL Serial Input Selector Pin
SINB
27
VEE
28
VBB0
29
MC10EP445
MC100EP445
14
Q4
Q0-Q7
ECL Parallel Data Outputs
13
VCC
CLK*, CLK*
ECL Differential Clock Inputs
12
VCC
PCLK, PCLK
ECL Differential Parallel Clock Output
SYNC*
ECL Conversion Synchronizing Input
CKSEL*
ECL Clock Input Selector Pin
CKEN*
ECL Clock Enable Pin
RESET*
ECL Reset Pin
VBB0, VBB1
VCC
Output Reference Voltage
VEE
Negative Supply
SINA
30
11
Q5
SINA
31
10
Q6
VCC
32
9
Q7
7
8
VCC
CKSEL
6
VBB1
5
CLK
4
CLK
3
CKEN
2
SYNC
RESET
1
Positive Supply
* Pins will default logic LOW or differential logic LOW
when left open.
Warning: All VCC and VEE pins must be externally
connected to Power Supply to guarantee proper
operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
TRUTH TABLE
FUNCTION
High
PIN
SINSEL
CKSEL
Low
Select SINB Input
Select SINA Input
Q: PCLK = 8:1
CLK: Q = 1:1
Q: PCLK = 8:1
CLK: Q = 1:2
CLK
CLK
Q
Q
CKEN
Synchronously Disable Internal Clock Circuitry
Synchronously Enable Internal
Clock Circuitry
RESET
Asynchronous Master Reset
Synchronous Enable
SYNC
Asynchronously Applied to Swallow a Data Bit
Normal Conversion Process
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MC10EP445, MC100EP445
SINA
VEE
SINA
SINB
1:2
DEMUX
SINB
1:2
DEMUX
1:2
DEMUX
SINSEL
1:2
DEMUX
CKEN
T
C
Q4
Q2
Q6
Q
1:2
DEMUX
R
T
C
Q0
Q
R
1:2
DEMUX
1:2
DEMUX
SYNC
Q1
Q5
Q3
Q7
Control
Logic
DIV2
CLK
PCLK
DIV2
PCLK
CLK
CKSEL
RESET
Figure 2. Logic Diagram
ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
75 k
Internal Input Pull-up Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
Flammability Rating
Value
> 2 kV
> 200 V
> 2 kV
Level 2
Oxygen Index: 28 to 34
Transistor Count
UL 94 V-0 @ 0.125 in
993 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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MC10EP445, MC100EP445
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
VI VCC
VI VEE
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
95
119
143
98
122
146
100
125
150
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single-Ended)
1365
1690
1460
1755
1490
1815
mV
VBB
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
1890
2.0
150
0.5
1955
150
0.5
0.5
2015
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC - 2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP445, MC100EP445
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 7)
95
119
143
98
122
146
100
125
150
mA
VOH
Output HIGH Voltage (Note 8)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 8)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 9)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
3590
2.0
3655
150
3715
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
8. All loading with 50 to VCC-2.0 volts.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 10)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 11)
95
119
143
98
122
146
100
125
150
mA
VOH
Output HIGH Voltage (Note 12)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 12)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VBB
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
-1 185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 13)
0.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
-1410
VEE+2.0
0.0
VEE+2.0
150
0.5
-1345
0.0
VEE+2.0
150
0.5
-1285
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
10. Input and output parameters vary 1:1 with VCC.
11. Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
12. All loading with 50 to VCC-2.0 volts.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP445, MC100EP445
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 14)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
95
119
143
98
122
146
100
125
150
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 15)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 15)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 16)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
1875
2.0
1875
150
0.5
1875
150
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
14. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
15. All loading with 50 to VCC-2.0 volts.
16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 17)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 18)
95
119
143
98
122
146
100
125
150
mA
VOH
Output HIGH Voltage (Note 19)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 19)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
3575
2.0
150
0.5
3575
150
0.5
0.5
3575
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
17. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
18. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP445, MC100EP445
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 21)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 22)
95
119
143
98
122
146
100
125
150
mA
VOH
Output HIGH Voltage (Note 23)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 23)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 24)
0.0
V
IIH
Input HIGH Current
150
A
-1425
VEE + 2.0
0.0
-1425
VEE + 2.0
150
0.0
-1425
VEE + 2.0
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
21. Input and output parameters vary 1:1 with VCC.
22. Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) > 3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
23. All loading with 50 to VCC - 2.0 volts.
24. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 25)
-40 °C
Symbol
Min
Typ
CKSEL = LOW
CKSEL = HIGH
2.0
2.8
2.5
3.3
CLK to Q
CLK TO PCLK
1230
1000
1450
1240
Characteristic
25°C
Max
Min
Typ
2.0
2.8
2.5
3.3
1300
1050
1530
1310
85°C
Max
Min
Typ
1.7
2.8
2.2
3.3
1400
1140
1650
1420
Max
Unit
fmax
Maximum Input CLK Frequency
(See Figure 12. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
ts
Setup Time
SINA, B+ TO CLK+ (Figure 4)
CKEN+ TO CLK- (Figure 5)
-300
100
-400
50
-300
100
-400
50
-300
100
-400
50
ps
th
Hold Time
CLK+ TO SINA, B- (Figure 4)
CLK- TO CKEN (Figure 5)
650
45
550
-35
675
45
575
-35
725
45
625
-35
ps
tRR/tRR2
Reset Recovery (Figure 3)
350
180
350
180
350
180
ps
tPW
Minimum Pulse Width
tJITTER
Cycle-to-Cycle Jitter
(See Figure 12. Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
(Note 26)
tr
tf
Output Rise/Fall Times
(20% - 80%)
RESET
400
PCLK
Q
1660
1490
1760
1580
400
0.2
<1
150
800
1200
100
180
250
272
1900
1710
400
0.2
<1
150
800
1200
100
200
300
25. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC - 2.0 V.
26. VPP(min) is the minimum input swing for which AC parameters are guaranteed.
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GHz
ps
ps
0.2
<1
ps
150
800
1200
mV
125
230
325
ps
MC10EP445, MC100EP445
Reset
tRR
CLK
CLK
Figure 3. Reset Recovery
CLK
Data Setup Time
+
ts
Data Hold Time
+
th
Figure 4. Data Setup and Hold Time
CLK
CKEN Setup Time
+
ts
CKEN Hold Time -
+
th
Figure 5. CKEN Setup and Hold Time
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MC10EP445, MC100EP445
APPLICATION INFORMATION
The two selectable serial data paths can be used for
loop-back testing as well as the bit error testing.
Upon power-up, the internal flip-flops will attain a
random state. To synchronize multiple flip–flops in the
device, the Reset (pin 1) must be asserted. The reset pin will
disable the internal clock signal irrespective of the CKEN
state (CKEN disables the internal clock circuitry). The
device will grab the first stream of data after the falling edge
of RESET, followed by the falling edge of CLK, on
second rising edge of CLK in either CKSEL modes. (See
Figure 6)
The MC10/100EP445 is an integrated 1:8 serial to parallel
converter with two modes of operation selected by
CKSEL (Pin 7). CKSEL HIGH mode only latches data on
the rising edge of the input CLK and CKSEL LOW mode
latches data on both the rising and falling edge of the input
CLK. CKSEL LOW is the open default state. Either of the
two differential input serial data path provided for this
device, SINA and SINB, can be chosen with the SINSEL pin
(pin 25). SINA is the default input path when SINSEL pin
is left floating. Because of internal pull-downs on the input
pins, all input pins will default to logic low when left open.
RESET
(Asynchronous Reset)
RESET
(Synchronous ENABLE)
CLK
RESET
PCLK
Figure 6. Reset Timing Diagram
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MC10EP445, MC100EP445
For CKSEL LOW operation, the data is latched on both
the rising edge and the falling edge of the clock and the time
from when the serial data is latched to when the data is seen
on the parallel output is 6 clock cycles (see Figure 7).
Number of Clock Cycles from Data Latch to Q
1
2
3
4
5
6
CLK
SINA
D0
D1 D2 D3
D4 D5
D6
D7 D8
D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
RESET
CKEN
CKSEL
PCLK
Q0
D0
D8
D16
Q1
D1
D9
D17
Q2
D2
D10
D18
Q3
D3
D11
D19
Q4
D4
D12
D20
Q5
D5
D13
D21
Q6
D6
D14
D22
Q7
D7
D15
D23
Figure 7. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL LOW
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MC10EP445, MC100EP445
Similarly, for CKSEL HIGH operation, the data is latched
only on the rising edge of the clock and the time from when
the serial data is latched to when the data is seen on the
parallel output is 12 clock cycles (see Figure 8).
Number of Clock Cycles from Data Latch to Q
2
3
4
5
6
7
8
9
10
1
11
12
CLK
SINA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
RESET
CKEN
CKSEL
PCLK
Q0
D0
Q1
D1
Q2
D2
Q3
D3
Q4
D4
Q5
D5
Q6
D6
Q7
D7
Figure 8. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL HIGH
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MC10EP445, MC100EP445
clock cycles shifts the start bit for conversion from Qn to
Qn- 1. The bit is swallowed following the two clock cycle
pulse width of SYNC on the next triggering edge of
clock (either on the rising or the falling edge of the clock).
Each additional shift requires an additional pulse to be
applied to the SYNC pin. (See Figure 9)
To allow the user to synchronize the output byte data
correctly, the start bit for conversion can be moved using the
SYNC input pin (pin 2). Asynchronously asserting the
SYNC pin will force the internal clock to swallow a clock
pulse, effectively shifting a bit from the Qn to the Qn- 1 output
as shown in Figure 9 and Figure 10. For CKSEL LOW, a
single pulse applied asynchronously for two consecutive
2 Clock Cycles for SYNC
1
2
Next Triggering Edge of Clock
Bit D8 is Swallowed
CLK
SINA
D0
D1 D2 D3
D4 D5 D6
D7 D8
D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
CKSEL
PCLK
SYNC
Q0
D0
D9
D17
Q1
D1
D10
D18
Q2
D2
D11
D19
Q3
D3
D12
D20
Q4
D4
D13
D21
Q5
D5
D14
D22
Q6
D6
D15
D23
Q7
D7
D16
D24
Figure 9. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL LOW
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MC10EP445, MC100EP445
triggering edge of clock (on the rising edge of the clock
only). Each additional shift requires an additional pulse to be
applied to the SYNC pin. (See Figure 10)
For CKSEL HIGH, a single pulse applied asynchronously
for three consecutive clock cycles shifts the start bit for
conversion from Qn to Qn- 1. The bit is swallowed following
the three clock cycle pulse width of SYNC on the next
3 Clock Cycles for Sync
1
2
3
Next Triggering Edge of Clock
Bit D8 is Swallowed
CLK
SINA
SYNC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
PCLK
Q0
D0
Q1
D1
Q2
D2
Q3
D3
Q4
D4
Q5
D5
Q6
D6
Q7
D7
Figure 10. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL HIGH
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MC10EP445, MC100EP445
edge of CLK will suspend all activities. The first data bit will
clock on the rising edge, since the falling edge of CKEN
followed by the falling edge of the incoming clock triggers
the enabling of the internal process. (See Figure 11)
The synchronous CKEN (pin 3) applied with at least one
clock cycle pulse length will disable the internal clock
signal. The synchronous CKEN will suspend all of the
device activities and prevent runt pulses from being
generated. The rising edge of CKEN followed by the falling
Internal Clock
Disabled
Internal Clock
Enabled
CLK
CKEN
PCLK
CKSEL
Figure 11. Timing Diagram with CKEN with CKSEL HIGH
conditions, the unused differential input is connected to
VBB as a switching reference voltage. VBB may also rebias
AC coupled inputs. When used, decouple VBB and VCC via
a 0.01 F capacitor, which will limit the current sourcing or
sinking to 0.5mA. When not used, VBB should be left open.
Also, both outputs of the differential pair must be terminated
(50 to VTT = VCC – 2 V) even if only one output is used.
The differential PCLK output (pins 22 and 23) is a word
framer and can help the user to synchronize the parallel data
outputs. During CKSEL LOW operation, the PCLK will
provide a divide by 4-clock frequency, which frames the
serial data in period of PCLK output. Likewise during
CKSEL HIGH operation, the PCLK will provide a divide by
8-clock frequency.
The VBB pin, an internally generated voltage supply, is
available to this device only. For single–ended input
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MC10EP445, MC100EP445
VOUTpp (mV)
CKSEL HIGH
10
900
9
800
8
700
7
CKSEL LOW
600
6
500
5
400
300
200
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
4
3
2
(JITTER)
100
0
JITTEROUT ps (RMS)
1000
1
0
500
1000
1500
2000
2500
3000
3500
INPUT CLK FREQUENCY (MHz)
Figure 12. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 13. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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MC10EP446, MC100EP446
3.3V/5V 8−Bit
CMOS/ECL/TTL Data Input
Parallel/Serial Converter
The MC10/100EP446 is an integrated 8- bit parallel to serial data
converter. The device is designed with unique circuit topology to
operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence
from parallel data into a serial data stream is from bit D0 to D7. The
parallel input pins D0- D7 are configurable to be threshold controlled by
CMOS, ECL, or TTL level signals. The serial data rate output can be
selected at internal clock data rate or twice the internal clock data rate
using the CKSEL pin.
Control pins are provided to reset (SYNC) and disable internal clock
circuitry (CKEN). In either CKSEL modes, the internal flip-flops are
triggered on the rising edge for CLK and the multiplexers are switched
on the falling edge of CLK, therefore, all associated specification
limits are referenced to the negative edge of the clock input.
Additionally, VBB pin is provided for single-ended input condition.
The 100 Series devices contain temperature compensation network.
•
•
•
•
•
•
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MARKING
DIAGRAM*
MCXXX
EP446
AWLYYWW
LQFP-32
FA SUFFIX
CASE 873A
1
XXX
A
WL
YY
WW
3.2 Gb/s Typical Data Rate Capability
Differential Clock and Serial Outputs
VBB Output for Single-ended Input Applications
Asynchronous Data Reset (SYNC)
PECL Mode Operating Range:
VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State
May, 2002 - Rev. 4
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
•
• Safety Clamp on Inputs
• Parallel Interface Can Support PECL, TTL or CMOS
 Semiconductor Components Industries, LLC, 2002
32
ORDERING INFORMATION
Device
281
Package
Shipping
MC10EP446FA
LQFP-32
250 Units/Tray
MC10EP446FAR2
LQFP-32
2000/Tape & Reel
MC100EP446FA
LQFP-32
250 Units/Tray
MC100EP446FAR2
LQFP-32
2000/Tape & Reel
Publication Order Number:
MC10EP446/D
D1
D2
D3
D4
D5
D6
24
23
22
21
20
19
18
D7
D0
MC10EP446, MC100EP446
17
VCC
25
16
VEE
VCF
26
15
PCLK
VEF
27
14
PCLK
VEE
28
13
VCC
SYNC
29
12
SOUT
SYNC
30
11
SOUT
VBB2
31
10
VCC
VCC
32
9
VCC
1
2
3
4
5
6
7
8
VCC
CKSEL
CLK
CLK
VBB1
CKEN
CKEN
VEE
MC10EP446
MC100EP446
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
PIN DESCRIPTION
PIN
FUNCTION
D0*-D7*
ECL, CMOS, or TTL Parallel Data Input
SOUT, SOUT
ECL Differential Serial Data Output
CLK*, CLK*
ECL Differential Clock Input
PCLK, PCLK
ECL Differential Parallel Clock Output
SYNC*, SYNC**
ECL Conversion Synchronizing Differential Input (Reset)***
CKSEL*
ECL Clock Input Selector
CKEN*, CKEN*
ECL Clock Enable Differential Input
VCF
ECL, CMOS, or TTL Input Selector
VEF
ECL Reference Mode Connection
VBB1, VBB2
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed
by the falling edge of CLK initiates the conversion process synchronously on the next rising edge of CLK.
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MC10EP446, MC100EP446
TRUTH TABLE
FUNCTION
HIGH
PIN
CKSEL
LOW
SOUT: PCLK = 8:1
CLK: SOUT = 1:1
SOUT: PCLK = 8:1
CLK: SOUT = 1:2
CLK
CLK
SOUT
SOUT
CKEN
Synchronously Disables Normal Parallel to Serial
Conversion
Synchronously Enables Normal Parallel to
Serial Conversion
SYNC
Asynchronously Resets Internal Flip-Flops*
Synchronous Enable
*The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by
the falling edge of CLK initiates the conversion process synchronously on the next rising edge of CLK.
INPUT VOLTAGE LEVEL SELECTION TABLE
INPUT FUNCTION
CONNECT TO VCF PIN
ECL Mode
VEF Pin
CMOS Mode
No Connect
TTL Mode*
1.5 V 100 mV
*For TTL Mode, if no external voltage can be provided, the
reference voltage can be provided by connecting the
appropriate resistor between VCF and VEE pins.
Power Supply
Resistor Value
10% (Tolerance)
3.3 V
1.5 k
5.0 V
500 DATA INPUT OPERATING VOLTAGE TABLE
POWER SUPPLY
(VCC,V
VEE)
DATA INPUTS (D [0:7])
CMOS
TTL
PECL
NECL
PECL
N/A
NECL
N/A
N/A
N/A
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MC10EP446, MC100EP446
D0
D
Q
CR
MUX
2:1
D
Q
CR
D4
D
Q
CR
MUX
2:1
D
Q
C R
D2
D
Q
C R
MUX
2:1
D
Q
CR
D6
D
Q
CR
D1
D
MUX
2:1
SOUT
SOUT
Q
CR
MUX
2:1
D
Q
CR
D5
D
Q
CR
MUX
2:1
D
Q
CR
D3
D
Q
CR
MUX
2:1
D
Q
CR
D7
D
Q
CR
÷2
÷2
÷2
CKEN
CKEN
CLK
CLK
D
Q
C R
CKSEL
SYNC
SYNC
VCC
VEE
VBB
VCF
VEF
Figure 2. Logic Diagram
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284
MUX
2:1
Control
Logic
PCLK
PCLK
MC10EP446, MC100EP446
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
> 2 kV
> 100 V
> 2 kV
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
Level 2
Flammability Rating
Oxygen Index
UL 94 V-0 @ 0.125 in
28 to 34
Transistor Count
962 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
265
°C
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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VI ≤ VCC
VI ≥ VEE
MC10EP446, MC100EP446
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
90
110
130
90
110
130
95
115
135
mA
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
CMOS
PECL
TTL
2000
2090
2000
3300
3300
3300
2000
2155
2000
3300
3300
3300
2000
2215
2000
3300
3300
3300
mV
Input LOW Voltage (Single-Ended)
CMOS
PECL
TTL
0
1365
0
800
1690
800
0
1460
0
800
1755
800
0
1490
0
800
1815
800
mV
VBB
Output Voltage Reference
1740
1940
1805
2005
1865
2065
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
Symbol
Characteristic
IEE
Power Supply Current
VOH
VIL
1840
2.0
1905
150
1965
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 ohms to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
90
110
130
90
110
130
95
115
135
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 7)
3865
3950
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
CMOS
PECL
TTL
3500
3790
2000
5000
5000
5000
3500
3855
2000
5000
5000
5000
3500
3915
2000
5000
5000
5000
mV
Input LOW Voltage (Single-Ended)
CMOS
PECL
TTL
0
3065
0
1500
3390
800
0
3130
0
1500
3455
800
0
3190
0
1500
3915
800
mV
VBB
VIHCMR
Output Voltage Reference
3440
3640
3505
3705
3565
3765
mV
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
A
VIL
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
Input LOW Current
3540
2.0
150
0.5
3605
150
0.5
0.5
3665
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 ohms to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP446, MC100EP446
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
90
110
130
90
110
130
95
115
135
mA
Output HIGH Voltage (Note 10)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
VIH
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
VBB
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
Output Voltage Reference
-1560
-1360
-1495
-1295
-1435
-1235
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
IIL
Input HIGH Current
150
A
Input LOW Current
-1460
VEE+2.0
0.0
-1395
VEE+2.0
150
0.5
0.0
-1335
VEE+2.0
150
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 ohms to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
90
110
130
90
110
130
95
115
135
mA
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single-Ended)
CMOS
PECL
TTL
2000
2075
2000
3300
3300
3300
2000
2075
2000
3300
3300
3300
2000
2075
2000
3300
3300
3300
mV
Input LOW Voltage (Single-Ended)
CMOS
PECL
TTL
0
1355
0
800
1675
800
0
1355
0
800
1675
800
0
1355
0
800
1675
800
mV
VBB
VIHCMR
Output Voltage Reference
1725
1925
1725
1925
1725
1925
mV
3.3
2.0
3.3
2.0
3.3
V
IIH
IIL
Input HIGH Current
150
A
Symbol
Characteristic
IEE
VOH
Power Supply Current
VOL
VIH
VIL
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
Input LOW Current
1825
2.0
150
0.5
1825
150
0.5
0.5
1825
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 ohms to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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287
MC10EP446, MC100EP446
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
90
110
130
90
110
130
95
115
135
mA
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
VIH
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
Input HIGH Voltage (Single-Ended)
CMOS
PECL
TTL
3500
3775
2000
5000
5000
5000
3500
3775
2000
5000
5000
5000
3500
3775
2000
5000
5000
5000
mV
Input LOW Voltage (Single-Ended)
CMOS
PECL
TTL
0
3055
0
1500
3375
800
0
3055
0
1500
3375
800
0
3055
0
1500
3375
800
mV
VBB
VIHCMR
Output Voltage Reference
3425
3625
3425
3625
3425
3625
mV
5.0
2.0
5.0
2.0
5.0
V
IIH
IIL
Input HIGH Current
150
A
VIL
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
Input LOW Current
3525
2.0
3525
150
3525
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 ohms to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
90
110
130
90
110
130
95
115
135
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Voltage Reference
-1575
-1375
-1575
-1375
-1575
-1375
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
0.0
V
IIH
Input HIGH Current
150
A
-1475
VEE+2.0
0.0
150
-1475
VEE+2.0
0.0
150
-1475
VEE+2.0
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 ohms to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP446, MC100EP446
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Characteristic
Min
Typ
Maximum Frequency
(See Figure 14. Fmax/JITTER)
CKSEL High
CKSEL Low
3.2
1.6
3.4
1.7
Propagation Delay to Output Differential
CKSEL = 0
CLK TO SOUT,
CLK TO PCLK
650
700
750
800
CLK TO SOUT,
CLK TO PCLK
775
850
875
950
(Figure 3)
(Figure 4)
(Figure 5)
-375
200
70
(Figure 3)
-525
0
75
Symbol
fmax
tPLH,
tPHL
CKSEL = 1
tS
th
tpw
Setup Time
D to CLK+
SYNC- to CLKCKEN+ to CLKHold Time
D to CLK+
SYNC- to CLKCLK- to CKEN-
(Figure 5)
Minimum Pulse Width (Note 23)
Data (D0-D7)
SYNC
CKEN
tJITTER
Cycle-to-Cycle Jitter (PCLK)
(See Figure 14. Fmax/JITTER)
VPP
Input Differential Voltage Swing
(Note 22)
tr
tf
Output Rise/Fall Times
(20% - 80%)
25°C
Max
Min
Typ
3.2
1.6
3.4
1.7
850
900
700
750
800
850
975
1050
825
900
925
1000
-425
140
40
-400
200
70
-575
-550
0
75
45
150
200
145
SOUT
85°C
Max
Min
Typ
3.2
1.6
3.4
1.7
900
950
725
775
850
900
975
1025
ps
1025
1100
875
950
1000
1075
1125
1200
ps
-450
140
40
-450
200
70
-500
140
40
ps
-600
-600
0
75
-650
ps
45
150
200
145
0.2
<1
150
800
1200
50
100
150
0.2
<1
150
800
1200
70
120
170
289
Unit
GHz
45
150
200
145
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
22. VPP(min) is the minimum input swing for which AC parameters are guaranteed.
23. The minimum pulse width is valid only if the setup and hold times are respected.
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Max
ps
0.2
<1
ps
150
800
1200
mV
90
140
190
ps
MC10EP446, MC100EP446
CLK
Data
Valid
Data
Setup Time
ts
th
+ 0 -
Figure 3. Setup and Hold Time for Data
SYNC
CLK
SYNC
ts
CLK
CKEN
tS
CLK
Figure 4. Setup Time for SYNC
th
Figure 5. Setup and Hold Time for CKEN
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290
MC10EP446, MC100EP446
APPLICATION INFORMATION
Note: all pins requiring ECL voltage inputs must have a
50 terminating resistor to VTT (VTT = VCC – 2.0 V).
The CKSEL input (pin 2) is provided to enable the user to
select the serial data rate output between internal clock data
rate or twice the internal clock data rate. For CKSEL LOW
operation, the time from when the parallel data is latched to when the data is seen on the SOUT is on the falling edge
of the 7th clock cycle plus internal propagation delay (See
Figure 6). Note the PCLK switches on the falling edge of
CLK.
The MC10/100EP446 is an integrated 8:1 parallel to serial
converter. An attribute for EP446 is that the parallel inputs
D0–D7 (pins 17 – 24) can be configured to accept either
CMOS, ECL, or TTL level signals by a combination of
interconnects between VEF (pin 27) and VCF (pin 26) pins.
For CMOS input levels, leave VEF and VCF open. For ECL
operation, short VCF and VEF (pins 26 and 27). For TTL
operation, connect a 1.5 V supply reference to VCF and leave
the VEF pin open. The 1.5 V reference voltage to VCF pin can
be accomplished by placing a 1.5 k or 500 between VCF
and VEE for 3.3 V or 5.0 V power supplies, respectively.
Number of Clock Cycles from Data Latch to SOUT
1
2
3
4
5
6
7
CLK
D0
D0-1
D0-2
D0-3
D0-4
D1
D1-1
D1-2
D1-3
D1-4
D2
D2-1
D2-2
D2-3
D2-4
D3
D3-1
D3-2
D3-3
D3-4
D4
D4-1
D4-2
D4-3
D4-4
D5
D5-1
D5-2
D5-3
D5-4
D6
D6-1
D6-2
D6-3
D6-4
D7
D7-1
D7-2
D7-3
D7-4
Data Latched
Data Latched
CKSEL
PCLK
Figure 6. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW
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D6-2
D5-2
D4-2
D3-2
D2-2
D0-2
D1-2
D7-1
D6-1
Data Latched
D5-1
D4-1
D3-1
D2-1
D1-1
SOUT
D0-1
Data Latched
MC10EP446, MC100EP446
Similarly, for CKSEL HIGH operation, the time from
when the parallel data is latched to when the data is seen
on the SOUT is on the rising edge of the 14th clock cycle
plus internal propagation delay (See Figure 7). Furthermore,
the PCLK switches on the rising edge of CLK.
Number of Clock Cycles from Data Latch to SOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
D0
D0-1
D0-2
D0-3
D1
D1-1
D1-2
D1-3
D2
D2-1
D2-2
D2-3
D3
D3-1
D3-2
D3-3
D4
D4-1
D4-2
D4-3
D5
D5-1
D5-2
D5-3
D6
D6-1
D6-2
D6-3
D7
D7-1
D7-2
D7-3
CKSEL
PCLK
Figure 7. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL HIGH
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292
D1-2
D0-2
D7-1
D6-1
D5-1
D4-1
D3-1
D2-1
SOUT
D1-1
Data Latched
Data Latched
D0-1
Data Latched
MC10EP446, MC100EP446
initiates the start of the conversion process on the next rising
edge of CLK (See Figures 8 and 9). As shown in the figures
below, the device will start to latch the parallel input data
after the a falling edge of SYNC , followed by the falling
edge CLK , on the next rising of edge of CLK for
CKSEL LOW
The device also features a differential SYNC input (pins
29 and 30), which asynchronously reset all internal
flip–flops and clock circuitry on the rising edge of SYNC.
The release of SYNC is a synchronous process, which
ensures that no runt serial data bits are generated. The falling
edge of the SYNC followed by a falling edge of CLK
SYNC
(Synchronous ENABLE)
Number of Clock Cycles from Data Latch to SOUT
1
SYNC
(Asynchronous RESET)
SYNC
3
4
5
6
7
D0
D0-1
D0-2
D0-3
D0-4
D1
D1-1
D1-2
D1-3
D1-4
D2
D2-1
D2-2
D2-3
D2-4
D3
D3-1
D3-2
D3-3
D3-4
D4
D4-1
D4-2
D4-3
D4-4
D5
D5-1
D5-2
D5-3
D5-4
D6
D6-1
D6-2
D6-3
D6-4
D7
D7-1
D7-2
D7-3
D7-4
Data Latched
Data Latched
SOUT
CKSEL
PCLK
Figure 8. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW and SYNC
SYNC
CLK
Figure 9. Synchronous Release of SYNC for CKSEL LOW
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D5-2
D4-2
D3-2
D2-2
D1-2
D0-2
D7-1
D6-1
Data Latched
D5-1
D4-1
D0-1
D1-1
D2-1
D3-1
Data Latched
D6-2
CLK
2
MC10EP446, MC100EP446
edge CLK , on the second rising edge of CLK (See
Figures 10 and 11).
For CKSEL HIGH, as shown in the timing diagrams
below, the device will start to latch the parallel input data
after the falling edge of SYNC , followed by the falling
SYNC
(Synchronous ENABLE)
Number of Clock Cycles from Data Latch to SOUT
SYNC
(Asynchronous RESET)
CLK
SYNC
1
2
3
4
5
6
7
8
9
10 11 12 13 14
D0
D0-1
D0-2
D0-3
D0-4
D1
D1-1
D1-2
D1-3
D1-4
D2
D2-1
D2-2
D2-3
D2-4
D3
D3-1
D3-2
D3-3
D3-4
D4
D4-1
D4-2
D4-3
D4-4
D5
D5-1
D5-2
D5-3
D5-4
D6
D6-1
D6-2
D6-3
D6-4
D7
D7-1
D7-2
D7-3
D7-4
Data Latched
SOUT
CKSEL
PCLK
Figure 10. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL HIGH and SYNC
SYNC
CLK
Figure 11. Synchronous Release of SYNC for CKSEL HIGH
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294
D1-2
D0-2
D7-1
D6-1
D5-1
D4-1
D3-1
D2-1
D1-1
Data Latched
D0-1
Data Latched
MC10EP446, MC100EP446
followed by the falling edge of CLK will suspend all
activities. The falling edge of CKEN followed by the falling
edge of CLK will resume all activities (See Figure 12).
The differential synchronous CKEN inputs (pins 6 and 7),
disable the internal clock circuitry. The synchronous CKEN
will suspend all of the device activities and prevent runt
pulses from being generated. The rising edge of CKEN
Internal Clock
Disabled
Internal Clock
Enabled
CLK
CKEN
SOUT
D0-1
D1-1
D2-1
D3-1
D4-1
D5-1
PCLK
CKSEL
Figure 12. Timing Diagram with CKEN with CKSEL HIGH
conditions, the unused differential input is connected to VBB
as a switching reference voltage. VBB may also rebias AC
coupled inputs. When used, decouple VBB and VCC via a
0.01 F capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open. Also, both
outputs of the differential pair must be terminated (50 to
VTT) even if only one output is used.
The differential PCLK output (pins 14 and 15) is a word
framer and can help the user synchronize the serial data
output, SOUT (pins 11 and 12), in their applications.
Furthermore, PCLK can be used as a trigger for input
parallel data (see Figure 13).
An internally generated voltage supply, the VBB pin, is
available to this device only. For single–ended input
CLK
RESET
CLK
SYNC
TRIGGER
EP446
PARALLEL
DATA INPUT
PARALLEL
DATA OUTPUT
Pattern Generator
Data Format Logic
(FPGA, ASIC)
SOUT SERIAL DATA
PCLK
Figure 13. PCLK as Trigger Application
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295
MC10EP446, MC100EP446
800
8
CKSEL High
700
VOUTpp (mV)
600
6
500
5
400
4
JITTEROUT ps (RMS)
7
CKSEL Low
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
300
3
200
2
(JITTER)
100
1
0
0
500
1000
1500
2000
2500
3000
3500
INPUT CLOCK FREQUENCY (MHz)
Figure 14. Fmax/Jitter
Figure 15. SOUT System Jitter Measurement
(Condition: 3.4 GHz input frequency, CKSEL HIGH, BEOFE32 bit pattern on SOUT
D
Q
Driver
Device
Receiver
Device
Q
D
50 Ω
50 Ω
VTT
VTT = VCC - 2.0 V
Figure 16. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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296
MC10EP451, MC100EP451
3.3V / 5VECL 6−Bit
Differential Register with
Master Reset
The MC10/100EP451 is a 6-bit fully differential register with
common clock and Single-Ended Master Reset (MR). It is ideal for
very high frequency applications where a registered data path is
necessary.
All inputs have a 75 k pulldown resistor internally. Differential
inputs have an override clamp. Unused differential register inputs can
be left open and will default LOW. When the differential inputs are
forced to <VEE + 1.2 V, the clamp will override and force the output to
a default state. When in the default state, and since the flip-flop is edge
triggered, the output reaches a determined, but not predicted, valid
state.
The positive transition of CLK (pin 4) will latch the registers.
Master Reset (MR) HIGH will asynchronously reset all registers
forcing Q outputs to go LOW.
The 100 Series contains temperature compensation.
•
•
•
•
•
•
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MARKING
DIAGRAM*
LQFP-32
FA SUFFIX
CASE 873A
xxx
A
WL
YY
WW
Maximum Frequency > 3.0 GHz Typical
Asynchronous Master Reset
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
With VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
With VEE = -3.0 V to -5.5 V
Open Input Default State
•
• Safety Clamp on Inputs
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 5
32
1
450 ps Typical Propagation Delay
20 ps Skew Within Device, 35 ps Skew Device-To-Device
MCxxx
EP451
AWLYYWW
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
297
Package
Shipping
MC10EP451FA
LQFP-32
250 Units/Tray
MC10EP451FAR2
LQFP-32
2000 Tape & Reel
MC100EP451FA
LQFP-32
250 Units/Tray
MC100EP451FAR2
LQFP-32
2000 Tape & Reel
Publication Order Number:
MC10EP451/D
MC10EP451, MC100EP451
D4
D5
D5
Q5 Q5 VEE Q4 Q4
D0
D0
24
23
22
21
20
19
18
25
16
VCC
D3
26
15
Q3
D3
27
14
Q3
VEE
28
13
VCC
MR
29
12
Q2
D2
30
11
Q2
D2
31
10
Q1
D1
32
9
Q1
MC10EP451
MC100EP451
2
3
4
5
6
7
R
D1
D1
D0
D0 CLK CLK VCC Q0
Q
D
Q1
Q1
R
D2
D2
Q
D
Q2
Q2
R
8
D3
D3
D1
Q0
Q0
17
D4
1
Q
D
Q
D
Q3
Q3
Q0
R
Warning: All VCC and VEE pins must be externally connected to Power
Supply to guarantee proper operation.
D4
D4
Figure 1. 32-Lead LQFP Pinout (Top View)
Q
D
Q4
Q4
R
PIN DESCRIPTION
FUNCTION
PIN
D [0:5]*, D [0:5]*
ECL Differential Data Inputs
MR*
ECL Master Reset Input
D5
D5
Q
D
Q5
CLK
CLK
CLK*, CLK*
ECL Differential Clock Inputs
Q [0:5], Q [0:5]
ECL Differential Data Outputs
VCC
Positive Supply
VEE
Negative Supply
R
VEE
MR
* Pins will default LOW when left open.
Figure 2. Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
Flammability Rating
Q5
> 2 kV
> 200 V
> 2 kV
Level 2
Oxygen Index: 28 to 34
Transistor Count
UL 94 V-0 @ 0.125 in
919 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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298
MC10EP451, MC100EP451
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JC
Thermal Resistance (Junction to Case)
std bd
32 LQFP
12 to 17
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
VI VCC
VI VEE
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
80
95
125
80
95
125
80
95
125
mA
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1470
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single-Ended)
1365
1690
1430
1755
1490
1815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
Symbol
Characteristic
IEE
Power Supply Current
VOH
150
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
80
95
125
80
95
125
80
95
125
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3170
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
150
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. All loading with 50 to VCC-2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP451, MC100EP451
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
80
95
125
80
95
125
80
95
125
mA
VOH
Output HIGH Voltage (Note 10)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 10)
-1935
-1810
-1685
-1870
-1745
-1620
-1830
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
Input HIGH Current
150
A
VEE+2.0
0.0
VEE+2.0
150
0.0
VEE+2.0
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC-2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
85
105
135
85
105
135
85
105
135
mA
VOH
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
0.5
150
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
13. All loading with 50 to VCC-2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
85
105
135
85
105
135
85
105
135
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
150
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
16. All loading with 50 to VCC-2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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300
MC10EP451, MC100EP451
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18)
-40 °C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
85
105
135
85
105
135
85
105
135
mA
Output HIGH Voltage (Note 19)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 19)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
0.0
V
IIH
Input HIGH Current
150
A
Symbol
Characteristic
IEE
Power Supply Current
VOH
VEE+2.0
0.0
VEE+2.0
0.0
150
VEE+2.0
150
IIL
Input LOW Current
0.5
0.5
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40 °C
Symbol
Min
Characteristic
Typ
25°C
Max
Min
> 3.0
Typ
85°C
Max
Min
Max
Maximum Frequency
(See Figure 3 Fmax/JITTER) (Note 22)
tPLH,
tPHL
Propagation Delay to
Output Differential
tRR
Reset Recovery
tS
tH
Setup Time
Hold Time
tPW
Minimum Pulse Rate
tSKEW
Within-Device Skew (Note 23)
Device-T o-Device Skew (Note 24)
20
35
40
100
20
35
40
100
20
35
40
100
tJITTER
Cycle-to-Cycle Jitter
(See Figure 3 Fmax/JITTER)
0.2
<1
0.2
<1
0.2
<1
ps
tr
tf
Output Rise/Fall Times
(20% - 80%)
150
150
250
250
160
160
260
260
180
180
280
280
ps
330
430
430
530
MR to CLK
240
D to CLK
CLK to D
80
80
MR
400
Q, Q
100
100
530
630
350
450
450
550
145
250
40
40
80
80
> 3.0
Unit
fmax
CLK to Q, Q
MR to Q, Q
> 3.0
Typ
550
650
390
490
490
590
150
260
160
ps
40
40
80
80
40
40
ps
400
110
110
301
590
690
400
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
22. VOL and VOH specifications not guaranteed for Fmax testing.
23. Skew is measured between outputs under identical transitions and conditions on any one device.
24. Device-T o-Device skew for identical transitions at identical VCC levels.
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GHz
130
130
ps
ps
800
8
700
7
600
6
500
5
400
4
300
3
200
2
100
1
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
JITTEROUT ps (RMS)
VOUTpp (mV)
MC10EP451, MC100EP451
ÉÉ
ÉÉ
0
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 3. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices.)
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302
MC100EP809
3.3V1:9 Differential
HSTL/PECL to HSTL Clock
Driver with LVTTL Clock
Select and Enable
The MC100EP809 is a low skew 1- to- 9 differential clock driver,
designed with clock distribution in mind, accepting two clock sources into
an input multiplexer. The part is designed for use in low voltage
applications which require a large number of outputs to drive precisely
aligned low skew signals to their destination. The two clock inputs are
differential HSTL or PECL and they are selected by the CLK_SEL pin
which is LVTTL. To avoid generation of a runt clock pulse when the
device is enabled/disabled, the Output Enable (OE), which is LVTTL, is
synchronous ensuring the outputs will only be enabled/disabled when they
are already in LOW state (See Figure 8).
The MC100EP809 guarantees low output- to- output skew. The optimal
design, layout, and processing minimize skew within a device and from lot
to lot. The MC100EP809 output structure uses open emitter architecture
and will be terminated with 50 to ground instead of a standard HSTL
configuration (See Figure 6). To ensure the tight skew specification is
realized, both sides of the differential output need to be terminated
identically into 50 even if only one output is being used. If an output pair
is unused, both outputs may be left open (unterminated) without affecting
skew.
Designers can take advantage of the EP809’s performance to
distribute low skew clocks across the backplane of the board. HSTL
clock inputs may be driven single-end by biasing the non-driven pin
in an input pair (see Figure 7).
• 100 ps Typical Device-to- Device Skew
• 15 ps Typical Within Device Skew
• HSTL Compatible Outputs Drive 50 to Ground with no Offset
Voltage
Maximum Frequency > 750 MHz
850 ps Typical Propagation Delay
•
•
• Fully Compatible with Micrel SY89809L
• PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V
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MARKING
DIAGRAM*
MC100
EP809
32-LEAD LQFP
FA SUFFIX
CASE 873A
AWLYYWW
32
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC100EP809FA
LQFP-32
250 Units/Tray
MC100EP809FAR2
LQFP-32
2000/Tape & Reel
with GND = 0 V, VCCO = 1.6 V to 2.0 V
• Open Input Default State
 Semiconductor Components Industries, LLC, 2002
August, 2002 - Rev. 5
303
Publication Order Number:
MC100EP809/D
VCCO
Q3
Q3
Q4
Q4
Q5
Q5
VCCO
MC100EP809
24
23
22
21
20
19
18
17
VCCO
25
16
VCCO
Q2
26
15
Q6
Q2
27
14
Q6
Q1
28
13
Q7
Q1
29
12
Q7
Q0
30
11
Q8
Q0
31
10
Q8
VCCO
32
MC100EP809
4
5
6
HSTL_CLK
HSTL_CLK
CLK_SEL
LVPECL_CLK
LVPECL_CLK
7
8
OE
3
GND
2
VCCI
9
1
VCCO
All VCCI, VCCO, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (VCCI VCCO).
Figure 1. 32-Lead LQFP Pinout (Top View)
PIN DESCRIPTION
FUNCTION TABLE
PIN
FUNCTION
HSTL_CLK*, HSTL_CLK**
LVPECL_CLK*, LVPECL_CLK**
CLK_SEL**
OE**
Q0-Q8, Q0-Q8
VCCI
VCCO
HSTL or LVDS Differential Inputs
LVPECL Differential Inputs
LVCMOS/LVTTL Input CLK Select
LVCMOS/LVTTL Output Enable
HSTL Differential Outputs
Positive Supply_Core (3.0 V - 3.6 V)
Positive Supply_HSTL Outputs
(1.6 V - 2.0 V)
Ground
GND
OE*
CLK_SEL
Q0-Q8
Q0-Q8
L
L
H
H
L
H
L
H
L
L
HSTL_CLK
LVPECL_CLK
H
H
HSTL_CLK
LVPECL_CLK
* The OE (Output Enable) signal is synchronized with the
rising edge of the HSTL_CLK and LVPECL_CLK signal.
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
CLK_SEL
HSTL_CLK
0
9
HSTL_CLK
9
LVPECL_CLK
VCCI
GND
Q0-Q8 (HSTL)
Q0-Q8 (HSTL)
1
LVPECL_CLK
Q
D
OE
Figure 2. Logic Diagram
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304
VCCO
MC100EP809
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
37.5 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity (Note 1)
Level 2
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
478 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
VCCI
Core Power Supply
GND= 0 V
VCCO= 1.8 V
4
V
VCCO
HSTL Output Power Supply
GND= 0 V
VCCI = 3.3 V
4
V
PECL Mode Input Voltage
GND = 0 V
VI ≤ VCCI
6
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
0 to +85
°C
-65 to +150
°C
VI
Tstg
Storage Temperature Range
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
LVPECL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V
0°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
75
95
115
75
95
115
75
95
115
mA
ICC
Core Power Supply Current
VIH
Input HIGH Voltage (Single-Ended)
VCCI1.165
VCCI
-0.88
VCCI1.165
VCCI
-0.88
VCCI1.165
VCCI
-0.88
V
VIL
Input LOW Voltage (Single-Ended)
VCCI1.945
VCCI
-1.6
VCCI1.945
VCCI
-1.6
VCCI1.945
VCCI
-1.6
V
1.2
VCCI
1.2
VCCI
1.2
VCCI
V
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential) (Note 3) (Figure 4)
LVPECL_CLK/LVPECL_CLK
IIH
Input HIGH Current
-150
150
-150
150
-150
150
A
IIL
Input LOW Current
-150
150
-150
150
-150
150
A
NOTE:
100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
3. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal.
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305
MC100EP809
LVTTL/LVCMOS DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Max
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIH
Input HIGH Current
-150
150
-150
150
IIL
Input LOW Current
-300
300
-300
300
NOTE:
2.0
Typ
85°C
2.0
Min
Typ
Max
2.0
0.8
Unit
V
0.8
0.8
V
-150
150
A
-300
300
A
100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
HSTL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
VOH
Output HIGH Voltage (Note 4)
1.0
1.2
1.0
1.2
1.0
1.2
V
VOL
Output LOW Voltage (Note 4)
0.1
0.4
0.1
0.4
0.1
0.4
V
VIH
VIL
Input HIGH Voltage (Figure 5)
VX+0.1
-0.3
-
1.6
1.6
1.6
V
-
-
HSTL Input Crossover Voltage
0.68
-
0.68
-
0.68
-
VX-0.1
0.9
V
VX
VX-0.1
0.9
VX+0.1
-0.3
-
VX-0.1
0.9
VX+0.1
-0.3
-
-
IIH
Input HIGH Current
-150
150
-150
150
-150
150
A
IIL
Input LOW Current
-300
300
-300
300
-300
300
A
0.6
VCCI
-1.2
0.6
VCCI
-1.2
0.6
VCCI
-1.2
V
V
VIHCMR
Input LOW Voltage (Figure 5)
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
HSTL_CLK/HSTL_CLK
NOTE:
V
100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
4. All outputs loaded with 50 to GND (See Figure 6).
5. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal.
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306
MC100EP809
AC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V (Note 6)
0°C
25°C
Min
Typ
fout < 100 MHz
fout < 500 MHz
fout < 750 MHz
600
600
450
850
750
575
tPLH
tPHL
Propagation Delay (Differential)
LVPECL_CLK to Q
HSTL_CLK to Q
680
690
800
830
930
990
tskew
Within-Device Skew (Note 7)
Device-to-Device Skew (Note 8)
15
100
Random Clock Jitter (Figure 3) (RMS)
1.4
Symbol
VOpp
tJITTER
VPP
Characteristic
Differential Output Voltage
(Figure 3)
Max
85°C
Min
Typ
Max
Min
Typ
600
600
450
850
750
575
700
700
820
850
950
1000
50
200
15
100
3.0
1.4
Max
600
600
450
850
750
575
780
790
920
950
1070
1110
ps
ps
50
200
15
100
50
200
ps
ps
3.0
1.4
3.0
ps
Unit
mV
mV
Input Swing (Differential Mode) (Note 10)
(Figure 4)
LVPECL
HSTL
200
200
200
200
200
200
mV
mV
tS
OE Set Up Time (Note 9)
0.5
0.5
0.5
ns
tH
OE Hold Time
0.5
0.5
0.5
ns
tr/tf
Output Rise/Fall Time
(20%-80%)
350
600
350
450
600
350
600
ps
6. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 to Ground
(See Figure 6).
7. Skew is measured between outputs under identical transitions and conditions on any one device.
8. Device-to-Device skew for identical transitions and conditions.
9. OE Set Up Time is defined with respect to the rising edge of the clock. OE High-to-Low transition ensures outputs remain disabled during
the next clock cycle. OE Low-to-High transition enables normal operation of the next input clock (See Figure 8).
10. VPP is the Differential Input Voltage swing required to maintain AC characteristics listed herein.
900
9
800
8
VOPP
7
600
6
500
5
400
4
300
3
tJITTER ps (RMS)
VOPP (mV)
700
RMS JITTER
200
2
100
1
0
0
100
200
300
400
500
600
700
800
900
1000
FREQUENCY (MHz)
Figure 3. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER)
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307
MC100EP809
VCCI
VCCO(HSTL)
VCCI(LVPECL)
VIH(DIFF)
VPP
VIH(DIFF)
VX
VIL(DIFF)
VIHCMR
VIL(DIFF)
GND
VPP
Figure 4. LVPECL Differential Input Levels
GND
Figure 5. HSTL Differential Input Levels
Z = 50 Q
HSTL OUTPUT Q
50 50 GROUND
Figure 6. HSTL Output Termination and AC Test Reference
CLK/CLK
D.C. Bias*
*Must fall within 680 to 900 mV (Preferably (VIH + VIL)/2).
Figure 7. HSTL Single-Ended Input Configuration
CLK
CLK
OE
Q
Q
Figure 8. Output Enable (OE) Timing Diagram
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308
CHAPTER 2
ECLinPS Plus Translator Data Sheets
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309
MC10EPT20, MC100EPT20
3.3VLVTTL/LVCMOS to
Differential LVPECL
Translator
The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL
translator. Because PECL (Positive ECL) levels are used, only +3.3 V
and ground are required. The small outline 8- lead SOIC package and the
single gate of the EPT20 makes it ideal for those applications where
space, performance, and low power are at a premium.
The 100 Series contains temperature compensation.
•
•
•
•
•
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MARKING DIAGRAMS*
8
8
390 ps Typical Propagation Delay
Maximum Frequency > 1 GHz Typical
PNP TTL Inputs for Minimal Loading
Operating Range VCC = 3.0 V to 3.6 V
with GND = 0 V
Q Output will default HIGH with inputs open
8
1
SO-8
D SUFFIX
CASE 751
HPT20
ALYW
1
1
8
8
1
TSSOP-8
DT SUFFIX
CASE 948R
KPT20
ALYW
8
HT20
ALYW
1
KT20
ALYW
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
ORDERING INFORMATION
Package
Shipping
MC10EPT20D
Device
SO-8
98 Units/Rail
MC10EPT20DR2
SO-8
2500 Tape & Reel
MC100EPT20D
SO-8
98 Units/Rail
MC100EPT20DR2
 Semiconductor Components Industries, LLC, 2001
April, 2001 - Rev. 4
310
SO-8
2500 Tape & Reel
MC10EPT20DT
TSSOP-8
100 Units/Rail
MC10EPT20DTR2
TSSOP-8
2500 Tape & Reel
MC100EPT20DT
TSSOP-8
100 Units/Rail
MC100EPT20DTR2
TSSOP-8
2500 Tape & Reel
Publication Order Number:
MC10EPT20/D
MC10EPT20, MC100EPT20
PIN DESCRIPTION
NC
Q
Q
1
8
LVTTL
2
3
7
VCC
D
6
NC
5
GND
PIN
FUNCTION
Q, Q
Differential PECL Outputs
D
LVTTL Input
VCC
Positive Supply
GND
Ground
NC
No Connect
LVPECL
NC
4
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1.5 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
150 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Parameter
Symbol
Condition 1
VCC
Power Supply
GND = 0 V
VI
Input Voltage
GND = 0 V
Iout
Output Current
Continuous
Surge
TA
Condition 2
VI VCC
Rating
Units
6
V
6
V
50
100
mA
mA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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311
MC10EPT20, MC100EPT20
LVTTL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0 V, TA = -40°C to +85°C
Characteristic
Symbol
Min
Typ
Max
Unit
20
µA
IIH
Input HIGH Current (Vin = 2.7 V)
IIHH
Input HIGH Current MAX (Vin = 6.0 V)
100
µA
IIL
Input LOW Current (Vin = 0.5 V)
-0.6
mA
VIK
Input Clamp Voltage (Iin = -18 mA)
-1.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
2.0
V
0.8
V
10EPT PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0 V (Note 3.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
18
23
28
18
23
28
19
24
29
mA
ICC
Power Supply Current HIGH
VOH
Output HIGH Voltage (Note 4.)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
NOTE: 10EPT circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Output parameters vary 1:1 with VCC.
4. All loading with 50 ohms to VCC-2.0 volts.
100EPT PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0 V (Note 5.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
25
30
22
27
32
23
28
33
mA
Output HIGH Voltage (Note 6.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
Output LOW Voltage (Note 6.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
IEE
Power Supply Current
VOH
VOL
NOTE: 100EPT circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Output parameters vary 1:1 with VCC.
6. All loading with 50 ohms to VCC-2.0 volts.
AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V (Note 7.)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Device-to-Device Skew (Note 8.)
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Min
Typ
25°C
Max
Min
>1
Typ
85°C
Max
Min
>1
Typ
Max
>1
Unit
GHz
ps
280
350
430
300
370
150
Q, Q
70
1
<2
100
170
450
312
400
150
80
1
<2
120
180
7. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
8. Skew is measured between outputs under identical transitions.
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320
90
490
170
ps
1
<2
ps
140
190
ps
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉ
ÉÉ
100
1
(JITTER)
0
0
JITTEROUT ps (RMS)
VOUTpp (mV)
MC10EPT20, MC100EPT20
200
400
600
800
1000
1200
1400
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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313
1600
MC100EPT21
3.3VDifferential LVPECL to
LVTTL Translator
The MC100EPT21 is a Differential LVPECL to LVTTL translator.
Because LVPECL (Positive ECL) levels are used only +3.3 V and
ground are required. The small outline 8-lead SOIC package makes
the EPT21 ideal for applications which require the translation of a
clock or data signal.
The VBB output allows this EPT21 to be cap coupled in either
single-ended or differential input mode. When single-ended cap
coupled, VBB output is tied to the D input and D is driven for a
non-inverting buffer, or VBB output is tied to the D input and D is
driven for an inverting buffer. The D0 input for an inverting buffer.
When cap coupled differentially, VBB output is connected through a
resistor to each input pin. If used, the VBB pin should be bypassed to
VCC via a 0.01 F capacitor. For additional information see
AND8020. For a single-ended direct connection use an external
voltage reference source such as a resistor divider. Do not use VBB for
a single-ended direct connection or port to another device.
•
•
•
•
•
•
•
•
•
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MARKING
DIAGRAMS*
8
SO-8
D SUFFIX
CASE 751
8
1
1
8
TSSOP-8
DT SUFFIX
CASE 948R
8
1
1.4 ns Typical Propagation Delay
KPT21
ALYW
KA21
ALYW
1
Maximum Frequency > 275 MHz Typical
24 mA TTL outputs
A
L
Y
W
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
Open Input Default State
Q Output Will Default LOW with Inputs Open or at GND
The 100 Series Contains Temperature Compensation
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
VBB Output
New Differential Input Common Mode Range
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2002
November, 2002 - Rev. 8
314
Package
Shipping
MC100EPT21D
SO-8
98 Units/Rail
MC100EPT21DR2
SO-8
2500 Tape & Reel
MC100EPT21DT
TSSOP-8
100 Units/Rail
MC100EPT21DTR2
TSSOP-8 2500 Tape & Reel
Publication Order Number:
MC100EPT21/D
MC100EPT21
NC
1
D
2
D
LVTTL
3
8
VCC
7
Q
6
PIN DESCRIPTION
NC
LVPECL
VBB
4
5
GND
PIN
FUNCTION
Q
LVTTL Output
D**, D**
Differential LVPECL Input Pair
VCC
VBB
Positive Supply
Output Reference Voltage
GND
Ground
NC
No Connect
** Pins will default to VCC/2 when left open.
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
> 1.5 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
81 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Rating
Units
3.8
V
0 to 3.8
V
± 0.5
mA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 SOIC
41 to 44
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
VCC
PECL Power Supply
GND = 0 V
VIN
PECL Input Voltage
GND = 0 V
IBB
VBB Sink/Source
TA
2. Maximum Ratings are those values beyond which device damage may occur.
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315
Condition 2
VI VCC
MC100EPT21
PECL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 3)
Symbol
-40 °C
Characteristic
Min
25°C
Typ
Max
Min
Max
Min
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 4)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
0.5
A
1875
2.0
Typ
Unit
85°C
1875
150
D
D
1875
150
0.5
-150
Typ
0.5
-150
Max
-150
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
3. Input parameters vary 1:1 with VCC.
4. VIHCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the
differential input signal.
TTL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V, TA = -40°C to 85°C
Symbol
Characteristic
Condition
Min
VOH
Output HIGH Voltage (Note 5)
IOH = -3.0 mA
VOL
Output LOW Voltage (Note 5)
IOL = 24 mA
ICCH
Power Supply Current
Outputs set to HIGH
5
ICCL
Power Supply Current
Outputs set to LOW
8
IOS
Output Short Circuit Current
Typ
Max
2.4
Unit
V
0.5
V
12
20
mA
18
26
mA
-80
mA
-130
5. All loading with 500 to GND.
AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0.0 V (Note 6)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
275
350
tPLH,
tPHL
Propagation Delay to
Output Differential
1200
1200
1450
1400
tSK++
tSK- tSKPP
Output-to-Output Skew++
Output-to-Output Skew- Part- to- Part Skew (Note 7)
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2 Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(0.8V - 2.0V)
Min
Typ
275
350
1200
1200
1450
1400
85°C
Max
Min
Typ
275
350
1300
1200
1450
1400
Max
Unit
MHz
1800
1800
60
25
500
0.2
<1
150
800
1200
330
500
900
1800
1800
1900
1900
ps
60
25
500
ps
0.2
<1
ps
mV
60
25
500
0.2
<1
150
800
1200
150
800
1200
330
500
900
330
500
900
ps
Q, Q
6. Measured with a 750 mV 50% duty-cycle clock source. RL = 500 to GND and CL = 20 pF to GND. Refer to FIgure 3.
7. Skews are measured between outputs under identical transitions.
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316
MC100EPT21
3000
6
5
2000
4
VOL 0.5 V
1500
3
1000
2
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
(JITTER)
500
1
0
0
50
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*CL includes
fixture
capacitance
CL*
RL
AC TEST LOAD
GND
Figure 3. TTL Output Loading Used For Device Evaluation
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317
550
600
JITTEROUT ps (RMS)
VOUTpp (mV)
VOH
2500
É
É
MC100EPT22
3.3VDual LVTTL/LVCMOS
to Differential LVPECL
Translator
The MC100EPT22 is a dual LVTTL/LVCMOS to differential
LVPECL translator. Because LVPECL (Positive ECL) levels are used
only +3.3 V and ground are required. The small outline 8- lead package
and the single gate of the EPT22 makes it ideal for those applications
where space, performance, and low power are at a premium. Because the
mature MOSAIC 5 process is used, low cost and high speed can be added
to the list of features.
•
•
•
•
•
•
420 ps Typical Propagation Delay
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MARKING
DIAGRAMS*
8
SO-8
D SUFFIX
CASE 751
8
1
Maximum Frequency > 1.1 GHz Typical
KPT22
ALYW
1
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
PNP LVTTL Inputs for Minimal Loading
8
Q Output Will Default HIGH with Inputs Open
TSSOP-8
DT SUFFIX
CASE 948R
8
The 100 Series Contains Temperature Compensation.
1
KA22
ALYW
1
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2002
September, 2002 - Rev. 8
318
Package
Shipping
MC100EPT22D
SO-8
98 Units/Rail
MC100EPT22DR2
SO-8
2500 Tape & Reel
MC100EPT22DT
TSSOP-8
100 Units/Rail
MC100EPT22DTR2
TSSOP-8 2500 Tape & Reel
Publication Order Number:
MC100EPT22/D
MC100EPT22
Q0
1
8
VCC
Q0
2
7
D0
LVPECL
Q1
Q1
PIN DESCRIPTION
PIN
FUNCTION
Q0, Q1, Q0, Q1
LVPECL Differential Outputs
D0, D1
LVTTL Inputs
VCC
Positive Supply
GND
Ground
LVTTL
3
6
4
5
D1
GND
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
164 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
VCC
Power Supply
GND = 0 V
VI
Input Voltage
GND = 0 V
Iout
Output Current
Continuous
Surge
TA
Condition 2
VI VCC
Rating
Units
6
V
6 to 0
V
50
100
mA
mA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 SOIC
41 to 44
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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319
MC100EPT22
TTL INPUT DC CHARACTERISTICS VCC= 3.3 V, GND= 0.0 V, TA= -40°C to 85°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
IIH
Input HIGH Current
VIN= 2.7 V
20
A
IIHH
Input HIGH Current MAX
VIN= 6.0 V
100
A
IIL
Input LOW Current
VIN= 0.5 V
-0.6
mA
VIK
Input Clamp Voltage
IIN= -18 mA
-1.0
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
2.0
V
0.8
V
PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
ICC
Power Supply Current
32
43
55
35
45
60
37
46
62
mA
VOH
Output HIGH Voltage
(Note 4)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage
(Note 4)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
3. Output parameters vary 1:1 with VCC.
4. All loading with 50 to VCC- 2.0 V.
AC CHARACTERISTICS VCC= 3.0 V to 3.6 V, GND= 0.0 V (Note 5)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
0.8
1.1
tPLH,
tPHL
Propagation Delay to
Output Differential
250
400
650
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
0.2
<1
tr
tf
Output Rise/Fall Times
(20% - 80%)
110
200
50
85°C
Min
Typ
0.8
1.1
250
420
675
0.2
<1
120
220
60
Max
Q, Q
5. Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
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320
Min
Typ
0.8
1.1
300
500
700
ps
0.2
<1
ps
140
250
ps
70
Max
Unit
GHz
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
100
1
(JITTER)
0
0
200
400
600
800
1000
1200
1400
1600
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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321
JITTEROUT ps (RMS)
VOUTpp (mV)
MC100EPT22
ÉÉ
ÉÉ
ÉÉ
MC100EPT23
3.3VDual Differential
LVPECL to LVTTL
Translator
The MC100EPT23 is a dual differential LVPECL to LVTTL translator.
Because LVPECL (Positive ECL) levels are used, only +3.3 V and
ground are required. The small outline 8-lead package and the dual gate
design of the EPT23 makes it ideal for applications which require the
translation of a clock and a data signal.
The EPT23 is available in only the ECL 100K standard. Since there
are no LVPECL outputs or an external VBB reference, the EPT23 does
not require both ECL standard versions. The LVPECL inputs are
differential. Therefore, the MC100EPT23 can accept any standard
differential LVPECL input referenced from a VCC of +3.3 V.
•
•
•
•
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MARKING
DIAGRAMS*
8
8
1
1.5 ns Typical Propagation Delay
KPT23
ALYW
SO-8
D SUFFIX
CASE 751
1
8
Maximum Operating Frequency > 275 MHz
24 mA LVTTL Outputs
TSSOP-8
DT SUFFIX
CASE 948R
8
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
1
KA23
ALYW
1
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC100EPT23D
SO-8
98 Units/Rail
MC100EPT23DR2
SO-8
2500 Tape & Reel
TSSOP-8
100 Units/Rail
MC100EPT23DT
MC100EPT23DTR2 TSSOP-8 2500 Tape & Reel
 Semiconductor Components Industries, LLC, 2002
November, 2002 - Rev. 8
322
Publication Order Number:
MC100EPT23/D
MC100EPT23
D0
1
8
VCC
PIN DESCRIPTION
D0
2
7
LVPECL
D1
D1
Q0
LVTTL
3
6
4
5
PIN
FUNCTION
Q0, Q1
LVTTL Outputs
D0**, D1**
D0**, D1**
Differential LVPECL Inputs
VCC
Positive Supply
GND
Ground
Q1
** Pins will default to (2/3)VCC when left open.
GND
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
> 1.2 kV
> 150 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
91 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
3.8
V
3.8
V
50
100
mA
mA
VCC
Power Supply
GND = 0 V
VI
Input Voltage
GND = 0 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 SOIC
41 to 44
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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323
VI VCC
MC100EPT23
PECL DC CHARACTERISTICS VCC = 3.3 V, GND = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
ICCH
Power Supply Current (Outputs set to HIGH)
10
18
25
10
18
25
10
18
25
mA
ICCL
Power Supply Current (Outputs set to LOW)
15
26
33
15
26
33
15
26
33
mA
VIH
Input HIGH Voltage
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage
1355
1675
1355
1675
1355
1675
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Note 4)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
0.5
A
150
D
D
-150
-150
150
-150
-150
-150
-150
NOTE: Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. All values vary 1:1 with VCC.
4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
TTL DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V, TA = -40°C to 85°C
Symbol
Characteristic
Condition
VOH
Output HIGH Voltage (Note 5)
IOH = -3.0 mA
VOL
Output LOW Voltage (Note 5)
IOL = 24 mA
IOS
Output Short Circuit Current
Min
Typ
Max
Unit
2.4
V
-180
0.5
V
-50
mA
NOTE: Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
5. All loading with 500 to GND.
AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0.0 V (Note 6)
-40 °C
Min
Typ
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
275
350
tPLH,
tPHL
Propagation Delay to
Output Differential (Note 7)
1.2
1.2
1.5
1.5
tSK+ +
tSK- tSKPP
Output-to-Output Skew++
Output-to-Output Skew- Part- to- Part Skew (Note 8)
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2 Fmax/JITTER)
VPP
Input Voltage Swing
(Differential)
tr
tf
Output Rise/Fall Times
(0.8 V - 2.0 V)
Symbol
Characteristic
25°C
Max
1.8
1.8
Min
Typ
275
350
1.2
1.2
1.5
1.5
60
25
500
0.2
<1
150
800
1200
330
600
900
85°C
Max
1.8
1.8
Min
Typ
275
350
1.3
1.2
1.7
1.5
Max
Unit
MHz
2.2
1.8
ns
60
25
500
ps
0.2
<1
ps
mV
60
25
500
0.2
<1
150
800
1200
150
800
1200
330
600
900
330
650
900
ps
Q, Q
6. Measured with a 750 mV 50% duty-cycle clock source. RL = 500 to GND and CL = 20 pF to GND. Refer to Figure 3.
7. Reference (VCC = 3.3V ± 5%; GND = 0V)
8. Skews are measured between outputs under identical conditions.
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324
MC100EPT23
3000
6
5
2000
4
VOL 0.5 V
1500
3
1000
2
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
(JITTER)
500
0
0
50
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*CL includes
fixture
capacitance
CL*
RL
AC TEST LOAD
GND
Figure 3. TTL Output Loading Used for Device Evaluation
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325
JITTEROUT ps (RMS)
VOUTpp (mV)
VOH
2500
1
550
600
MC100EPT24
3.3VLVTTL/LVCMOS to
Differential LVECL Translator
The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL
translator. Because LVECL levels and LVTTL/LVCMOS levels are
used, a -3.3 V, +3.3 V and ground are required. The small outline
8-lead package and the single gate of the EPT24 makes it ideal for
those applications where space, performance, and low power are at a
premium.
•
•
•
•
•
•
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MARKING
DIAGRAMS*
350 ps Typical Propagation Delay
Maximum Frequency > 1.0 GHz Typical
The 100 Series Contains Temperature Compensation
8
Operating Range: VCC = 3.0 V to 3.6 V;
VEE = -3.6 V to -3.0 V; GND = 0 V
PNP LVTTL Inputs for Minimal Loading
Q Output Will Default HIGH with Input Open
KPT24
ALYW
SO-8
D SUFFIX
CASE 751
8
1
1
8
TSSOP-8
DT SUFFIX
CASE 948R
8
1
KA24
ALYW
1
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2001
June, 2001 - Rev. 5
326
Package
Shipping
MC100EPT24D
SO-8
98 Units / Rail
MC100EPT24DR2
SO-8
2500 Tape & Reel
MC100EPT24DT
TSSOP-8
100 Units / Rail
MC100EPT24DTR2
TSSOP-8 2500 Tape & Reel
Publication Order Number:
MC100EPT24/D
MC100EPT24
VEE
1
8
VCC
PIN DESCRIPTION
LVTTL
D
2
7
Q
LVECL
NC
NC
3
6
4
5
FUNCTION
PIN
Q
GND
Q, Q
Differential LVECL Outputs
D
LVTTL Input
VCC
Positive Supply
GND
Ground
VEE
Negative Supply
NC
No Connect
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Flammability Rating
Oxygen Index
Level 1
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
181 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
Positive Power Supply
GND = 0 V
VEE = -3.3 V
3.8
V
VEE
Negative Power Supply
GND = 0 V
VCC = +3.3 V
-3.8
V
VIN
Input Voltage
GND = 0 V
VI VCC
0 to VCC
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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327
MC100EPT24
LVTTL INPUT DC CHARACTERISTICS VCC= 3.3 V, VEE= -3.6 V to -3.0 V, GND= 0.0 V; TA= -40°C to 85°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
IIH
Input HIGH Current
VIN = 2.7 V
20
µA
IIHH
Input HIGH Current
VIN = 6.0 V
100
µA
IIL
Input LOW Current
VIN = 0.5 V
-0.6
mA
VIK
Input Clamp Diode Voltage
IIN = -18 mA
-1.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
2.0
V
0.8
V
NECL OUTPUT DC CHARACTERISTICS VCC= 3.3 V, VEE= -3.3 V, GND= 0.0 V (Note 3.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
Output HIGH Voltage (Note 4.)
-1145
-1020
-895
-1145
-1020
-895
-1145
-1030
-895
mV
VOL
Output LOW Voltage (Note 4.)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
ICC
Power Supply Current
2.0
4.0
2.0
4.0
2.0
4.0
mA
IEE
Power Supply Current
30
38
30
38
30
38
mA
20
20
20
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
3. Output levels will vary 1:1 with GND. VEE can vary ± 0.3 V.
4. Outputs are terminated through a 50 ohm resistor to GND-2 volts.
AC CHARACTERISTICS VCC= 3.0 V to 3.6 V, VEE= -3.6 V to -3.0 V, GND= 0.0 V (Note 5.)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential (Note 6.)
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
tr
tf
Output Rise/Fall Times
(20% - 80%)
Min
Typ
25°C
Max
Min
>1
300
Q, Q
70
Typ
85°C
Max
Min
>1
500
800
0.2
<1
125
170
300
80
328
Max
>1
530
800
0.2
<1
130
180
300
100
5. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
6. Specifications for standard TTL input signal.
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Typ
Unit
GHz
560
800
ps
0.2
<1
ps
150
200
ps
900
9
800
8
700
7
600
6
500
5
400
4
300
3
ÉÉ
ÉÉ
2
200
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
(JITTER)
100
0
100
300
500
700
900
1100
1300
1
1500
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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329
JITTEROUT ps (RMS)
VOUTpp (mV)
MC100EPT24
MC100EPT25
−3.3V / −5VDifferential ECL
to +3.3V LVTTL Translator
The MC100EPT25 is a Differential ECL to LVTTL translator. This
device requires +3.3 V, -3.3 V to -5.2 V, and ground. The small
outline 8-lead package and the single gate of the EPT25 make it ideal
for applications which require the translation of a clock or data signal.
The VBB output allows the EPT25 to also be used in a single-ended
input mode. In this mode the VBB output is tied to the D input for a
inverting buffer or the D input for a non-inverting buffer. If used, the
VBB pin should be bypassed to ground with at least a 0.01 F
capacitor.
• 1.1 ns Typical Propagation Delay
• Maximum Frequency > 275 MHz Typical
• Operating Range: VCC = 3.0 V to 3.6 V;
•
•
•
•
•
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MARKING
DIAGRAMS*
8
SO-8
D SUFFIX
CASE 751
8
1
KPT25
ALYW
1
8
VEE = -5.5 V to -3.0 V; GND = 0 V
24 mA TTL Outputs
TSSOP-8
DT SUFFIX
CASE 948R
8
Q Output Will Default LOW with Inputs Open or at VEE
1
KA25
ALYW
1
VBB Output
Open Input Default State
A
L
Y
W
Safety Clamp on Inputs
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC100EPT25D
SO-8
98 Units/Rail
MC100EPT25DR2
SO-8
2500 Tape & Reel
TSSOP-8
100 Units/Rail
MC100EPT25DT
MC100EPT25DTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2002
November, 2002 - Rev. 9
330
2500 Tape & Reel
Publication Order Number:
MC100EPT25/D
MC100EPT25
VEE
D
D
1
8
LVTTL
2
3
PIN DESCRIPTION
VCC
7
Q
NC
6
LVECL/ECL
VBB
4
5
GND
PIN
FUNCTION
Q
LVTTL Output
D*, D*
Differential ECL Input Pair
VCC
Positive Supply
VBB
GND
Ground
VEE
Negative Supply
NC
No Connect
Output Reference Voltage
* Pins will default LOW when left open.
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Level 1
UL-94 V-0 @ 0.125 in
Transistor Count
111 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
VCC
Positive Power Supply
GND = 0 V
VEE = -5.0 V
3.8
V
VEE
Negative Power Supply
GND = 0 V
VCC = +3.3 V
-6
V
VIN
Input Voltage
GND = 0 V
0 to VEE
V
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 SOIC
41 to 44
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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331
MC100EPT25
NECL DC CHARACTERISTICS VCC = 3.3 V; VEE = -5.5 V to -3.0 V; GND = 0.0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
8.0
16
25
8.0
16
25
8.0
16
25
mA
IEE
Power Supply Current
VIH
Input HIGH Voltage Single-Ended
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage Single-Ended
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 4)
0.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
-1425
VEE + 2.0
0.0
-1425
VEE + 2.0
0.0
150
-1425
VEE + 2.0
150
0.5
0.5
A
0.5
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input parameters vary 1:1 with GND.
4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
TTL OUTPUT DC CHARACTERISTICS VCC = 3.3 V; VEE = -5.5 V to -3.0 V; GND = 0.0 V; TA = -40°C to 85°C
Symbol
Characteristic
Condition
Min
VOH
Output HIGH Voltage (Note 5)
IOH = -3.0 mA
VOL
Output LOW Voltage (Note 5)
IOL = 24 mA
ICCH
Power Supply Current
6
ICCL
Power Supply Current
7
Typ
Max
2.2
Unit
V
0.5
V
10
14
mA
12
17
mA
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. All loading with 500 to GND; CL = 20 pF.
AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; VEE = -5.5 V to -3.0 V; GND = 0.0 V (Note 6)
-40 °C
Symbol
fmax
Min
Characteristic
Maximum Frequency
(See Figure 2 Fmax/JITTER)
275
tPLH,PHL
t
Propagation Delay to Output Differential
(Cross-Point to 1.5 V)
800
tSKPP
Device- to- Device Skew (Note 7)
tJITTER
CLOCK Random Jitter
(See Figure 2 Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(0.8 V - 2.0 V)
Typ
25°C
Max
Min
Typ
Max
275
1200
1800
800
0.2
<1
150
800
1200
450
900
600
1160
750
1400
Min
Typ
1100
1600
800
332
Unit
MHz
1100
1600
ps
500
ps
0.2
<1
ps
500
0.2
<1
150
800
1200
150
800
1200
mV
450
900
600
1100
750
1400
450
900
600
1100
750
1400
ps
6. Measured with a 750 mV 50% duty-cycle clock source. RL = 500 to GND and CL = 20 pF to GND. Refer to Figure 3.
7. Skews are measured between outputs under identical conditions.
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Max
275
500
Q, Q
85°C
MC100EPT25
7
2800
VOH
6
2000
5
1600
4
1200
3
VOL 0.5 V
2
800
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
(JITTER)
400
0
25
100
175
250
325
400
475
550
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*CL includes
fixture
capacitance
CL*
RL
AC TEST LOAD
GND
Figure 3. TTL Output Loading Used for Device Evaluation
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333
1
625
JITTEROUT ps (RMS)
VOUTpp (mV)
2400
É
É
MC100EPT26
3.3V1:2 Fanout Differential
LVPECL to LVTTL Translator
The MC100EPT26 is a 1:2 Fanout Differential LVPECL to LVTTL
translator. Because LVPECL (Positive ECL) levels are used only +3.3 V
and ground are required. The small outline 8- lead package and the 1:2
fanout design of the EPT26 makes it ideal for applications which require
the low skew duplication of a signal in a tightly packed PC board.
The VBB output allows the EPT26 to be used in a single-ended input
mode. In this mode the VBB output is tied to the D0 input for a
non-inverting buffer or the D0 input for an inverting buffer. If used,
the VBB pin should be bypassed to ground via a 0.01 F capacitator.
•
•
•
•
•
•
•
•
•
1.4 ns Typical Propagation Delay
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MARKING
DIAGRAMS*
8
SO-8
D SUFFIX
CASE 751
8
1
Maximum Frequency > 275 MHz Typical
KPT26
ALYW
1
The 100 Series Contains Temperature Compensation
8
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
Open Input Default State
TSSOP-8
DT SUFFIX
CASE 948R
8
1
Safety Clamp on Inputs
KA26
ALYW
1
24 mA TTL outputs
Q Outputs Will Default LOW with Inputs Open or at VEE
A
L
Y
W
VBB Output
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC100EPT26D
SO-8
98 Units/Rail
MC100EPT26DR2
SO-8
2500 Tape & Reel
TSSOP-8
100 Units/Rail
MC100EPT26DT
MC100EPT26DTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2002
November, 2002 - Rev. 7
334
2500 Tape & Reel
Publication Order Number:
MC100EPT26/D
MC100EPT26
NC
1
8
VCC
PIN DESCRIPTION
PIN
D
2
7
Q0
LVTTL
D
VBB
3
6
4
5
LVPECL
Q1
GND
FUNCTION
Q0, Q1
LVTTL Outputs
D**, D**
Differential LVPECL Input Pair
VCC
VBB
Positive Supply
GND
Ground
NC
No Connect
Output Reference Voltage
** Pins will default to VCC/2 when left open.
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
117 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
3.8
V
0 to 3.8
V
± 0.5
mA
-40 to +85
°C
VCC
Positive Power Supply
GND = 0 V
VIN
Input Voltage
GND = 0 V
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 SOIC
41 to 44
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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335
VI VCC
MC100EPT26
PECL INPUT DC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V (Note 3)
-40 °C
Max
Min
Max
Min
Max
Unit
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 4)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
Characteristic
Typ
85°C
VIH
Symbol
Min
25°C
1875
2.0
Typ
1875
150
D
D
Typ
1875
150
0.5
-150
0.5
-150
A
0.5
-150
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
3. Input parameters vary 1:1 with VCC.
4. VIHCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the
differential input signal.
TTL OUTPUT DC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V; TA = -40°C to 85°C
Symbol
Characteristic
Condition
Min
VOH
Output HIGH Voltage (Note 5)
IOH = -3.0 mA
VOL
Output LOW Voltage (Note 5)
IOL = 24 mA
ICCH
Power Supply Current
10
ICCL
Power Supply Current
15
Typ
Max
2.4
IOS
Output Short Circuit Current
5. All loading with 500 to GND, CL = 20 pF.
Unit
V
0.5
V
20
18
mA
28
35
mA
-150
mA
-50
AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; GND = 0.0 V (Note 6)
-40 °C
25°C
Min
Typ
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
275
350
tPLH,
tPHL
Propagation Delay to
Output Differential (Note 7)
1.2
1.2
1.5
1.5
tSK+ +
tSK- tSKPP
Within Device Skew++
Within Device Skew- Device- to- Device Skew (Note 8)
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
150
800
1200
150
800
1200
150
800
1200
tr
tf
Output Rise/Fall Times
(0.8V - 2.0V)
330
600
900
330
600
900
330
650
900
Symbol
Characteristic
Max
1.8
1.8
Min
Typ
275
350
1.2
1.2
1.5
1.5
85°C
60
25
500
Max
1.8
1.8
Min
Typ
275
350
1.3
1.2
1.7
1.5
60
25
500
TBD
TBD
Max
Unit
MHz
2.2
1.8
ns
60
25
500
ps
TBD
ps
mV
ps
Q, Q
6. Measured with a 750 mV 50% duty-cycle clock source. RL = 500 to GND and CL = 20 pF to GND. Refer to Figure 3.
7. Reference (VCC = 3.3V ± 5%; GND = 0V)
8. Skews are measured between outputs under identical transitions.
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336
MC100EPT26
3000
6
5
2000
4
VOL 0.5 V
1500
3
1000
2
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
(JITTER)
500
1
0
0
50
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*CL includes
fixture
capacitance
CL*
RL
AC TEST LOAD
GND
Figure 3. TTL Output Loading Used for Device Evaluation
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337
550
600
JITTEROUT ps (RMS)
VOUTpp (mV)
VOH
2500
ÉÉ
ÉÉ
MC100EPT622
3.3VLVTTL/LVCMOS to
LVPECL Translator
The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL
translator. Because LVPECL (Positive ECL) levels are used only +3.3 V
and ground are required. The device has an OR- ed enable input which
can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs
(ENTTL). If the inputs are left open, they will default to the enable state.
The device design has been optimized for low channel- to- channel skew
•
•
•
•
•
•
•
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MARKING
DIAGRAM*
450 ps Typical Propagation Delay
Maximum Frequency > 1.5 GHz Typical
MC100
EPT622
PECL Mode
Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
AWLYYWW
LQFP-32
TBD SUFFIX
CASE 873A
PNP LVTTL Inputs for Minimal Loading
Q Output Will Default HIGH with Inputs Open
32
1
The 100 Series Contains Temperature Compensation.
A
WL
YY
WW
ENPECL
ENTTL
D0
D1
D2
Q0
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
Q1
ORDERING INFORMATION
Q2
Device
Package
Shipping
LQFP32
250 Unit Trays
MC100EPT622FA
D3
LVCMOS/TTL
D4
MC100EPT622FAR2 LQFP32
Q3
2000 Tape & Reel
Q4 LVPECL
TRUTH TABLE
D5
D6
D7
D8
D9
Q5
Q6
Q7
ENPECL
ENTTL
D
Q
H
X
H
H
H
X
L
L
X
H
H
H
X
H
L
L
L
L
X
L
Q8
Q9
Figure 4. Logic Symbol
 Semiconductor Components Industries, LLC, 2002
August, 2002 - Rev. 0
338
Publication Order Number:
MC100EPT622/D
VCCO
Q4
Q3
VCCO
Q2
Q1
Q0
VCCO
MC100EPT622
PIN DESCRIPTION
24
23
22
21
20
19
18
17
PIN
FUNCTION
D0:9
Data Input (TTL)
Q0:9
Data Output (PECL)
ENTTL
Enable Control (TTL)
VCCO
25
16
VCCO
D0
26
15
Q5
D1
27
14
Q6
VEE
28
13
VCC
ENPECL
Enable Control (PECL)
D2
29
12
Q7
VCC
Positive Supply
D3
30
11
Q8
VEE
Ground
D4
31
10
Q9
VCCO
32
9
5
D8
D9
6
7
8
VEE
4
ENPECL
3
ENTTL
2
D7
D5
1
D6
MC100EPT622
VCCO
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack
Flammability Rating
Level 2
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
596 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
MAXIMUM RATINGS (Note 9)
Symbol
Parameter
Condition 1
Rating
Units
5
V
5 to 0
V
50
100
mA
mA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
265
°C
VCC
Power Supply
VEE = 0 V
VI
Input Voltage
VEE = 0 V
Iout
Output Current
Continuous
Surge
TA
Tsol
Wave Solder
<2 to 3 sec @ 248°C
9. Maximum Ratings are those values beyond which device damage may occur.
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339
Condition 2
VI VCC
MC100EPT622
TTL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = -40°C to 85°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
IIH
Input HIGH Current
VIN= 2.7 V
20
A
IIHH
Input HIGH Current MAX
VIN= VCC
100
A
IIL
Input LOW Current
VIN= 0.5 V
-0.6
mA
VIK
Input Clamp Voltage
IIN= -18 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
-1.2
-0.9
V
2.0
V
0.8
V
Max
Unit
PECL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = -40°C to 85°C
Symbol
Characteristic
Condition
Min
Typ
IIH
Input HIGH Current
VIN= 2420 mV
150
A
IIL
Input LOW Current
VIN= 1490 mV
200
A
VIH
Input HIGH Voltage
2075
2420
mV
VIL
Input LOW Voltage
1490
1675
mV
PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 10)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
85°C
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
85
115
145
90
120
155
95
130
155
mA
VOH
Input High Voltage
(Note 11)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Input Low Current
(Note 11)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
10. Input and output parameters vary 1:1 with VCC.
11. All loading with 50 to VCC- 2.0 V.
AC CHARACTERISTICS VCC = 3.0 V to 3.8 V (Note 12)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 2)
tPLH,
tPHL
Propagation Delay to Output (Figure 3, Note 13)
D to Q
ENPECL to Q
ENTTL to Q
tJITTER
Random Clock Jitter (RMS)
(See Figure 2)
tr / tf
Output Rise/Fall Times
(20% - 80%)
TSKEW
Duty Cycle Skew (Note 14)
D to Q
25°C
Min
Typ
Max
1.0
1.5
100
200
300
450
450
450
800
850
800
0.7
3.0
200
450
120
200
120
120
300
500
350
250
85°C
Min
Typ
Max
1.0
1.5
100
200
300
500
500
500
800
850
800
0.7
3.0
200
250
120
200
120
120
300
500
350
250
Min
Typ
Max
1.0
1.5
100
200
300
500
500
500
800
850
800
0.7
3.0
ps
200
300
ps
120
200
120
120
300
500
350
250
Unit
GHz
ps
100
100
100
ps
Channel 0-7
Channel 8-9
ENPECL to Q
ENTTL to Q
12. Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
13. 1.5 V to 50% point of the output.
14. Duty cycle skew |tPLH - tPHL| on the specific path.
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MC100EPT622
2400
10.0
9.0
8.0
VCC = 3.3 V
TA = 25°C
2000
VOH (mV)
7.0
6.0
VOL (mV)
1800
5.0
1600
4.0
1400
3.0
RMS Jitter (ps)
RMS JITTER (ps)
OUTPUT AMPLITUDE (mV)
2200
2.0
1200
1.0
1000
0.5
1.0
1.5
2.0
0.0
FREQUENCY (GHz)
Figure 2. Average Output Amplitude/Jitter (3.3 V, 25C)
800
700
tPLH, tPHL (ps)
600
500
400
300
200
100
0
ÉÉ
ÉÉ
É
ÉÉ
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
ÉÉ
ÉÉÉ
ÉÉ
É
É
ÉÉ
ÉÉ
ÉÉ
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
tPLH
tPHL
CHANNEL
Figure 3. Average Propagation Delay (3.3 V, 25C)
Q
D
Driver
Device
Receiver
Device
50 VTT
VTT = VCC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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341
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342
CHAPTER 3
Low Voltage ECLinPS Plus Data Sheets
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343
MC10LVEP11, MC100LVEP11
2.5V / 3.3VECL 1:2
Differential Fanout Buffer
The MC10/100LVEP11 is a differential 1:2 fanout buffer. The
device is pin and functionally equivalent to the EP11 device. With AC
performance the same as the EP11 device, the LVEP11 is ideal for
applications requiring lower voltage. Single- ended CLK input
operation is limited to a VCC 3.0 V in PECL mode, or VEE -3.0
V in NECL mode.
The 100 Series contains temperature compensation.
• 240 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 2.375 V to 3.8 V
•
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MARKING DIAGRAMS*
8
8
8
HVP11
ALYW
1
SO-8
D SUFFIX
CASE 751
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -2.375 V to -3.8 V
Open Input Default State
•
• Q Output Will Default LOW with Inputs Open or at VEE
• LVDS Input Compatible
1
1
8
8
1
TSSOP-8
DT SUFFIX
CASE 948R
KVP11
ALYW
8
HU11
ALYW
1
H = MC10
K = MC100
A = Assembly Location
KU11
ALYW
1
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
MC10LVEP11D
SO-8
98 Units/Rail
MC10LVEP11DR2
SO-8
2500 Tape & Reel
MC100LVEP11D
SO-8
98 Units/Rail
MC100LVEP11DR2
SO-8
2500 Tape & Reel
TSSOP-8
100 Units/Rail
MC10LVEP11DTR2
TSSOP-8
2500 Tape & Reel
MC100LVEP11DT
TSSOP-8
100 Units/Rail
MC10LVEP11DT
MC100LVEP11DTR2 TSSOP-8
 Semiconductor Components Industries, LLC, 2001
October, 2001 - Rev. 4
344
Shipping
2500 Tape & Reel
Publication Order Number:
MC10LVEP11/D
MC10LVEP11, MC100LVEP11
Q0
Q0
1
2
PIN DESCRIPTION
VCC
8
7
D
Q1
3
6
D
Q1
4
5
VEE
PIN
FUNCTION
D*, D**
ECL Data Inputs
Q0, Q0, Q1, Q1
ECL Data Outputs
VCC
VEE
Positive Supply
Negative Supply
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
110 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
6
V
-6
V
6
-6
V
V
50
100
mA
mA
VCC
PECL Mode Power Supply
VEE = 0 V
VEE
NECL Mode Power Supply
VCC = 0 V
VI
Input
PECL Mode In
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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345
VI VCC
VI VEE
MC10LVEP11, MC100LVEP11
10LVEP DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 3.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
24
30
36
24
30
36
25
31
38
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VOL
Output LOW Voltage (Note 4.)
565
690
815
630
755
880
690
815
940
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5.)
1.2
2.5
1.2
2.5
1.2
2.5
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
D
D
0.5
-150
150
0.5
-150
µA
0.5
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -1.3 V.
4. All loading with 50 ohms to VCC-2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
10LVEP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 6.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
24
30
36
24
30
36
25
31
38
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 7.)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 7.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single Ended)
(Note 8.)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single Ended)
(Note 8.)
1365
1690
1430
1755
1490
1815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 9.)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
D
D
0.5
-150
150
0.5
-150
0.5
-150
µA
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.5 V.
7. All loading with 50 ohms to VCC-2.0 volts.
8. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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346
MC10LVEP11, MC100LVEP11
10LVEP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.8 V to -2.375 V (Note 10.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
24
30
36
24
30
36
25
31
38
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 11.)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 11.)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single Ended)
(Note 12.)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single Ended)
(Note 12.)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 13.)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
VEE+1.2
0.0
VEE+1.2
0.0
150
D
D
0.5
-150
VEE+1.2
150
0.5
-150
µA
0.5
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
10. Input and output parameters vary 1:1 with VCC.
11. All loading with 50 ohms to VCC-2.0 volts.
12. Single ended input CLK pin operation is limited to VEE -3.0 V in NECL mode.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100LVEP DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 14.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
25
31
37
29
35
41
32
38
45
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 15.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
Output LOW Voltage (Note 15.)
555
680
805
555
680
805
555
680
805
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 16.)
1.2
2.5
1.2
2.5
1.2
2.5
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
D
D
0.5
-150
150
0.5
-150
0.5
-150
µA
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
14. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -1.3 V.
15. All loading with 50 ohms to VCC-2.0 volts.
16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
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347
MC10LVEP11, MC100LVEP11
100LVEP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 17.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
25
31
37
29
35
41
32
38
45
mA
Output HIGH Voltage (Note 18.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
Output LOW Voltage (Note 18.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single Ended)
(Note 19.)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single Ended)
(Note 19.)
1355
1675
1355
1675
1355
1675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20.)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
IIL
Input HIGH Current
150
µA
IEE
VOH
Power Supply Current
VOL
VIH
150
150
D
0.5
0.5
0.5
µA
-150
-150
D -150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
17. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.5 V.
18. All loading with 50 ohms to VCC-2.0 volts.
19. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Input LOW Current
100LVEP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -3.8 V to -2.375 V (Note 21.)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current
25
31
37
29
35
41
32
38
45
mA
Output HIGH Voltage (Note 22.)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
VIH
Output LOW Voltage (Note 22.)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
Input HIGH Voltage (Single Ended)
(Note 23.)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single Ended)
(Note 23.)
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 24.)
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
-1425
VEE+1.2
0.0
-1425
VEE+1.2
150
D
D
0.5
-150
0.0
-1425
VEE+1.2
150
0.5
-150
µA
0.5
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
21. Input and output parameters vary 1:1 with VCC.
22. All loading with 50 ohms to VCC-2.0 volts.
23. Single ended input CLK pin operation is limited to VEE -3.0 V in NECL mode.
24. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.8 V to -2.375 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 25.)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay (Differential)
CLK to Q, Q
tSKEW
tJITTER
Min
Typ
25°C
Max
Min
>3
170
Typ
85°C
Max
Min
>3
230
300
Within Device Skew
Q, Q
Device to Device Skew (Note 26.)
5.0
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
0.2
180
310
20
130
5.0
<1
0.2
210
Unit
GHz
270
360
ps
20
130
5.0
20
150
ps
<1
0.2
<1
ps
800
1200
mV
140
200
ps
VPP
Input Voltage Swing (Differential)
150
800
1200
150
800
1200
150
tr
Output Rise/Fall Times
Q, Q
70
110
170
80
120
180
100
tf
(20% - 80%)
25. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
26. Skew is measured between outputs under identical transitions.
348
Max
>3
240
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Typ
900
9
800
8
700
7
600
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
200
2
100
0
0
1000
2000
3000
4000
1
(JITTER)
5000
6000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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349
JITTEROUT ps (RMS)
VOUTpp (mV)
MC10LVEP11, MC100LVEP11
MC100LVEP14
2.5V / 3.3V1:5 Differential
ECL/PECL/HSTL Clock Driver
The MC100LVEP14 is a low skew 1- to- 5 differential driver, designed
with clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
single- ended (if the VBB output is used). HSTL inputs can be used when
the LVEP14 is operating under PECL conditions.
The LVEP14 specifically guarantees low output- to- output skew.
Optimal design, layout, and processing minimize skew within a device and
from device to device.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated identically into 50 even if only one output is being used. If an output pair is unused, both
outputs may be left open (unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock; therefore, all associated specification limits are referenced to
the negative edge of the clock input.
The MC100LVEP14, as with most other ECL devices, can be
operated from a positive VCC supply in PECL mode. This allows the
LVEP14 to be used for high performance clock distribution in +3.3 V
or +2.5 V systems. Single ended CLK input pin operation is limited to
a VCC ≥ 3.0 V in PECL mode, or VEE ≤ -3.0 V in NECL mode.
Designers can take advantage of the LVEP14’s performance to
distribute low skew clocks across the backplane or the board.
•
•
•
•
•
•
•
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MARKING
DIAGRAM*
20
20
100
VP14
ALYW
1
TSSOP-20
DT SUFFIX
CASE 948E
A
L
Y
W
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
100 ps Device-to-Device Skew
25 ps Within Device Skew
400 ps Typical Propagation Delay
ORDERING INFORMATION
Maximum Frequency > 2 GHz Typical
Device
The 100 Series Contains Temperature Compensation
MC100LVEP14DT
PECL and HSTL Mode: VCC = 2.375 V to 3.8 V
with VEE = 0 V
NECL Mode: VCC = 0 V
with VEE = -2.375 V to -3.8 V
LVDS Input Compatible
Package
Shipping
TSSOP
75 Units/Rail
MC100LVEP14DTR2 TSSOP
2500 Tape & Reel
•
• Open Input Default State
 Semiconductor Components Industries, LLC, 2002
January, 2002 - Rev. 5
350
Publication Order Number:
MC100LVEP14/D
VCC
EN
VCC
CLK1
CLK1
VBB
CLK0
CLK0
CLK_SEL
MC100LVEP14
20
19
18
17
16
15
14
13
12
11
1
D
VEE
0
Q
1
2
3
4
5
6
7
8
9
10
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram
PIN DESCRIPTION
PINS
FUNCTION TABLE
FUNCTION
CLK0*, CLK0**
ECL/PECL/HSTL CLK Input
CLK1*, CLK1**
ECL/PECL/HSTL CLK Input
Q0:4, Q0:4
ECL/PECL Outputs
CLK_SEL*
ECL/PECL Active Clock Select Input
EN*
ECL Sync Enable
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
CLK0
CLK1
CLK_SEL
EN
Q
L
H
X
X
X
X
X
L
H
X
L
L
H
H
X
L
L
L
L
H
L
H
L
H
L*
* On next negative transition of CLK0 or CLK1
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index
> 2 kV
> 100 V
> 2 kV
Level 1
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
357 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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351
MC100LVEP14
MAXIMUM RATINGS (Note 2)
Symbol
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
140
100
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
20 TSSOP
23 to 41
°C/W
265
°C
VI VCC
VI VEE
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
100LVEP DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
60
75
45
60
75
45
60
75
mA
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
680
680
680
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
VOL
Output LOW Voltage (Note 4)
555
805
555
805
555
805
mV
VIH
Input HIGH Voltage (Single-Ended) (Note 5)
1335
1620
1335
1620
1275
1620
mV
VIL
Input LOW Voltage (Single-Ended) (Note 5)
555
875
555
875
555
875
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential) (Note 6)
1.2
2.5
1.2
2.5
1.2
2.5
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
CLK
CLK
0.5
-150
150
0.5
-150
0.5
-150
µA
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -1.3 V.
4. All loading with 50 ohms to VCC-2.0 volts.
5. Do not use VBB at VCC < 3.0 V.
6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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352
MC100LVEP14
100LVEP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 7)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
60
75
45
60
75
45
60
75
mA
Output HIGH Voltage (Note 8)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 8)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Reference Voltage (Note 9)
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 10)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IEE
Power Supply Current
VOH
1875
1875
150
CLK
CLK
1875
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.5 V.
8. All loading with 50 ohms to VCC-2.0 volts.
9. Single ended input operation is limited to VCC 3.0 V in PECL mode.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100LVEP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.8 V to -2.375 V (Note 11)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
45
60
75
45
60
75
45
60
95
mA
VOH
Output HIGH Voltage (Note 12)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 12)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1 165
-880
-1 165
-880
-1 165
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Reference Voltage (Note 13)
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
-1425
VEE+1.2
0.0
VEE+1.2
150
CLK
CLK
0.5
-150
-1425
0.0
VEE+1.2
150
0.5
-150
-1425
0.5
-150
µA
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC.
12. All loading with 50 ohms to VCC-2.0 volts.
13. Single ended input operation is limited to VEE 3.0 V in NECL mode.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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353
MC100LVEP14
DC CHARACTERISTICS, HSTL VCC = 2.375 V to 3.8 V, VEE = 0 V
-40 °C
Symbol
Characteristic
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Min
25°C
Typ
Max
1200
Min
Typ
85°C
Max
1200
Min
Typ
Max
1200
400
Unit
mV
400
400
mV
Max
Unit
AC CHARACTERISTICS VCC = 0 V, VEE = -2.375 V to -3.8 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 15)
-40 °C
Symbol
Characteristic
fmaxLVPECL
/HSTL
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH
tPHL
Propagation Delay to
Output Differential
tskew
Within-Device Skew
Device-to-Device Skew
(Note 16)
ts
th
Setup Time
Hold Time
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
VPP
Minimum Input Swing
tr/tf
Output Rise/Fall Time
(20%-80%)
Min
25°C
Typ
Max
Min
>2
300
EN
EN
100
200
Typ
85°C
Max
Min
Typ
>2
375
425
10
100
25
125
50
140
300
100
200
0.2
<1
150
800
1200
125
165
225
>2
400
475
15
150
25
175
50
140
300
100
200
0.2
<1
150
800
1200
125
180
250
430
525
ps
15
200
25
225
ps
50
140
<1
ps
150
800
1200
mV
125
200
275
ps
9
800
8
700
7
600
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
2
(JITTER)
1
0
0
1000
2000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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354
JITTEROUT ps (RMS)
VOUTpp (mV)
900
100
3000
ps
0.2
15. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
16. Skew is measured between outputs under identical transitions.
200
GHz
4000
MC100LVEP14
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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355
MC10LVEP16, MC100LVEP16
2.5V / 3.3VECL Differential
Receiver/Driver
The MC10/100LVEP16 is a world class differential receiver/driver.
The device is functionally equivalent to the EL16, EP16 and LVEL16
devices. With output transition times significantly faster than the EL16
and LVEL16, the LVEP16 is ideally suited for interfacing with high
frequency and low voltage (2.5 V) sources. Single- ended CLK input
operation is limited to a VCC 3.0 V in PECL mode, or VEE -3.0 V
in NECL mode.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
• 240 ps Propagation Delay
• Maximum Frequency > 4 GHz Typical
• PECL Mode Operating Range: VCC = 2.375 V to 3.8 V
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MARKING DIAGRAMS*
8
8
8
HVP16
ALYW
1
SO-8
D SUFFIX
CASE 751
8
1
1
8
1
TSSOP-8
DT SUFFIX
CASE 948R
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
with VEE = -2.375 V to -3.8 V
8
KU16
ALYW
HU16
ALYW
1
1
H = MC10
K = MC100
A = Assembly Location
• VBB Output
• Open Input Default State
• LVDS Input Compatible
KVP16
ALYW
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
MC10LVEP16D
April, 2001 - Rev. 3
356
Shipping
SO-8
98 Units/Rail
MC10LVEP16DR2
SO-8
2500 Tape & Reel
MC100LVEP16D
SO-8
98 Units/Rail
MC100LVEP16DR2
SO-8
2500 Tape & Reel
TSSOP-8
100 Units/Rail
MC10LVEP16DTR2
TSSOP-8
2500 Tape & Reel
MC100LVEP16DT
TSSOP-8
100 Units/Rail
MC100LVEP16DTR2
TSSOP-8
2500 Tape & Reel
MC10LVEP16DT
 Semiconductor Components Industries, LLC, 2001
Package
Publication Order Number:
MC10LVEP16/D
MC10LVEP16, MC100LVEP16
NC
D
D
VBB
1
8
2
7
3
6
4
5
PIN DESCRIPTION
VCC
Q
Q
VEE
PIN
FUNCTION
D*, D**
ECL Data Inputs
Q, Q
ECL Data Outputs
VBB
Ref. Voltage Output
VCC
Positive Supply
VEE
Negative Supply
NC
No Connect
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8”
28 to 34
Transistor Count
167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
6
V
-6
V
6
-6
V
V
50
100
mA
mA
± 0.5
mA
-40 to +85
°C
VCC
PECL Mode Power Supply
VEE = 0 V
VEE
NECL Mode Power Supply
VCC = 0 V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 SOIC
41 to 44
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
8 TSSOP
41 to 44
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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357
VI VCC
VI VEE
MC10LVEP16, MC100LVEP16
10EP DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 3.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
17
22
27
17
22
27
17
22
28
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VOL
Output LOW Voltage (Note 4.)
565
690
815
630
755
880
690
815
940
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential)
(Note 5., Note 6.)
1.2
2.5
1.2
2.5
1.2
2.5
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
D
D
0.5
-150
150
0.5
-150
µA
0.5
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -1.3 V.
4. All loading with 50 ohms to VCC-2.0 volts.
5. Do not use VBB at VCC < 3.0 V. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 7.)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
17
22
27
17
22
27
17
22
28
mA
VOH
Output HIGH Voltage (Note 8.)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 8.)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single Ended)
1365
1690
1430
1755
1490
1815
mV
VBB
Output Voltage Reference (Note 9.)
1790
1990
1855
2055
1915
2115
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 10.)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
1890
150
D
D
0.5
-150
1955
150
0.5
-150
0.5
-150
2015
µA
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.5 V.
8. All loading with 50 ohms to VCC-2.0 volts.
9. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10LVEP16, MC100LVEP16
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.8 V to -2.375 V (Note 11.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
17
22
27
17
22
27
17
22
28
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 12.)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 12.)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VBB
Output Voltage Reference (Note 13.)
-1510
-1310
-1445
-1245
-1385
-1 185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14.)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
-1410
VEE+1.2
0.0
-1345
VEE+1.2
0.0
150
D
D
0.5
-150
-1285
VEE+1.2
150
0.5
-150
µA
0.5
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC.
12. All loading with 50 ohms to VCC-2.0 volts.
13. Single ended input CLK pin operation is limited to VEE -3.0 V in NECL mode.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 15.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
19
24
29
22
28
34
24
30
36
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 16.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
Output LOW Voltage (Note 16.)
555
680
805
555
680
805
555
680
805
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential)
(Note 17., Note 18.)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
D
D
0.5
-150
150
0.5
-150
0.5
-150
µA
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -1.3 V.
16. All loading with 50 ohms to VCC-2.0 volts.
17. Do not use VBB at VCC < 3.0 V. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
18. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10LVEP16, MC100LVEP16
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 19.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
19
24
29
22
28
34
24
30
36
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 20.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 20.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
VBB
Input LOW Voltage (Single Ended)
1355
1675
1355
1675
1355
1675
mV
Output Voltage Reference (Note 21.)
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 22.)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
IIL
Input HIGH Current
150
µA
1875
1875
150
Input LOW Current
D
D
1875
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
19. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.5 V.
20. All loading with 50 ohms to VCC-2.0 volts.
21. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
22. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.8 V to -2.375 V (Note 23.)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
19
24
29
22
28
34
24
30
36
mA
IEE
VOH
Power Supply Current
Output HIGH Voltage (Note 24.)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
VIH
Output LOW Voltage (Note 24.)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
VBB
Input LOW Voltage (Single Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
Output Voltage Reference (Note 25.)
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 26.)
0.0
V
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
-1425
VEE+1.2
0.0
-1425
VEE+1.2
150
D
D
0.5
-150
0.0
-1425
VEE+1.2
150
0.5
-150
µA
0.5
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
23. Input and output parameters vary 1:1 with VCC.
24. All loading with 50 ohms to VCC-2.0 volts.
25. Single ended input CLK pin operation is limited to VEE -3.0 V in NECL mode.
26. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.8 V to -2.375 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 27.)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Min
Typ
25°C
Max
Min
>4
150
Max
Min
>4
220
300
Duty Cycle Skew (Note 28.)
5.0
tJITTER
Cycle-to-Cycle Jitter
(See Figure 2. Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
150
Typ
85°C
170
Max
>4
240
320
20
5.0
0.2
<1
800
1200
150
Typ
190
Unit
GHz
260
330
ps
20
5.0
20
ps
0.2
<1
0.2
<1
ps
800
1200
800
1200
mV
150
tr
Output Rise/Fall Times
Q, Q
70
120
170
80
130
180
100
150
200
ps
tf
(20% - 80%)
27. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
28. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
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360
900
9
800
8
700
7
600
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
200
2
100
1
(JITTER)
0
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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361
JITTEROUT ps (RMS)
VOUTpp (mV)
MC10LVEP16, MC100LVEP16
MC100LVEP34
2.5V / 3.3VECL ÷2, ÷4, ÷8
Clock Generation Chip
The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The VBB pin, an internally
generated voltage supply, is available to this device only. For
single- ended input conditions, the unused differential input is
connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 F capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, VBB should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple LVEP34s in a system. Single-ended CLK
input operation is limited to a VCC ≥ 3.0 V in PECL mode, or VEE ≤
-3.0 V in NECL mode.
•
•
•
•
•
•
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MARKING
DIAGRAMS*
16
16
100LVEP34
AWLYWW
1
SO-16
D SUFFIX
CASE 751B
16
16
Synchronous Enable/Disable
Master Reset for Synchronization
The 100 Series Contains Temperature Compensation.
100
LVEP34
ALYW
1
TSSOP-16
DT SUFFIX
CASE 948F
A
L, WL
Y
W, WW
35 ps Output-to-Output Skew
1
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, refer to Application Note
AND8002/D
PECL Mode Operating Range: VCC = 2.375 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -2.375 V to -3.8 V
Open Input Default State
ORDERING INFORMATION
•
• LVDS Input Compatible
Device
Package
MC100LVEP34D
SO- 16
48 Units/Rail
MC100LVEP34DR2
SO- 16
2500 Units/Reel
TSSOP- 16
96 Units/Rail
MC100LVEP34DT
MC100LVEP34DTR2 TSSOP- 16
 Semiconductor Components Industries, LLC, 2001
September, 2001 - Rev. 4
362
Shipping
2500 Units/Reel
Publication Order Number:
MC100LVEP34/D
MC100LVEP34
PIN DESCRIPTION
Q0
16
1
Q
Q0
÷2
15
2
R
VCC
Q1
Q
3
EN
D
R
4
14
13
NC
CLK
Q
Q1
÷4
5
12
CLK
R
VCC
6
11
PIN
FUNCTION
CLK*, CLK**
ECL Diff Clock Inputs
EN*
ECL Sync Enable
MR*
ECL Master Reset
Q0, Q0
ECL Diff ÷2 Outputs
Q1, Q1
ECL Diff ÷4 Outputs
Q2, Q2
ECL Diff ÷8 Outputs
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
NC
No Connect
VCC
VBB
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
FUNCTION TABLE
Q2
7
10
MR
CLK
EN
MR
FUNCTION
Z
ZZ
X
L
H
X
L
L
H
Divide
Hold Q0- 3
Reset Q0- 3
Q
÷8
Q2
8
9
R
VEE
Z = Low-to-High Transition
ZZ = High-to-Low Transition
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 16-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index
> 2 kV
> 200 V
> 2 kV
Level 1
UL 94 V-0 A @ 0.125 in
28 to 34
Transistor Count
210 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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363
MC100LVEP34
MAXIMUM RATINGS (Note 2)
Symbol
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL
C Mode
ode Input
u Voltage
o age
VEE = 0 V
VCC = 0 V
NECL Mode Input Voltage
Condition 2
VI VCC
VI VEE
Continuous
Surge
6
V
-6
V
50
100
mA
mA
± 0.5
mA
Iout
Output Current
IBB
VBB Sink/Source
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
16 SOIC
16 SOIC
100
60
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
16 SOIC
33 to 36
°C/W
θJA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
16 TSSOP
16 TSSOP
138
108
°C/W
°C/W
θJC
Thermal Resistance (Junction to Case)
std bd
16 TSSOP
33 to 36
°C/W
265
°C
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
100EP DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
50
60
40
50
60
42
52
62
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
Output LOW Voltage (Note 4)
555
680
925
555
680
925
555
680
925
mV
VIH
Input HIGH Voltage (Single Ended)
(Note 5)
1335
1620
1335
1620
1275
1620
mV
VIL
Input LOW Voltage (Single Ended)
(Note 5)
555
875
555
875
555
875
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5, Note 6)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
D
D
0.5
-150
150
0.5
-150
0.5
-150
µA
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC.
4. All loading with 50 ohms to VCC-2.0 volts.
5. Do not use VBB at VCC < 3.0 V. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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364
MC100LVEP34
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 7)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
50
60
40
50
60
42
52
62
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 8)
1355
1570
1725
1355
1570
1725
1355
1570
1725
mV
VIH
Input HIGH Voltage (Single Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference (Note 9)
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 10)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
1875
1875
150
D
D
1875
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.5 V.
8. All loading with 50 ohms to VCC-2.0 volts.
9. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.8 V to -2.375 V (Note 11)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
50
60
40
50
60
42
52
62
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 12)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 12)
-1945
-1700
-1575
-1945
-1700
-1575
-1945
-1700
-1575
mV
VIH
Input HIGH Voltage (Single Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Voltage Reference (Note 13)
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
-1425
VEE+1.2
0.0
VEE+1.2
150
D
D
0.5
-150
-1425
0.0
VEE+1.2
150
0.5
-150
-1425
0.5
-150
µA
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC.
12. All loading with 50 ohms to VCC-2.0 volts.
13. Single ended input CLK pin operation is limited to VEE -3.0 V in NECL mode.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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365
MC100LVEP34
AC CHARACTERISTICS VCC= 0 V; VEE= -3.8 V to -2.375 V or VCC= 2.375 V to 3.8 V; VEE= 0 V (Note 15)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
fmax
Maximum Toggle Frequency
(See Figure 4. Fmax/JITTER)
2.8
tPLH
tPHL
Propagation
Delay to Output
550
500
tJITTER
Cycle-to-Cycle Jitter
(See Figure 4. Fmax/JITTER)
tS
Setup Time EN
150
50
150
50
tH
Hold Time EN
200
100
200
tRR
Set/Reset Recovery
300
200
300
VPP
Input Swing (Note 16)
150
CLK to Q0, Q1, Q2
MR to Q
85°C
Max
2.8
650
600
750
700
600
550
<1
Min
150
700
650
800
750
650
600
366
Unit
GHz
750
700
850
800
ps
<1
ps
150
50
ps
100
200
100
ps
200
300
200
ps
1000
150
tr
Output Rise/Fall Times Q
90
170
200
100
180
250
120
tf
(20% - 80%)
15. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
16. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
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Max
2.8
<1
1000
Typ
200
1000
mV
280
ps
MC100LVEP34
There are two distinct functional relationships between the Master Reset and Clock:
Internal Clock
Disabled
Internal Clock
Enabled
MR
CLK
Q0
Q1
Q2
EN
CASE 1: If the MR is de-asserted (L-H), while the Clock is still high, the
outputs will follow the first ensuing clock rising edge.
Internal Clock
Disabled
Internal Clock
Enabled
MR
CLK
Q0
Q1
Q2
EN
CASE 2: If the MR is de-asserted (L-H), after the Clock has transitioned low, the
outputs will follow the second ensuing clock rising edge.
Figure 2. Timing Diagrams
The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will
maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will
transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted.
TRR
TRR
CLOCK
CLOCK
MR
MR
OUTPUT
OUTPUT
CASE 1
CASE 2
Figure 3. Reset Recovery Time
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367
MC100LVEP34
900
9
VOUTpp (mV)
800
8
4 / 8
700
7
600
6
2
500
5
400
4
300
3
200
2
JITTEROUT ps (RMS)
100
1
0
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 4. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Qb
Db
50 50 V TT
V TT = V CC - 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices.)
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368
MC100LVEP111
2.5V / 3.3V1:10 Differential
ECL/PECL/HSTL Clock Driver
The MC100LVEP111 is a low skew 1- to- 10 differential driver,
designed with clock distribution in mind, accepting two clock sources into
an input multiplexer. The PECL input signals can be either differential or
single- ended (if the VBB output is used). HSTL inputs can be used when
the LVEP111 is operating under PECL conditions.
The LVEP111 specifically guarantees low output- to- output skew.
Optimal design, layout, and processing minimize skew within a device and
from device to device.
To ensure tightest skew, both sides of differential outputs identically
terminate into 50 even if only one output is being used. If an output
pair is unused, both outputs may be left open (unterminated) without
affecting skew.
The MC100LVEP111, as with most other ECL devices, can be
operated from a positive VCC supply in PECL mode. This allows the
LVEP111 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. Single- ended CLK input operation is limited to a VCC ≥
3.0 V in PECL mode, or VEE ≤ -3.0 V in NECL mode. Designers can
take advantage of the LVEP111’s performance to distribute low skew
clocks across the backplane or the board. In a PECL environment, series
or Thevenin line terminations are typically used as they require no
additional power supplies. For more information on using PECL,
designers should refer to Application Note AN1406/D.
•
•
•
•
•
•
•
•
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MARKING
DIAGRAM*
MC100
LVEP111
32-LEAD LQFP
FA SUFFIX
CASE 873A
AWLYYWW
32
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, refer to Application Note
AND8002/D
85 ps Typical Device-to- Device Skew
20 ps Typical Output-to-Output Skew
Jitter Less than 1 ps RMS
Maximum Frequency > 3 Ghz Typical
ORDERING INFORMATION
VBB Output
430 ps Typical Propagation Delay
Device
Package
Shipping
The 100 Series Contains Temperature Compensation
MC100LVEP111FA
LQFP-32
250 Units/Tray
PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V
with VEE = 0 V
MC100LVEP111FAR2
LQFP-32
2000 Tape & Reel
• NECL Mode Operating Range: VCC = 0 V
with VEE = -2.375 V to -3.8 V
Open Input Default State
•
• LVDS Input Compatible
• Fully Compatible with Motorola MC100EP111
 Semiconductor Components Industries, LLC, 2002
May, 2002 - Rev. 6
369
Publication Order Number:
MC100LVEP111/D
MC100LVEP111
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
PIN DESCRIPTION
24
23
22
21
20
19
18
17
PIN
FUNCTION
VCC
25
16
VCC
CLK0*, CLK0**
ECL/PECL/HSTL CLK Input
Q2
26
15
Q7
CLK1*, CLK1**
ECL/PECL/HSTL CLK Input
Q2
27
14
Q7
Q0:9, Q0:9
ECL/PECL Outputs
Q1
28
13
Q8
CLK_SEL*
ECL/PECL Active Clock Select Input
29
12
VBB
Reference Voltage Output
Q1
Q8
VCC
Positive Supply
Q0
30
11
Q9
VEE
Negative Supply
Q0
31
10
Q9
VCC
32
9
1
2
3
4
5
6
7
8
VCC
CLK_SEL
CLK0
CLK0
VBB
CLK1
CLK1
MC100LVEP111
VEE
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
VCC
FUNCTION TABLE
CLK_SEL
Active Input
L
H
CLK0, CLK0
CLK1, CLK1
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Q0
Q0
Figure 1. 32-Lead LQFP Pinout (Top View)
Q1
Q1
Q2
Q2
Q3
Q3
CLK0
CLK0
Q4
0
Q4
Q5
CLK1
Q5
1
Q6
CLK1
VBB
CLK_SEL
VEE
Q6
Q7
Q7
Q8
VCC
Q8
Q9
Q9
Figure 2. Logic Diagram
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370
MC100LVEP111
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
37.5 k
ESD Protection
> 2 kV
> 100 V
> 2 kV
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
Level 2
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8″
28 to 34
Transistor Count
602 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
VCC
PECL Mode Power Supply
VEE = 0 V
VEE
NECL Mode Power Supply
VCC = 0 V
VI
PECL
C Mode
ode Input
u Voltage
o age
VEE = 0 V
VCC = 0 V
NECL Mode Input Voltage
Condition 2
Rating
Units
6
V
-6
V
6
V
-6
V
50
100
mA
mA
± 0.5
mA
-40 to +85
°C
VI ≤ VCC
VI ≥ VEE
Iout
Output Current
Continuous
Surge
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
265
°C
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
PECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
70
100
120
70
100
120
70
100
120
mA
VOH
Output HIGH Voltage (Note 4)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 4)
1355
1480
1695
1355
1480
1695
1355
1480
1695
mV
VIH
Input HIGH Voltage (Single-Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1490
1675
1490
1675
1490
1675
mV
VBB
Output Reference Voltage (Note 5)
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 6)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
1875
150
CLK
CLK
0.5
-150
3.
4.
5.
6.
150
0.5
-150
NOTE:
1875
0.5
-150
1875
µA
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
Input and output parameters vary 1:1 with VCC. VEE can vary + 0.925 V to -0.5 V.
All loading with 50 Ω to VCC-2.0 volts.
Single ended input operation is limited VCC ≥ 3.0 V in PECL mode.
VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC100LVEP111
PECL DC CHARACTERISTICS VCC = 2.5 V; VEE = 0 V (Note 7)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
70
100
120
70
100
120
70
100
120
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
Output LOW Voltage (Note 8)
555
680
895
555
680
895
555
680
895
mV
VIH
Input HIGH Voltage (Single-Ended)
(Note 9)
1335
1620
1335
1620
1275
1620
mV
VIL
Input LOW Voltage (Single-Ended)
(Note 9)
555
875
555
875
555
875
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 10)
1.2
2.5
1.2
2.5
1.2
2.5
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
CLK
CLK
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE:
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.125 V to -1.3 V.
8. All loading with 50 Ω to VEE.
9. Do not use VBB at VCC < 3.0 V.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
NECL DC CHARACTERISTICS VCC = 0 V, VEE = -2.375 V to -3.8 V (Note 11)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
70
100
120
70
100
120
70
100
120
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 12)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 12)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1 165
-880
-1 165
-880
-1 165
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1810
-1625
-1810
-1625
-1810
-1625
mV
VBB
Output Reference Voltage (Note 13)
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
-1425
VEE + 1.2
0.0
-1425
VEE + 1.2
150
CLK
CLK
0.5
-150
0.0
-1425
VEE + 1.2
150
0.5
-150
µA
0.5
-150
NOTE:
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC.
12. All loading with 50 Ω to VCC-2.0 volts.
13. Single ended input operation is limited VEE ≤ -3.0V in NECL mode.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
HSTL DC CHARACTERISTICS VCC = 2.375 to 3.8 V, VEE = 0 V
-40 °C
Symbol
Characteristic
Min
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
V
Input Crossover Voltage
680
ICC
Power Supply Current
70
Typ
25°C
Max
1200
Min
Typ
85°C
Max
1200
680
120
70
372
Max
100
900
680
120
70
Unit
mV
400
900
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Typ
1200
400
100
Min
100
400
mV
900
mV
120
mA
MC100LVEP111
AC CHARACTERISTICS VCC = 0 V; VEE = -2.375 to -3.8 V or VCC = 2.375 to 3.8 V; VEE = 0 V (Note 15)
-40 °C
Characteristic
Min
fmaxPECL/HSTL
Maximum Frequency
(See Figure 3. Fmax/JITTER)
tPLH
tPHL
Propagation Delay (Differential)
tskew
Typ
Max
Min
>3
325
475
Within- Device Skew (Note 16)
Within- Device Skew @ 2.5 V (Note 16)
Device- to- Device Skew (Note 17)
20
20
85
tJITTER
Cycle-to-Cycle Jitter
(See Figure 3. Fmax/JITTER)
VPP
Minimum Input Swing
350
Min
500
25
25
150
20
20
85
0.2
<1
800
1200
150
440
25
25
150
25
20
85
35
25
150
ps
0.2
<1
0.2
<1
ps
800
1200
150
800
1200
mV
275
150
230
320
ps
7
600
6
500
5
400
4
300
3
200
2
(JITTER)
100
1
É
É
0
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 3. Fmax/Jitter
D
Q
Receiver
Device
Driver
Device
D
Q
50 Ω
50 Ω
VTT
VTT = VCC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices.)
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373
GHz
ps
700
1000
Unit
590
8
0
Max
510
800
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
Typ
>3
430
tr/tf
Output Rise/Fall Time (20%-80%)
105
200
255
125
200
15. Measured with 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC-2 V.
16. Skew is measured between outputs under identical transitions and conditions on any one device.
17. Device-to-Device skew for identical transitions at identical VCC levels.
VOUTpp (mV)
Max
>3
400
150
Typ
85°C
JITTEROUT ps (RMS)
Symbol
25°C
MC100LVEP210
2.5V / 3.3V1:5 Dual
Differential ECL/PECL/HSTL
Clock Driver
The MC100LVEP210 is a low skew 1- to- 5 dual differential driver,
designed with clock distribution in mind. The ECL/PECL input signals
can be either differential or single- ended if the VBB output is used. The
signal is fanned out to 5 identical differential outputs. HSTL inputs can be
used when the EP210 is operating in PECL mode.
The LVEP210 specifically guarantees low output- to- output skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
To ensure the tight skew specification is realized, both sides of the
differential output need to be terminated identically into 50 Ω even if
only one output is being used. If an output pair is unused, both outputs
may be left open (unterminated) without affecting skew.
The MC100LVEP210, as with most other ECL devices, can be
operated from a positive VCC supply in PECL mode. This allows the
LVEP210 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. Single- ended CLK input operation is limited to a VCC ≥
3.0 V in PECL mode, or VEE ≤ -3.0 V in ECL mode.
Designers can take advantage of the LVEP210’s performance to
distribute low skew clocks across the backplane or the board. In a PECL
environment, series or Thevenin line terminations are typically used as
they require no additional power supplies. For more information on using
PECL, designers should refer to Application Note AN1406/D.
•
•
•
•
•
•
•
•
•
85 ps Typical Device-to- Device Skew
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MARKING
DIAGRAM*
MC100
LVEP210
32-LEAD LQFP
FA SUFFIX
CASE 873A
AWLYYWW
32
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
20 ps Typical Output-to-Output Skew
VBB Output
Jitter Less than 1 ps RMS
350 ps Typical Propagation Delay
ORDERING INFORMATION
Maximum Frequency > 3 GHz Typical
Device
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -2.375 V to -3.8 V
Open Input Default State
Package
Shipping
MC100LVEP210FA
LQFP
250 Units/Tray
MC100LVEP210FAR2
LQFP
2000 Tape & Reel
•
• LVDS Input Compatible
• Fully Compatible with Motorola MC100EP210
 Semiconductor Components Industries, LLC, 2002
January, 2002 - Rev. 6
374
Publication Order Number:
MC100LVEP210/D
MC100LVEP210
Qa3 Qa3 Qa4 Qa4 Qb0 Qb0 Qb1 Qb1
24
23
22
21
20
19
18
17
VCC
25
16
VCC
Qa2
26
15
Qb2
Qa2
27
14
Qb2
CLKn*, CLKn**
ECL/PECL/HSTL CLK Inputs
Qa1
28
13
Qb3
Qn0:4, Qn0:4
ECL/PECL Outputs
12
Qb3
VBB
Reference Voltage Output
MC100LVEP210
PIN DESCRIPTION
PIN
FUNCTION
11
Qb4
VCC
Positive Supply
Qa0
31
10
Qb4
VEE
Negative Supply
VCC
32
9
VCC
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
1
2
VCC NC
3
4
5
6
7
8
VBB
CLKb
30
CLKb
Qa0
CLKa
29
CLKa
Qa1
VEE
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
Qa0
Qb0
Qa0
Qb0
Qb1
Qa1
CLKa
CLKb
Qa1
CLKa
Qa2
Qb1
CLKb
Qb2
Qb2
Qa2
Qa3
Qb3
VBB
Qa3
Qb3
VCC
VEE
Qa4
Qa4
Qb4
Qb4
Figure 2. Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pull-up Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
> 2 kV
> 100 V
> 2 kV
Level 2
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8″
28 to 34
Transistor Count
461 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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375
MC100LVEP210
MAXIMUM RATINGS (Note 2)
Symbol
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL
C Mode
ode Input
u Voltage
o age
VEE = 0 V
VCC = 0 V
NECL Mode Input Voltage
Condition 2
VI ≤ VCC
VI ≥ VEE
Continuous
Surge
6
V
-6
V
50
100
mA
mA
± 0.5
mA
Iout
Output Current
IBB
VBB Sink/Source
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
θJA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
θJC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
265
°C
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
PECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
60
70
90
60
70
90
60
70
90
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 4)
1355
1480
1695
1355
1480
1695
1355
1480
1695
mV
VIH
Input HIGH Voltage (Single-Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1490
1675
1490
1675
1490
1675
mV
VBB
Output Reference Voltage (Note 5)
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 6)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
1875
150
CLK
CLK
0.5
-150
3.
4.
5.
6.
150
0.5
-150
NOTE:
1875
0.5
-150
1875
µA
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
Input and output parameters vary 1:1 with VCC. VEE can vary + 0.925 V to -0.5 V.
All loading with 50 Ω to VCC-2.0 volts.
Single ended input operation is limited VCC ≥ 3.0 V in PECL mode.
VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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376
MC100LVEP210
PECL DC CHARACTERISTICS VCC = 2.5 V; VEE = 0 V (Note 7)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
60
70
90
60
70
90
60
70
90
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
Output LOW Voltage (Note 8)
555
680
895
555
680
895
555
680
895
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 9)
1.2
2.5
1.2
2.5
1.2
2.5
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
CLK
CLK
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE:
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC.. VEE can vary + 0.125 V to -1.3 V.
8. All loading with 50 Ω to VEE.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
NECL DC CHARACTERISTICS VCC = 0 V, VEE = -2.375 V to -3.8 V (Note 10)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
60
70
90
60
70
90
60
70
90
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 11)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 11)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1 165
-880
-1 165
-880
-1 165
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1810
-1625
-1810
-1625
-1810
-1625
mV
VBB
Output Reference Voltage (Note 12)
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 13)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
150
µA
-1425
VEE + 1.2
0.0
-1425
VEE + 1.2
150
CLK
CLK
0.5
-150
0.0
-1425
VEE + 1.2
150
0.5
-150
0.5
-150
NOTE:
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
10. Input and output parameters vary 1:1 with VCC.
11. All loading with 50 Ω to VCC-2.0 volts.
12. Single ended input operation is limited VEE ≤ -3.0V in NECL mode.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
HSTL DC CHARACTERISTICS VCC = 2.375 to 3.8 V, VEE = 0 V
-40 °C
Symbol
Characteristic
Min
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
V
Input Crossover Voltage
680
ICC
Power Supply Current
60
Typ
25°C
Max
1200
Min
Typ
85°C
Max
1200
680
90
60
377
Max
70
900
680
90
60
Unit
mV
400
900
http://onsemi.com
Typ
1200
400
70
Min
70
400
mV
900
mV
90
mA
MC100LVEP210
AC CHARACTERISTICS VCC = 0 V; VEE = -2.375 to -3.8 V or VCC = 2.375 to 3.8 V; VEE = 0 V (Note 14)
-40 °C
Characteristic
fmaxPECL/
HSTL
Maximum Frequency
(See Figure 3. Fmax/JITTER)
tPLH
tPHL
Propagation Delay
Propagation Delay @ 2.5 V
tskew
Min
Typ
Max
Min
>3
220
380
Within- Device Skew (Note 15)
Device- to- Device Skew (Note 16)
20
85
tJITTER
Cycle-to-Cycle Jitter
(See Figure 3. Fmax/JITTER)
VPP
Minimum Input Swing
270
Min
430
25
160
20
85
0.2
<1
800
1200
150
300
330
25
160
20
85
35
160
ps
0.2
<1
0.2
<1
ps
800
1200
150
800
1200
mV
270
150
280
350
ps
7
600
6
500
5
400
4
300
3
200
2
ÉÉ
ÉÉ
(JITTER)
100
1
0
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 3. Fmax/Jitter
D
Q
Receiver
Device
Driver
Device
D
Q
50 Ω
50 Ω
VTT
VTT = VCC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices.)
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378
GHz
ps
700
1000
Unit
750
490
8
0
Max
500
410
800
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
Typ
>3
350
tr/tf
Output Rise/Fall Time (20%-80%)
100
170
250
120
190
14. Measured with 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC-2 V.
15. Skew is measured between outputs under identical transitions of similar paths through a device.
16. Device-to-Device skew for identical transitions at identical VCC levels.
VOUTpp (mV)
Max
>3
300
150
Typ
85°C
JITTEROUT ps (RMS)
Symbol
25°C
MC100EP210S
2.5V1:5 Dual Differential
LVDS Compatible Clock
Driver
The MC100EP210S is a low skew 1-to-5 dual differential driver,
designed with LVDS clock distribution in mind. The LVDS or
LVPECL input signals are differential and the signal is fanned out to
five identical differential LVDS outputs.
The EP210S specifically guarantees low output-to-output skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
Two internal 50 resistors are provided across the inputs. For
LVDS inputs, VTA and VTB pins should be unconnected. For
LVPECL inputs, VTA and VTB pins should be connected to the VTT
(VCC-2.0 V) supply.
Designers can take advantage of the EP210S performance to
distribute low skew LVDS clocks across the backplane or the board.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
•
•
•
•
•
•
•
•
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MARKING
DIAGRAM*
MC100
EP210S
LQFP-32
FA SUFFIX
CASE 873A
AWLYYWW
32
1
A
WL
YY
WW
20 ps Typical Output-to-Output Skew
85 ps Typical Device-to- Device Skew
= Assembly Location
= Wafer Lot
= Year
= Work Week
550 ps Typical Propagation Delay
The 100 Series Contains Temperature Compensation
*For additional information, refer to Application Note
AND8002/D
Maximum Frequency > 1 GHz Typical
Operating Range: VCC = 2.375 V to 2.625 V with VEE = 0 V
Internal 50 Input Termination Resistors
LVDS Input/Output Compatible
ORDERING INFORMATION
 Semiconductor Components Industries, LLC, 2002
May, 2002 - Rev. 5
379
Device
Package
Shipping
MC100EP210SFA
LQFP-32
250 Units/Tray
MC100EP210SFAR2
LQFP-32 2000 Tape & Reel
Publication Order Number:
MC100EP210S/D
MC100EP210S
Qa3 Qa3 Qa4 Qa4 Qb0 Qb0 Qb1 Qb1
24
23
22
21
20
19
18
17
VCC
25
16
VCC
Qa2
26
15
Qb2
Qa2
27
14
Qb2
Qa1
28
13
Qb3
Qa1
29
Qb3
VTA
50 Ω Termination Resistors
MC100EP210S
12
Qa0
31
10
Qb4
VCC
32
9
VCC
1
2
VEE VTA
3
4
5
6
7
8
VTB
CLKb
Qb4
CLKb
11
CLKa
30
CLKa
Qa0
VEE
PIN DESCRIPTION
PIN
FUNCTION
CLKn, CLKn
LVDS, LVPECL CLK Inputs
Qn0:4, Qn0:4
LVDS Outputs
VTB
50 Ω Termination Resistors
VCC
Positive Supply
VEE
Ground
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
VTA
50 VTB
Qa0
Qa0
50 50 Qb0
Qb0
50 Qa1
CLKa
Qa1
CLKa
Qa2
Qb1
CLKb
Qb1
CLKb
Qb2
Qa2
Qb2
Qa3
Qb3
Qa3
Qb3
Qa4
Qb4
Qa4
Qb4
Figure 2. Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
> 2 kV
> 100 V
> 2 kV
Level 2
Flammability Rating
Oxygen Index
UL-94 code V-0 A 1/8″
28 to 34
Transistor Count
461 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
http://onsemi.com
380
MC100EP210S
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
VEE = 0 V
VCC = 2.5 V
Rating
Units
6
V
-6
V
VCC
VEE
Power Supply
VI
Iout
LVDS LVPECL Input Voltage
LVDS,
TA
Operating Temperature Range
Tstg
θJA
Storage Temperature Range
-65 to +150
°C
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
θJC
Tsol
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
Power Supply (GND)
VI ≤ VCC
VEE = 0 V
Continuous
Surge
Output Current
6
V
50
100
mA
mA
-40 to +85
°C
2. Maximum Ratings are those values beyond which device damage may occur.
DC CHARACTERISTICS VCC = 2.5 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
Min
25°C
Typ
Max
150
200
Min
85°C
Typ
Max
150
200
Min
Typ
Max
Unit
150
200
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
1250
1400
1550
1250
1400
1550
1250
1400
1550
mV
VOL
Output LOW Voltage (Note 4)
800
950
1100
800
950
1100
800
950
1100
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
1.2
2.5
1.2
2.5
1.2
2.5
V
RT
Internal Termination Resistor
43
57
43
57
43
57
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
50
150
CLK
CLK
150
0.5
-150
0.5
-150
µA
0.5
-150
NOTE:
100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC.
4. All loading with 100 Ω across LVDS differential outputs.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 2.375 to 2.625 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
fmaxLVDS/
LVPECL
Maximum Frequency
(See Figure 3. Fmax/JITTER)
tPLH
tPHL
Propagation Delay
tskew
Min
Typ
25°C
Max
Min
>1
425
Max
Min
>1
525
625
Within- Device Skew (Note 7)
Device- to- Device Skew (Note 8)
Duty Cycle Skew (Note 9)
20
85
80
tJITTER
Cycle-to-Cycle Jitter
(See Figure 3. Fmax/JITTER)
VPP
Minimum Input Swing
150
Typ
85°C
450
Max
>1
550
650
25
160
100
20
85
80
.2
<1
800
1200
150
Typ
475
Unit
GHz
575
675
ps
25
160
100
20
85
80
35
160
100
ps
.2
<1
.2
<1
ps
800
1200
800
1200
mV
150
tr/tf
Output Rise/Fall Time (20%-80%)
50
130
200
75
150
225
80
160
230
ps
6. Measured with 400 mV source, 50% duty cycle clock source. All loading with 100 Ω across differential outputs.
7. Skew is measured between outputs under identical transitions of similar paths through a device.
8. Device-to-Device skew for identical transitions at identical VCC levels.
9. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
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381
MC100EP210S
450
9
Simulated
8
350
7
300
6
250
5
200
4
150
3
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
100
ÉÉ
ÉÉ
ÉÉ
2
(JITTER)
50
1
0
0
200
400
600
800
1000
1200
1400
FREQUENCY (MHz)
Figure 3. Fmax/Jitter
Q
Driver
Device
D
Recceiver
Device
100 Ω
D
Q
Figure 4. Typical Termination for Output Driver and Device Evaluation
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382
JITTEROUT ps (RMS)
VOUTpp (mV)
400
CHAPTER 4
Case Outlines and Package Dimensions
http://onsemi.com
383
Logic Devices
Device Nomenclatures
ECLinPS, ECLinPS Lite, ECLinPS Plus
MC
WWW
XXX
YYY
ZZ
Package Type
• FN = PLCC
• D = Plastic SOIC
• L = Ceramic DIP
• P = Plastic DIP
Circuit Identifier
• MC = Fully Qualified Circuit
• XC = Non Reliability Qualified
Function Type
• YYY = 3-Digits for ECLinPS
• YY= 2-Digits for ECLinPS Lite
Compatibility Identifier
• 10 = 10H Compatible (0 to +85°C)
• 100 = 100K Compatible (0 to +85°C)
ECLinPS Family Identifier
• E = ECLinPS
• EL = ECLinPS Lite
• ELT = ECLinPS Lite Translator
• EP = ECLinPS Plus
• EPT = ECLinPS Plus Translator
• LVEP = Low Voltage ECLinPS Plus
• LVE = Low Voltage ECLinPS
• LVEL = Low Voltage ECLinPS Lite
• LVELT = Low Voltage ECLinPS
Lite Translator
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384
CASE OUTLINES AND PACKAGE DIMENSIONS
SO-8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-07
ISSUE AA
-X-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDAARD IS 751−07
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
-YG
C
N
X 45 SEATING
PLANE
-Z-
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
X
S
J
S
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
TSSOP-8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R-02
ISSUE A
8x
0.15 (0.006) T U
K REF
0.10 (0.004)
S
2X
L/2
8
1
PIN 1
IDENT
S
T U
S
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
5
0.25 (0.010)
B
-U-
L
0.15 (0.006) T U
M
M
4
A
-V-
F
DETAIL E
C
0.10 (0.004)
-T-
SEATING
PLANE
D
-WG
DETAIL E
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385
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0
6
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0
6
CASE OUTLINES AND PACKAGE DIMENSIONS
SO-16
D SUFFIX
CASE 751B-05
ISSUE J
-A16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
-B1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
DIM
A
B
C
D
F
G
J
K
M
P
R
F
X 45 C
-T-
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
0.10 (0.004)
M
T U
V
S
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
K1
2X
L/2
16
9
J1
B
-U-
L
SECTION N-N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
-V-
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
F
DETAIL E
-W-
C
0.10 (0.004)
-T-
SEATING
PLANE
H
D
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.229
0.244
0.010
0.019
TSSOP-16
DT SUFFIX
CASE 948F-01
ISSUE O
16X K REF
0.15 (0.006) T U
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
DETAIL E
G
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386
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
−−−
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
CASE OUTLINES AND PACKAGE DIMENSIONS
SO-20
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-05
ISSUE F
D
20
X 45 h
1
10
20X
DIM
A
A1
B
C
D
E
e
H
h
L
B
B
0.25
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
A
e
18X
SEATING
PLANE
A1
C
T
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0
7
TSSOP-20
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E-02
ISSUE A
20X
0.15 (0.006) T U
2X
S
20
L/2
M
T U
S
V
S
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
B
L
J J1
-U-
PIN 1
IDENT
SECTION N-N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25
(0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
K REF
0.10 (0.004)
S
M
A
-VN
F
DETAIL E
-W-
C
D
G
H
DETAIL E
0.100 (0.004)
-T-
SEATING
PLANE
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387
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
1.20
−−−
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
0.047
−−−
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
PACKAGE DIMENSIONS
A
32
-T-, -U-, -Z-
TQFP
FA SUFFIX
32-LEAD PLASTIC PACKAGE
CASE 873A-02
ISSUE A
4X
A1
0.20 (0.008) AB T−U Z
25
1
-U-
-TB
V
AE
P
B1
DETAIL Y
17
8
AE
DETAIL Y
9
4X
-Z9
V1
0.20 (0.008) AC T−U Z
S1
S
DETAIL AD
G
-AB0.10 (0.004) AC
AC T−U Z
-ACBASE
METAL
ÉÉ
ÉÉ
ÉÉ
ÉÉ
F
8X
M
R
M
N
D
J
0.20 (0.008)
SEATING
PLANE
SECTION AE-AE
W
K
X
DETAIL AD
Q
GAUGE PLANE
H
0.250 (0.010)
C E
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388
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED
AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12 REF
0.090
0.160
0.400 BSC
1
5
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12 REF
0.004
0.006
0.016 BSC
1
5
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
CHAPTER 5
Index
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389
Index
Device Number
Page
Device Number
Page
Device Number
Page
MC100EP01
10
MC100EP40
129
MC10EP105
MC100EP016
178
MC100EP445
266
MC10EP11
28
MC100EP016A
188
MC100EP446
281
MC10EP116
209
MC100EP05
16
MC100EP451
297
MC10EP131
216
MC100EP08
22
MC100EP51
134
MC10EP139
222
MC100EP101
197
MC100EP52
140
MC10EP142
234
MC100EP105
203
MC100EP56
146
MC10EP16
39
MC100EP11
28
MC100EP57
153
MC100EP116
209
MC10EP16T
50
MC100EP58
160
MC100EP131
216
MC10EP16VA
56
MC100EP809
303
MC100EP139
222
MC100EP90
172
MC100EPT20
310
MC100EPT21
314
MC100EPT22
318
MC100EPT23
322
MC100EPT24
326
MC100EPT25
330
MC100EPT26
334
MC100EP14
34
MC100EP140
229
MC100EP142
234
MC100EP16
39
MC100EP16F
45
MC100EP16T
50
MC100EP16VA
56
MC100EP16VB
62
MC100EP16VC
67
MC100EP16VS
74
MC100EP16VT
82
MC100EP17
203
MC10EP17
90
MC10EP195
242
MC10EP29
96
MC10EP31
103
MC10EP32
109
MC10EP33
116
MC10EP35
123
MC10EP445
266
MC10EP446
281
MC10EP451
297
MC10EP51
134
MC10EP52
140
MC100EPT622
338
MC100LVEP11
344
MC100LVEP111
369
90
MC100LVEP14
350
MC100EP195
242
MC100LVEP16
356
MC10EP56
146
MC100EP196
255
MC100LVEP210
374
MC10EP57
153
362
MC10EP58
160
MC100EP210S
379
MC100LVEP34
MC100EP29
96
MC10EP01
10
MC10EP89
166
MC100EP31
103
MC10EP016
178
MC10EP90
172
MC100EP32
109
MC10EP05
16
MC10EPT20
310
MC100EP33
116
MC10EP08
22
MC10LVEP11
344
MC100EP35
123
MC10EP101
197
MC10LVEP16
356
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390
ON SEMICONDUCTOR MAJOR WORLDWIDE SALES OFFICES
AND REPRESENTATIVES
UNITED STATES
UNITED STATES (continued)
NORTH CAROLINA
ALABAMA
Huntsville . . . . . . . . . . . . . . . . . . 256-774-1010
Huntsville (Sales Rep) . . . . . . . . 256-705-5205
ARIZONA
Phoenix (Sales Rep) . . . . . . . . . . 480-769-0968
CALIFORNIA
Los Angeles (Sales Rep) . . . . . .
Sacramento (Sales Rep) . . . . . .
Santa Clara (Sales Rep) . . . . . . .
San Diego (Sales Rep) . . . . . . . .
949-580-0270
916-652-0268
408-350-3900
858-635-5960
COLORADO
Denver (Sales Rep) . . . . . . . . . . . 303-741-0900
CONNECTICUT
Southbury . . . . . . . . . . . . . . . . . . 203-267-5451
FLORIDA
Boca Raton . . . . . . . . . . . . . . . . 561-995-1466
Tampa . . . . . . . . . . . . . . . . . . . . . 813-286-6181
Raleigh (Sales Rep) . . . . . . . . . . 919-845-9900
OREGON
Portland . . . . . . . . . . . . . . . . . . . 503-590-5852
IDAHO
Boise (Sales Rep) . . . . . . . . . . . . 208-424-1002
ILLINOIS
Chicago . . . . . . . . . . . . . . . . . . . 847-330-6979
Itasca (Sales Rep) . . . . . . . . . . . . 630-250-9586
INDIANA
Carmel (Sales Rep) . . . . . . . . . . . 317-848-9958
Kokomo . . . . . . . . . . . . . . . . . . . 765-865-2085
Kokomo (Sales Rep) . . . . . . . . . . 765-455-0777
MARYLAND
Philadelphia/Horsham . . . . . . . 215-997-4340
Hatboro (Sales Rep) . . . . . . . . . . 215-957-0600
Austin (Sales Rep) . . . . . . . . . . . . 512-343-1 199
Dallas (Sales Rep) . . . . . . . . . . . . 972-680-2800
Houston (Sales Rep) . . . . . . . . . . 281-999-0101
Livonia . . . . . . . . . . . . . . . . . . . . 734-953-6704
MINNESOTA
Plymouth . . . . . . . . . . . . . . . . . . 763-249-2360
MISSOURI
St. Louis . . . . . . . . . . . . . . . . . . . 618-288-0619
NEW YORK
New York Metro (Sales Rep) . . . 516-466-2300
Binghamton (Sales Rep) . . . . . . 607-722-3580
Rochester (Sales Rep) . . . . . . . . 585-385-6500
HONG KONG
Hong Kong . . . . . . . . . . . . . . . . 852-2689-0088
Bangalore . . . . . . . . . . . . . . . . 91-80-226-7272
ISRAEL
Herzelia . . . . . . . . . . . . . . 972 (0) 9-9609-111
ITALY
UTAH
Draper (Sales Rep) . . . . . . . . . . . 801-572-4010
Milan . . . . . . . . . . . . . . . . . . 39 (0) 2-530-0951
JAPAN
VIRGINIA
Herndon (Sales Rep) . . . . . . . . . 804-897-6007
Tokyo . . . . . . . . . . . . . . . . . . . 81-3-5740-2737
KOREA
WISCONSIN
Brookfield (Sales Rep) . . . . . . . . 262-797-7977
Seoul . . . . . . . . . . . . . . . . . . . . . 82-2-528-2700
MALAYSIA
Penang . . . . . . . . . . . . . . . . . . . 60-4-226-9368
MEXICO
CANADA
ALBERTA
Calgary (Sales Rep) . . . . . . . . . . 403-730-6225
BRITISH COLUMBIA
Vancouver (Sales Rep) . . . . . . . . 604-532-3881
ONTARIO
Nepean (Sales Rep) . . . . . . . . . . 613-596-9294
Toronto . . . . . . . . . . . . . . . . . . . . 905-812-0092
Mississauga (Sales Rep) . . . . . . 905-607-1444
QUEBEC
Mascouche (Sales Rep) . . . . . . . 450-966-9530
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ON SEMICONDUCTOR STANDARD DOCUMENT TYPE DEFINITIONS
DATA SHEET CLASSIFICATIONS
A Data Sheet is the fundamental publication for each individual product/device, or series of products/devices, containing detailed
parametric information and any other key information needed in using, designing-in or purchasing of the product(s)/device(s) it describes.
Below are the three classifications of Data Sheet: Product Preview; Advance Information; and Fully Released Technical Data
PRODUCT PREVIEW
A Product Preview is a summary document for a product/device under consideration or in the early stages of development. The
Product Preview exists only until an “Advance Information” document is published that replaces it. The Product Preview is often
used as the first section or chapter in a corresponding reference manual. The Product Preview displays the following disclaimer at
the bottom of the first page: “This document contains information on a product under development. ON Semiconductor reserves the
right to change or discontinue this product without notice.”
ADVANCE INFORMATION
The Advance Information document is for a device that is NOT fully qualified, but is in the final stages of the release process,
and for which production is eminent. While the commitment has been made to produce the device, final characterization and
qualification may not be complete. The Advance Information document is replaced with the “Fully Released Technical Data”
document once the device/part becomes fully qualified. The Advance Information document displays the following disclaimer at
the bottom of the first page: “This document contains information on a new product. Specifications and information herein are subject
to change without notice.”
FULLY RELEASED TECHNICAL DATA
The Fully Released Technical Data document is for a product/device that is in full production (i.e., fully released). It replaces the
Advance Information document and represents a part that is fully qualified. The Fully Released Technical Data document is virtually
the same document as the Product Preview and the Advance Information document with the exception that it provides information
that is unavailable for a product in the early phases of development, such as complete parametric characterization data. The Fully
Released Technical Data document is also a more comprehensive document than either of its earlier incarnations. This document
displays no disclaimer, and while it may be informally referred to as a “data sheet,” it is not labeled as such.
DATA BOOK
A Data Book is a publication that contains primarily a collection of Data Sheets, general family and/or parametric information,
Application Notes and any other information needed as reference or support material for the Data Sheets. It may also contain cross reference
or selector guide information, detailed quality and reliability information, packaging and case outline information, etc.
APPLICATION NOTE
An Application Note is a document that contains real-world application information about how a specific ON Semiconductor
device/product is used, or information that is pertinent to its use. It is designed to address a particular technical issue. Parts and/or software
must already exist and be available.
SELECTOR GUIDE
A Selector Guide is a document published, generally at set intervals, that contains key line-item, device-specific information for
particular products or families. The Selector Guide is designed to be a quick reference tool that will assist a customer in determining the
availability of a particular device, along with its key parameters and available packaging options. In essence, it allows a customer to quickly
“select” a device. For detailed design and parametric information, the customer would then refer to the device’s Data Sheet. The Master
Components Selector Guide (SG388/D) is a listing of ALL currently available ON Semiconductor devices.
REFERENCE MANUAL
A Reference Manual is a publication that contains a comprehensive system or device-specific descriptions of the structure and function
(operation) of a particular part/system; used overwhelmingly to describe the functionality or application of a device, series of devices or
device category. Procedural information in a Reference Manual is limited to less than 40 percent (usually much less).
HANDBOOK
A Handbook is a publication that contains a collection of information on almost any give subject which does not fall into the Reference
Manual definition. The subject matter can consist of information ranging from a device specific design information, to system design, to
quality and reliability information.
ADDENDUM
A documentation Addendum is a supplemental publication that contains missing information or replaces preliminary information in the
primary publication it supports. Individual addendum items are published cumulatively. The Addendum is destroyed upon the next revision
of the primary document.
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