Logic_Data.pdf

Digital Logic
Pocket Data Book
2003
SLL
Digital Logic
Pocket Data Book
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Copyright  2002, Texas Instruments Incorporated
Little Logic
Supply Voltage VCC (V)
Operating Free-air
Temperature Ta (℃)
SN74AUC1G/2G/3G
0.8∼2.7
–40∼85
SN74LVC1G/2G/3G
Series
1.65∼5.5
–40∼85
SN74AHC1G
2.0∼5.5
–40∼85
SN74AHC1GxxH
2.0∼5.5
–40∼85
SN74AHC2GxxH
2.0∼5.5
–40∼85
SN74AHCT1G
4.5∼5.5
–40∼85
GATE/OCTAL/WidebusTM/Widebus+
Supply Voltage VCC (V)
Operating Free-air
Temperature Ta (℃)
SN74ABT
4.5∼5.5
–40∼85
SN74BCT
SN74F
SN74ALS
SN74AS
4.5∼5.5
0∼70
4.75∼5.25
0∼70
SN74AC
SN74AC11
SN74AHC
2.0∼5.5
–40∼85
SN74HC
2.0∼6.0
–40∼85
SN74LV
2.0∼5.5
–40∼85
SN74LVC
2.0∼3.6
–40∼85
SN74LVT
2.7∼3.6
–40∼85
SN74ALVC
1.65∼3.6
–40∼85
SN74ALVT
2.3∼3.6
–40∼85
SN74AVC
1.4∼3.6
–40∼85
Series
SN74LS
SN74S
SN74xx(STD)
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA
information current as of publication date. Products conform to specifications per the
terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
See www.ti.com/sc/logic for the most current data sheets.
INDEX
Function
Device
Page
Device
TTL
CMOS SN74
BiCMOS
Page
TTL
CMOS SN74
BiCMOS
Function
1G00 SINGLE 2-INPUT POSITIVE-NAND GATE
27
00
QUAD 2-INPUT NAND
139
1G02 SINGLE 2-INPUT POSITIVE-NOR GATE
27
01
QUAD 2-INPUT NAND O.C.
140
1G04 SINGLE INVERTER GATE
28
02
QUAD 2-INPUT NOR
141
1GU04 SINGLE INVERTER GATE
28
03
QUAD 2-INPUT NAND O.C.
142
1G06 SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT
29
04
HEX INVERTERS
143
1G07 SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT
29
U04
HEX INVERTERS
144
1G08 SINGLE 2-INPUT POSITIVE-AND GATE
30
05
HEX INVERTERS O.C
144
1G14 SINGLE SCHMITT-TRIGGER INVERTER
30
06
HEX INVERTER BUFFERS/DRIVERS O.C
145
1G17 SINGLE SCHMITT-TRIGGER BUFFER
31
07
HEX BUFFERS/DRIVERS O.C
145
1G18 1-OF-2 NONINVERTING DEMULTIPLEXER
WITH 3-STATE DESELECTED OUTPUT
31
08
QUAD 2-INPUT AND
146
09
QUAD 2-INPUT AND O.C
147
1G32 SINGLE 2-INPUT POSITIVE-OR GATE
32
10
TRIPLE 3-INPUT NAND
148
1G66 SINGLE ABILATERAL ANALOG SWITCH
32
11
TRIPLE 3-INPUT AND
149
1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
33
14
HEX SCHMITT-TRIGGER INVERTERS
150
1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
33
16
HEX INVERTER BUFFERS/DRIVERS O.C
151
1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE
34
17
HEX BUFFERS/DRIVERS O.C
151
1G125 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
34
19
HEX SCHMITT-TRIGGER INVERTERS
152
1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
35
20
DUAL 4-INPUT NAND
153
1G240 SINGLE BUFFER/DRIVER WITH 3-STATE OUTPUT
35
21
DUAL 4-INPUT AND
154
2G00 DUAL 2-INPUT POSITIVE-NAND GATE
36
25
DUAL 4-INPUT NOR WITH STROBE
154
2G02 DUAL 2-INPUT POSITIVE-NOR GATE
36
26
QUAD 2-INPUT HIGH VOLTAGE INTERFACE NAND
155
2G04 DUAL INVERTER GATE
37
27
TRIPLE 3-INPUT NOR
155
2GU04 DUAL INVERTER GATE
37
30
8-INPUT NAND
156
2G06 DUAL BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
38
31
DELAY ELEMENTS
156
2G07 DUAL BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
38
32
QUAD 2-INPUT OR
157
2G08 DUAL 2-INPUT POSITIVE-AND GATE
39
33
QUAD 2-INPUT NOR BUFFERS O.C.
158
2G14 DUAL SCHMITT-TRIGGER INVERTER
39
35
HEX NON-INVERTERS WITH O.C.
158
2G17 DUAL SCHMITT-TRIGGER BUFFER
40
37
QUAD 2-INPUT NAND BUFFERS
159
2G32 DUAL 2-INPUT POSITIVE-OR GATE
40
38
QUAD 2-INPUT NAND BUFFERS O.C.
159
2G34 DUAL BUFFER GATE
41
42
4-LINE TO 10-LINE DECODER
160
2G53 DUAL ANALOG MULTIPLEXER/DEMULTIPLEXER
41
45
BCD-TO-DECIMAL DECODER/DRIVER
162
42
47
BCD-TO-SEVEN SEGMENT DECODERS/DRIVERS
164
42
51
AND-OR-INVERT
166
2G66 DUAL BILATERAL ANALOG SWITCH
2G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE
FLIP-FLOP WITH CLEAR AND PRESET
64
4-2-3-2 INPUT AND-OR-INVERT
167
2G86 DUAL 2-INPUT EXCLUSIVE-OR GATE
43
73
DUAL J-K FLIP-FLOPS
168
2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
43
74
DUAL D-TYPE FLIP-FLOPS
170
2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
44
75
4-BIT BISTABLE LATCHES
172
2G157 SINGLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER
44
85
4-BIT COMPARATORS
173
2G240 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
45
86
QUAD 2-INPUT EXCLUSIVE-OR
174
2G241 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
45
90
DECADE COUNTER
175
3G04 TRIPLE INVERTER GATE
46
92
DIVIDE-BY-12 COUNTERS
176
TRIPLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
46
93
4-BIT BINARY COUNTERS
177
3G07 TRIPLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
47
3G14 TRIPLE SCHMITT-TRIGGER INVERTER
47
3G17 TRIPLE SCHMITT-TRIGGER BUFFER
48
3G34 TRIPLE BUFFER GATE
48
3G06
97
SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIER
178
107
DUAL J-K FLIP-FLOPS
180
109
DUAL J-K FLIP-FLOPS
182
112
DUAL J-K FLIP-FLOPS
184
121
MONOSTABLE MULTIVIBRATORS
186
122
MONOSTABLE MULTIVIBRATORS
187
123
DUAL MONOSTABLE MULTIVIBARATORS
188
124
DUAL VOLTAGE-CONTROLLED OSCILLATORS 189
125
QUAD BUS BUFFER GATES 3-STATE
126
QUAD BUS BUFFER GATES 3-STATE
191
128
LINE DRIVER
192
190
3
132
Function
Function
QUAD 2-INPUT NAND SCHMITT TRIGGERS 192
257
133
13-INPUT NAND
193
258
QUAD 2-TO-1 DATA SELECTOR/MULTIPLEXERS 3-STATE 284
136
QUAD EXCLUSIVE-OR O.C.
193
259
8-BIT ADDRESSABLE LATCHES
286
137
3-TO-8 LINE DECODERS/DEMULTIPLEXERS LATCH 194
260
DUAL 5-INPUT NOR GATES
288
138
3-TO-8 LINE DECODERS/DEMULTIPLEXERS
196
265
QUAD COMPLEMENTARY-OUTPUT ELEMENTS
289
139
DUAL 2-TO-4 LINE DECODERS/DEMULTIPLEXERS 198
266
QUAD 2-INPUT EXCLUSIVE-NOR O.C.
290
140
DUAL 4-INPUT NAND LINE DRIVERS
200
273
OCTAL D-TYPE FLIP-FLOPS
291
145
BCD-TO-DECIMAL DECODERS/DRIVERS
201
276
QUAD J-K FLIP-FLOPS
292
147
10-TO-4 LINE PRIORITY ENCODER
202
279
QUAD S-R LATCHES
293
148
8-TO-3 LINE PRIORITY ENCODERS
204
280
9-BIT PARITY GENERATORS/CHECKERS
294
150
1-OF-16 DATA SELECTOR
206
283
4-BIT FULL ADDERS
296
151
8-TO-1 LINE DATA SELECTORS/MULTIPLEXERS
208
286
9-BIT PARITY GENERATORS/CHECKERS
298
153
DUAL 4-TO-1 LINE DATA SELECTORS/MULTIPLEXERS 210
292
PROGRAMMABLE FREQUENCY DIVIDER/DIGITAL TIMER 300
154
4-TO-16 LINE DECODERS/DEMULTIPLEXER 212
293
4-BIT BINARY COUNTERS
155
DUAL 2-TO-4 LINE DECODERS/DEMULTIPLEXERS 214
294
PROGRAMMABLE FREQUENCY DIVIDER/DIGITAL TIMER 304
156
DUAL 2-TO-4 LINE DECODERS/DEMULTIPLEXERS 216
297
DIGITAL PLL FILTERS
157
QUAD 2-TO-1 LINE DATA SELECTORS/MULTIPLEXERS 218
298
QUAD 2-INPUT MULTIPLEXERS WITH STORAGE 308
158
QUAD 2-TO-1 LINE DATA SELECTORS/MULTIPLEXERS 220
299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS 310
159
4-TO-16 LINE DECODER/MULTIPLEXER
222
321
CRYSTAL-CONTROLLED OSCILLATOR
161
SYNCHRONOUS BINARY COUNTERS
224
323
8-BIT BIDIRELTIONAL SHIFT/STORAGE REGISTERS 314
163
SYNCHRONOUS BINARY COUNTERS
226
348
8-TO-3 LINE PRIORITY ENCODER
164
8-BIT SHIFT REGISTERS (P-OUT SERIAL)
228
354
8-INPUT MULTIPLEXERS/REGISTERS 3-STATE 318
165
8-BIT SHIFT REGISTERS (P-LOAD)
230
356
8-INPUT MULTIPLEXERS/REGISTERS 3-STATE 320
166
8-BIT SHIFT REGISTERS (P-LOAD)
232
365
HEX BUS DRIVERS HEX BUFFERS/LINE DRIVERS 3-STATE
322
169
UP-DOWN SYNCHRONOUS BINARY COUNTERS
234
366
HEX BUS DRIVERS HEX BUFFERS/LINE DRIVERS 3-STATE
323
170
4-BY-4 REGISTER FILES
236
367
HEX BUS DRIVERS HEX BUFFERS/LINE DRIVERS 3-STATE
324
173
4-BIT D-TYPE REGISTERS
238
368
HEX BUS DRIVERS HEX BUFFERS/LINE DRIVERS 3-STATE
324
174
HEX D-TYPE FLIP-FLOPS
240
373
OCTAL D-TYPE LATCHES 3-STATE
325
175
QUAD D-TYPE FLIP-FLOPS
241
374
OCTAL D-TYPE FLIP-FLOPS 3-STATE
326
QUAD 2-TO-1 DATA SELECTOR/MULTIPLEXERS 3-STATE 282
327
302
306
312
316
181
4-BIT ALU/FUNCTION GENERATORS
242
375
QUAD LATCHES
182
LOOK-AHEAD CARRY GENERATORS
244
377
OCTAL D-TYPE FLIP-FLOPS CLOCK
328
190
SYNCHRONOUS UP/DOWN DECADE COUNTER
246
378
HEX D-TYPE FLIP-FLOPS CLOCK
329
191
SYNCHRONOUS UP/DOWN COUNTERS
248
390
DUAL DECADE COUNTERS
330
192
PRESETTABLE SYNCHRONOUS 4-BIT UP/DOWN COUNTERS
250
393
DUAL BINARY COUNTERS
331
193
SYNCHRONOUS UP/DOWN DUAL CLOCK COUNTERS 252
395
4-BIT CASCADABLE SHIFT REGISTER 3-STATE
332
194
4-BIT BIDIRECTIONAL SHIFT REGISTERS
254
399
QUAD 2-INPUT MULTIPLEXER WITH STORAGE 334
195
4-BIT PARALLEL ACCESS SHIFT REGISTERS 256
423
MONO-STABLE MULTIVIBRATOR
221
DUAL MONOSTABLE MULTIVIBRATORS
258
442
QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS 336
237
3-TO-8 LINE DECODER DEMULTIPLEXER
260
465
OCTAL BUFFERS 3-STATE
338
238
3-TO-8-LINE DECODERS/DEMULTIPLEXERS 262
518
8-BIT IDENTITY COMPARATOR
340
240
OCTAL BUS DRIVERS 3-STATE
264
520
8-BIT IDENTITY COMPARATOR
342
264
521
8-BIT IDENTITY COMPARATOR
344
OCTAL D-TYPE LATCHES
346
347
240-1 OCTAL BUS DRIVERS /IOL=48mA 3-STATE
241
OCTAL BUS DRIVERS 3-STATE
266
533
243
QUADRUPLE BUS TRANSCEIVERS
268
534
OCTAL D-TYPE FLIP-FLOPS
244
OCTAL BUS DRIVERS 3-STATE
270
540
OCTAL BUFFERS/DRIVERS 3-STATE
244-1 OCTAL BUS DRIVERS /IOL=48mA 3-STATE
245
OCTAL BUS TRANSCEIVERS 3-STATE
245-1 OCTAL BUS TRANSCEIVERS /IOL=48mA 3-STATE
4
Device
Page
Device
TTL
CMOS SN74
BiCMOS
Page
TTL
CMOS SN74
BiCMOS
270
272
272
540-1 OCTAL BUFFERS/DRIVERS (IOL=48mA)
541
OCTAL BUFFERS/DRIVERS 3-STATES
541-1 OCTAL BUFFERS/DRIVERS (IOL=48mA)
335
348
348
349
349
247
BCD-TO-SEVEN SEGMENT DECODERS/DRIVERS
274
543
OCTAL REGISTERED TRANSCEIVERS
350
250
1-OF-16 GENERATORS/MULTIPLEXER 3-STATE
276
561
SYNCHRONOUS 4-BIT COUNTER
352
251
DATA SELECTORS/MULTIPLEXERS 3-STATE 278
563
OCTAL TRANSPARENT LATCHES
354
253
DUAL 4-TO-1 LINE DATA SELECTOR/
MULTIPLEXERS 3-STATE
564
OCTAL D-TYPE FLIP-FLOPS
355
569
SYNCHRONOUS BINARY COUNTER 3-STATE
356
280
Function
Device
Page
Device
TTL
CMOS SN74
BiCMOS
Page
TTL
CMOS SN74
BiCMOS
Function
573
OCTAL D-TYPE LATCHES
358
686
8-BIT IDENTITY COMPARATOR
574
OCTAL D-TYPE FLIP-FLOPS
359
688
8-BIT IDENTITY COMPARATOR
428
575
OCTAL D-TYPE FLIP-FLOPS
360
697
SYNCHRONOUS UP-DOWN COUNTERS
430
576
OCTAL D-TYPE FLIP-FLOPS
361
699
SYNCHRONOUS UP-DOWN COUNTERS
432
577
OCTAL D-TYPE FLIP-FLOPS
362
756
OCTAL BUFFER/LINE DRIVER WITH O.C. OUTPUTS 434
580
OCTAL D-TYPE LATCHES
363
757
OCTAL BUFFER/LINE DRIVER WITH O.C. OUTPUTS 435
590
8-BIT COUNTER/OUTPUT REGISTER 3-STATE 364
760
OCTAL BUFFER/LINE DRIVER WITH O.C. OUTPUTS 436
592
8-BIT BINARY COUNTERES
366
804
HEX 2-INPUT NAND DRIVERS
593
8-BIT BINARY COUNTERES
368
805
HEX 2-INPUT NOR DRIVERS
438
594
8-BIT SHIFT REGISTERS
370
808
HEX 2-INPUT AND DRIVERS
438
595
8-BIT SHIFT REGISTERS
372
821
10-BIT BUS INTERFACE FLIP-FLOPS
439
596
8-BIT SHIFT REGISTERS
374
823
9-BIT BUS INTERFACE FLIP-FLOP
440
597
8-BIT SHIFT REGISTERS
376
825
8-BIT BUS INTERFACE FLIP-FLOP
442
598
8-BIT SHIFT REGISTERS
378
827
10-BIT BUFFERS/BUS DRIVERS
444
620
OCTAL BUS TRANSCEIVERS 3-STATE
380
828
10-BIT BUFFERS/BUS DRIVERS
444
621
OCTAL BUS TRANSCEIVERS O.C.
381
832
HEX 2-INPUT OR DRIVERS
445
621-1 OCTAL BUS TRANSCEIVERS/IOL=48mA
426
437
381
833
10-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 446
623
OCTAL BUS TRANSCEIVERS
382
841
10-BIT BUS INTERFACE LATCHES
624
VOLTAGE CONTROLLED OSCILLATORS
383
843
9-BIT BUS INTERFACE LATCHES
450
628
VOLTAGE CONTROLLED OSCILLATORS
384
853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
452
629
VOLTAGE CONTROLLED OSCILLATORS
385
857
HEX 2-TO-1 UNIVERSAL MULTIPLEXERS
454
638
OCTAL BUS TRANSCEIVERS
386
861
10-BIT TRANSCEIVERS WITH 3-STATEOUTPUTS 456
386
863
9-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS 457
387
867
8-BIT SYNCHRONOUS COUNTER
458
387
869
8-BIT SYNCHRONOUS COUNTER
460
388
870
DUAL 16-BY 4-BIT REGISTER FILES
462
388
873
DUAL 4-BIT D-TYPE LATCHES
464
389
874
DUAL 4-BIT D-TYPE FLIP-FLOPS
465
389
876
DUAL 4-BIT D-TYPE FLIP-FLOPS
WITH INVERTED OUTPUTS
466
390
885
8-BIT MAGNITUDE COMPARATOR
468
391
990
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES 470
391
992
9-BIT D-TYPE TRANSPARENT
READ-BACKLATCHES 3-STATE
471
10-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
472
638-1 OCTAL BUS TRANSCEIVERS/IOL=48mA
639
OCTAL BUS TRANSCEIVERS
639-1 OCTAL BUS TRANSCEIVERS/IOL=48mA
640
OCTAL BUS TRANSCEIVERS 3-STATE
640-1 OCTAL BUS TRANSCEIVERS/IOL=48mA 3-STATE
641
OCTAL BUS TRANSCEIVERS O.C.
641-1 OCTAL BUS TRANSCEIVERS/IOL=48mA O.C.
642
OCTAL BUS TRANSCEIVERS O.C.
642-1 OCTAL BUS TRANSCEIVERS/IOL=48mA O.C.
645
OCTAL BUS TRANSCEIVERS 3-STATE
645-1 OCTAL BUS TRANSCEIVERS/IOL=48mA 3-STATE
646
390
OCTAL BUS TRANSCEIVERS AND REGISTERS 392
448
392
994
647
OCTAL BUS TRANSCEIVERS AND REGISTERS 394
996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES 474
648
OCTAL BUS TRANSCEIVERS AND REGISTERS 396
1000
QUAD 2-INPUT NAND BUFFERS/DRIVERS
651
OCTAL BUS TRANSCEIVERS AND REGISTERS 398
1004
HEX INVERTER
476
398
1005
HEX INVERTER O.C.
477
652
OCTAL BUS TRANSCEIVERS AND REGISTERS 400
1008
QUAD 2-INPUT AND BUFFERS/DRIVERS
477
653
OCTAL BUS TRANSCEIVERS AND REGISTERS 402
1032
QUAD 2-INPUT OR BUFFERS/DRIVERS
478
654
OCTAL BUS TRANSCEIVERS AND REGISTERS 404
1034
HEX DRIVERS
478
1035
HEX BUFFERS O.C.
479
657
OCTAL TRANSCEIVERS WITH PARITY
GENERATORS/CHECKERS 3-STATE
406
1240
OCTAL BUS DRIVER
479
666
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES 408
1244
OCTAL BUS DRIVER 3-STATE
480
667
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES 410
1245
OCTAL BIDIRECTIONAL BUS TRANSCEIVER 3-STATE
480
669
SYNCHRONOUS UP/DOWN BINARY COUNTER
412
1640
OCTAL BIDIRECTIONAL BUS TRANSCEIVER 3-STATE
481
670
4 x 4 REGISTER FILE
414
1645
OCTAL BIDIRECTIONAL BUS TRANSCEIVER 3-STATE
481
673
16-BIT SHIFT REGISTER
416
2240
482
674
16-BIT SHIFT REGISTER
418
OCTAL BUFFERS AND LINE DRIVERS
MOS DRIVERS WITH 3-STATE OUTPUTS
2241
OCTAL LINE MOS DRIVERS WITH SERIES
DUMPING REGISTER, NON-INVERTING
483
646-1 OCTAL BUS TRANSCEIVERS AND REGISTERS/IOL=48mA
651-1 OCTAL BUS TRANSCEIVERS AND REGISTERS/IOL=48mA
679
ADRESS COMPARATOR
420
682
8-BIT IDENTITY COMPARATOR
422
684
8-BIT IDENTITY COMPARATOR
424
476
5
Function
2244
OCTAL LINE/MOS DRIVERS WITH SERIES
DUMPING REGISTER, NON-INVERTING
484
2245
OCTAL TRANSCEIVER AND LINE/MOS DRIVERS
WITH 3-STATE OUTPUTS
Page
Device
Device
Function
5401
11-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
534
5402
12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
535
485
5403
11-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
535
25-Ω OCTAL TRANSPARENT D-TYPE LATCH
486
WITH 3-STATE OUTPUTS
7001
QUAD POSITIVE-AND GATES
WITH SCHMITT-TRIGGER INPUTS
536
2414
MEMORY DECODER WITH ON-CHIP VCC MONITOR
7002
QUAD POSITIVE-NOR GATES
WITH SCHMITT-TRIGGER INPUTS
536
2541
OCTAL LINE DRIVERS/MOS DRIVERS
WITH 3-STATE OUTPUTS
490
7032
QUAD 2-INPUT POSITIVE-OR GATES
WITH SCHMITT-TRIGGER INPUTS
537
2827
10-BIT BUS/MOS MEMORY DRIVERS
490
7046
PHASE-LOCKED LOOP WITH VCO AND LOCK DETECTOR 538
2828
10-BIT BUS/MOS MEMORY DRIVERS INVERTING
491
7266
QUAD 2-INPUT EXCLUSIVE-NOR GATES
539
2952
REGISTERED TRANSCEIVERS (2mA, 24mA, 48mA, 64mA) 492
8003
DUAL 2-INPUT NAND GATES
539
2953
REGISTERED TRANSCEIVERS (2mA, 24mA, 48mA, 64mA) 494
16240 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
540
3245
OCTAL BUS TRANSCEIVER 3-STATE
496
16241 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
542
4002
DUAL 4-INPUT POSITIVE-NOR GATES
497
16244 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
544
4015
DUAL 4-STAGE STATIC SHIFT REGISTER
498
16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
4016
QUAD BILATERAL SWITCH
499
4017
DECADE COUNTERS/DRIVERS
500
4020
14-STAGE BINARY COUNTERS
502
4024
7-STAGE BINARY COUNTERS
503
4040
12-STAGE BINARY COUNTERS
504
4046
PHASE-LOCKED-LOOP WITH VCO
505
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
16270
WITH 3-STATE OUTPUTS
4049
HEX INVERTING BUFFERS
506
16271
4050
HEX NON-INVERTING BUFFERS
506
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
554
WITH 3-STATE OUTPUTS
4051
8-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
507
16282
DUAL 4-CHANNEL ANALOG
MULTIPLEXERS/DEMULTIPLEXERS
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
556
4052
508
16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
558
4053
TRIPLE 2-CHANNEL ANALOG
MULTIPLEXERS/DEMULTIPLEXERS
16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
560
509
16373 16-BIT TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
562
4059
CMOS PROGRAMMABLE DIVIDE-BY-N COUNTER
510
16374
564
4060
ASYNCHRONOUS 14-STAGE BINARY COUNTERS
511
AND OSCILLATORS
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
566
4066
QUAD BILATERAL SWITCHES
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
16409
WITH 3-STATE OUTPUTS
4-TO-1 MULTIPLEXED/DEMULTIPLEXED
16460
TRANSCEIVERS WITH 3-STATE OUTPUTS
568
2373
6
TTL
CMOS SN74
BiCMOS
Page
TTL
CMOS SN74
BiCMOS
488
512
4067
16-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER 513
4075
TRIPLE 3-INPUT OR GATES
514
546
16260
12-BIT TO 24-BIT MULTIPLEXES D-TYPE
LATCH WITH 3-STATE OUTPUTS
548
16269
12-BIT TO 24-BIT REGISTERED BUS
TRANSCEIVER WITH 3-STATE OUTPUTS
550
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
552
4094
8-STAGE SHIFT AND STORE BUS REGISTER, THREE-STATE 516
16470
4245
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
518
WITH 3-STATE OUTPUTS
18-BIT UNIVERSAL BUS TRANSCEIVER
16500
WITH 3-STATE OUTPUTS
572
4316
QUAD ANALOG SWITCH WITH LEVEL TRANSLATION
4351
ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH 520
18-BIT UNIVERSAL BUS TRANSCEIVER
16501
WITH 3-STATE OUTPUTS
574
4352
ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH 521
OCTAL EDGE-TRIGGERED D-TYPE DUAL522
RANK FLIP-FLOP WITH 3-STATE OUTPUTS
576
4374
18-BIT REGISTERED BUS TRANSCEIVER
16524
WITH 3-STATE OUTPUTS
4511
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS 523
18-BIT REGISTERED BUS TRANSCEIVER
16525
WITH 3-STATE OUTPUTS
578
4514
4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS
WITH INPUT LATCHES
524
16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
580
4515
4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS
WITH INPUT LATCHES
526
4518
DUAL SYNCHRONOUS COUNTERS
528
4520
DUAL SYNCHRONOUS COUNTERS
529
4538
DUAL RETRIGGERABLE PRECISION
MONOSTABLE MULTIVIBRATOR
4543
5400
519
16541 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
570
581
16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
582
16600
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
584
18-BIT UNIVERSAL BUS TRANSCEIVERS
16601
WITH 3-STATE OUTPUTS
586
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS 532
16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
588
11-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
16623 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
590
530
534
Function
Device
591
29843
Page
Device
16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
TTL
CMOS SN74
BiCMOS
Page
TTL
CMOS SN74
BiCMOS
Function
9-BIT BUS INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
634
16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
592
WITH 3-STATE OUTPUTS
16651
16-BIT BUS TRANSCEIVERS AND REGISTERS
594
WITH 3-STATE OUTPUTS
29863 9-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
638
29864 9-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
639
16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
596
WITH 3-STATE OUTPUTS
32240 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
640
32244 36-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
642
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/
CHECKERS AND 3-STATE OUTPUTS
598
32245 36-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
644
16721 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
600
16657
16722 22-BIT FLIP-FLOP WITH 3-STATE OUTPUTS 601
16820
16821
10-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH DUAL OUTPUTS
602
20-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
603
18-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
16823
WITH DUAL OUTPUTS
604
16825 18-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
16827 20-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER 636
32316 16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS 646
32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS 648
32373
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
650
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
32374
652
WITH 3-STATE OUTPUTS
32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
654
605
36-BIT REGISTERED BUS TRANSCEIVERS
32543
WITH 3-STATE OUTPUTS
656
606
40103 8-STAGE SYNCHRONOUS DOWN COUNTERS
658
1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
607
162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1-TO-4 ADDRESS REGISTER/DRIVER
16832
WITH 3-STATE OUTPUTS
608
162241
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
16831
16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 610
16834
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
612
659
660
162244 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
661
162245 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS
662
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
664
666
162260
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER
16835
WITH 3-STATE OUTPUTS
613
20-BIT BUS INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
614
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
162268
WITH 3-STATE OUTPUTS
18-BIT BUS INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
615
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
162280
WITH BYTE MASKS AND 3-STATE OUTPUTS
668
16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 616
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
162282
WITH 3-STATE OUTPUTS
670
16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
618
162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
672
16863 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
619
162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
674
16841
16843
16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
620
162373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
676
WITH 3-STATE OUTPUTS
16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH
622
PARITY CHECKER AND DUAL 3-STATE OUTPUTS
162374
3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
677
WITH 3-STATE OUTPUTS
16-BIT REGISTERED TRANSCEIVERS
16952
WITH 3-STATE OUTPUTS
624
162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED
678
TRANSCEIVERS WITH 3-STATE OUTPUTS
25Ω OCTAL BUS BUFFERS/DRIVERS
25244
WITH 3-STATE OUTPUTS
626
162500
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
25Ω OCTAL BUS TRANSCEIVERS
25245
WITH 3-STATE OUTPUTS
627
18-BIT UNIVERSAL BUS TRANSCEIVERS
162501
WITH 3-STATE OUTPUTS
682
25642 25-Ω OCTAL BUS TRANSCEIVER
628
16-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
684
29821
29825
29827
29828
162525
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
629
8-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
680
686
630
3.3-V ABT 16-BIT BUFFERS/DRIVERS
162541
WITH 3-STATE OUTPUTS
10-BIT BUFFERS AND BUS DRIVERS
WITH 3-STATE OUTPUTS
688
631
18-BIT UNIVERSAL BUS TRANSCEIVER
162601
WITH 3-STATE OUTPUTS
10-BIT BUFFERS AND BUS DRIVERS
WITH 3-STATE OUTPUTS
632
162820
3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS
691
AND 3-STATE OUTPUTS
633
162823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
10-BIT BUS INTERFACE D-TYPE LATCHES
29841
WITH 3-STATE OUTPUTS
162721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS 690
692
7
Device
Page
TTL
CMOS SN74
BiCMOS
Function
162825 18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 693
162827 20-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
694
162830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
695
162831
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
696
WITH 3-STATE OUTPUTS
162832
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
697
WITH 3-STATE OUTPUTS
162834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
698
162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
699
162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
20-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
701
164245
16-BIT TRANSCEIVER AND 3.3-V TO 5-V
SHIFTER WITH 3-STATE OUTPUTS
702
3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
322374
WITH 3-STATE OUTPUTS
8
700
162841
703
FUNCTION
1G / 2G / 3G
LITTLE LOGIC GATE (AND/NAND/OR/NOR/EX-OR)
Technology
POSITIVE-NAND
2
POSITIVE- OR
2
POSITIVE- NOR
2
EXCLUSIVE-OR
2
2G08
1
1G00
2
2G00
1
1G32
2
2G32
1
1G02
2
2G02
1
1G86
2
2G86
○
○
○
○
○
○
○
○
AVC
○
AUC
ALVC
○
LV
○
LVC
AC
AHC
1G08
2
AHCT
1
Advanced CMOS
ACT
Type
LVT
Output
ALVT
2
Input
ABT
POSITIVE-AND
Curcuit
BiCMOS
BCT
No. of
Input
HC
Description
HCT
CMOS
○
○
*
○
○
○
*
○
○
○
*
○
○
○
*
○
*
○
*
Explanatory notes [Input] SCH：Schmitt-Trigger Inputs
Explanatory notes [Output] BUF：Buffered Output OC：Open-Collector Output 3S：3-State Output
Status ○：Product available in technology indicated *：New product planned in technology indicated ×：Discontinued
LITTLE LOGIC GATE (INVERTER/NONINVERTER)
Technology
SCH
1G14
○
○
1
*
○
*
2G14
○
*
2G04
○
*
3G04
*
*
UBF
3GU04
OC
3G06
○
SCH
2G14
○
*
SCH
3G14
○
*
1G07
○
○
1G17
○
○
1G66
○
2G07
○
○
*
2G17
○
*
2G34
○
2G66
○
*
3G07
*
3G17
○
*
2G34
○
*
3G34
○
*
SCH
SCH
OC
3
AUC
○
2G06
OC
1
AVC
○
2GU04
OC
OC
NON-INVERTING
○
○
*
3
2
○
○
UBF
SCH
1
○
○
○
○
*
2G04
2
INVERTING
○
ALVC
AC
ACT
ALVT
○
○
LVT
○
1G06
BCT
1G04
1GU04
OC
LV
Advanced CMOS
UBF
Type
LVC
BiCMOS
AHC
1
Output
ABT
Input
HC
Curcuit
HCT
No. of
Input
AHCT
CMOS
Description
SCH
*
*
Explanatory notes [Input] SCH：Schmitt-Trigger Inputs
Explanatory notes [Output] BUF：Buffered Output OC：Open-Collector Output 3S：3-State Output
Status ○：Product available in technology indicated *：New product planned in technology indicated ×：Discontinued
11
LITTLE LOGIC BUFFER/DRIVER
Technology
2
INVERTING
2G241
○
*
*
*
1
3S
1G240
○
○
AVC
3S
AUC
○
ALVC
2G126
LV
3S
LVC
○
○
AC
○
○
ACT
○
○
LVT
○
○
2G125
ALVT
○
1G126
3S
BCT
1G125
3S
ABT
AHC
1
NON-INVERTING
Advanced CMOS
3S
Type
Output
HC
Curcuit
HCT
Description
BiCMOS
AHCT
CMOS
Explanatory notes Output 3S：3-State Output R3S：Series Resistor and 3-State output OC：Open-Collector Output
Status ○：Product available in technology indicated *：New product planned in technology indicated ×：Discontinued
LITTLE LOGIC D-TYPE FLIP-FLOP
Technology
B
2S
Q
1G79
○
2S
/Q
1G80
○
2S
B
2G74
○
AUC
AVC
ALVC
LV
LVC
AHC
AHCT
AC
Advanced CMOS
ACT
LVT
Type
ALVT
1
Q・/Q
BCT
POS
Output
BiCMOS
ABT
Curcuit
HC
Trigger
HCT
CMOS
PRE
・
CLR
*
*
*
Explanatory notes [Trigger] POS：POSITIVE EDGE、NEG：NEGATIVE EDGE
Explanatory notes [PRE・CLR] B：Preset and Clear、 C：Clear only
Explanatory notes [Output] 2S：Totem pole Output 3S：3-State Output
Explanatory notes [Q･/Q] B：Q･/Q-Output Q：Q-Output /Q：/Q-Output
Status ○：Product available in technology indicated *：New product planned in technology indicated ×：Discontinued
LITTLE LOGIC Data Selectors/Multiplexers
Technology
12
○
AUC
AVC
ALVC
LV
2G157
Explanatory notes [Output] 2S：Totem Pole Output 3S：3-State Output OC：Open-Collector Output
Status ○：Product available in technology indicated *：New product planned in technology indicated ×：Discontinued
LVC
AHC
AHCT
AC
ACT
LVT
1
Advanced CMOS
ALVT
2S
BiCMOS
BCT
2/1
Type
ABT
Curcuit
HC
Output
HCT
CMOS
No. of
Input/Output
*
LITTLE LOGIC ANALOG SWITCH
Technology
AVC
AUC
LVC
ALVC
LV
AHC
AHCT
AC
ACT
LVT
Advanced CMOS
ALVT
BCT
BiCMOS
ABT
Type
HC
Description
HCT
CMOS
SINGLE ANALOG SWITCH
1G66
○
One of Two Noninverting Demultiplexer with 3-State
Deselected Output
1G18
○
○
SINGLE 2-CHANNELANALOG
MULTIPLEXERS/DEMULTIPLEXERS
2G53
○
*
DUAL ANALOG SWITCH
2G66
○
*
Status ○：Product available in technology indicated *：New product planned in technology indicated ×：Discontinued
13
PIN ASSIGNMENTS
1G / 2G / 3G
Pin Assinments
1G00
1G06
SINGLE 2-INPUT POSITIVE-NAND GATE
SINGLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
Y = AB
VCC
Y
VCC
Y
5
4
5
4
1
2
3
A
B
GND
1
2
3
NC
A
GND
NC – No internal connection
See page 27
See page 29
1G02
1G07
SINGLE 2-INPUT POSITIVE-NOR GATE
SINGLE BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
Y=A+B
VCC
Y
VCC
Y
5
4
5
4
1
2
3
1
2
3
A
B
GND
NC
A
GND
NC – No internal connection
See page 27
See page 29
1G04
1G08
SINGLE INVERTER GATE
SINGLE 2-INPUT POSITIVE-AND GATE
Y=A
Y = AB
VCC
Y
VCC
Y
5
4
5
4
1
2
3
1
2
3
NC
A
GND
A
B
GND
NC – No internal connection
See page 28
See page 30
1GU04
1G14
SINGLE INVERTER
SINGLE SCHMITT-TRIGGER INVERTER GATE
Y=A
Y=A
VCC
Y
VCC
Y
5
4
5
4
1
2
3
NC
A
GND
NC – No internal connection
See page 28
1
2
3
NC
A
GND
NC – No internal connection
See page 30
17
Pin Assinments
1G17
1G79
SINGLE SCHMITT-TRIGGER BUFFER
SINGLE POSITIVE-EDGE-TRIGGERED
D-TYPE FLIP-FLOP
VCC
Y
VCC
Q
5
4
5
4
Q
D
CK
1
2
3
1
2
3
NC
A
GND
D
CLK
GND
NC – No internal connection
See page 31
See page 33
1G18
1G80
1-OF-2 NONINVERTING DEMULTIPLEXER
WITH 3-STATE DESELECTED OUTPUT
SINGLE POSITIVE-EDGE-TRIGGERED
D-TYPE FLIP-FLOP
Y0
VCC
Y1
VCC
Q
6
5
4
5
4
Q
D
CK
1
2
3
1
2
3
S
GND
A
D
CLK
GND
See page 31
See page 33
1G32
1G86
SINGLE 2-INPUT POSITIVE-OR GATE
SINGLE 2-INPUT EXCLUSIVE-OR GATE
Y=A+B
Y = A ⊕ B = AB + AB
VCC
Y
VCC
Y
5
4
5
4
1
2
3
1
2
3
A
B
GND
A
B
GND
See page 32
See page 34
1G66
1G125
SINGLE ABILATERAL ANALOG SWITCH
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
Y=A
See page 32
18
VCC
C
VCC
Y
5
4
5
4
1
2
3
1
2
3
A
B
GND
OE
A
GND
See page 34
Pin Assinments
1G126
2G02
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
DUAL 2-INPUT POSITIVE-NOR GATE
Y=A
VCC
Y
VCC
1Y
2B
2A
5
4
8
7
6
5
1
2
3
1
2
3
4
OE
A
GND
1A
1B
2Y
GND
See page 35
See page 36
1G240
2G04
SINGLE BUFFER/DRIVER WITH 3-STATE OUTPUT
DUAL INVERTER GATE
VCC
Y
1Y
VCC
2Y
5
4
6
5
4
1
2
3
1
2
3
OE
A
GND
1A
GND
2A
1Y
VCC
2Y
6
5
4
See page 35
See page 37
2G00
2GU04
DUAL 2-INPUT POSITIVE-NAND GATE
DUAL INVERTER GATE
See page 36
VCC
1Y
2B
2A
8
7
6
5
1
2
3
4
1A
1B
2Y
GND
1
2
3
1A
GND
2A
See page 37
19
Pin Assinments
2G06
2G14
DUAL INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
DUAL SCHMITT-TRIGGER INVERTER
1Y
VCC
2Y
1Y
VCC
2Y
6
5
4
6
5
4
1
2
3
1
2
3
1A
GND
2A
1A
GND
2A
See page 39
See page 38
2G07
2G17
DUAL BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
DUAL SCHMITT-TRIGGER BUFFER
VCC
2Y
1Y
VCC
2Y
6
5
4
6
5
4
1
2
3
1
2
3
1A
GND
2A
1A
GND
2A
See page 38
See page 40
2G08
2G32
DUAL 2-INPUT POSITIVE-AND GATE
DUAL 2-INPUT POSITIVE-OR GATE
See page 39
20
1Y
VCC
1Y
2B
2A
VCC
1Y
2B
2A
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
1A
1B
2Y
GND
1A
1B
2Y
GND
See page 40
Pin Assinments
2G34
2G74
DUAL BUFFER GATE
SINGLE POSITIVE-EDGE-TRIGGERED
D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
1Y
VCC
2Y
VCC
PRE
CLR
Q
6
5
4
8
7
6
5
CK CLR Q
D
Q
PRE
1
2
3
1
2
3
4
1A
GND
2A
CLK
D
Q
GND
See page 41
See page 42
2G53
2G86
DUAL ANALOG MULTIPLEXER/DEMULTIPLEXER
DUAL 2-INPUT EXCLUSIVE-OR GATE
VCC
Y1
Y2
A
VCC
1Y
2B
2A
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
COM
INH
GND
GND
1A
1B
2Y
GND
See page 41
See page 43
2G66
2G125
DUAL BILATERAL ANALOG SWITCH
DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
See page 42
VCC
1C
2B
2A
VCC
2OE
1Y
2A
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
1A
1B
2C
GND
1OE
1A
2Y
GND
See page 43
21
Pin Assinments
2G126
2G241
DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
2OE
1Y
2A
VCC
2OE
1Y
2A
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
1OE
1A
2Y
GND
1OE
1A
2Y
GND
See page 44
See page 45
2G157
3G04
SINGLE 2-LINE TO 1-LINE DATA
SELECTOR/MULTIPLEXER
TRIPLE INVERTER GATE
VCC
G
A/B
Y
VCC
1Y
3A
2Y
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
A
B
Y
GND
1A
3Y
2A
GND
See page 44
See page 46
2G240
3G06
DUAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
TRIPLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
See page 45
22
VCC
VCC
2OE
1Y
2A
VCC
1Y
3A
2Y
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
1OE
1A
2Y
GND
1A
3Y
2A
GND
See page 46
Pin Assinments
3G07
3G34
TRIPLE BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
TRIPLE BUFFER GATE
VCC
1Y
3A
2Y
VCC
1Y
3A
2Y
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
1A
3Y
2A
GND
1A
3Y
2A
GND
See page 47
See page 48
3G14
TRIPLE SCHMITT-TRIGGER INVERTER
VCC
1Y
3A
2Y
8
7
6
5
1
2
3
4
1A
3Y
2A
GND
VCC
1Y
3A
2Y
8
7
6
5
See page 47
3G17
TRIPLE SCHMITT-TRIGGER BUFFER
1
2
3
4
1A
3Y
2A
GND
See page 48
23
FUNCTION
AND
ELECTRICAL
CHARACTERISTICS
1G / 2G / 3G
Logic Diagram
1G00
A
SINGLE 2-INPUT POSITIVE-NAND GATE
B
1
4
2
Y
● Y = AB
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
INPUT
A
B
H
H
L
X
L
X
PARAMETER MAX or MIN AHC AHCT
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
0.01
-9
9
0.01
-8
8
mA
mA
mA
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
4
4
4.7
4.7
5.5
5.5
8
8
2
2
2.2
2.2
MAX
MAX
MAX
0.01
-8
8
0.01
-8
8
OUTPUT
Y
L
H
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A or B
Y
MAX
AHC AHCT
8.5
8.5
9
9
Logic Diagram (positive logic)
1G02
A
SINGLE 2-INPUT POSITIVE-NOR GATE
B
1
4
2
Y
●Y=A+B
FUNCTION TABLE
INPUT
A
B
H
X
X
H
L
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC AHCT
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
0.01
-9
9
0.01
-8
8
mA
mA
mA
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
4
4
4.5
4.5
5.5
5.5
8
8
2.1
2.1
2.4
2.4
MAX
MAX
MAX
0.01
-8
8
0.01
-8
8
OUTPUT
Y
L
L
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A or B
Y
MAX
AHC AHCT
8.5
8.5
8.5
8.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
27
1G04
Logic Diagram
SINGLE INVERTER GATE
A
2
4
Y
●Y=A
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
INPUT
A
H
L
PARAMETER MAX or MIN AHC AHCT
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
0.01
-9
9
0.01
-8
8
mA
mA
mA
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
3.7
3.7
4.2
4.2
5.2
5.2
7.5
7.5
1.9
1.9
2.2
2.2
MAX
MAX
MAX
0.01
-8
8
0.01
-8
8
OUTPUT
Y
L
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
AHC AHCT
8.5
8.5
8.5
8.5
1GU04
Logic Diagram
SINGLE INVERTER
A
2
4
●Y=A
● Unbuffered Output
● Supply Voltage Renge : 2V ∼ 5.5V
FUNCTION TABLE
INPUT
A
H
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
0.01
-9
9
0.01
-8
8
mA
mA
mA
MAX
MAX
MAX
0.01
-8
8
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
28
INPUT
OUTPUT
MAX or MIN
AHC
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
A
Y
MAX
8
8
3
3
3.7
3.7
4
4
5
5
2.1
2.1
2.4
2.4
OUTPUT
Y
L
H
Y
1G06
Logic Diagram
SINGLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
A
2
Y
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
UNIT
ICC
VO
IOL
0.01
5.5
32
0.01
5.5
24
0.01
5.5
8
0.01
5.5
4
0.01
2.7
9
0.01
2.7
8
mA
V
mA
MAX
MAX
MAX
4
INPUT
A
H
L
OUTPUT
Y
L
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
A
Y
MAX
3
3
4
4
4
4
5.6
5.6
1.8
1.8
2.5
2.5
1G07
Logic Diagram
SINGLE BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
A
2
4
Y
FUNCTION TABLE
INPUT
A
H
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
UNIT
ICC
IOH
IOL
0.01
5.5
32
0.01
5.5
24
0.01
5.5
8
0.01
5.5
4
0.01
2.7
9
0.01
2.7
8
mA
V
mA
MAX
MAX
MAX
OUTPUT
Y
H
L
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
A
Y
MAX
3.5
3.5
4.2
4.2
5.5
5.5
8.3
8.3
1.8
1.8
2.5
2.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
29
1G08
Logic Diagram
SINGLE 2-INPUT POSITIVE-AND GATE
A
B
● Y = AB
1
4
2
Y
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
INPUT
A
B
H
H
L
X
L
X
PARAMETER MAX or MIN AHC AHCT
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
0.01
-9
9
0.01
-8
8
mA
mA
mA
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
4
4
4.5
4.5
5.5
5.5
8
8
2
2
2.4
2.4
MAX
MAX
MAX
0.01
-8
8
0.01
-8
8
OUTPUT
Y
H
L
L
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A or B
Y
MAX
AHC AHCT
9
9
9
9
1G14
Logic Diagram
SINGLE SCHMITT-TRIGGER INVERTER GATE
A
2
4
●Y=A
FUNCTION TABLE
INPUT
A
H
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC AHCT
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
0.01
-9
9
0.01
-8
8
mA
mA
mA
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
5
5
5.5
5.5
6.5
6.5
11
11
2.5
2.5
2.5
2.5
MAX
MAX
MAX
0.01
-8
8
0.01
-8
8
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
30
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
AHC AHCT
12
12
9
9
OUTPUT
Y
L
H
Y
1G17
Logic Diagram
SINGLE SCHMITT-TRIGGER BUFFER
A
2
4
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
0.01
-9
9
0.01
-8
8
mA
mA
mA
MAX
MAX
MAX
Y
INPUT
A
H
L
OUTPUT
Y
H
L
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
A
Y
MAX
5
5
5.5
5.5
6.5
6.5
11
11
2.5
2.5
2.4
2.4
1G18
Logic Diagram
6
1-OF-2 NONINVERTING DEMULTIPLEXER
WITH 3-STATE DESELECTED OUTPUT
S
AY
1
3
4
1
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
INPUTS
A
S
L
L
H
L
L
H
H
H
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
3.2
3.2
3.4
3.4
3.3
3.3
4.2
4.2
4.6
4.6
4.9
4.9
5
5
5.6
5.6
5.3
5.3
9.3
9.3
10.2
10.2
12.7
12.7
MAX
MAX
MAX
Y0
OUTPUT
Y0
Y1
L
Z
H
Z
L
Z
Z
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZL
tPZH
tPLZ
tPHZ
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
S
Y
MAX
S
Y
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
31
1G32
Logic Diagram
SINGLE 2-INPUT POSITIVE-OR GATE
1
A
4
2
B
●Y=A+B
Y
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
INPUT
A
B
H
X
X
H
L
L
PARAMETER MAX or MIN AHC AHCT
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
0.01
-9
9
0.01
-8
8
mA
mA
mA
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
4
4
4.5
4.5
5.5
5.5
8
8
2.1
2.1
2.4
2.4
MAX
MAX
MAX
0.01
-8
8
0.01
-8
8
OUTPUT
Y
H
H
L
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A or B
Y
MAX
AHC AHCT
8.5
8.5
9
9
1G66
Logic Diagram
SINGLE ABILATERAL ANALOG SWITCH
A
1
2
4
C
FUNCTION TABLE
CONTROL
INPUT
SWITCHI
(C)
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
AUC
1.8V
UNIT
ICC
0.01
0.01
mA
MAX
L
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
32
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
C
B or A
MAX
C
B or A
MAX
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
0.6
0.6
4.2
4.2
5
5
0.8
0.8
5
5
6.5
6.5
1.2
1.2
6.5
6.5
6.9
6.9
2
2
12
12
10
10
0.1
0.1
1
1
2.2
2.2
0.2
0.2
1.1
1.1
2.9
2.9
OFF
ON
B
1G79
Logic Diagram
SINGLE POSITIVE-EDGE-TRIGGERED
D-TYPE FLIP-FLOP
CLK
2
C
C
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
INPUT
CLK
D
H
L
L
X
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
MIN
160
2.5
1.2
1.2
0.5
4.5
4.5
160
2.5
1.3
1.3
1.0
5.2
5.2
160
2.5
1.4
1.4
0.4
7
7
160
2.5
2.2
2.6
0.3
9.9
9.9
MAX
MAX
MAX
→ →
PARAMETER MAX or MIN
LVC
5V
OUTPUT
Q
H
L
Q0
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
INPUT
OUTPUT
CLK high or low
Before CLK , Data high
Before CLK , Data low
Data after CLK
th
tPLH
CLK
tPHL
UNIT fmax : MHz other : ns
Q
MIN
MIN
MIN
MAX
1G80
Logic Diagram
SINGLE POSITIVE-EDGE-TRIGGERED
D-TYPE FLIP-FLOP
CLK
2
C
C
FUNCTION TABLE
INPUT
CLK
D
H
L
L
X
→ →
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
MIN
MIN
160
2.5
1.1
1.1
0.4
4.5
4.5
160
2.5
1.3
1.3
0.9
5.2
5.2
160
2.5
1.5
1.5
0.2
7
7
160
2.5
2.3
2.5
0
9.9
9.9
MAX
MAX
MAX
OUTPUT
Q
L
H
Q0
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
INPUT
OUTPUT
CLK high or low
Before CLK , Data high
Before CLK , Data low
Data after CLK
th
tPLH
CLK
tPHL
UNIT fmax : MHz other : ns
Q
MIN
MIN
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
33
1G86
Logic Diagram
EXCLUSIVE OR
SINGLE 2-INPUT EXCLUSIVE-OR GATE
=1
● Y = A ⊕ B = AB + AB
An exclusive-OR gate has many applications, some of which
can be represented better by alternative logic symbols.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC AHCT
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX
MAX
MAX
0.01
-8
8
0.01
-8
8
FUNCTION TABLE
INPUT
A
B
L
L
L
H
H
L
H
H
OUTPUT
Y
L
H
H
L
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A or B
Y
MAX
AHC AHCT
10
10
9
9
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
4
4
5
5
5.5
5.5
9.9
9.9
1G125
Logic Diagram
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
OE
A
1
2
4
●Y=A
FUNCTION TABLE
INPUT
OE
A
H
L
L
L
X
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC AHCT
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
0.01
-9
9
0.01
-8
8
mA
mA
mA
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
4
4
5
5
4.2
4.2
4.5
4.5
5.3
5.3
5
5
5.5
5.5
6.5
6.5
5
5
8
8
9.4
9.4
9.2
9.2
1.7
1.7
1.9
1.9
1.7
1.7
2.5
2.5
2.6
2.6
3.1
3.1
MAX
MAX
MAX
0.01
-8
8
0.01
-8
8
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
34
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
AHC AHCT
8.5
8.5
8
8
10
10
8.5
8.5
8
8
10
10
OUTPUT
Y
H
L
Z
Y
1G126
Logic Diagram
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
OE
A
1
2
4
Y
●Y=A
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
INPUT
OE
A
H
H
H
L
L
X
PARAMETER MAX or MIN AHC AHCT
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
0.01
-9
9
0.01
-8
8
mA
mA
mA
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
4
4
5
5
4.2
4.2
4.5
4.5
5.3
5.3
5.5
5.5
5.5
5.5
6.6
6.6
5.5
5.5
8
8
9.4
9.4
9.8
9.8
1.7
1.7
1.9
1.9
1.7
1.7
2.5
2.5
2.5
2.5
3.1
3.1
MAX
MAX
MAX
0.01
-8
8
0.01
-8
8
OUTPUT
Y
H
L
Z
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
AHC AHCT
8.5
8.5
8
8
10
10
8.5
8.5
8
8
10
10
1G240
Logic Diagram
SINGLE BUFFER/DRIVER
WITH 3-STATE OUTPUT
OE
A
1
2
4
Y
FUNCTION TABLE
INPUT
OE
A
L
H
L
L
H
X
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
0.01
-9
9
0.01
-8
8
mA
mA
mA
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
AUC
2.5V
AUC
1.8V
4
4
5.2
5.2
4.1
4.1
4.5
4.5
5.4
5.4
5.2
5.2
5.5
5.5
6.5
6.5
4.9
4.9
8
8
9.4
9.4
9.4
9.4
1.7
1.7
1.9
1.9
1.7
1.7
2.5
2.5
2.6
2.6
3.1
3.1
MAX
MAX
MAX
OUTPUT
Y
L
H
Z
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
35
2G00
Logic Diagram
DUAL 2-INPUT POSITIVE-NAND GATE
1A
1B
2A
2B
1
7
2
5
3
6
1Y
2Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX
MAX
MAX
FUNCTION TABLE
(each gate)
INPUT
A
B
H
H
L
X
L
X
OUTPUT
Y
L
H
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A or B
Y
MAX
3.3
3.3
4.3
4.3
4.8
4.8
8.6
8.6
2G02
Logic Diagram
DUAL 2-INPUT POSITIVE-NOR GATE
1A
1B
2A
2B
RECOMMENDED OPERATING CONDITIONS
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
36
3
6
INPUT
A
B
H
X
X
H
L
L
SWITCHING CHARACTERISTICS
tPLH
tPHL
UNIT:ns
5
(each gate)
LVC
5V
PARAMETER
7
2
FUNCTION TABLE
PARAMETER MAX or MIN
MAX
MAX
MAX
1
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A or B
Y
MAX
4.4
4.4
4.9
4.9
5.4
5.4
8.9
8.9
OUTPUT
Y
L
L
H
1Y
2Y
2G04
Logic Diagram
DUAL INVERTER GATE
1A
2A
1
6
3
4
1Y
2Y
FUNCTION TABLE
(each inverter)
INPUT
A
H
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX
MAX
MAX
OUTPUT
Y
L
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A
Y
MAX
3.2
3.2
4.1
4.1
4.4
4.4
8
8
2GU04
Logic Diagram
DUAL INVERTER GATE
1A
2A
1
6
3
4
1Y
2Y
FUNCTION TABLE
(each inverter)
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX
MAX
MAX
INPUT
A
H
L
OUTPUT
Y
L
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A
Y
MAX
3
3
3.7
3.7
4
4
5.5
5.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
37
2G06
Logic Diagram
DUAL INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
1A
2A
1
6
3
4
2Y
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
(each inverter)
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
VO
IOL
0.01
5.5
32
0.01
5.5
24
0.01
5.5
8
0.01
5.5
4
mA
V
mA
MAX
MAX
MAX
1Y
INPUT
A
H
L
OUTPUT
Y
L
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A
Y
MAX
2.9
2.9
3.4
3.4
3.9
3.9
7.2
7.2
2G07
Logic Diagram
DUAL BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
1A
2A
1
6
3
4
FUNCTION TABLE
(each buffer/deiver)
INPUT
A
H
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
VO
IOL
0.01
5.5
32
0.01
5.5
24
0.01
5.5
8
0.01
5.5
4
mA
V
mA
MAX
MAX
MAX
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
38
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A
Y
MAX
2.9
2.9
3.7
3.7
4.4
4.4
8.6
8.6
OUTPUT
Y
H
L
1Y
2Y
2G08
Logic Diagram
DUAL 2-INPUT POSITIVE-AND GATE
1A
1B
2A
2B
1
7
2
5
3
6
1Y
2Y
RECOMMENDED OPERATING CONDITIONS
FUNCTION TABLE
PARAMETER MAX or MIN
ICC
IOH
IOL
MAX
MAX
MAX
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
(each gate)
INPUT
A
B
H
H
L
X
L
X
OUTPUT
Y
H
L
L
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A or B
Y
MAX
3.8
3.8
4.7
4.7
5.1
5.1
9
9
2G14
Logic Diagram
DUAL SCHMITT-TRIGGER INVERTER
1A
2A
1
6
3
4
1Y
2Y
FUNCTION TABLE
(each inverter)
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX
MAX
MAX
INPUT
A
H
L
OUTPUT
Y
L
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A
Y
MAX
4.3
4.3
5.4
5.4
5.7
5.7
9.5
9.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
39
2G17
Logic Diagram
DUAL SCHMITT-TRIGGER BUFFER
1A
2A
1
6
3
4
2Y
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
(each inverter)
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX
MAX
MAX
1Y
INPUT
A
H
L
OUTPUT
Y
H
L
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A
Y
MAX
4.3
4.3
5.4
5.4
5.7
5.7
9.3
9.3
2G32
Logic Diagram
DUAL 2-INPUT POSITIVE-OR GATE
1A
1B
2A
2B
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
40
3
6
INPUT
A
B
H
X
X
H
L
L
SWITCHING CHARACTERISTICS
tPLH
tPHL
UNIT:ns
5
(each gate)
PARAMETER MAX or MIN
LVC
5V
PARAMETER
7
2
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
MAX
MAX
MAX
1
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A or B
Y
MAX
3.2
3.2
3.8
3.8
4.4
4.4
8
8
OUTPUT
Y
H
H
L
1Y
2Y
2G34
Logic Diagram
DUAL BUFFER GATE
1A
2A
1
6
3
4
1Y
2Y
FUNCTION TABLE
(each gate)
INPUT
A
H
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX
MAX
MAX
OUTPUT
Y
H
L
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A
Y
MAX
3.2
3.2
4.1
4.1
4.4
4.4
8.6
8.6
2G53
Logic Diagram
DUAL ANALOG
MULTIPLEXER/DEMULTIPLEXER
A
5
SW
SW
INH
LVC
5V
UNIT
ICC
0.01
mA
MAX
6
1
2
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
7
Y1
Y2
COM
FUNCTION TABLE
CONTROL INPUT
ON
CHANNEL
INH
A
L
L
Y1
L
H
Y2
X
None
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
INPUT
OUTPUT
MAX or MIN
COM or Y
Y or COM
MAX
INH
COM or Y
MAX
A
COM or Y
MAX
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
0.6
0.6
4.5
4.5
8
8
5.4
5.4
5
5
0.8
0.8
5.4
5.4
8.1
8.1
5.8
5.8
7.2
7.2
1.2
1.2
6.1
6.1
8.3
8.3
7.2
7.2
7.9
7.9
2
2
9
9
10.9
10.9
10.3
10.3
9.4
9.4
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
41
2G66
Logic Diagram, each switch
DUAL BILATERAL ANALOG SWITCH
1A
1C
1
2
1B
7
One of Two Switches
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LVC
UNIT
FUNCTION TABLE
MAX
0.01
mA
CONTROL
INPUT
SWITCHI
(C)
(each section)
ICC
L
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
C
A or B
MAX
C
A or B
MAX
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
0.6
0.6
3.9
3.9
6.3
6.3
0.8
0.8
4.4
4.4
7.2
7.2
1.2
1.2
5.6
5.6
6.9
6.9
2
2
10
10
10.5
10.5
2G74
OFF
ON
Logic Diagram
SINGLE POSITIVE-EDGE-TRIGGERED
D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
PRE
CLK
7
1
C
C
C
5
TG
C
C
TG
TG
TG
C
C
C
Q
C
C
D
RECOMMENDED OPERATING CONDITIONS
2
3
ICC
IOH
IOL
MAX or MIN
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
MAX
MAX
MAX
0.01
-32
32
0.01
-16
16
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
200
2
2
1.1
1
0.5
4.1
4.1
4.4
4.4
4.1
4.1
175
2.7
2.7
1.3
1.2
1.2
5.9
5.9
6.2
6.2
5.9
5.9
175
2.7
2.7
1.7
1.4
0.3
7.1
7.1
7.7
7.7
7
7
80
6.2
6.2
2.9
1.9
0
13.4
13.4
14.4
14.4
12.9
12.9
CLR
6
FUNCTION TABLE
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT:ns
42
MIN
CLK
PRE or CLR low
Data
PRE or CLR inactive
MIN
MIN
MIN
CLK
Q
MAX
CLK
Q
MAX
PRE or CLR
Q or Q
MAX
PRE
L
H
L
H
H
H
INPUT
CLR CLK
X
H
X
L
X
L
H
H
L
H
→→
PARAMETER
LVC
5V
D
X
X
X
H
L
X
OUTPUT
Q
Q
L
H
L
H
H†
H†
L
H
H
L
Q0
Q0
† This configuration is nonstable; that is, it does not persist
when PRE or CLR returns to its inactive (high) level.
Q
2G86
Logic Diagram
EXCLUSIVE OR
DUAL 2-INPUT EXCLUSIVE-OR GATE
=1
An exclusive-OR gate has many applications, some of which
can be represented better by alternative logic symbols.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
MAX
MAX
MAX
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
FUNCTION TABLE
(each gate)
INPUT
A
B
L
L
L
H
H
L
H
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX
MAX
MAX
2G125
OUTPUT
Y
L
H
H
L
Logic Diagram
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
1OE
1A
2OE
2A
1
6
2
1Y
7
5
3
2Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
3.7
3.7
3.8
3.8
3.4
3.4
4.3
4.3
4.7
4.7
4.6
4.6
4.8
4.8
5.6
5.6
5.8
5.8
9.1
9.1
9.9
9.9
11.6
11.6
FUNCTION TABLE
(each buffer)
MAX
MAX
MAX
INPUT
OE
A
H
L
L
L
X
H
OUTPUT
Y
H
L
Z
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
43
2G126
Logic Diagram
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
1OE
1A
2OE
2A
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
ICC
IOH
IOL
MAX
MAX
MAX
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
3.2
3.2
3.1
3.1
3.3
3.3
4
4
4.1
4.1
4.4
4.4
4.9
4.9
5
5
5.7
5.7
9.8
9.8
10
10
12.6
12.6
1
6
2
1Y
7
5
3
2Y
FUNCTION TABLE
(each buffer)
INPUT
OE
A
H
H
H
L
L
X
OUTPUT
Y
H
L
Z
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
2G157
Logic Diagram
SINGLE 2-LINE TO 1-LINE DATA
SELECTOR/MULTIPLEXER
A
1
5
B
G
A/B
2
3
7
6
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
4
4
4
4
4
4
6
6
6
6
6
6
8
8
9
9
8
8
14
14
16
16
14
14
MAX
MAX
MAX
FUNCTION TABLE
G
H
L
L
L
L
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT:ns
44
INPUT
OUTPUT
MAX or MIN
A or B
Y or Y
MAX
A/B
Y or Y
MAX
G
Y or Y
MAX
INPUT
A
A/B
X
X
L
L
H
L
H
X
X
H
B
X
X
X
L
H
OUTPUT
Y
Y
L
L
L
H
L
H
L
H
H
L
Y
Y
2G240
Logic Diagram
1
DUAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1OE
1A
6
2
1Y
7
2OE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX
MAX
MAX
2A
3
5
2Y
FUNCTION TABLE
(each buffer)
INPUT
OE
A
L
H
L
L
H
X
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPLZ
tPHZ
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
4
4
5
5
4.2
4.2
4.6
4.6
5.4
5.4
5.5
5.5
5.5.
5.5
6.6
6.6
5.7
5.7
11.3
11.3
11.7
11.7
12.8
12.8
2G241
Logic Diagram
DUAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
1OE
1A
2OE
RECOMMENDED OPERATING CONDITIONS
2A
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX
MAX
MAX
tPLH
tPHL
tPZL
tPZH
tPLZ
tPHZ
tPZL
tPZH
tPLZ
tPHZ
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
OE
Y
MAX
OE
Y
MAX
1
6
2
1Y
7
3
5
2Y
FUNCTION TABLE
SWITCHING CHARACTERISTICS
PARAMETER
OUTPUT
Y
L
H
Z
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
3.7
3.7
3.8
3.8
3.4
3.4
3.3
3.3
3.3
3.3
4.3
4.3
4.7
4.7
4.4
4.4
4.1
4.1
4.2
4.2
4.8
4.8
5.6
5.6
5.8
5.8
4.7
4.7
5.2
5.2
8.8
8.8
9.9
9.9
11.6
11.6
8.8
8.8
12.5
12.5
INPUT
1OE
1A
L
H
L
L
H
X
OUTPUT
1Y
H
L
Z
INPUT
2OE
2A
H
H
L
H
L
X
OUTPUT
2Y
H
L
Z
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
45
3G04
Logic Diagram
TRIPLE INVERTER GATE
1A
2A
3A
1
7
3
5
6
2
1Y
2Y
3Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
FUNCTION TABLE
(each inverter)
MAX
MAX
MAX
INPUT
A
H
L
OUTPUT
Y
L
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A
Y
MAX
3.2
3.2
4.1
4.1
4.4
4.4
7.9
7.9
3G06
Logic Diagram
TRIPLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
1A
2A
3A
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
ICC
VO
IOL
MAX
MAX
MAX
tPLH
tPHL
UNIT:ns
46
7
3
5
6
2
FUNCTION TABLE
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
0.01
5.5
32
0.01
5.5
24
0.01
5.5
8
0.01
5.5
4
mA
V
mA
(each inverter)
INPUT
A
H
L
SWITCHING CHARACTERISTICS
PARAMETER
1
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A
Y
MAX
2.9
2.9
3.4
3.4
3.9
3.9
7.2
7.2
OUTPUT
Y
L
H
1Y
2Y
3Y
3G07
Logic Diagram
TRIPLE BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
1A
2A
3A
1
7
3
5
6
2
1Y
2Y
3Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
VO
MAX
MAX
0.01
5.5
0.01
5.5
0.01
5.5
0.01
5.5
mA
V
IOL
MAX
32
24
8
4
mA
FUNCTION TABLE
(each buffer/driver)
INPUT
A
H
L
OUTPUT
Y
H
L
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A
Y
MAX
2.9
2.9
3.7
3.7
4.3
4.3
7.8
7.8
3G14
Logic Diagram
TRIPLE SCHMITT-TRIGGER INVERTER
1A
2A
3A
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
ICC
IOH
IOL
MAX
MAX
MAX
1
7
3
5
6
2
1Y
2Y
3Y
FUNCTION TABLE
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
(each inverter)
INPUT
A
H
L
OUTPUT
Y
L
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A
Y
MAX
4.3
4.3
5.4
5.4
5.7
5.7
9.2
9.2
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
47
3G17
Logic Diagram
TRIPLE SCHMITT-TRIGGER BUFFER
1A
2A
3A
1
7
3
5
6
2
1Y
2Y
3Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX
MAX
MAX
FUNCTION TABLE
INPUT
A
H
L
OUTPUT
Y
H
L
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A
Y
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
3G34
Logic Diagram
TRIPLE BUFFER GATE
1A
2A
3A
1
7
3
5
6
2
1Y
2Y
3Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
UNIT
ICC
IOH
IOL
0.01
-32
32
0.01
-24
24
0.01
-8
8
0.01
-4
4
mA
mA
mA
MAX
MAX
MAX
FUNCTION TABLE
(each gate)
INPUT
A
H
L
OUTPUT
Y
H
L
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
48
INPUT
OUTPUT
MAX or MIN
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
A
Y
MAX
3.2
3.2
4.1
4.1
4.4
4.4
7.9
7.9
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION
GATE (AND/NAND/OR/NOR)
3
3
4
2
BUF
BUF
BUF
2
OC
OC
SCH
2
OC
BUF
OC
4
SCH
SCH
6
POS-NAND
3
3
BUF
OC
OC
OC
BUF
BUF
OC
BUF
SCH
SCH
4
8
12
13
2
3
1
1
1
OC
BUF
BUF
BUF
SCH
3S
4
POS- OR
2
BUF
SCH
BUF
BUF
6
3
3
BUF
OC
4
BUF
BUF
2
SCH
POS- NOR
6
3
3
4
2
5
2
BUF
BUF
BUF
8003
00
01
03
24
26
37
38
132
1000
1003
7003
39
804
1804
10
12
1010
13
18
20
22
40
140
1020
618
30
134
133
○
×
×
×
×
○
×
○
○
×
○
×
○
○
○
○
× ○
○ ○A ○
×
× ○B
×/-/-
×/-/-
○
○/○
×/○/○
○/○
○/○/○
○/○/○
○
○
○A ○A
○/○
-/○
×/-/-
×/-/-
○
○
○A
-/○
×/○/○
×/○/○
×/-/-
-/×/-
○ ○A
×
○ ○B
○
×
×A ○A
×A
LV
×/○/-
×/○
LVC
×/○/-
○/○
AVC
AHCT
-/○
○
LVT
○/○
○A ○A
ALVC
ACT
AHC
ALVT
○
○/○/○
○B
×
○ ○
○
○
○/○
○ ○ ○
○
×
×
×A ○A
ABT
×
×
× ○A
×
○A
BCT
○
○/○/○
○/○
×/-
F
○
○
×
AC
6
○
○
×
Advanced CMOS
HCT
SCH
POS-AND
08 ×
09 ×
15
1008
7001
808
1808
11
1011
21
Technology
BiCMOS
CMOS
HC
OC
OC
BUF
4
2
Device
AS
Output
S
Input
LS
Curcuit
TTL
No. of
Input
ALS
Bipolar
Description
○
○/×/○A
○A
○
-/○
×/×
○
×
○
×
×
×
×
×
×
×
○
×
×
×
×
○
32 ○
1032
7032
832
1832
4075
○
02
28
33
36
128
1002
7002
1036
805
1805
27
23
25
4002
260
○
×
○
○
×
×
○A ○B
×A ×
○ ○A ○ ○
×
×
× ○A ○
× ×
× ×
○
×
× ○A ○
×
× ○
○
○
○A ○A
○/○
-/○
×/×/○
×/×/○
×/○
-/○
×/-/×
○/-/×
○/○
○/○/○
○/○/○
○
○
○A ○A
○
○
○A ○A
○
○A
×
○
×/-
○ ○ ○
× ○A
○/○
○
○/×/-
○A ○B
×A ×
○ ○A ○
×
○A
×/○/○
×/○
-/○
○
○/○
○/○
×/-/○
×/-/○
×
×/-
-/○
×/-/×
×/-/×
○
×A
○/-
×
×
○
×A
○A ○B
× ×
○A ○ ○
○
×/○/○
○A
×/○
○
○
Explanatory notes [Input] SCH：Schmitt-Trigger Inputs
Explanatory notes [Output] BUF：Buffered Output OC：Open-Collector Output 3S：3-State Output
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
51
GATE (EX-OR/EX-NOR/INVERTER/NONINVERTER/etc.)
OC
4
SCH
1
6
OC
SCH
BUF
OC
8
SCH
4
NONINVERTING
OTHER
OC
OC
1
6
1
2
6
6
4
2
8
1
10
1
11
1
12
3
-
6
OC
BUF
OC
OC
BUF
BUF
×
×
×/-/-
×/○
×
○
×
○
○
○
425
426
07
17
34
35
1034
1035
4050
×
×
○
○
○
○
○
○
○ ○B ○
○ ○A
○
○/○
○/-
○/○
○/○/○
-/-/○
○/○/○
-/-/○
○
○
○
○/○
○/○
×/○/○
×/○/○
○
○
○A
○ ○A
○
ー/○
○/○
○
○
○A ○A
× ×
○A
○ ○A
○
×/-/-
×/-/-
×/-/-
×/-/-
ー/○
×
○
×
×
×
×
○
×
×
×
×
×
×/-
×
×/×
×
×/-/-
×/-/-
×/-/×/-/-
×/-/×/-/-
×/×/×/×/×/-
Explanatory notes [Input] SCH：Schmitt-Trigger Inputs
Explanatory notes [Output] BUF：Buffered Output OC：Open-Collector Output 3S：3-State Output
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
52
○A ○A
×
○
○
AVC
○A ○A
○A
○A ○A
○A ○A
×/-/-
ALVC
○A ○A
LV
○
LVC
LVT
ALVT
ABT
BCT
HCT
F
○
○/×
×
04
05
06
14
16
19
1004
1005
4049
U04
619
63
31
50
51
60
53
55
4078
54
64
65
800
802
7006
7008
7074
7075
7076
×/○/○
○/○/○
×/-
○
135
OC
OC
INVERTING
266
810
811
7266
-/○
AHCT
2
4
○/○
ACT
EX-OR/NOR
2
○ ○A ○
× ×
AHC
OC
EX-NOR
86 × ○A ○
136 × ○
386
×
Advanced CMOS
AC
OC
Technology
BiCMOS
CMOS
HC
4
Device
S
2
Output
AS
EX-OR
Input
ALS
Curcuit
LS
No. of
Input
TTL
Bipolar
Description
BUFFER/DRIVER(NON-INVERTING)
8
NONINVERTING
10
11
12
16
18
20
32
3S
3S
3S
3S
3S
3S
OC
OC
3S
3S
R3S
R3S
R3S
3S
3S
OC
OC
3S
R3S
3S
R3S
3S
R3S
3S
455
465
467
541
656
747
757
760
1241
1244
2241
2244
2541
25241
25244
25757
25760
827
2827
29827
5400
5402
16903
16241
○
○C
○C/
○C1
H○
○A
○B/
T○/
H○A/
Z○
○B
H○
○/○
○
×
○
×
×
○/○1
○ ○/○ ○/○
○
○
○
○A/-
×
○/○/-
○A/
H○A/
Z○A
○
○
○A
○A
AVC
ACT
○A
-
×/○/○
○/○/○ ○/○/○
-/-/○
×/-/-
-/-/○
×/-/-
○
○A
○/H○
○A
×/○/○
×/×/-
○
○C/○B/-
○
○
×/-/-
×/-/-
○A
×
H×A
○A
○A
H○
○A
H○
○A/ H
○
○B/
H○A
○A
H○
H○
○A/H○
162244
○
R3S
3S
R3S
162541
16825
162825
○
○
16827
162827
32244
○
○
○
○
R3S
3S
3S
3S
○
○A
○A
○A
16244
16835
○A
○A
○A
○/○
○/-
16541
162241
162835
○
×
3S
3S
○
○
○
×/-
3S
R3S
R3S
×/○/-
○
○
ALVC
○A
○A ○ ○/○ ○/○
AC
H○
H○
ALVT
BCT
HCT
F
HC
AS
ALS
S
○
○
○
○ ○/○ ○/○ ○A/○A
○ ○/○ -/○ ×A/○A
○/○ -/○
○/○ -/○
○A ○ ○/○ ×/○
○/-
LV
244
○A
○A
○A
○A
○ ○
LVC
3S
×
×
×
×
AHCT
125
126
365
367
241
LVT
3S
3S
3S
3S
3S
Advanced CMOS
AHC
6
Technology
BiCMOS
CMOS
ABT
4
Device
LS
No. of Output
Output
TTL
Bipolar
Description
H○
○
○
○
○
○
○
○
○A/
H○A/
Z○A
H○A
○A/
H○A
H○
○
H○
○/H○
H○
H○
H○
○
×
H○
×
H○
H○
○
○A
○A/
H○
○
○/H○
○/
H○
○/
H○
H○
H○
H○
○
○
Explanatory notes [Output] 3S：3-State Output R3S：Series Resistor and 3-State Output OC：Open-Collector Output
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
53
BUFFER/DRIVER(INVERTING､INVERTING AND NON-INVERTING､ADDRESS DRIVERS)
8
INVERTING
10
11
12
16
20
32
INVERTING
AND
NONINVERTING
○A ○ ○/○ ○/○
○/○/○ ○/○/○
○A
○A/
Z○A
○
○
○A
○A
×/×
×
○
×
×
○/○1
×
×
× ○/○ ○/○
○
×
×
×
×
○A/-
○/-
-/-/○
×/-/-
×/-/-
×/-/-
×
○
○
○
×
○
○
○A
×/×/○A
×/×B/-
■
○
○
3S
16240
○A
16540
162240
162540
16828
32240
○A
230
-/-/○
×/-/-
○/-
○/H○
H○
○/H○
×
H○
×
×
×
○
×
×
8
1-2
ADDRESS
DRIVERS
1-4
OC
762
3S
16830
R3S
162830
3S
3S
3S
R3S
R3S
R3S
16344
16831
16832
162344
162831
162832
×
Explanatory notes [Output] 3S：3-State Output R3S：Series Resistor and 3-State Output OC：Open-Collector Output
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
54
H○A/
Z○A
H○A
H*
H○/
HS○
H○
H○
H○
H○
○/H○
H○
AVC
○
ALVC
LV
○
×
3S
R3S
R3S
3S
3S
3S
LVC
H○
AHCT
○
ACT
○A/H○
AHC
○A
Advanced CMOS
AC
○/-
ALVT
F
AS
ALS
S
○
LVT
○
-/○
ABT
240
456
466
468
540
655
746
756
763
1240
2240
2540
25240
25756
828
2828
29828
5401
5403
×
○A/
○A1
×/○
○/○
BCT
3S
3S
3S
3S
3S
3S
3S
OC
OC
3S
R3S
R3S
3S
OC
3S
R3S
3S
R3S
R3S
366 × ×
368 × ○A
436
×
437 ×
231
HCT
3S
3S
3S
3S
3S
Technology
BiCMOS
CMOS
HC
6
Device
LS
No. of Output
Output
TTL
Bipolar
Description
BUS TRANSCEIVER(NON-INVERTING)
NONINVERTING
8
×/-/○
○/-/○
○A
○A/
H○A/
Z○A
○/H○
AVC
○
×/-/×/-/×/-/○/-/-
ALVC
○
×/-/×/-/×/-/×/-/-
LV
ALVT
○/○/○
○/○/○
LVC
OC
621
×
3S
3SOC
623
639
○
×
OC
641
○
3S
645
○/
○1
×
○A/
○A1
○A
○A
○A/
○A1
○A/
○A1
3S
646
○
○A
OC
647
×
×
3S
652
○
○A
3SOC
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
654
657
659
665
852
856
877
899
1245
1645
2245
2623
2645
2952
25245
25543
25621
25623
25641
25646
25647
25652
25654
3245
×
○
861
29861
AHCT
470
472
474
543
615
3S
3S
○B/ H
○A/ R
○
ACT
3S
3S
3S
3S
OC
10
○B/
H○
AHC
○
16409
○/○
AC
245
3S
LVT
3S
9X4
BCT
○/○
ABT
-/○
○/○
×
×
○
×
×
×
×
○
833
853
29833
29853
863
29863
HCT
F
-/○
○
HC
AS
S
×
○
440
441
442
443
444
448
449
243
1243
4245
9
×
226
3S
OC
3S
3S
3S
OC
3S
3S
3S
3S
8+1P
○A
○A/
○A1
Advanced CMOS
×
3S
3SOC
3SOC
3SOC
3SOC
3S
3S
Technology
BiCMOS
CMOS
ALS
4
Device
LS
No. of Output
Output
TTL
Bipolar
Description
○
×
×
×
×
×
○/-
○/-
○/-
○A
○/-
○
H○
○A
○
○
○/-
○/-
○
○/○
○/○
○/-
○/
○A
H○
×/-/○
×/-/○
○A
○
○/○
○/○
○/-
○/
○A
H○
×/-/○
○/-/○
○A
×/-
○A
×/-/-
×/-/-
×/×/-
×/×/×/-/×/-/×/-/-
×/-/×/-/×/-/-
○
×
×
×
×/○A
○A
○/-
○/R○
H○
R○A
×/○/×/×/×/×/×/×/×/×/-
○A
○H
H○
○A
×
×
×
×
×
×/×/-
○
○B/-
×
×B/-
C○A
○A/
C○A
○
○
×/-/×/-/-
×/-/×/-/-
○
×/-/-
×/-/-
○A
○
×/-/-
×/-/-
○A
H○/
HR○
Explanatory notes [No. of Output] +P：With Parity Bit
Explanatory notes [Output] 3S：3-State Output R3S：Series Resistor and 3-State Output
Explanatory notes [Output] OC：Open-Collector Output 3SOC：3-State Output / Open-Collector Output
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
55
BUS TRANSCEIVER (NON-INVERTING)
12/24
16/32
16
16X3
18X3
NONINVERTING
16+2P
18
18/36
20
32
36
3S
16268
3S
16269
3S
3S
3S
3S
3S
3S
16270
16271
16272
162268
162269
162280
3S
16245
3S
3S
16334
16470
○
3S
16543
○
3S
3S
3S
3S
16623
16646
16652
16952
○
○
○
○
R3S
162245
○/H○
AVC
ALVC
LV
×
H○/
HR○A
H○
H○
×
H○
○
HG○
○A/
H○
R3S
164245
R3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
162334
32316
32318
16657
16833
16853
16472
16474
16500
16501
16525
16600
3S
16601
3S
3S
3S
R3S
R3S
R3S
R3S
16834
16863
16901
162500
162501
162525
162600
R3S
162601
○
R3S
3S
R3S
3S
3S
R3S
3S
3S
162834
16282
162282
16836
16861
162836
32543
32952
H○
×
○B/
H○A
H○
○
○
*
○
○A/
H○A/
HR○A/
Z○A
H○/
HR○
○
○/H○
○
×
H○
H○
H○
H○
○A/
H○
*
×
○
*
×
×
○
○
○
○
○
H○
○/
H○A
H○
H○A
H○A
H○A
H○
×
H○
○
○
○/
H○
R○
○/H○
H○
H○
○
○
○
○
×
×
×
×
○B
○
H○
H○
-
○
○
-
H○
○
○
H○
H○
H○
H○
H○
H○/
HR○
○
H○
H○
○
○
○
H○
H○/
HR×
○
H○
HG○
H*
○
○/H○
3S
32245
H○
3S
3S
32500
32501
×
H○
H○
Explanatory notes [No. of Output] +P：With Parity Bit
Explanatory notes [Output] 3S：3-State Output R3S：Series Resistor and 3-State Output
Explanatory notes [Output] OC：Open-Collector Output 3SOC：3-State Output / Open-Collector Output
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
56
LVC
AHCT
ACT
AHC
Advanced CMOS
AC
LVT
ALVT
BCT
HCT
F
HC
ABT
Technology
BiCMOS
CMOS
AS
S
ALS
Device
LS
No. of
Output
Output
TTL
Bipolar
Description
○/ H
○A
H○
H○
*
BUS TRANSCEIVER(INVERTING､NON-INVERTING/INVERTING)
8
INVERTING
8+1P
9
10
16
18
NONINVERTING
/INVERTING
8
3S
640
OC
642
3S
OC
3S
3SOC
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3SOC
3SOC
3SOC
3SOC
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
648
649
651
653
658
664
1640
2620
2640
2953
25620
25622
25640
25642
25648
25649
25651
25653
834
854
29834
29854
864
29864
862
29862
16471
16544
16620
16640
16648
16651
16862
16953
16475
16524
16864
3S
OC
OC
OC
3S
643
644
758
759
7340
AVC
×/-/-
ALVC
×/-/-
LV
×/-/×/-/×/-/×/-/-
LVC
×/-/×/-/×/-/×/-/-
AHCT
ACT
Advanced CMOS
AHC
LVT
×/-
ALVT
×/-
BCT
×
ABT
S
HCT
×
×
F
638
×
HC
×
×
3SOC
×
×
AS
242
446
1242
2242
544
471
473
475
614
620
622
ALS
3S
3S
3S
R3S
3S
3S
3S
3S
OC
3S
OC
Technology
BiCMOS
CMOS
AC
4
Device
LS
No. of Output
Output
TTL
Bipolar
Description
×
×
×
○/
○1
○/
○1
○
×
×
×
×
○A × ×
×
× ×
○A/
○A
○A1
○B/ ○
○B1
○A/
×
○A1
○A ○
×
○A ×
○
×/-
×/-
×/-
×/-
○
○/○
×/○
○/-
○
×/-
×/-
×/-
×/-
×/-
×/-
×/×/-
×/×/-
×/-/-
×/-/-
×/-/-
×/-/-
×/-/-
×/-/○
×/-/×/-/-
×/-/×/-/-
×/-
○
×
×
×
×/×/×/×/×/○/×/×/×/×/-
×
○
×/○/-
×
○B/-
×
×B/-
○
×/-/-
×/-/-
×/-/-
×/-/-
×
×
×
×
×
×
○
×
×
H○
×
×
×
×
×
×
×
×
×
×
×/-
×/-
×/-/-
×/-/-
×/-
Explanatory notes [No. of Output] +P：With Parity Bit
Explanatory notes [Output] 3S：3-State Output R3S：Series Resistor and 3-State Output
Explanatory notes [Output] OC：Open-Collector Output 3SOC：3-State Output / Open-Collector Output
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
57
J/K FLIP-FLOP
2
4
AVC
ALVC
16534
162374
16823
162823
16721
16821
162721
162821
16722
32374
322374
×/-/○
LV
/Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
×/-/○
LVC
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
-/○
-/○
AHCT
16374
×/×/×/○
○/○
×/×/-
AHC
Q
×/-/○
LVT
3S
ALVT
74
171
175
379
174
378
273
374
377
478
534
564
574
575
576
577
825
826
874
876
878
879
4374
29825
29826
823
824
29823
29824
821
822
1821
29821
29822
16820
162820
×/-/○
ABT
B
B
B
B
Q
Q
Q
Q
Q
Q
/Q
/Q
Q
Q
/Q
/Q
Q
Q
Q
/Q
Q
/Q
Q
Q
Q
Q
/Q
Q
/Q
Q
/Q
Q
Q
/Q
Q
Q
-/○
-/○
BCT
2S
2S
2S
2S
2S
2S
2S
3S
2S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
×
×
× ○A
× ○A
○A ○A ○
×
×
×
× ×
×
○ ○A
○A ○A ○A
○
× × ×
×
× × ×
×
×
Advanced CMOS
×/○
○/○
F
Q
・
/Q
AS
Output
72
70
73
109
110
111
376
76
78
107
112
113
114
276
S
B
B
B
B
B
B
Q
B
B
B
B
B
B
Q
ALS
2S
2S
2S
2S
2S
2S
2S
2S
2S
2S
2S
2S
2S
2S
Technology
BiCMOS
CMOS
ACT
NEG
B
B
B
B
B
B
B
B
B
B
B
B
B
B
Device
AC
4
Q
・
/Q
HCT
2
Output
HC
1
POS
Bipolar
PRE
･
CLR
LS
Curcuit
TTL
Trigger
○A
D-TYPE FLIP-FLOP
C
C
8
C
P
C
C
POS
9
C
C
C
C
10
10X2
16
18
20
22
32
C
C
○
○
×/-/×/-/×/-/-
○
×/-/×/-/-
×/-/×/-/-
○A
○A
×/-/×/-/-
×/-/×/-/-
○A
○
○
×
×
×
×
○
×
○A
H○
H○
H○
○A
○A
○A
○
○
○A
○
○
○
○
○A
○A
○A
○
○
○A
○A
H○
○/×/-
×/×/-
○/×/H○
H○
○A
H○ H○
○
○
○A/
H○A
H○
○
×
H○
○/○H
○A
○
×
*
H○
H○
H○
○
H○
H○
H○
×
×
○
H○ H○
H○
Explanatory notes [Trigger] POS：Positive edge NEG：Negative Edge
Explanatory notes [PRE ･ CLR] B：Preset and Clear C：Clear Only
Explanatory notes [Output] 2S：Totem pole Output 3S：3-State Output
Explanatory notes [Q･/Q] B：Q･/Q-Output Q：Q-Output /Q：/Q-Output
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
58
LVC
×/-/×/-/×/-/-
○B
○A
×
×A
○
×
○
×
○A
×
○
○
×
×
○B
×
×
○A
×A
×
×
○A
×
×
×
×
×
×
○
-/○
LV
○A
×
LVT
×/○ ×/×/○ ×/○/○ ○/-
○A
○B
○B
○A
○B
○A
ABT
×/○
×/○
○/○
○ ○B ○
×
○ ○ ○ ○A
×
○
×
○ ○A ○ ○
○A
BCT
○
○A
○A
×/-/○
×/-/×/-/○
×/-/×/-/○
○/○/○
×/-/×/-/×/○/×/○/×/○/○
F
○/○
○/○ ○/○/○
○/-/○
×/-/×/-/○
×/-/×/-/○
×/○/○
×/-/×/-/×/○/○
×/○/×/○/○
AS
○/○/○
-/○
ALS
○/○
○/○
×/○/○
×/○/○
○/○
○/○
S
○/○
○
AVC
AHCT
○/○/○
○ ○A ○A ○
ALVC
ACT
ALVT
AHC
× ○A
×
○
×
× ○
○
× ○
○
○
×
Advanced CMOS
AC
6
B
C
C
Technology
BiCMOS
CMOS
HCT
4
Bipolar
Device
HC
2
PRE
･
CLR
LS
Curcuit
TTL
Trigger
H○A
H○
LATCH
2S
2S
2S
2S
Q
Q
Q
Q
75 ×
77
375
100 ×
R/B
8
8
8
8
8
9
9
10
10
3S
3S
3S
3S
3S
3S
3S
3S
3S
Q
/Q
Q
Q
/Q
Q
/Q
Q
/Q
990
991
666
996
667
992
993
994
995
8
8
8
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
10
10
10
10
12/24
12/24
2S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
3S
Q
Q
Q
/Q
Q
/Q
/Q
Q
Q
Q
Q
/Q
/Q
Q
Q
Q
/Q
/Q
Q
Q
/Q
/Q
Q
Q
116 ×
373
2373
533
573
563
580
873
880
845
29845
846
29846
843
1843
29843
844
29844
841
29841
842
29842
16260
162260
16
3S
Q
16373
16
16
18
20
20
32
3S
3S
3S
3S
3S
3S
/Q
Q
Q
Q
Q
Q
16533
162373
16843
16841
162841
32373
D
B
C
B
C
C
C
C
P
B
B
B
B
B
B
B
B
B
B
○
○/○/○
○
○
○A
○A
H○
×/○/×/○/○
×/○/○
×/○/×/○/○
×/○/-
○
○
○A
○A
×/-/-
×/-/-
×/-/-
×/-/-
×/-/-
×/-/-
×/-/-
×/-/-
×/-/-
×/-/-
LVT
×/-/-
ABT
×/-/-
○/-/-
HC
-/○
×/○
AVC
×/○/○
ALVT
HCT
H○
○A
○A H○
○/○
×/×/○
×/×/-
F
○
○
ALVC
BIS
4
4
4
8
LV
259 × ○B
4724
LVC
279 × ○A
Q
Q
AHCT
Q
2S
2S
ACT
2S
8
8
AHC
4
AD
Advanced CMOS
AC
S-R
Technology
BiCMOS
CMOS
BCT
Bipolar
Device
AS
Q
･
/Q
S
PRE
・
CLR
LS
Output
ALS
Curcuit
TTL
Type
○
×
○
○
○
○
×
○
×
○
○ ○A ○
○/○ ○/-
○A
○C
○B
○B
○B
×A
×
×
×
×
○
○ ○/○
○
○A × ×/○
○A ○ ○A/○
× ○/○
×
×A
×
×
×
×
×
×
×/○ ×/○/○ ○/×/○ ×/-
× ×
× ×
× ×
○ ×A
× ×
× ×
×
○
×/×/○
○/×/○A
×/-/-
×/-/-
×/-/-
×/-/-
○
○
○A
×/×/H○
H○
H○
H○
○A H○
H○
○
○
○A/
H○A
H○
○
×
×
×
H○
H○
H○
○
○
○
×
○
H○
H○
H○A
*
Explanatory notes [Type] S-R：S-R Latch AD：Addressable Latch BIS：Bistable Latch
Explanatory notes [Type] R-B：Read-Back Latch D：D-Type Transparent Latch
Explanatory notes [PRE ･ CLR] B：Preset and Clear C：Clear Only
Explanatory notes [Output] 2S：Totem-Pole Output 3S：3-State Output
Explanatory notes [Q･/Q] B：Q･/Q-Output Q：Q-Output /Q：/Q-Output
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
59
SHIFT REGISTER
C
S
S
8
P
S
4
16
C
2S
164 ×
2S
898
R
2S
91 ×
×
R
R
2S
3S
94 ×
674
○
LV
AHCT
×/○
○
×
×
○
○
○
×/-/○
×/-/○
AVC
C
10
×/-/○
×/-/○
ALVC
8
P
×/-/-
AVC
S/P
S
×/-/-
AHC
R
S
LVT
165 × ○A
166 × ○A
ALVT
2S
2S
-/○
ALVC
8
ABT
R
R
S
×/○
HCT
C
S/P
○
LVC
8
×/○
LVC
5
×
×
ACT
S/P
× ×
×
×C
×A
× ○A ×
× ×
×
×
○ ×
×
×
Advanced CMOS
AC
S/P
×
×
×
×
BCT
178
179
195
95
295
395
194
96
322
198
299
323
199
F
2S
2S
2S
2S
2S
3S
2S
2S
3S
2S
3S
3S
2S
Technology
BiCMOS
CMOS
HC
C
C
C
C
C
C
C
C
R
R
R
B
B
R
B
R
R
B
B
B
B
C
4
Device
AS
Output
S
Shift
CLR
LS
No. of
Bit
TTL
Output
Type
ALS
Bipolar
Input
Type
○
×
×
○A
×/○
-/○
○/○
○/○
-/○
-/○
○/○
-/○
×/×/-
○A
○A
-/-/○
-/-/○
×/-/-
×/-/-
○A
SHIFT REGISTER WITH LATCH
C
C
C
C
C
R
R
R
R
B
3S
OC
OC
2S
3S
595
599
596
594
673
○
×
○
○
○
S/P
S
8
C
R
2S
597
○
○/-
○/-
-/○
LV
8
8
8
8
16
AHCT
S/P
ACT
S
AHC
×
×
○
Advanced CMOS
AC
671
672
598
ALVT
3S
3S
2S
LVT
B
B
R
ABT
C
C
C
HCT
4
4
8
BCT
S/P
Technology
BiCMOS
CMOS
HC
S/P
Device
F
Output
AS
Shift
ALS
CLR
LS
No. of
Bit
TTL
Output
Type
S
Bipolar
Input
Type
○
○
○A
○
○
○A
-/○
Explanatory notes [Input/Output Type] S：Serial P：Parallel S/P：Alternative Serial/Parallel
Explanatory notes [CLR] C：With Clear
Explanatory notes [Shift] R：Right-Shift B：Alternative Shift Right/Left
Explanatory notes [Output] 2S：Totem-Pole Output 3S：3-State Output
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
60
REGISTER(ETC）
ALVC
AVC
AVC
×/-/×/-/-
ALVC
×/-/×/-/-
LV
×/-/-
AHCT
×/-/×/-/-
×/-/-
AHC
LVT
ALVT
ABT
×/-/×/-/-
LVC
○A
-/○
LVC
○
×
× ○A
×
-/○
ACT
×
HCT
×
BCT
×
×
F
○
×
○
HC
S
AS
×
×
Advanced CMOS
AC
8BIT DIAGNOTICCS/PIPELINE REGISTER
172
170
670
870
858
871
859
298
398
173
396
818
819
29818
Technology
BiCMOS
CMOS
ALS
REGISTER FILES 8WX2B
REGISTER FILES 4WX4B
REGISTER FILES 4WX4B
REGISTER FILES 16WX5B
REGISTER FILES 16WX5B
REGISTER FILES 16WX6B
REGISTER FILES 32WX4B
MUX WITH STRAGE
MUX WITH STRAGE
4BIT BUS-BUFFER REGISTER
8BIT STORAGE REGISTER
LS
Device
TTL
Bipolar
Descriotion
×/×/○
-/○
×
×/-
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
MONOSTABLE MULTIVIBRATOR
R
R
-/○
-/○
-/○
-/○
○A
○A
LV
ACT
AC
ALVT
LVT
ABT
HCT
-/○
-/○
-/○
-/○
AHCT
○
○
○
Advanced CMOS
AHC
123 ○
221 ○
423
4538
BCT
R
○
×
HC
C
C
C
C
2
121 ○
122 ×
422
F
R
R
Technology
BiCMOS
CMOS
AS
C
C
ALS
1
Device
LS
Retrigger
TTL
CLR
S
Bipolar
Curcuit
○A
○A
Explanatory notes [CLR] C：With Clear
Explanatory notes [Retrigger] R：With Retrigger
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
61
DECADE/BINARY COUNTER
S
4
Y
A
S
A
A
8
A
A
9
D
S
S
S
S
S
S
S
A
S
S
A
J
A
4
A
A
A
A
A
A
A
A
A
7
12
14
S
S
A
A
D
A
A
S
S
S
S
D
4
S
BIN
Y
A
A
A
A
S
A
A
A
A
A
S
8
S
S
S
A
S
A
A
S
S
A
A
A
A
A
R
R
R
R
J
J
S
Y
OTH
A
1
S
A
S
S
12
68
90
290
390
176
196
490
560
162
160
690
692
568
168
668
190
696
698
192
4017
69
93
293
393
177
197
4024
4040
4020
4060
4061
561
163
693
161
691
4518
669
699
169
191
697
193
569
461
463
590
591
592
593
4022
4520
7022
40103
469
579
869
867
92
×
×
×
×
×
×
×
×
-/○
-/○
○/○
-/○
×/○
○/○
○/○
○/○
×/-
-/○
-/○
-/○
-/○
×/-/-
×/-/-
×/-/-
×/-/-
○A
× ○A ○ ○B ○ ○A ○/○ -/○
×
× ○A
○B ○ ○A ○/○ -/○
×
-/○
○
×
○B × ○B ○A ○
× ○
○A
○/○ -/○
○
× ○
○A
×A ○/○ -/○
○A
×
○
×
○
○
○A/-
○A
×/-/○
×/-/○
○A
×/-/○
×/-/○
○A
×/-/×/-/-
×/-/×/-/-
×/-/×/-/×/-/×/-/×/-/-
×/-/×/-/×/-/×/-/×/-/-
×/-/×/-/-
×/-/×/-/-
×/-/×/-/×/-/×/-/-
×/-/×/-/×/-/×/-/-
×/-/○
×/-/○
○ ○
○A ○
×
○
Explanatory notes [DEC･BIN] DEC：Decoder BIN：Binary Counter OHE：Other
Explanatory notes [ASYN･SYN] ASYN：Asynchronous SYN：Synchronous
Explanatory notes [Up/Down] Y：Up/Down
Explanatory notes [CLR] A：With Asynchronous Clear S：With Synchronous Clear
Explanatory notes [LOAD] A：With Asynchronous Clear S：With Synchronous Clear 9：Preset 9
Explanatory notes [ETC] D：2-Curcuit R：With Series Register J：Johnson Counter 12：Devide By-Twelve Counter
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
62
AVC
ALVC
LV
○A
×
LVC
×/-/×/-/-
AHC
×/-/×/-/-
AHCT
LVT
×/-/×/-/-
×
×
○
○
○
×
×/-/×/-/-
×
×
× ×A × ×B × × ×/× ×A
×B × × ×/×
×
×
×
× × × ×
×
× ×
×
×A ×/○
×
×
× ×
×
×/○
×/○
×
×
×
×
×
ALVT
-/○
ABT
×/○
BCT
F
AS
×
○
×
○
ACT
S
A
A
S
DEC
D
Advanced CMOS
AC
A
A
A
A
HCT
9
4
Technology
BiCMOS
CMOS
HC
A
A
Device
S
UP/DOWN CLR LOAD ETC
Mode
ALS
No. of
Bit
LS
DEC ASYN
･
･
BIN SYN
TTL
Bipolar
RATE MULTIPLIER/FREQUENCY DIVIDERS
ALVC
AVC
ALVC
AVC
LV
LVC
AHC
ACT
AHCT
Advanced CMOS
AC
LVT
ALVT
ABT
HCT
BCT
F
HC
×
×
Technology
BiCMOS
CMOS
AS
56
57
97 ○
167 ×
292
294
S
LS
FREQUENCY DIVIDERS
FREQUENCY DIVIDERS
6BIT BINARY RATE MULTIPLIER
DECADE RATE MULTILIER
PROGRAMABLE FREQUENCY
DIVIDER/DIGITAL TIMERS
TTL
Device
ALS
Bipolar
Descriotion
○
○
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
DATA SELECTOR/MULTIPLEXER
×/○
×
○
○
×
○
○
×
○
×
○ ○B ○/○
×/× ○B ○/○
×/○
×/-/○
-/○
× × ×
○ ○ ○
○ ○A ○
× × ×
×/○/○
○/○
×/-/○
-/○
157 × ○ ○ ○A ○ ○A ○/○
158
○ × ○ ○ ×A ○/○
399
○
257
○B ○ ○A ○ ○ ○/○
258
○B × ○A ○ ○ ○/○
4053
-/○
857
○ ×
604
×
×
605
×
606
×
607
×
16254
LV
AD
×/-/×
LVC
16
×/-/○
×/-/○
AHC
3S
16
×/-/○
-/○
-/○
-/○
-/○
-/○
AHCT
U
S
S
S
S
2/1
S
ACT
1
1
4
1
1
4
6
8
8
8
8
AC
2S
2S
2S
3S
3S
3S
3S
3S
OC
3S
OC
352
153 ×
253
353
4052
4352
16460
162460
ALVT
2
2
2
2
2
2
4
4
-/○
○A
×
×
LVT
2S
3S
3S
3S
3S
3S
3S
3S
4/1
×/-/×/-/-
ABT
151 ×A ○
152
251 × ○
354
×
356
×
4051
4351
355
×
357
×
BCT
1
1
1
1
1
1
1
1
1
Advanced CMOS
×/-/×/-/-
HCT
8/1
2S
2S
3S
3S
3S
3S
3S
OC
OC
HC
150 ○
250
850
851
4067
F
1
1
1
1
1
Technology
BiCMOS
CMOS
AS
2S
3S
3S
3S
2S
Device
ALS
16/1
ETC
LS
Curcuit
TTL
Output
S
Bipolar
No. of
Input/output
○A
×/-/×/-/○
×/-/○
×/-/-
-/○
-/○
×/-/×/-/○
×/-/○
×/-/○A
-/○
×
H○
H○
○/○
-/○
×/-/○
×/-/○
×/-/○
×/-/○
○/○
-/○
-/○
○/-/○
×/-/-
○/-/○
×/-/○
○
○
○
○
○A
○A
○A
-
○A
×
Explanatory notes [Output] 2S：Totem pole Output 3S：3-State Output OC：Open-Collector Output
Explanatory notes [ETC] S：Storage Register
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
63
DECODER/DEMULTIPLEXER
×
○/○
×/-
○/○
×/-/○
○/-/○
×/-/○
×/-/○
×/-/○
×/-/-
○/-/○
×/-/-
○
○
○A
○A
○
○
○A
○A
AVC
×
ALVC
139
○A ○A ○
239
155 × ○A
156 × ○
○
-/○
○/○
-/○
×/○
AVC
○A ×
× ×
×/○
○/○
×/○
×/○
ALVC
×
○
LV
2
2
2
2
○ ○A ○A ○
LVC
2S
2S
2S
OC
2/4
238
138
237
137
131
×/-/-
AHC
AD
AD
AD
×/-/-
AHCT
1
1
1
1
1
-/○
ACT
2S
2S
2S
2S
2S
○/○
Advanced CMOS
AC
3/8
42 ×A ○
43 ×
44 ×
LVT
BD
BD
BD
-/○
-/○
-/○
ALVT
1
1
1
×/○
×/○
×/○
ABT
4/10
2S
2S
2S
4514
4515
154 ○
159 ○
BCT
AD
AD
HCT
1
1
1
1
F
2S
2S
3S
OC
HC
4/16
Device
Technology
BiCMOS
CMOS
AS
ETC
S
Curcuit
ALS
Output
LS
No. of
Input/output
TTL
Bipolar
Explanatory notes [Output] 2S：Totem pole Output 3S：3-State Output OC：Open-Collector Output
Explanatory notes [ETC] AD：Adress Latch BD：BCD TO DECIMAL
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
CODE CONVERTER、 PRIORITY ENCODER／REGISTER
×
278 ×
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
64
LV
LVC
AHC
AHCT
ACT
Advanced CMOS
AC
ALVT
LVT
ABT
-/○
○/-
-/○
×
BCT
AS
ALS
S
LS
×
○
○
HCT
×
×
×
×
HC
184
185
147
148
348
Technology
BiCMOS
CMOS
F
CODE CONVERTER
CODE CONVERTER
10-4 PRIORITY ENCODER
8-3 PRIORITY ENCODER
8-3 PRIORITY ENCODER
4BIT CASCADABLE PRIORITY
REGISTER
Device
TTL
Bipolar
Descriotion
Display Decoder/Driver
ALVC
AVC
ALVC
AVC
LV
LVC
AHCT
ACT
AHC
Advanced CMOS
AC
LVT
ALVT
HCT
BCT
F
HC
AS
ABT
Technology
BiCMOS
CMOS
LVC
45
141
145
445
46
47
48
49
246
247
347
447
248
249
142
143
144
S
30
60
15
7
30
15
5.5
5.5
30
15
7
7
5.5
5.5
7
7
7
ALS
D
D
D
D
7
7
7
7
7
7
7
7
7
7
B
B
B
Device
LS
V OH (V)
TTL
Bipolar
Function
○
×
○
○
×
×
○A ○
× ×
×
×
× ○
×
×
×
×
×
Explanatory notes [Function] D：BCD TO DECIMAL、7：BCD TO 7-SEGMENT、B：COUNTER/LATCH/DECODER/DRIVER
Explanatory notes [VOH] Off-Stage Output Voltage(V)
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
COMPARATOR
×
×
○
○
×
○
×
×/-/-
×/-/-
×/-/×/-/×/-/-
×/-/×/-/×/-/-
LV
×/-/-
AHC
T
×/-/-
AHC
ALVT
LVT
ABT
-/○
○/×
○
○
×
×
×
○
×
×A/○
×
×
BCT
○
F
○
AS
85 ×
29806
518
520
522
682
683
519
521
684
685
686
687
688
689
860
865
885
866
29809
ACT
2S
2S
OC
2S
OC
2S
OC
OC
2S
2S
OC
2S
OC
2S
OC
2S
2S
2S
OC
2S
Advanced CMOS
AC
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
N
HCT
Y
N
N
N
N
Y
Y
N
N
Y
Y
Y
Y
N
N
Y
Y
Y
Y
N
Technology
BiCMOS
CMOS
HC
N
Y
N
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
Y
S
Y
N
Y
N
N
N
N
Y
N
N
N
N
N
N
N
Y
N
N
Y
N
LS
S
S
20
20
20
20
20
S
S
S
S
S
S
S
S
S
S
LP
LPQ
-
Device
TTL
4
6
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
9
Input P=Q P=Q P＞Q P＜Q Output
ALS
Bipolar
No. of
Bit
×
○
○/-
○
×
○/○
○
×A
-/○
×
Explanatory notes [Input] S：Standard 20：20-kW Pullup Resistors LP：P-Port Latch LPQ：L,P-port Latch
Explanatory notes [P=Q, P=Q, P＞Q, P＜Q] Y：Yes N：No
Explanatory notes [Output] 2S：Totem Pole Output、OC：Open-Collector Output
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
65
ADRESS COMPARATOR 、FUSE-PROGRAMMABLE IDENTITY COMPARATOR
AVC
ALVC
LV
LVC
×/-/×/-/-
AHC
×/-/×/-/-
AHCT
LVT
ALVT
ABT
BCT
HCT
×
×
×
×
ACT
×A
×
○
×
×
×
×
Advanced CMOS
AC
677
678
679
680
526
528
527
F
OE
L
OE
L
HC
16-4
16-4
12-4
12-4
16
12
8
Technology
BiCMOS
CMOS
AS
A
A
A
A
F
F
F
Device
S
ETC
ALS
No. of Bit
LS
Descriotion
TTL
Bipolar
Explanatory notes [Function] A：Adress Comparator F：Fuse-Programmable Identity Comparators
Explanatory notes [ETC] OE：Output-With Enable L：Output-With Latch
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
PARITY GENERATOR／CHECKER
ALVC
AVC
ALVC
AVC
LV
LVC
×/-/○
○/-/-
LVC
AHC
×/ー/○
×/-/-
AHCT
ACT
-/○
Advanced CMOS
AC
ALVT
×
○ ○B ×/○
○ ×
LVT
○
ABT
AS
○
BCT
ALS
○
HC
S
180 ×
280
286
F
LS
8
9
9
Technology
BiCMOS
CMOS
TTL
Device
HCT
Bipolar
No. of Bit
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
VOLTAGE CONTROLLED OSCILLATOR(VCO)
2
20
20
20
20
60
24
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
624
628
7046
○
○
Y
×
○
×
×
Y
627
629
625
626
124
4046
○
-/○
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
66
LV
AHC
AHCT
ACT
Advanced CMOS
AC
ALVT
LVT
-/○
ABT
-/○
BCT
F
AS
HCT
Y
Y
Technology
BiCMOS
CMOS
HC
Y
Y
ALS
20
20
24
S
1
COMP'L ENABLE RANGE Rext PLL
Device
Z OUT
INPUT
LS
Fmax
(MHz)
TTL
Bipolar
Curcuit
ACCUMULATORS, ARITHMETIC LOGIC UNIT(ALU), LOOK-AHEAD CARRY GENERATOR
ALVC
AVC
ALVC
AVC
ALVC
AVC
LV
LVC
AHCT
ACT
AHC
AC
LVT
ALVT
BCT
ABT
HCT
F
HC
AS
S
ALS
LS
Advanced CMOS
LVC
281
681
181 ×
381
881
382
264
182 ×
282
882
385
Technology
BiCMOS
CMOS
LVC
4BIT PARALLEL BINARY ACCUMULATORS
4BIT PARALLEL BINARY ACCUMULATORS
4BIT ALU/FUNCTION GENERATORS
4BIT ALU/FUNCTION GENERATORS
4BIT ALU/FUNCTION GENERATORS
4BIT ALU WITH RIPPLE CARRY
LOOK AHEAD CARRY GENERATORS
LOOK AHEAD CARRY GENERATORS
LOOK AHEAD CARRY GENERATORS
LOOK AHEAD CARRY GENERATORS
QUAD SERIAL ADDER/SUBTRACTOR
Device
TTL
Bipolar
Descriotion
×
×
○
×
×
×
○A
×/-/-
×/-/-
×/-/-
×/-/-
×/-/-
×/-/-
×
×A
×
×
×
×
×
×A
○
×
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
ADDER
-/-/○
LV
-/-/○
AHCT
ACT
AHC
LVT
ALVT
ABT
BCT
-/○
Advanced CMOS
AC
○ -/○
HCT
HC
○
F
×
○
×
Technology
BiCMOS
CMOS
AS
×
×
ALS
S
83
283
183
80
82
LS
4BIT BINARY FULL ADDER
4BIT BINARY FULL ADDER
DUAL CARRY SAVE FULL ADDER
GATED FULL ADDER
2BIT BINARY FULL ADDER
Device
TTL
Bipolar
Descriotion
×
×
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
MULTIPLIER
LV
AHCT
ACT
AHC
Advanced CMOS
AC
LVT
ALVT
ABT
BCT
HCT
HC
F
×
Technology
BiCMOS
CMOS
AS
261
284 ×
285 ×
384
ALS
LS
PARALLEL BINARY MULTIPLIERS
PARALLEL BINARY MULTIPLIERS
PARALLEL BINARY MULTIPLIERS
COMPLEMENT MULTIPLIERS
TTL
2-4
4-4
4-4
2'S
Device
S
Bipolar
Descriotion
×
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
67
MEMORY
ALVC
AVC
ALVC
AVC
ALVC
AVC
LV
LVC
AHCT
ACT
AHC
AC
LVT
ALVT
BCT
ABT
HCT
F
HC
AS
S
ALS
LS
Advanced CMOS
LVC
600
601
603
608
612
613
610
611
412
2414
Technology
BiCMOS
CMOS
LVC
MEMORY REFRESH CONTROLLERS
MEMORY REFRESH CONTROLLERS
MEMORY REFRESH CONTROLLERS
MEMORY CYCLE CONTROLLER
MEMMORY MAPPERS
MEMMORY MAPPERS
MEMMORY MAPPERS WITH LATCH
MEMMORY MAPPERS WITH LATCH
MULTI-MODE LATCH
3-8 MEMORY DECIDER
Device
TTL
Bipolar
Descriotion
×
×
×
×
×
×
×
×
×
○/-
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
CLOCK GENERATOR CIRCUIT
LV
AHCT
ACT
AHC
Advanced CMOS
AC
LVT
ALVT
-/○
ABT
HCT
-/○
BCT
HC
F
×
×
○
Technology
BiCMOS
CMOS
AS
LS
265 ×
120 ×
320
321
297
ALS
TTL
QUAD COMPLEMENTARY-OUTPUT LOGIC
DUAL PULSE SYNCHRONIZERS/DRIVERS
CRYSTAL-CONTOROLLED OSCILLATORS
CRYSTAL-CONTOROLLED OSCILLATORS
DIGITAL PHASE-LOCK LOOP
Device
S
Bipolar
Descriotion
-/-/○
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
SWITCH , SHIFTER , ERROR DETECTION CORRECTION CIRCUIT , HARD DISK DRIVER
16BIT PARALLEL ERROR DETECTION CORRECTION
CIRCUIT
32BIT PARALLEL ERROR DETECTION CORRECTION
CIRCUIT
HARD DISK DRIVER
4016
4066
4316
350
636
637
616
617
630
631
632
633
634
635
1250
×
×
×
×
×
×
×
Status ○：Product available in technology indicated *：New product planned in technology indicated
Status ×：Discontinued ■：Not recommended for new designs
Status HC：SN74HCxx / CD74HCxx
Status HCT：SN74HCxx / CD74HCTxx
Status BCT：SN74BCTxx / SN64BCTxx
Status AC：74AC11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACxx / CD74ACxx
Status ACT：74ACT11xxx (Product available in reduced-noise advanced CMOS：11000 Series) / SN74ACTxx / CD74ACTxx
68
LV
AHCT
ACT
○A
×
×
×
×
×
×
AHC
Advanced CMOS
AC
LVT
ALVT
-/○
-/○
ABT
-/○
○/○
-/○
BCT
F
AS
ALS
S
LS
×
HCT
ANALOG SWITCHES WITH LEVEL TRANSLATION
4BIT SHIFTERS
8BIT PARALLEL ERROR DETECTION CORRECTION
CIRCUIT
Technology
BiCMOS
CMOS
HC
QUAD BILATERAL SWITCHES
Device
TTL
Bipolar
Descriotion
PIN ASSIGNMENTS
Pin Assignments
00
04
QUADRUPLE 2-INPUT
POSITIVE-NAND GATES
HEX INVERTERS
positive logic:
Y=A
positive logic:
Y=A•B
VCC
4B
4A
4Y
3B
3A
3Y
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
1A
1Y
2A
2Y
3A
3Y
GND
See page 139
See page 143
01
U04
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
WITH OPEN-COLLECTOR OUTPUTS
HEX INVERTERS
positive logic:
Y=A
positive logic:
Y=A•B
VCC
4Y
4B
4A
3Y
3B
3A
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1Y
1A
1B
2Y
2A
2B
GND
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
See page 140
See page 144
02
05
QUADRUPLE 2-INPUT
POSITIVE-NOR GATES
HEX INVERTERS
WITH OPEN-COLLECTOR OUTPUTS
positive logic:
Y=A+B
positive logic:
Y=A
VCC
4Y
4B
4A
3Y
3B
3A
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1Y
1A
1B
2Y
2A
2B
GND
1A
1Y
2A
2Y
3A
3Y
GND
See page 141
See page 144
03
06
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
WITH OPEN-COLLECTOR OUTPUTS
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
positive logic:
Y=A•B
See page 142
positive logic:
Y=A
VCC
4B
4A
4Y
3B
3A
3Y
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
1A
1Y
2A
2Y
3A
3Y
GND
See page 145
71
Pin Assignments
07
11
HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR
HIGH-VOLTAGE OUTPUTS
TRIPLE 3-INPUT
POSITIVE-AND GATES
positive logic:
Y=A
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
See page 145
See page 149
08
14
QUADRUPLE 2-INPUT POSITIVE-AND GATES
HEX SCHMITT-TRIGGER
INVERTERS
positive logic:
Y=A•B
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
VCC
1C
1Y
3C
3B
3A
3Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
2A
2B
2C
2Y
GND
positive logic:
Y=A
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
See page 146
See page 150
09
16
QUADRUPLE 2-INPUT POSITIVE-AND GATES
WITH OPEN-COLLECTOR OUTPUTS
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
positive logic:
Y=A•B
positive logic:
Y=A
VCC
4B
4A
4Y
3B
3A
3Y
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
See page 147
See page 151
10
17
TRIPLE 3-INPUT
POSITIVE-NAND GATES
HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR
HIGH-VOLTAGE OUTPUTS
positive logic:
Y=A•B•C
See page 148
72
positive logic:
Y=A•B•C
positive logic:
Y=A
VCC
1C
1Y
3C
3B
3A
3Y
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1A
1B
2A
2B
2C
2Y
GND
1A
1Y
2A
2Y
3A
3Y
GND
See page 151
Pin Assignments
19
26
HEX SCHMITT-TRIGGER INVERTERS
QUADRUPLE 2-INPUT HIGH-VOLTAGE
INTERFACE POSITIVE-NAND GATES
positive logic:
Y=A
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
positive logic:
Y = AB
See page 152
See page 155
20
27
DUAL 4-INPUT
POSITIVE-NAND GATES
TRIPLE 3-INPUT
POSITIVE-NOR GATES
positive logic:
Y=A•B•C•D
VCC
2D
2C
NC
2B
2A
2Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
NC
1C
1D
1Y
GND
positive logic:
Y=A+B+C
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
VCC
1C
1Y
3C
3B
3A
3Y
14
13
12
11
10
9
8
NC – No internal connection
1
2
3
4
5
6
7
1A
1B
2A
2B
2C
2Y
GND
See page 153
See page 155
21
30
DUAL 4-INPUT
POSITIVE-AND GATES
8-INPUT POSITIVE-NAND GATES
positive logic:
Y=A•B•C•D
positive logic:
Y=A•B•C•D•E•F•G•H
VCC
2D
2C
NC
2B
2A
2Y
VCC
NC
H
G
NC
NC
Y
14
13
12
11
10
9
8
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1A
1B
NC
1C
1D
1Y
GND
A
B
C
D
E
F
GND
NC – No internal connection
NC – No internal connection
See page 154
See page 156
25
31
DUAL 4-INPUT POSITIVE-NOR GATES
WITH STROBE
DELAY ELEMENTS
positive logic:
Y = G (A + B + C + D)
See page 154
VCC
2D
2C
STROBE
2G
2B
2A
2Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
STROBE
1G
1C
1D
1Y
GND
VCC
NC
H
G
NC
NC
Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
A
B
C
D
E
F
GND
NC – No internal connection
See page 156
73
Pin Assignments
32
38
QUADRUPLE 2-INPUT
POSITIVE OR GATES
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
positive logic:
Y=A+B
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
positive logic:
Y=A•B
See page 157
33
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
positive logic:
Y=A+B
See page 159
VCC
4Y
4B
4A
3Y
3B
3A
14
13
12
11
10
9
8
42
4-LINE-TO-10-LINE DECODERS
OUTPUTS
INPUTS
1
2
3
4
5
6
7
VCC
A
B
C
D
9
8
7
1Y
1A
1B
2Y
2A
2B
GND
16
15
14
13
12
11
10
9
B
C
3 4
5
See page 158
35
A
HEX NONINVERTERS
WITH OPEN-COLLECTOR OUTPUTS
positive logic:
Y=A
0
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
1
2
D
6
7
8
9
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
GND
OUTPUTS
See page 160
45
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
BCD-TO-DECIMAL DECODER/DRIVER
See page 158
37
positive logic:
Y=A•B
OUTPUTS
INPUTS
QUADRUPLE 2-INPUT
POSITIVE-NAND BUFFERS
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
VCC
A
B
C
D
9
8
7
16
15
14
13
12
11
10
9
B
C
A
D
BCD-TO-DECIMAL
0
1
2
3 4
See page 159
74
2
3
4
5
6
7
1B
1Y
2A
2B
2Y
GND
See page 162
6
7
8
9
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
GND
OUTPUTS
1
1A
5
Pin Assignments
47
64
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
4-2-3-2 INPUT AND-OR INVERT GATE
positive logic:
Y = ABCD + EF + GHI + JK
OUTPUTS
VCC
f
g
a
b
c
d
e
16
15
14
13
12
11
10
9
f
g
B
BI/
C LT RBO RBI D A
a
b
c
d
D
C
B
K
J
Y
13
12
11
10
9
8
1
2
3
4
5
6
7
A
E
F
G
H
I
GND
e
1
2
3
4
5
6
7
8
B
C
LAMP
TEST
RB
OUTPUT
RB
INPUT
D
A
GND
INPUTS
VCC
14
See page 167
73
DUAL J-K FLIP-FLOPS WITH CLEAR
INPUTS
See page 164
51
1J
1Q
1Q
GND
2K
2Q
2Q
14
13
12
11
10
9
8
AND-OR-INVERT GATES
’51, ’S51 DUAL 2-WIDE 2-INPUT
positive logic:
Y = AB + CD
Q
CK
J
MAKE NO EXTERNAL CONNECTION
VCC
1B
14
13
12
11
1D
1C
1Y
10
9
8
Q
Q
CLR
CLR
K
K
Q
CK
J
1
2
3
4
5
6
7
1CK
1CLR
1K
VCC
2CK
2CLR
2J
See page 168
74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET AND CLEAR
1
2
3
4
5
6
7
VCC
2CLR
2D
2CK
2PR
2Q
1A
2A
2B
2C
2D
2Y
GND
14
13
12
11
10
9
D
CK
CLR
PR
8
Q
CLR
Q
2Q
Q
CK
AND-OR-INVERT GATES
D
‘LS51 2-WIDE 3-INPUT, 2-WIDE 2-INPUT
positive logic:
1Y = (1A • 1B • 1C) + (1D • 1E • 1F)
2Y = (2A • 2B) + (2C • 2D)
Q
PR
1
2
3
4
5
6
7
1CLR
1D
1CK
1PR
1Q
1Q
GND
See page 170
75
VCC
1C
1B
1F
1E
1D
1Y
14
13
12
11
10
9
8
4-BIT BISTABLE LATCHES
1Q
2Q
2Q
16
15
14
Q
1
1Y
See page 166
2
2A
3
2B
4
2C
5
2D
6
2Y
7
See page 172
13
D
D
G
G
Q
GND
ENABLE
1–2
GND
1
2
3
1Q
1D
2D
12
Q
Q
Q
Q
4
5
ENABLE VCC
3–4
3Q
3Q
4Q
11
10
9
D
D
G
G
Q
Q
6
7
8
3D
4D
4Q
75
Pin Assignments
93
85
4-BIT MAGNITUDE COMPARATORS
4-BIT BINARY COUNTERS
DATA INPUTS
VCC
A3
B2
A2
A1
B1
A0
B0
INPUT
A
NC
QA
QD
GND
QB
QC
16
15
14
13
12
11
10
9
14
13
12
11
10
9
8
QA
QD
A3
B2
A2
A1
B1
A0
B3
AB
IN
A>B
OUT
A=B
OUT
B0
AB
A>B
A=B
A<B
GND
CASCADE INPUTS
1
2
3
INPUT R0 (1) R0 (2)
B
OUTPUTS
4
5
6
7
NC
VCC
NC
NC
NC – No internal connection
See page 173
See page 177
86
97
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIER
positive logic:
Y = A ⊕ B or Y = AB + AB
RATE INPUT
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
ENAUNITY/
BLE
CLEAR CASCADE INPUT
VCC
D
C
STROBE
CLOCK
16
15
14
13
12
11
10
9
D
C
CLEAR
UNITY/
CASCADE
ENABLE
INPUT
STROBE
E
F
A
Z
Y
1
2
3
4
5
6
B
E
F
A
Z
Y
B
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
CK
RATE INPUTS
See page 174
See page 178
90
107
DECADE COUNTER
ENABLE
OUTPUT
7
ENABLE
OUTPUT
8
GND
OUTPUTS
DUAL J-K FLIP-FLOPS WITH CLEAR
INPUT
A
NC
QA
QD
GND
QB
QC
14
13
12
11
10
9
8
QA
QD
VCC
1CLR
1CK
2K
2CLR
2CK
2J
14
13
12
11
10
9
8
QB
QC
A
J
Q9 (2)
Q9 (1)
BD
R0 (1) R0 (2)
CK
1
2
3
BD R0 (1) R0 (2)
INPUT
4
5
NC
VCC
6
K
K
CLR
CK
J
CLR
Q
Q
Q
Q
7
Q9 (1) Q9 (2)
1
2
3
4
5
6
7
1J
1Q
1Q
1K
2Q
2Q
GND
NC – No internal connection
See page 175
See page 180
92
109
DIVIDE-BY-TWELVE COUNTERS
DUAL J-K POSITIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH PRESET AND CLEAR
INPUT
A
NC
QA
QB
GND
QC
QD
14
13
12
11
10
9
8
QA
QD
VCC
2CLR
2J
2K
2CK
2PR
2Q
2Q
16
15
14
13
12
11
10
9
J
QC
A
QD
B
R0 (2)
R0 (1)
CK
CLR
K
PR Q
Q
Q
K
CLR
CK
Q
J
PR
1
2
INPUT
B
NC
3
4
5
NC
NC
VCC
6
7
R0 (1) R0 (2)
NC – No internal connection
See page 176
76
See page 182
1
2
3
4
5
6
7
8
1CLR
1J
1K
1CK
1PR
1Q
1Q
GND
Pin Assignments
112
124
DUAL J-K NEGATIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH PRESET AND CLEAR
DUAL VOLTAGE-CONTROLLED OSCILLATORS
WITH ENABLE INPUTS
2Cext
2Y
2G
ENABLE OUTPUT GND
2
VCC ∼ VCC RANGE
VCC
1CLR
2CLR
2CK
2K
2J
2PR
2Q
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
6
7
8
RNG Cext
Y
FREQ
CONT EN
K CLR Q
PR
J
CK
Q
CK
J
Q
FREQ EN
CONT
Q
K
PR
Y
RNG C
ext
CLR
1
2
3
4
5
6
7
8
1CK
1K
1J
1PR
1Q
1Q
2Q
GND
See page 184
See page 189
121
125
MONOSTABLE MULTIVIBRATOR
1
2
3
2
1
1
RANGE
FREQUENCY
CONTROL
4
5
1Y ∼ GND
1G
ENABLE OUTPUT
1Cext
QUADRUPLE BUS BUFFER GATES
WITH THREE-STATE OUTPUTS
VCC
NC
NC
14
13
12
Rext／
Cext
Cext
11
10
Rint
NC
9
8
positive logic:
Y=A
VCC
4C
4A
4Y
3C
3A
3Y
14
13
12
11
10
9
8
Q
Q
1
2
3
4
5
6
7
Q
NC
A1
A2
B
Q
GND
1
2
3
4
5
6
7
1C
1A
1Y
2C
2A
2Y
GND
NC – No internal connection
See page 186
See page 190
122
126
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
WITH CLEAR
QUADRUPLE BUS BUFFER GATES
WITH THREE-STATE OUTPUTS
VCC
Rext／
Cext
NC
Cext
NC
Rint
Q
14
13
12
11
10
9
8
positive logic:
Y=A
VCC
4C
4A
4Y
3C
3A
3Y
14
13
12
11
10
9
8
Q
Q
CLR
1
2
3
4
5
6
7
A1
A2
B1
B2
CLR
Q
GND
1
2
3
4
5
6
7
1C
1A
1Y
2C
2A
2Y
GND
NC – No internal connection
See page 187
See page 191
123
128
DUAL RETRIGGERABLE MONOSTABLE
MULTIVIBARATORS WITH CLEAR
SN54128...75-Ω LINE DRIVER
SN74128...50-Ω LINE DRIVER
VCC
16
positive logic:
Y=A+B
1Rext／ 1
Cext
Cext
15
14
1Q
2Q
2CLR
2B
2A
VCC
4Y
4B
4A
3Y
3B
3A
13
12
11
10
9
14
13
12
11
10
9
8
7
8
CLR
Q
Q
Q
Q
CLR
See page 188
1
2
3
4
5
1A
1B
1CLR
1Q
2Q
6
2 2Rext／ GND
Cext
Cext
1
2
3
4
5
6
7
1Y
1A
1B
2Y
2A
2B
GND
See page 192
77
Pin Assignments
132
138
QUADRUPLE 2-INPUT POSITIVE-NAND
SCHMITT TRIGGERS
3-TO-LINE DECODERS/DEMULTIPLEXRS
DATA OUTPUTS
positive logic:
Y=A•B
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
16
15
14
13
12
11
10
9
Y0
Y1
Y2
Y3
Y4
Y5
B
C
G2A
G2B
G1
Y7
1
2
3
4
5
6
7
8
A
B
C
G2A
G2B
G1
Y7
GND
A
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
Y6
SELECT
OUTPUT
ENABLE
See page 192
See page 196
133
139
13-INPUT POSITIVE-NAND GATES
DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS
positive logic:
Y=A•B•C•D•E•F•G•H•I•J•K•L•M
SELECT
VCC
M
L
K
J
I
H
Y
16
15
14
13
12
11
10
9
DATA OUTPUTS
VCC
ENABLE
2G
2A
2B
2Y0
2Y1
2Y2
2Y3
16
15
14
13
12
11
10
9
G
A
B
Y0
Y1
Y2
Y3
G
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
GND
A
B
Y0
Y1
Y2
1
2
3
4
5
6
7
8
1G
ENABLE
1A
1B
1Y0
1Y1
1Y2
1Y3
GND
SELECT
See page 193
See page 198
136
140
QUAD 2-INPUT EXCLUSIVE-OR GATES
WITH OPEN COLLECTOR OUTPUTS
DUAL 4-INPUT POSITIVE-NAND 50-Ω
LINE DRIVERS
positive logic:
Y = A ⊕ B = AB + AB
positive logic:
Y = ABCD
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
DATA OUTPUTS
VCC
2D
2C
NC
2B
2A
2Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
NC
1C
1D
1Y
GND
NC – No internal connection
See page 193
See page 200
137
145
3-TO 8-LINE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
Y3
BCD-TO-DECIMAL DECODERS/DRIVERS
FOR LAMPS, RELAYS, MOS
DATA OUTPUTS
PARALLEL INPUTS
OUTPUTS
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
VCC
A
B
C
D
9
8
7
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
Y0
Y1
Y2
Y3
Y4
Y5
A
B
C
D
BCD-TO-DECIMAL
A
Y6
78
G2
G1
Y7
C
1
2
3
4
5
6
7
8
1
A
B
C
GL
G2
G1
Y7
GND
0
SELECT
See page 194
GL
B
ENABLE
0
OUTPUT
2 3
4
2
3
4
5
6
7
8
1
2
3
4
5
6
GND
1
5
OUTPUTS
See page 201
6
7
8
9
Pin Assignments
147
151
10-TO-4 LINE PRIORITY ENCODER
8-TO-1 LINE DATA SELECTORS/MULTIPLEXERS
INPUTS
DATA INPUTS
DATA SELECT
VCC
NC
Y3
I3
I2
I1
I9
Y0
VCC
4
5
6
7
A
B
C
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
D4
D
3
2
1
9
6
7
8
C
B
3
4
5
6
7
8
1
I6
I7
I8
Y2
Y1
GND
3
4
A
5
1
2
I4
I5
INPUTS
D5
D6
D7
A
B
D2
D1
D0
Y
W
S
2
3
4
5
6
2
1
0
Y
W
D3
C
DATA INPUTS
OUTPUTS
7
8
STROBE GND
OUTPUTS
NC – No internal connection
See page 202
See page 208
148
153
8-TO-3-LINE OCTAL PRIORITY ENCODERS
DUAL 4-LINE TO 1-LINE DATA
SELECTORS/MULTIPLEXERS
OUTPUTS
INPUTS
VCC
E0
GS
3
2
1
0
OUTPUT
A0
16
15
14
13
12
11
10
9
E0
GS
3
2
1
0
5
6
7
EI
A2
A1
4
DATA INPUTS
STROBE
VCC
2G
16
15
OUTPUT
A
SELECT 2C3
14
2C2
2C1
2C0
13
12
11
10
9
2C3
2G
2C2
2C1
2C0
2Y
B
B A A
B
B A A
2Y
A0
1
2
3
4
5
6
7
8
4
5
6
7
EI
A2
A1
GND
INPUTS
1G
1C3
1C2
1C1
1C0
2
3
4
5
6
STROBE
B
1C3
1C2
1C1
1G
SELECT
1
OUTPUTS
1Y
7
8
1C0 OUTPUT GND
1Y
DATA INPUTS
See page 204
See page 210
150
154
1-OF-16 DATA SELECTOR
4-LINE TO 16-LINE DECODER/DEMULTIPLEXER
DATA INPUTS
DATA SELECT
8
9
10
11
12
13
14
15
A
B
C
VCC
A
B
C
D
G2
G1
15
14
13
12
11
24
23
22
21
20
19
18
17
16
15
14
13
24
23
22
21
20
19
18
17
16
15
14
13
E8
E9
E10
E11
E12
E13
E14
E15
A
B
A
B
C
D
G2
G1
15
14
13
12
1
2
3
4
5
6
7
8
9
10
E6
E5
E4
E3
E2
E1
E0
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
0
DATA INPUTS
S
W
D
9
10
11
11
0
C
E7
See page 206
OUTPUTS
INPUTS
VCC
12
1
2
3
4
5
6
7
8
9
10
11
12
STROBE W
D
GND
OUT- DATA
PUT SELECT
0
1
2
3
4
5
6
7
8
9
10
GND
OUTPUTS
See page 212
79
Pin Assignments
155
156
161
163
DECODERS/DEMULTIPLEXERS
SYNCHRONOUS 4-BIT BINARY COUNTERS
OUTPUTS
OUTPUTS
VCC
DATA
2C
SELECT
STRB INPUT
2G
2Y3
A
2Y2
2Y1
2Y0
16
15
14
11
10
9
2Y1
2Y0
13
12
2Y3
2G 2C
2Y2
B
B
A
RIPPLE
CARRY
VCC OUTPUT QA
QB
QC
QD
16
14
13
12
11
10
RIPPLE QA
CARRY
OUTPUT
CLEAR
QB
QC
QD
ENABLE
T
A
B
C
D
ENABLE
P
3
4
5
6
A
B
C
D
A
15
CK
B
1G 1C
1Y3
1Y2
B
A
1Y1
2
3
4
STRB SELECT 1Y3
1G INPUT
9
LOAD
A
1Y0
1
1
DATA
1C
ENABLE
LOAD
T
5
6
7
8
1Y2
1Y1
1Y0
GND
2
CLEAR CLOCK
7
8
ENABLE GND
P
DATA INPUTS
OUTPUTS
See page 214, 216
See page 224, 226
157
158
164
8-BIT PARALLEL OUTPUT SERIAL SHIFT REGISTERS
QUAD 2-TO 1-LINE DATA SELECTORS/MULTIPLEXERS
INPUTS
16
OUTPUTS
INPUTS
OUTPUTS
OUTPUTS
4A
4B
4Y
3A
3B
3Y
VCC
QH
QG
QF
QE
15
14
13
12
11
10
9
14
13
12
11
10
9
G
4A
4B
4Y
3A
3B
QH
QG
QF
QE
CLEAR
QA
QB
QC
QD
VCC STROBE
S
A
3Y
1A
1B
1Y
2A
2B
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
A
B
QA
QB
QC
QD
GND
OUTPUTS
INPUTS
OUTPUTS
SERIAL INPUTS
See page 218, 220
See page 228
159
165
4-TO-16 LINE DECODER/DEMULTIPLEXER
8-BIT SHFT REGISTERS
INPUTS
OUTPUTS
PARALLEL INPUTS
OUTPUTS
VCC
A
B
C
D
G2
G1
15
14
13
12
11
24
23
22
21
20
19
18
17
16
15
14
13
A
B
C
D
G2
G1
15
14
13
12
CLOCK
VCC INHIBIT
16
15
CLOCK
INHIBIT
SERIAL OUTPUT
INPUT QH
D
C
B
A
14
13
12
11
10
D
C
B
A
SERIAL
IN
E
F
G
H
QH
3
4
5
6
E
F
G
H
SHIFT/
LOAD
11
0
CK
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
11
12
0
1
2
3
4
5
6
7
8
9
10
GND
1
2
SHIFT/ CLOCK
LOAD
OUTPUTS
80
CK
B
2Y
8
SELECT
INPUTS
See page 222
CLEAR CLOCK
QH
PARALLEL INPUTS
See page 230
9
7
8
OUTPUT GND
QH
Pin Assignments
166
173
8-BIT SHIFT REGISTERS
4-BIT D-TYPE REGISTERS
DATA ENABLE
INPUTS
DATA INPUTS
VCC
CLEAR
1D
2D
3D
4D
G2
G1
16
15
14
13
12
11
10
9
DATA
ENABLE
PARALLEL INPUTS
PARALLEL
SHIFT/ INPUT OUTPUT
LOAD
H
QH
VCC
16
15
14
SHIFT/
LOAD
13
G
F
E
CLEAR
12
11
10
9
H
QH
G
F
B
C
D
CLOCK
INHIBIT
SERIAL
INPUT
A
CLEAR
1D
2D
3D
4D
OUTPUT
CONTROL
1Q
2Q
3Q
4Q
CLEAR
CK
1
2
3
4
5
6
M
N
1Q
2Q
3Q
4Q
OUTPUT CONTROL
1
2
3
4
5
SERIAL
INPUT
A
B
C
D
6
7
8
CLOCK CLOCK GND
INHIBIT
174
VCC
6Q
6D
5D
5Q
4D
4Q
CLOCK
16
15
14
13
12
11
10
9
169
4-BIT UP/DOWN SYNCHRONOUS BINARY COUNTERS
Q
D
CK
CLEAR
D
Q
CK
CLEAR
D
Q
CK
CLEAR
CLEAR
CK
D
CLEAR
CK
D
Q
CLEAR
CK
D
Q
Q
OUTPUTS
ENABLE
T
LOAD
QA
QB
QC
QD
14
13
12
11
10
RIPPLE QA
CARRY
OUTPUT
UP/DOWN
QB
QC
QD
ENABLE
T
15
8
See page 238
See page 232
16
7
CLOCK GND
OUTPUTS
HEX D-TYPE FLIP-FLOPS
PARALLEL INPUTS
RIPPLE
CARRY
VCC OUTPUT
CK
E
1
2
3
4
5
6
7
8
CLEAR
1Q
1D
2D
2Q
3D
3Q
GND
9
See page 240
175
LOAD
CK
A
B
C
D
ENABLE
P
1
2
3
4
5
6
7
U/D
CK
A
B
C
D
QUAD D-TYPE FLIP-FLOPS
8
VCC
4Q
4Q
4D
3D
3Q
3Q
CLOCK
16
15
14
13
12
11
10
9
Q
CLR
Q
Q
Q
CLR
ENABLE GND
P
DATA INPUTS
See page 234
CLR
Q
170
4-BY-4-REGISTER FILES
CK D
D CK
CK D
D CK
Q
Q
CLR
Q
1
2
3
4
5
6
7
8
CLEAR
1Q
1Q
1D
2D
2Q
2Q
GND
See page 241
WRITE SELECT
ENABLE
OUTPUTS
181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
VCC
DATA
D1
WA
WB
Q1
Q2
16
15
14
13
12
11
10
9
D1
WA
WB
GW
GR
Q1
WRITE READ
INPUTS
OUTPUTS
VCC
A1
B1
A2
B2
A3
B3
G
Cn+4
P
A=B
F3
24
23
22
21
20
19
18
17
16
15
14
13
A1
B1
A2
B2
A3
B3
G
Cn+4
P
A=B
S3
S2
S1
S0
Cn
M
F0
F1
F2
Q2
D2
D3
D4
RB
RA
Q4
Q3
B0
1
2
3
4
5
6
7
8
D2
D3
D4
RB
RA
Q4
Q3
GND
DATA
READ SELECT
OUTPUTS
A0
F3
1
2
3
4
5
6
7
8
9
10
11
12
B0
A0
S3
S2
S1
S0
Cn
M
F0
F1
F2
GND
INPUTS
See page 236
OUTPUTS
See page 242
81
Pin Assignments
182
193
LOOK-AHEAD CARRY GENERATORS
SYNCHRONOUS UP/DOWN DUAL CLOCK COUNTERS
INPUTS
INPUTS
OUTPUTS
OUTPUTS
INPUTS
VCC
P2
G2
Cn
Cn+x
Cn+y
G
Cn+z
VCC
BODATA
DATA
CLEAR RROW CARRY LOAD
C
A
16
15
14
13
12
11
10
9
16
15
14
P2
G2
Cn
Cn+x
Cn+y
A
CLEAR
QB
QA
G
Cn+z
G1
P1
G0
P0
G3
P3
1
2
3
4
5
6
G1
P1
G0
P0
G3
P3
8
P
GND
OUTPUT
See page 244
See page 252
190
191
194
OUTPUTS
16
15
14
12
RIPPLE MAX/
CLOCK MIN
A
QB
13
QA
1
2
3
DATA
B
INPUT
QB
QA
OUTPUTS
CTEN DN/UP
4
5
ENA- DOWN/
BLE
UP
INPUTS
10
DATA
D
9
C
1
2
3
QB
QA
4
QC
5
COUNT COUNT
DOWN UP
INPUTS
QD
6
7
8
QC
QD
GND
OUTPUTS
4-BIT BIDIRECTIONAL UNIVERSAL
SHIFT REGISTERS
SYNCHRONOUS UP/DOWN DUAL CLOCK COUNTERS
INPUTS
BO- CARRY LOAD
RROW
COUNT COUNT
DOWN UP
OUTPUTS
RIPPLE MAX/
DATA
CLOCK CLOCK MIN
A
11
D
DATA
B
INPUT
INPUTS
VCC
12
B
P
7
13
INPUTS
LOAD
DATA
C
DATA
D
11
10
9
LOAD
C
VCC
QA
QB
QC
QD
CLOCK
S1
S0
16
15
14
13
12
11
10
9
QA
QB
QC
QD
CLOCK
S1
R
A
B
C
D
L
2
3
4
5
6
A
B
C
D
S0
CLEAR
QC
QD
6
7
8
QC
QD
GND
1
CLEAR SHIFT
RIGHT
SERIAL
INPUT
PARALLEL INPUTS
7
8
SHIFT GND
LEFT
SERIAL
INPUT
OUTPUTS
See page 246, 248
See page 254
192
195
PRESETTABLE SYNCHRONOUS
4-BIT UP/DOWN COUNTERS
4-BIT PARALLEL-ACCESS SHIFT REGISTERS
OUTPUTS
VCC
P0
MR
TCD
TCU
PL
P2
P3
VCC
QA
QB
QC
QD
QD
16
15
14
13
12
11
10
9
16
15
14
13
12
11
QA
QB
QC
QD
QD
1
2
3
4
5
6
7
8
1
Q1
Q0
CPD
CPU
Q2
Q3
GND
CLEAR
J
K
A
2
3
4
J
K
A
SERIAL INPUTS
See page 250
82
See page 256
10
9
CK
SHIFT/
LOAD
CLEAR
P1
SHIFT/
CLOCK LOAD
B
C
D
5
6
7
8
B
C
D
GND
PARALLEL INPUTS
Pin Assignments
221
241
DUAL MONOSTABLE MULTIVIBRATORS
OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
VCC
16
1
1 Rext/
Cext
Cext
15
14
1Q
2Q
2CLR
2B
2A
VCC
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
13
12
11
10
9
20
19
18
17
16
15
14
13
12
11
7
8
Q
CLR
Q
Q
CLR
Q
1
2
3
4
5
1A
1B
1CLR
1Q
2Q
6
2
2 Rext/ GND
Cext
Cext
1
2
3
4
5
6
7
8
9
10
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
See page 258
See page 266
237
243
3-TO-8 LINE DECODER DEMULTIPLEXER
WITH ADDRESS LATCHES
QUADRUPLE BUS TRANSCEIVERS
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
VCC
GBA
NC
1B
2B
3B
4B
16
15
14
13
12
11
10
9
14
13
12
11
10
9
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
A0
A1
A3
LE
OE1
OE0
Y7
GND
GAB
NC
1A
2A
3A
4A
GND
NC – No internal connection
See page 260
See page 268
238
244
3-TO-8-LINE DECODERS/DEMULTIPLEXERS
OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
VCC
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
16
15
14
13
12
11
10
9
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10
A0
A1
A2
E1
E2
E3
Y7
GND
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
See page 262
See page 270
240
245
OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
OCTAL BUS TRANSCEIVERS
See page 264
VCC
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
VCC
ENABLE
G
B1
B2
B3
B4
B5
B6
B7
B8
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
See page 272
83
Pin Assignments
247
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
WITH RIPPLE BLANKING
257
QUAD DATA SELECTORS/MULTIPLEXERS
OUTPUTS
VCC
f
g
a
b
c
d
e
VCC
16
15
14
13
12
11
10
9
16
f
g
a
B
BI/
C LT RBO RBI D
b
c
d
INPUTS
OUTPUT
CONTROL
OUTPUT
G
4A
AB
4Y
INPUTS
3B
OUTPUT
3Y
15
14
13
12
11
10
9
G
4A
AB
4Y
3A
3B
1A
1B
1Y
2A
2B
2Y
e
3A
S
A
3Y
1
2
3
4
5
6
7
8
1
2
3
4
5
6
B
C
LAMP
TEST
RB
OUTPUT
RB
INPUT
D
A
GND
SELECT
1A
1B
1Y
OUTPUT
2A
2B
INPUTS
INPUTS
INPUTS
See page 274
See page 282
250
258
1-OF-16 DATA GENERATOR/MULTIPLEXER
7
8
2Y
GND
OUTPUT
INPUTS
QUAD DATA SELECTORS/MULTIPLEXERS
DATA INPUTS
VCC
8
9
10
11
12
13
14
15
A
B
C
VCC
24
23
22
21
20
19
18
17
16
15
14
13
16
E8
E9
E10
E11
E12
E13
E14
E15
A
B
E7
INPUTS
OUTPUT
CONTROL
OUTPUT
G
4A
AB
4Y
C
E6
E5
E4
E3
E2
E1
E0
G
1
2
3
4
5
6
7
8
9
7
6
5
4
3
2
1
0
STROBE
W
D
10
11
INPUTS
3B
OUTPUT
3Y
15
14
13
12
11
10
9
G
4A
AB
4Y
3A
3B
1A
1B
1Y
2A
2B
2Y
3A
3Y
S
12
W
D
GND
OUT- DATA
PUT SELECT
1
2
3
4
5
6
SELECT
1A
1B
1Y
OUTPUT
2A
2B
DATA INPUTS
INPUTS
See page 276
7
8
2Y
GND
OUTPUT
INPUTS
See page 284
259
251
DATA SELECTORS/MULTIPLEXERS
8-BIT ADDRESSABLE LATCHES
OUTPUTS
DATA INPUTS
DATA SELECT
VCC
4
5
6
7
A
B
C
16
15
14
13
12
11
10
9
D4
D5
D6
D7
A
VCC
16
15
A
B
C
B
D3
ENCLEAR ABLE
CLEAR G
C
D2
D1
D0
Y
W
1
2
3
4
5
6
3
2
1
0
Y
W
14
DATA
IN
Q7
Q6
Q5
Q4
13
12
11
10
9
D
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
S
7
8
1
2
3
4
5
6
7
8
A
B
C
Q0
Q1
Q2
Q3
GND
STROBE GND
LATCH SEL
DATA INPUTS
See page 286
253
260
DUAL DATA SELECTORS/MULTIPLEXERS
DUAL 5-INPUT POSITIVE-NOR GATES
DATA INPUTS
OUTPUT
CONTROL A
VCC
2G SELECT 2C3
2C2
2C1
2CO
OUTPUT
2Y
16
13
12
11
10
9
2C3
2G
2C2
2CO
2Y
1C2
1C1
15
14
1G
1C3
1
2
3
OUTPUT
B
1C3
CONTROL SELECT
1G
2C1
B
B
4
5
1C2
1C1
B
A
B
A
positive logic:
Y=A+B+C+D+E
84
VCC
1E
1D
2E
2D
2C
2B
14
13
12
11
10
9
8
A
A
1C0
1Y
6
7
8
1C0 OUTPUT GND
1Y
DATA INPUTS
See page 280
OUTPUTS
OUTPUTS
See page 278
See page 288
1
2
3
4
5
6
7
1A
1B
1C
2A
1Y
2Y
GND
Pin Assignments
265
279
QUAD COMPLEMENTARY-OUTPUT ELEMENTS
QUAD S-R LATCHES
positive logic:
Y = A, W = A
Y = AB, W = AB
VCC
4A
4W
4Y
3B
3A
3W
3Y
VCC
4S
4R
4Q
3S1
3S1
3R
3Q
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1A
1W
1Y
2A
2B
2W
2Y
GND
1R
1S1
1S2
1Q
2R
2S
2Q
GND
VCC
F
E
D
C
B
A
14
13
12
11
10
9
8
F
E
D
C
B
I
Σ
EVEN
Σ
ODD
4
5
6
See page 289
See page 293
266
280
QUAD 2-INPUT EXCLUSIVE-NOR GATES
WITH OPEN-COLLECTOR OUTPUTS
9-BIT ODD/EVEN PARITY
GENERATORS/CHECKERS
positive logic:
Y=A⊕B
VCC
4B
4A
4Y
3Y
3B
3A
14
13
12
11
10
9
8
INPUTS
G
A
H
1
2
3
4
5
6
7
1A
1B
1Y
2Y
2A
2B
GND
1
2
3
G
H
NC
7
I
Σ EVEN Σ ODD GND
INPUT
INPUTS
OUTPUTS
NC – No internal connection
See page 290
See page 294
273
283
OCTAL D-TYPE FLIP-FLOPS
4-BIT BINARY FULL ADDERS
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLOCK
VCC
B3
A3
Σ3
A4
B4
Σ4
C4
20
19
18
17
16
15
14
13
12
11
16
15
14
13
12
11
10
9
Q
D
D
Q
Q
D
D
Q
B3
A3
Σ3
A4
B4
Σ4
A2
Σ1
A1
B1
C0
CK
CK
CK
CLEAR
CLEAR
CLEAR
CLEAR
CLEAR
CLEAR
CK
CLEAR
Σ2
CK
Q
D
CK
D
Q
Q
C4
CLEAR
CK
D
B2
CK
D
Q
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
CLEAR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
Σ2
B2
A2
Σ1
A1
B1
C0
GND
See page 291
See page 296
276
286
QUAD J-K FLIP-FLORS
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
WITH BUS DRIVER PARITY I/O PORT
INPUTS
VCC
4J
4CK
4K
4Q
3Q
3K
3CK
3J
PRESET
VCC
F
E
D
C
B
A
20
19
18
17
16
15
14
13
12
11
14
13
12
11
10
9
8
J
PR
Q
CK
K
CLR
K
CLR
CK
J
PR
Q
F
E
D
C
B
H
XMIT
I
G
Q
PR
J
CK
CLR
K
CLR
K
CK
Q
PR
J
A
1
2
3
4
5
6
7
8
9
10
1
2
3
CLEAR
1J
1CK
1K
1Q
2Q
2K
2CK
2J
GND
G
H
XMIT
INPUTS
See page 292
See page 298
4
PARITY PARITY
ERROR I/O
5
6
7
I
PARITY PARITY GND
INPUT ERROR I/O
OUTPUTS
85
Pin Assignments
292
298
PROGRAMMABLE FREQUENCY
DIVIDER/DIGITAL TIMER
QUAD 2-INPUT MULTIPLEXERS WITH STORAGE
OUTPUTS
DATA
WORD INPUT
CLOCK SELECT C1
VCC
C
D
TP3
NC
CLEAR
A
NC
VCC
QA
QB
QC
QD
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
QA
QB
QC
QD
CK
WS
A1
B1
C2
D2
D1
C
D
TP3
CLR
A
B
C1
B2
E
TP1
CLK1
CLK2
TP2
Q
9
A2
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
B
E
TP1
CLK1
CLK2
TP2
QOUT
GND
B2
A2
A1
B1
C2
D2
D1
GND
NC – No internal connection
See page 300
DATA INPUTS
See page 308
293
299
4-BIT BINARY COUNTERS
OUTPUTS
VCC
14
RO(2) RO(1)
13
12
RO(2) RO(1)
INPUT INPUT
B
A
11
10
B
A
QC
QB
QA
QD
9
8
8-BIT BIDIRECTIONAL UNIVERSAL
SHIFT/STORAGE REGISTERS
VCC
S1
SHIFT
LEFT
SL
QH´
H/QH
F/QF
D/QD
B/QB CLOCK
20
19
18
17
16
15
14
13
12
S1
SL
QH´
H/QH
F/QF
D/QD
B/QB
CK
G/QG
E/QE
C/QC
A/QA
QA´
CLEAR
QA
QD
S0
1
2
3
4
5
6
7
NC
NC
QC
QB
NC
GND
1
2
3
4
5
6
7
8
S0
G1
G2
G/QG
E/QE
C/QC
A/QA
QA´
OUTPUTS
NC – No internal connection
See page 302
11
SR
G
NC
SHIFT
RIGHT
SR
9
10
CLEAR GND
OUTPUT
CONTROLS
See page 310
294
321
PROGRAMMABLE FREQUENCY
DIVIDER/DIGITAL TIMER
CRYSTAL-CONTROLLED OSCILLATOR
VCC
C
D
NC
NC
CLEAR
NC
NC
VCC
XTAL
2
XTAL
1
F/2
F
VCC´
F´
F´
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
C
D
CLR
A
XTAL
2
XTAL
1
F/2
F
FFQ
FFD
F´
TANK1
B
A
TP
CLK1
CLK2
Q
F´
TANK2
F/4
F
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
B
A
TP
CLK1
CLK2
NC
QOUT
GND
TANK
1
TANK
2
GND
1
FFQ
FFD
F/4
F
GND
2
NC – No internal connection
See page 304
See page 312
297
323
DIGITAL PHASE-LOCKED-LOOP FILTERS
8-BIT BIDIRECTIONAL SHIFT/STORAGE REGISTERS
VCC
C
D
φ A2
ECPD EXOR
OUT
OUT
φB
φ A1
16
15
14
13
12
10
9
C
D
φ A2
11
ECPD EXOR
OUT
OUT
B
VCC
S1
SHIFT
LEFT
SL
QH´
20
19
18
17
16
15
14
13
12
S1
SL
QH´
H/QH
F/QF
D/QD
B/QB
CK
G/QG
E/QE
C/QC
A/QA
QA´
CLEAR
φB
ENA
K
CLK
I/D
CLK
U/D
86
D/QD
B/QB CLOCK
SHIFT
RIGHT
SR
11
SR
G
I/D
OUT
1
2
3
4
5
6
7
8
B
A
ENA
K
CLK
I/D
CLK
U/D
I/D
OUT
GND
1
2
3
4
5
6
7
8
S0
G1
G2
G/QG
E/QE
C/QC
A/QA
QA´
OUTPUT
CONTROLS
See page 306
F/QF
S0
φ A1
A
H/QH
See page 314
9
10
CLEAR GND
Pin Assignments
348
366
8-LINE TO 3-LINE PRIORITY ENCODER
HEX BUS DRIVERS
HEX BUFFERS/LINE DRIVERS 3-STATE
OUTPUTS
INPUTS
VCC
EO
GS
3
2
1
0
OUTPUT
A0
16
15
14
13
12
11
10
9
EO
GS
3
2
1
0
5
6
7
EI
A2
A1
4
VCC
G2
6A
6Y
5A
5Y
4A
4Y
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
G1
1A
1Y
2A
2Y
3A
3Y
GND
A0
1
2
3
4
5
6
7
8
4
5
6
7
EI
A2
A1
GND
INPUTS
See page 323
367
OUTPUTS
HEX BUS DRIVERS
See page 316
354
356
VCC
G2
6A
6Y
5A
5Y
4A
4Y
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
G1
1A
1Y
2A
2Y
3A
3Y
GND
8-INPUT MULTIPLEXERS/REGISTERS 3-STATE
SELECT
S2 CONTROL
VCC
Y
W
G3
G2
G1
S0
S1
20
19
18
17
16
15
14
13
12
Y
W
G3
G2
G1
S0
S1
S2
D6
D5
D4
D3
D2
D1
D0
DATA
C/C
11
See page 324
D7
SC
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
9
368
HEX BUS DRIVERS
10
DATA GND
CONTROL
/CLOCK
VCC
G2
6A
6Y
5A
5Y
4A
4Y
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
G1
1A
1Y
2A
2Y
3A
3Y
GND
See page 318, 320
365
HEX BUS DRIVERS
See page 324
VCC
G2
6A
6Y
5A
5Y
4A
4Y
16
15
14
13
12
11
10
9
373
OCTAL D-TYPE LATCHES
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
ENABLE
G
20
19
18
17
16
15
14
13
12
11
Q
D
G
D
G
Q
Q
D
G
D
G
Q
OE
1
2
3
4
5
6
7
8
G1
1A
1Y
2A
2Y
3A
3Y
GND
Q
D
G
D
G
OE
Q
Q
OE
OE
D
G
D
G
OE
Q
OE
2
3
4
5
6
7
8
9
10
OUTPUT 1Q
CONTROL
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
See page 322
OE
OE
See page 325
87
Pin Assignments
374
390
OCTAL D-TYPE FLIP-FLOPS
DUAL DECADE COUNTERS
OUTPUTS
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLOCK
VCC
2A
20
19
18
17
16
15
14
13
12
11
16
15
1
Q
D
CK
OE
D
Q
CK
OE
Q
D
CK
OE
D
Q
CK
OE
Q
D
CK
OE
D
Q
CK
OE
Q
D
CK
OE
D
Q
CK
OE
2 OUTPUT
CLEAR 2 QA
14
13
QA
CLEAR
A
A
CLEAR
QA
2
3
4
5
6
7
8
9
10
OUTPUT 1Q
CONTROL
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
1A
3
1
1 QA
CLEAR OUTPUT
2 QD
2B
2 QB
2 QC
12
11
10
9
B
QB
QC
QD
QD
B
QB
QC
4
5
6
7
8
1B
1 QB
1 QC
1 QD
GND
OUTPUTS
See page 326
See page 330
375
393
4-BIT BISTABLE LATCHES
DUAL 4-BIT BINARY COUNTERS
OUTPUTS
VCC
4D
4Q
4Q
ENABLE
3-4
16
15
14
13
12
Q
G
G
3Q
3Q
3D
VCC
2A
11
10
9
14
13
Q
Q
D
D
2
CLEAR 2 QA
12
11
2 QB
2 QC
10
9
8
QC
QD
QA
QB
CLEAR
Q
G
2 QD
A
D
D
Q
Q
Q
G
Q
1
2
3
4
5
6
7
8
1D
1Q
1Q
ENABLE
1-2
2Q
2Q
2D
GND
CLEAR
QB
QA
1
1A
2
3
1
1 QA
CLEAR
A
QD
QC
4
5
6
7
1 QB
1 QC
1 QD
GND
OUTPUTS
See page 327
See page 331
377
395
OCTAL D-TYPE FLIP-FLOPS
4-BIT UNIVERSAL SHIFT REGISTERS
OUTPUTS
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLOCK
20
19
18
17
16
15
14
13
12
11
Q
D
CK
G
D
Q
CK
G
Q
D
CK
G
CASCADE
OUTPUT
OUTPUT
QD´ CLOCK CONTROL
VCC
QA
QB
QC
QD
16
15
14
13
12
11
10
QA
QB
QC
QD
QD´
CK
SERIAL
INPUT
A
B
C
D
2
3
4
5
6
7
8
A
B
C
D
LOAD
SHIFT
GND
D
Q
CK
G
OUTPUT
CONTROL
CLEAR
G
G
CK
D
Q
Q
CK
D
1
2
3
4
ENABLE
G
1Q
1D
2D
G
G
CK
D
Q
Q
CK
D
5
6
7
8
9
10
2Q
3Q
3D
4D
4Q
GND
1
CLEAR SERIAL
INPUT
9
LOAD
SHIFT
PARALLEL INPUTS
See page 328
See page 332
378
399
HEX D-TYPE FLIP-FLOPS
QUAD 2-INPUT MULTIPLEXER WITH STORAGE
VCC
6Q
6D
5D
5Q
4D
4Q
CLOCK
VCC
QD
D1
D2
C2
C1
QC
CLOCK
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
QD
D1
D2
C2
C1
QC
A1
A2
B2
B1
QB
D
CK
G
D
Q
CK
G
Q
D
CK
G
G
CK
Q
D
G
CK
D
Q
G
CK
Q
D
Q
WS
See page 329
88
QA
CK
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
ENABLE
G
1Q
1D
2D
2Q
3D
3Q
GND
WORD
SELECT
QA
A1
A2
B2
B1
QB
GND
See page 334
Pin Assignments
520
521
423
RE-TRIGGERABLE MONO-STABLE MULTIVIBRATOR
positive logic:
Y=A
8-BIT IDENTITY COMPARATOR
VCC
16
1 Rext/
Cext 1 Cext
15
14
1Q
2Q
2CLR
2B
2A
VCC
P=Q
Q7
P7
Q6
P6
Q5
P5
Q4
P4
13
12
11
10
9
20
19
18
17
16
15
14
13
12
11
P=Q
Q7
P7
Q6
P6
Q5
P5
Q4
P0
Q0
P1
Q1
P2
Q2
P3
Q3
CLR
P4
G
CLR
1
2
3
4
5
1A
1B
1CLR
1Q
2Q
6
7
8
2
2 Rext/ GND
Cext
Cext
1
2
3
4
5
6
7
8
9
10
G
P0
Q0
P1
Q1
P2
Q2
P3
Q3
GND
See page 335
See page 342, 344
442
533
QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS
OCTAL D-TYPE TRANSPARENT LATCHES
VCC
GC
GB
GA
A1
A2
A3
A4
S1
S0
20
19
18
17
16
15
14
13
12
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
C
20
19
18
17
16
15
14
13
12
11
Q
Q
1
2
3
4
5
6
7
8
9
10
CS
B1
C1
C2
B2
B3
C3
C4
B4
GND
D
C8
OC
D
C7 Q
OC
Q
C1
OC D
C2
D OC
Q
Q
D
C6
OC
Q
D
C5
OC
C3
OC D
C4
D OC
Q
1
2
3
4
5
6
7
8
9
10
OC
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
See page 336
See page 346
465
534
OCTAL BUFFERS WITH 3-STATE OUTPUTS
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
VCC
G2
A8
Y8
A7
Y7
A6
Y6
A5
Y5
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
G2
A8
Y8
A7
Y7
A6
Y6
A5
8Q
CK
OC
D
7Q
6Q
2Q
CK
D OC
3Q
D
CK
OC
CK
OC
D
D
5Q
CK
OC
Y5
G1
1Q
A1
Y1
A2
Y2
A3
Y3
A4
CK
OC D
Y4
CK
OC D
4Q
CK
D OC
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
G1
A1
Y1
A2
Y2
A3
Y3
A4
Y4
GND
OC
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
See page 338
See page 347
518
540
541
8-BIT IDENTITY COMPARATOR
OCTAL BUFFERS AND LINE DRIVERS
VCC
P=Q
Q7
P7
Q6
P6
Q5
P5
Q4
P4
20
19
18
17
16
15
14
13
12
11
P=Q
Q7
P7
Q6
P6
Q5
P5
Q4
P0
Q0
P1
Q1
P2
Q2
P3
Q3
G
See page 340
VCC
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
20
19
18
17
16
15
14
13
12
11
P4
1
2
3
4
5
6
7
8
9
10
G
P0
Q0
P1
Q1
P2
Q2
P3
Q3
GND
1
2
3
4
5
6
7
8
9
10
G1
A1
A2
A3
A4
A5
A6
A7
A8
GND
See page 348, 349
89
Pin Assignments
543
569
OCTAL REGISTERED TRANSCEIVERS
SYNCHRONOUS 4-BIT UP/DOWN COUNTERS
VCC
CEBA
B1
B2
B3
B4
B5
B6
B7
B8
LEAB
OEAB
VCC
RCO
CCO
OC
QA
QB
QC
QD
ENT
SLOAD
24
23
22
21
20
19
18
17
16
15
14
13
20
19
18
17
16
15
14
13
12
11
CEBA
B1
B2
B3
B4
B5
B6
B7
B8
LEAB
RCO
CCO
OC
QA
QB
QC
QD
LEBA
U/D
OEAB
CLK
OEBA
A1
A2
A3
A4
A5
A6
A7
A8
ENT
SLOAD
DA
DB
DC
DD
ENP
ACLR
SCLR
CEAB
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
LEBA
OEBA
A1
A2
A3
A4
A5
A6
A7
A8
CEAB
GND
U/D
CLK
DA
DB
DC
DD
ENP
ACLR
SCLR
GND
See page 350
See page 356
561
573
SYNCHRONOUS 4-BIT COUNTER
OCTAL D-TYPE TRANSPARENT LATCHES
VCC
RCO
CCO
G
QA
QB
QC
QD
ENT
SLOAD
20
19
18
17
16
15
14
13
12
11
RCO
CCO
G
QA
QB
QC
QD
ENT
ALOAD
CLK
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
ENABLE
C
20
19
18
17
16
15
14
13
12
11
SLOAD
DA
DB
DC
DD
ENP
ACLR
Q OE
Q OE
Q OE
Q OE
Q OE
Q OE
Q OE
Q OE
D G
D G
D G
D G
D G
D G
D G
D G
SCLR
1
2
3
4
5
6
7
8
9
10
ALOAD
CLK
DA
DB
DC
DD
ENP
ACLR
SCLR
GND
1
2
3
4
5
6
7
8
9
10
OC
1D
2D
3D
4D
5D
6D
7D
8D
GND
See page 352
See page 358
563
574
OCTAL D-TYPE TRANSPARENT LATCHES
WITH INVERTED OUTPUTS
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
ENABLE
C
20
19
18
17
16
15
14
13
12
11
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
20
19
18
17
16
15
14
13
12
11
C
OC
1D
2D
3D
4D
5D
6D
7D
1
2
3
4
5
6
7
8
9
10
OC
1D
2D
3D
4D
5D
6D
7D
8D
GND
Q OE
Q OE
Q OE
Q OE
Q OE
Q OE
Q OE
Q OE
D CK
D CK
D CK
D CK
D CK
D CK
D CK
D CK
8D
4D
1
2
3
4
5
6
7
8
9
10
OC
1D
2D
3D
4D
5D
6D
7D
8D
GND
See page 354
See page 359
564
575
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
OCTAL D-TYPES EDGE-TRIGGERED FLIP-FLOPS
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
20
19
18
17
16
15
14
13
12
11
1Q
2Q
3Q
4Q
5Q
6Q
7Q
OC
VCC
NC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLK
NC
24
23
22
21
20
19
18
17
16
15
14
13
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
8
9
10
11
12
D5
D6
D7
NC
GND
8Q
CLK
SCLR
CLK
OC
1D
2D
3D
4D
5D
6D
7D
1
2
3
4
5
6
7
8
8D
9
10
OC
1D
2D
3D
4D
5D
6D
7D
8D
GND
1
2
3
4
5
6
7
SCLR
OC
D0
D1
D2
D3
D4
NC – No internal connection
See page 355
90
See page 360
Pin Assignments
576
592
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
8-BIT BINARY COUNTER WITH INPUT REGISTER
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
20
19
18
17
16
15
14
13
12
11
Q OE
Q OE
Q OE
Q OE
Q OE
Q OE
Q OE
Q OE
D CK
D CK
D CK
D CK
D CK
D CK
D CK
D CK
VCC
QA
16
15
CLOAD RCK CCKEN
14
QA
CLOAD
13
RCK
12
CCKEN
CCK
CCLR
RCO
11
10
9
CCK
QB
RCO
QC
1
2
3
4
5
6
7
8
9
10
OC
1D
2D
3D
4D
5D
6D
7D
8D
GND
QD
QE
QF
QG
1
2
3
4
5
6
7
8
QC
QD
QE
QF
QG
QH
GND
CCK
CCLR
RCO
13
12
11
See page 366
577
593
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
8-BIT BINARY COUNTER WITH INPUT REGISTER
RCKEN RCK CCKEN CCKEN
VCC
NC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLK
NC
VCC
G
G
24
23
22
21
20
19
18
17
16
15
14
13
20
19
18
17
G
G
RCKEN
B/QB
C/QC
D/QD
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
16
RCK
15
14
CCKEN CCKEN
CCK
CCLR
CLK
A/QA
SCLR
OC
QH
QB
See page 361
Q0
CCLR
RCO
E/QE
F/QF
G/QG
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
SCLR
OC
D0
D1
D2
D3
D4
D5
D6
D7
NC
GND
A/QA
B/QB
C/QC
D/QD
E/QE
F/QF
G/QG
H/QH CLOAD
8
9
10
H/QH CLOAD GND
NC – No internal connection
See page 362
See page 368
580
594
OCTAL D-TYPE TRANSPARENT LATCHES
WITH INVERTED OUTPUTS
8-BIT SHIFT REGISTER WITH OUTPUT LACH
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
ENABLE
C
VCC
QA
SER
RCLR
RCK
SCK
SCLR
QH'
20
19
18
17
16
15
14
13
12
11
16
15
14
13
12
11
10
9
QA
SER
RCLR
SCK
SCLR
QD
QE
QG
QH
Q OE
Q OE
Q OE
Q OE
Q OE
Q OE
Q OE
Q OE
D G
D G
D G
D G
D G
D G
D G
D G
RCK
QB
QH'
QC
QF
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
OC
1D
2D
3D
4D
5D
6D
7D
8D
GND
QB
QC
QD
QE
QF
QG
QH
GND
See page 363
See page 370
590
595
596
8-BIT BINARY COUNTER WITH OUTPUT REGISTER
8-BIT SHIFT REGISTER WITH OUTPUT LATCH
VCC
QA
G
16
15
14
QA
G
RCK CCKEN
CCK
CCLR
RCO
13
11
10
9
RCK
12
CCKEN
CCK
QB
VCC
QA
SER
G
RCK
SCK
SCLR
QH'
16
15
14
13
12
11
10
9
QA
SER
G
SCK
SCLR
QD
QE
QG
QH
CCLR
RCO
QC
QD
QE
QF
QG
QH'
QC
See page 364
RCK
QB
QH
1
2
3
4
5
6
7
8
QB
QC
QD
QE
QF
QG
QH
GND
QF
1
2
3
4
5
6
7
8
QB
QC
QD
QE
QF
QG
QH
GND
See page 372, 374
91
Pin Assignments
597
624
8-BIT SHIFT REGISTER WITH INPUT LATCH
VOLTAGE-CONTROLLED OSCILLATOR
VCC
A
16
15
A
SER SLOAD RCK
SCK
SCLR
QH'
~
VCC
FREQ
CONTROL
NC
NC
NC
14
12
11
10
9
14
13
12
11
10
RCK
SCK
13
SER SLOAD
B
SCLR
Z
VCC OUTPUT
FREQ
CONTROL
Z
RANGE
Cext
Y
9
8
6
7
QH'
C
D
E
F
G
H
1
2
3
4
5
6
7
8
B
C
D
E
F
G
H
GND
1
2
EN
3
4
~
RANGE CX1
GND
5
CX2 ENABLE Y
GND
OUTPUT
NC – No internal connection
See page 376
See page 383
598
628
8-BIT SHIFT REGISTERS
VOLTAGE-CONTROLLED OSCILLATOR
VCC
DS
SER0
SER1
G
20
19
18
17
16
DS
SER0
SER1
G
RCK SCKEN
SCK
SCLR
QH'
~
VCC
FREQ
CONTROL
15
14
13
12
11
14
13
SCKEN
SCK
SCLR
RCK
A/QA
Rext
Z
VCC OUTPUT
NC
12
11
10
FREQ
CONTROL
Z
RANGE
Cext
Y
9
8
6
7
QH'
B/QB
C/QC
D/QD
E/QE
F/QF
G/QG
1
2
3
4
5
6
7
A/QA
B/QB
C/QC
D/QD
E/QE
F/QF
G/QG
H/QH SLOAD
8
9
10
1
H/QH SLOAD GND
2
EN
3
4
~
RANGE CX1
GND
5
CX2 ENABLE Y
GND
OUTPUT
NC – No internal connection
See page 378
See page 384
620
621
623
629
VOLTAGE-CONTROLLED OSCILLATOR
OCTAL BUS TRANSCEIVERS
VCC
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
VCC
~
2
VCC RANGE
16
15
14
20 19 18 17 16 15 14 13 12 11
2Y
OUT2
ENABLE PUT
2Cext
13
12
11
10
6
7
GND
9
RNG Cext
Y
FREQ
CONT
EN
EN
FREQ
CONT
Y
RNG Cext
1
2
3
4
5
6
7
8
9
10
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
See page 380, 381, 382
92
1
2
3
2
1
1
RANGE
FREQ
CONTROL
See page 385
4
5
1Cext
1Y
1
ENABLE OUTPUT
8
~
GND
Pin Assignments
638
641
645
OCTAL BUS TRANSCEIVERS
OCTAL BUS TRANSCEIVERS
VCC
ENABLE
G
B1
B2
B3
B4
B5
B6
B7
B8
VCC
ENABLE
G
B1
B2
B3
B4
B5
B6
B7
B8
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
See page 386
See page 389, 391
639
646
647
648
OCTAL BUS TRANSCEIVERS
OCTAL BUS TRANSCEIVERS AND REGISTERS
VCC
ENABLE
G
B1
B2
B3
B4
B5
B6
B7
B8
20
19
18
17
16
15
14
13
12
11
VCC
24
CONTCLOCK SELECT ROL
BA
BA
G
23
22
21
CONTCLOCK SELECT
BA
ROL
BA
G
CLOCK
AB
SELECT DIRECAB
TION
1
2
3
4
5
6
7
8
9
10
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
A1
3
CLOCK SELECT DIRECAB
AB
TION
See page 387
See page 392, 394, 396
640
642
651
652
653
654
OCTAL BUS TRANSCEIVERS
B1
B2
B3
B4
B5
B6
B7
B8
20
19
18
17
16
15
14
13
B1
B2
B3
B4
B5
B6
B7
A2
A3
A4
A5
A6
A7
A8
B8
4
5
6
7
8
9
10
11
12
A1
A2
A3
A4
A5
A6
A7
A8
GND
OCTAL BUS TRANSCEIVERS AND REGISTERS
VCC
ENABLE
G
B1
B2
B3
B4
B5
B6
B7
B8
20
19
18
17
16
15
14
13
12
11
VCC
24
CLOCK SELECT ENABLE
BA
BA
GBA
23
22
21
CLOCK SELECT ENABLE
BA
GBA
BA
CLOCK
AB
SELECT ENABLE
AB
GAB
1
2
3
4
5
6
7
8
9
10
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
CLOCK SELECT ENABLE
AB
AB
GAB
See page 388, 390
A1
B1
B2
B3
B4
B5
B6
B7
B8
20
19
18
17
16
15
14
13
B1
B2
B3
B4
B5
B6
B7
A2
A3
A4
A5
A6
A7
A8
B8
4
5
6
7
8
9
10
11
12
A1
A2
A3
A4
A5
A6
A7
A8
GND
See page 398, 400, 402, 404
93
Pin Assignments
657
670
OCTAL BUS TRANSCEIVERS
WITH 8-BIT PARITY GENERATORS/CHECKERS
4-BY-4 REGISTER FILE
WRITE SELECT
OE
B1
B2
B3
B4
GND
GND
B5
B6
B7
B8
PARITY
24
23
22
21
20
19
18
17
16
15
14
13
B1
B2
B3
B4
B5
B6
B7
B8
OE
DATA
D1
WA
WB
16
15
14
13
12
D1
WA
WB
D3
D4
RB
PARITY
T/R
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
10
T/R
A1
A2
A3
A4
A5
VCC
A6
A7
A8
ERROR
ODD
/EVEN
11
ENABLE
VCC
WRITE READ
OUTPUT
Q1
Q2
11
10
9
GW
GR
Q1
RA
Q4
Q3
D2
12
ODD ERROR
/EVEN
Q2
1
2
3
4
5
6
7
8
D2
D3
D4
RB
RA
Q4
Q3
GND
DATA
See page 406
See page 414
666
667
673
READ SELECT
OUTPUTS
16-BIT SHIFT REGISTER
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
STORAGE REGISTER OUTPUT
VCC
OE2
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
PRE
C
24
23
22
21
20
19
18
17
16
15
14
13
OE2
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
PRE
OERB
OE1
VCC
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y8
Y7
Y6
Y5
24
23
22
21
20
19
18
17
16
15
14
13
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y8
Y7
Y6
Y0
Y1
Y2
Y3
Y4
CS
SH
CK
C
1D
2D
3D
4D
5D
6D
7D
8D
STORE
R/W
CLR
1
1
2
3
4
5
6
7
8
9
10
11
12
OE1
1D
2D
3D
4D
5D
6D
7D
8D
CLR
GND
2
3
4
669
674
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
16-BIT SHFT REGISTER
OUTPUTS
QB
QC
QD
16
14
13
12
11
RIPPLE QA
CARRY
OUTPUT
UP/DOWN
CK
A
QB
QC
QD
B
C
D
4
5
6
B
C
D
2
3
A
7
8
9
10
11
12
Y0
Y1
Y2
Y3
Y4
GND
PARALLEL INPUTS
RIPPLE
CARRY
VCC OUTPUT QA
CK
6
STRAGE REGISTER
OUTPUTS
See page 416
1
5
CHIP SHIFT READ/ STORE STORE DATA
SELECT CLOCK WRITE CLR
CK
I/O
See page 408, 410
U/D
Y5
CLR
OERB
15
STORE
DATA
CK
I/O
ENABLE
LOAD
T
10
9
VCC
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
24
23
22
21
20
19
18
17
16
15
14
13
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P0
P1
P2
P3
P4
8
9
10
11
12
P1
P2
P3
P4
GND
ENABLE
T
LOAD
ENABLE
P
7
P5
CS
CK
8
ENABLE GND
P
1
2
R/W
3
CHIP CLOCK READ/
SELECT
WRITE
DATA INPUTS
DATA
MODE I/O
4
NC
5
6
MODE DATA
CONTROL I/O
7
P0
PARALLEL INPUTS
NC – No internal connection
See page 412
94
See page 418
Pin Assignments
679
688
ADDRESS COMPARATOR
8-BIT IDENTITY COMPARATOR
VCC
G
Y
P3
P2
P1
P0
A12
A11
A10
20
19
18
17
16
15
14
13
12
11
G
Y
P3
P2
P1
P0
A12
A11
A10
VCC
P=Q
Q7
P7
Q6
P6
Q5
P5
Q4
P4
20
19
18
17
16
15
14
13
12
11
P=Q
Q7
P7
Q6
P6
Q5
P5
Q4
P0
Q0
P1
Q1
P2
Q2
P3
Q3
G
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
10
A1
A2
A3
A4
A5
A6
A7
A8
A9
GND
P4
A9
1
2
3
4
5
6
7
8
9
10
G
P0
Q0
P1
Q1
P2
Q2
P3
Q3
GND
See page 420
See page 428
682
684
697
699
8-BIT IDENTITY COMPARATOR
SYNCHRONOUS UP/DOWN COUNTER
WITH OUTPUT REGISTER, MULTIPLEXED
THREE-STATE OUTPUT
VCC
P=Q
Q7
P7
Q6
P6
Q5
P5
Q4
P4
20
19
18
17
16
15
14
13
12
11
P=Q
Q7
P7
Q6
P6
Q5
P5
RIPPLE
CAPPY
VCC OUTPUT QA
P>Q
QB
QC
QD
19
18
17
16
15
RCO
QA
QB
QC
QD
CCK
A
B
C
D
2
3
4
5
6
UP/
A
DOWN
COUNTER
CLOCK
B
C
D
20
Q4
3-STATE OUTPUT
P4
OUTPUT
ENABLE
CONTROL R/C
LOAD
SELECT
T
14
13
ENABLE LOAD
T
U/D
P0
Q0
P1
Q1
P2
Q2
P3
12
11
G
R/C
Q3
1
2
3
4
5
6
7
8
9
10
P>Q
P0
Q0
P1
Q1
P2
Q2
P3
Q3
GND
1
DATA INPUTS
ENA
P
CCLR
RCK
7
8
9
10
ENABLE
ESIST- GND
P COUNT- ER
ER CLOCK
CLEAR
See page 422, 424
See page 430, 432
686
756
8-BIT IDENTITY COMPARATOR
OCTAL BUFFER/LINE DRIVER/LINE RECEIVER
WITH OPEN-COLLECTOR OUTPUTS
VCC
G2
P=Q
Q7
P7
NC
Q6
P6
Q5
P5
Q4
P4
VCC
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
24
23
22
21
20
19
18
17
16
15
14
13
20
19
18
17
16
15
14
13
12
11
G2
P=Q
Q7
P7
Q6
P6
Q5
P5
Q4
G1
P0
Q0
P1
P2
Q2
P3
Q3
P>Q
P4
Q1
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
P>Q
G1
P0
Q0
P1
Q1
NC
P2
Q2
P3
Q3
GND
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
NC – No internal connection
See page 426
See page 434
95
Pin Assignments
757
808
OCTAL BUFFER/LINE DRIVER/LINE RECEIVER
WITH OPEN-COLLECTOR OUTPUTS
HEX 2-INPUT AND DRIVERS
positive logic:
Y=A+B
VCC
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
VCC
6B
6A
6Y
5B
5A
5Y
4B
4A
4Y
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
1A
1B
1Y
2A
2B
2Y
3A
3B
3Y
GND
See page 435
See page 438
760
821
OCTAL BUFFER/LINE DRIVER/LINE RECEIVER
WITH OPEN-COLLECTOR OUTPUTS
10-BIT BUS INTERFACE FLIP FLOPS
WITH 3-STATE OUTPUT
VCC
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
CLK
20
19
18
17
16
15
14
13
12
11
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
OC
CLK
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
11
12
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
OC
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
See page 436
See page 439
804
823
HEX 2-INPUT NAND DRIVERS
9-BIT BUS INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUT
positive logic:
A=A•B
VCC
6B
6A
6Y
5B
5A
5Y
4B
4A
4Y
20
19
18
17
16
15
14
13
12
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
CLKEN
CLK
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
CLKEN
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
OC
1
2
3
4
5
6
7
8
9
10
1A
1B
1Y
2A
2B
2Y
3A
3B
3Y
GND
See page 437
CLK
1
2
3
4
5
6
7
8
9
10
11
12
OC
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
See page 440
805
825
HEX 2-INPUT NOR DRIVERS
8-BIT BUS INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUT
positive logic:
Y=A+B
VCC
6B
6A
6Y
5B
5A
5Y
4B
4A
4Y
20
19
18
17
16
15
14
13
12
11
VCC
OC3
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLKEN
CLK
24
23
22
21
20
19
18
17
16
15
14
13
OC3
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLKEN
OC2
1D
2D
3D
4D
5D
6D
7D
8D
CLR
OC1
See page 438
96
1
2
3
4
5
6
7
8
9
10
1A
1B
1Y
2A
2B
2Y
3A
3B
3Y
GND
CLK
1
2
3
4
5
6
7
8
9
10
11
12
OC1
OC2
1D
2D
3D
4D
5D
6D
7D
8D
CLR
GND
See page 442
Pin Assignments
827
841
10-BIT BUFFER/BUS DRIVERS
10-BIT BUS INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
VCC
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
OE2
24
23
22
21
20
19
18
17
16
15
14
13
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
C
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
OC
1
2
3
4
5
6
7
8
9
10
11
12
OE1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
C
1
2
3
4
5
6
7
8
9
10
11
12
OC
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
See page 444
See page 448
828
843
10-BIT BUFFERS/BUS DRIVERS
9-BIT BUS INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
VCC
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
OE2
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
PRE
C
24
23
22
21
20
19
18
17
16
15
14
13
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
PRE
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
OC
C
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
OE1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
OC
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
See page 444
See page 450
832
853
HEX 2-INPUT OR DRIVERS
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
positive logic:
Y=A+B
VCC
6B
6A
6Y
5B
5A
5Y
4B
4A
4Y
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
1A
1B
1Y
2A
2B
2Y
3A
3B
3Y
GND
VCC
B1
B2
B3
B4
B5
B6
B7
B8
24
23
22
21
20
19
18
17
16
2
3
4
5
6
7
8
9
10
11
12
A2
A3
A4
A5
A6
A7
A8
ERR
CLR
GND
857
10-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
HEX 2-TO-1 UNIVERSAL MULTIPLEXERS
B1
B2
B3
B4
B5
B6
B7
B8
22
21
20
19
18
17
16
PARITY OEB
15
14
13
A1
See page 452
23
LE
14
1
833
24
15
OEA
See page 445
VCC
PARITY OEB
CLK
VCC
S1
6A
6B
6Y
5A
5B
5Y
4A
4B
4Y
T/C
13
24
23
22
21
20
19
18
17
16
15
14
13
S1
6A
6B
6Y
5A
5B
5Y
4A
4B
4Y
1A
1B
1Y
2A
2B
2Y
3A
3B
3Y
OPER=0
S0
T/C
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
OEA
A1
A2
A3
A4
A5
A6
A7
A8
ERR
CLR
GND
S0
1A
1B
1Y
2A
2B
2Y
3A
3B
3Y
OPER
ZERO
GND
See page 446
See page 454
97
Pin Assignments
861
873
10-BIT TRANSCEIVERS
WITH 3-STATE OUTPUTS
DUAL 4-BIT D-TYPE LATCHES
VCC
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
OEAB
VCC
24
23
22
21
20
19
18
17
16
15
14
13
24
ENABEL
1Q1
1C
23
1Q2
1Q3
1Q4
2Q1
2Q2
2Q3
2Q4
22
21
20
19
18
17
16
15
Q1
C
CLR
OC
D1
Q2
Q3
Q4
Q1
Q2
Q3
D2
D3
D4
D1
D2
D3
Q4
C
CLR
OC
D4
ENABEL
2CLR
2C
14
13
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
OEBA
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
1CLR
1OC
1D1
1D2
1D3
1D4
2D1
2D2
2D3
2D4
2OC
GND
See page 456
See page 464
863
874
9-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
VCC
B1
B2
B3
B4
B5
B6
B7
B8
B9
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
OEBA1
A1
A2
A3
A4
A5
A6
A7
A8
A9
OEAB2 OEAB1
14
13
11
12
OEBA2 GND
VCC
1CLK
1Q1
1Q2
1Q3
1Q4
2Q1
2Q2
2Q3
2Q4
2CLK
2CLR
24
23
22
21
20
19
18
17
16
15
14
13
Q1
CLK
CLR
OC
D1
Q2
Q3
Q4
Q1
Q2
Q3
D2
D3
D4
D1
D2
D3
Q4
CLK
CLR
OC
D4
1
2
3
4
5
6
7
8
9
10
11
12
1CLR
1OC
1D1
1D2
1D3
1D4
2D1
2D2
2D3
2D4
2OC
GND
NC – No internal connection
NC – No internal connection
See page 457
See page 465
867
869
876
DUAL 4-BIT D-TYPE FLIP-FLOPS
8-BIT SYNCHRONOUS BIDIRECTIONAL COUNTER
VCC
ENABEL
P
QA
QB
QC
QD
QE
QF
QG
QH
CLK
RCO
VCC
1CLK
1Q1
1Q2
1Q3
1Q4
2Q1
2Q2
2Q3
2Q4
2CLK
2PRE
24
23
22
21
20
19
18
17
16
15
14
13
24
23
22
21
20
19
18
17
16
15
14
13
EN
P
QA
QB
QC
QD
QE
QF
QG
QH
CLK
Q1
CLK
PRE
OC
D1
Q2
Q3
Q4
Q1
Q2
Q3
EN
T
D2
D3
D4
D1
D2
D3
Q4
CLK
PRE
OC
D4
S0
RCO
S1
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
8
9
10
S0
S1
A
B
C
D
E
F
G
H
11
1
2
3
4
5
6
7
8
9
10
11
12
1PRE
1OC
1D1
1D2
1D3
1D4
2D1
2D2
2D3
2D4
2OC
GND
See page 458, 460
See page 466
870
885
DUAL 16-BY 4-BIT REGISTER FILES
8-BIT MAGNITUDE COMPARATOR
P<QOUT
P>QOUT
VCC
CLK
SERIN
B1
B2
B3
B4
B5
B6
B7
B8
Q8
VCC
PLE
P7
P6
P5
P4
P3
P2
P1
P0
24
23
22
21
20
19
18
17
16
15
14
13
24
23
22
21
20
19
18
17
16
15
14
PLE
P7
P6
P5
P4
P3
P2
P1
P0
P<QOUT
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CLK
SERIN DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8
S0
Q8
S1
S2
L/A
P>QOUT
P<QIN P>QIN
DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8
13
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
S0
S1
S2
A1
A2
A3
A4
A5
A6
A7
A8
GND
L/A
P<Q
IN
P>Q
IN
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
GND
See page 462
98
12
ENABEL GND
T
See page 468
Pin Assignments
990
1000
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
QUAD 2-INPUT NAND BUFFERS/DRIVERS
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
C
VCC
4B
4A
4Y
3B
3A
3Y
20
19
18
17
16
15
14
13
12
11
14
13
12
11
10
9
8
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
2D
3D
4D
5D
6D
7D
8D
OERB
C
1D
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
OERB
1D
2D
3D
4D
5D
6D
7D
8D
GND
1A
1B
1Y
2A
2B
2Y
GND
See page 470
See page 476
992
1004
9-BIT D-TYPE TRANSPARENT
HEX INVERTING DRIVERS
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
OEQ
C
VCC
6A
6Y
5A
5Y
4A
4Y
24
23
22
21
20
19
18
17
16
15
14
13
14
13
12
11
10
9
8
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
OEQ
2D
3D
4D
5D
6D
7D
8D
9D
CLR
C
OERB
1D
1
2
3
4
5
6
7
8
9
10
11
12
OERB
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
See page 471
See page 476
994
1005
10-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
HEX INVERTING BUFFER GATES
WITH OPEN-COLLECTOR OUTPUTS
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
C
VCC
6A
6Y
5A
5Y
4A
4Y
24
23
22
21
20
19
18
17
16
15
14
13
14
13
12
11
10
9
8
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
2D
3D
4D
5D
6D
7D
8D
9D
10D
C
OERB
1D
1
2
3
4
5
6
7
8
9
10
11
12
OERB
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
See page 472
See page 477
996
1008
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
QUADRUPLE 2-INPUT POSITIVE-AND BUFFERS/DRIVERS
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
OE
T/C
CLR
VCC
4B
4A
4Y
3B
3A
3Y
24
23
22
21
20
19
18
17
16
15
14
13
14
13
12
11
10
9
8
1
2
3
4
5
6
7
8
9
10
11
12
1D
2D
3D
4D
5D
6D
7D
8D
EN
RD
CLK
GND
See page 474
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
See page 477
99
Pin Assignments
1032
1244
QUAD 2-INPUT OR BUFFERS/DRIVERS
OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
positive logic:
Y = A+B
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
VCC
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
See page 478
See page 480
1034
1245
HEX DRIVERS
OCTAL BUS TRANSCEIVERS
ENABLE
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
VCC
G
B1
B2
B3
B4
B5
B6
B7
B8
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
See page 478
See page 480
1035
1640
HEX BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
OCTAL BUS TRANSCEIVERS
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
20
ENABLE
G
B1
19
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
B7
B8
12
11
4
5
6
7
8
9
10
A3
A4
A5
A6
A7
A8
GND
VCC
20
See page 481
B6
13
3
OCTAL BUS TRANSCEIVERS
1Y1
B5
14
A2
1645
2G
B4
15
2
OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
19
B3
16
A1
See page 481
20
B2
17
1
1240
VCC
18
DIR
See page 479
See page 479
100
VCC
ENABLE
G
B1
19
18
B2
B3
B4
B5
B6
B7
B8
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
Pin Assignments
2240
2373
OCTAL BUFFERS AND LINE DRIVERS/MOS DRIVERS
WITH 3-STATE OUTPUTS
25-Ω OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
VCC
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
See page 482
See page 486
2241
2414
OCTAL BUFFERS AND LINE DRIVERS/MOS DRIVERS
WITH 3-STATE OUTPUTS
MEMORY DECODER WITH ON-CHIP VCC MONITOR
VCC
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
20
19
18
17
16
15
14
13
12
11
VCC
Vbat
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
20
19
18
17
16
15
14
13
12
11
Vbat
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
1A
2A
1B
2B
1G
2G
G
2Y3
VS
SD
1
2
3
4
5
6
7
8
9
10
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
1
2
3
4
5
6
7
8
9
10
VS
SD
1A
2A
1B
2B
1G
2G
G
GND
See page 483
See page 488
2244
2541
OCTAL BUFFERS AND LINE DRIVERS/MOS DRIVERS
WITH 3-STATE OUTPUTS
NON-INVERTED 3-STATE OUTPUTS
OCTAL LINE DRIVERS/MOS DRIVERS
WITH 3-STATE OUTPUTS
VCC
2G
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
See page 484
See page 490
2245
2827
2828
OCTAL TRANSCEIVER AND LINE/MOS DRIVERS
WITH 3-STATE OUTPUTS
VCC
20
ENABLE
G
B1
19
18
VCC
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
G1
A1
A2
A3
A4
A5
A6
A7
A8
GND
3-STATE OUTPUTS
3-STATE INVERTING OUTPUTS
BUS/MOS MEMORY DRIVERS
OUTPUTS
B2
B3
B4
B5
B6
B7
B8
17
16
15
14
13
12
11
VCC
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
OE2
24
23
22
21
20
19
18
17
16
15
14
13
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
A2
A3
A4
A5
A6
A7
A8
A9
A10
OE1
OE2
A1
See page 485
1
2
3
4
5
6
7
8
9
10
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
11
12
OE1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
See page 490, 491
101
Pin Assignments
2952
4015
OCTAL BUS TRANSCEIVERS AND REGISTERS
DUAL 4-STAGE STATIC SHIFT REGISTER
VCC
A8
A7
A6
A5
A4
A3
A2
A1
24
23
22
21
20
19
18
17
16
OEBA CLKBA
15
14
A8
A7
A6
A5
A4
A3
A2
B7
B6
B5
B4
B3
B2
CEBA
CLKAB
CEBA
B1 OEBA
B8
A1 OEBA
1
2
3
4
5
6
7
8
B8
B7
B6
B5
B4
B3
B2
B1
BA
13
VCC
2D
2MR
2Q0
2Q1
2Q2
1Q3
1CP
16
15
14
13
12
11
10
9
CLKBA
9
10
11
12
OEAB CLKAB CEBA GND
1
2
3
4
5
6
7
8
2CP
2Q3
1Q2
1Q1
1Q0
1MR
1D
GND
OUTPUTS
See page 492
See page 498
2953
4016
OCTAL BUS TRANSCEIVERS AND REGISTERS
QUAD BILATERAL SWITCH
OEBA CLKBA CEBA
VCC
A8
A7
A6
A5
A4
A3
A2
A1
24
23
22
21
20
19
18
17
16
15
14
A8
A7
A6
A5
A4
A3
A2
B7
B6
B5
B4
B3
B2
CEBA
CLKAB
CEAB
B1 OEAB
B8
13
VCC
1E
4E
4Y
4Z
3Z
3Y
14
13
12
11
10
9
8
A1 OEBA CLKBA
1
2
3
4
5
6
7
8
B8
B7
B6
B5
B4
B3
B2
B1
9
10
11
12
OEAB CLKAB CEAB GND
1
2
3
4
5
6
7
1Y
1Z
2Z
2Y
2E
3E
GND
OUTPUTS
See page 494
See page 499
3245
4017
OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT
VOLTAGE AND 3-STATE OUTPUTS
DECADE COUNTERS/DIVIDERS
OUTPUTS
VCCB
NC
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
VCC
CLR
CLK
CLKEN
CO
Y9
Y4
Y8
24
23
22
21
20
19
18
17
16
15
14
13
16
15
14
13
12
11
10
9
CO
Y9
Y4
Y6
Y7
Y3
CLR
CLK
Y5
Y8
Y1
Y0
Y2
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
VCCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
Y5
Y1
Y0
Y2
Y6
Y7
Y3
GND
NC – No internal connection
OUTPUTS
See page 496
See page 500
4002
4020
DUAL 4-INPUT POSITIVE-NOR GATES
14-STAGE BINARY COUNTERS
positive logic:
Y=A+B+C+D
OUTPUTS
VCC
2Y
2D
2C
2B
2A
NC
14
13
12
11
10
9
8
VCC
QK
QJ
QH
QI
CLR
CLK
OUTPUT
QA
16
15
14
13
12
11
10
9
QK
QJ
QH
QI
CLR
CLK
QN
QF
QE
QG
QD
QA
QL
QM
See page 497
102
1
2
3
4
5
6
7
1Y
1A
1B
1C
1D
NC
GND
1
2
3
QL
QM
QN
4
5
6
7
8
QF
QE
QG
QD
GND
OUTPUTS
See page 502
Pin Assignments
4024
4050
7-STAGE BINARY COUNTERS
HEX INVERTING BUFFERS NON-INVERTING
OUTPUTS
VCC
NC
QA
QB
NC
14
13
12
11
10
QA
QB
QG
QF
OUTPUT
QC
NC
9
8
NC
6Y
6A
NC
5Y
5A
4Y
4A
16
15
14
13
12
11
10
9
QC
CLK
CLR
QE
QD
1
2
3
4
5
6
7
CLK
CLR
QG
QF
QE
QD
GND
1
2
3
4
5
6
7
8
VCC
1Y
1A
2Y
2A
3Y
3A
GND
OUTPUTS
NC – No internal connection
NC – No internal connection
See page 503
See page 506
4040
4051
12-STAGE BINARY COUNTERS
8-CHANNEL ANALOG
MULTIPLEXERS/DEMULTIPLEXERS
OUTPUTS
VCC
QK
QJ
QH
QI
CLR
OUTPUT
CLK
QA
16
15
14
13
12
11
10
QJ
QH
QI
CLR
CLK
QE
QG
QD
QC
QB
QK
QL
9
VCC
Y2
Y1
Y0
Y3
A
B
C
16
15
14
13
12
11
10
9
QA
QF
1
2
3
QL
QF
QE
4
5
6
7
8
QG
QD
QC
QB
GND
1
2
3
4
5
6
7
8
Y4
Y6
COM
Y7
Y5
INH
GND
GND
OUTPUTS
See page 504
See page 507
4046
4052
PHASE-LOCKED-LOOP WITH VCO
DUAL 4-CHANNEL ANALOG
MULTIPLEXERS/DEMULTIPLEXERS
VCC PC3OUT SIGIN PC2OUT
R2
R1 DEMOUT VCOIN
16
15
14
13
12
11
1
2
3
4
5
PCPOUT PC1OUT COMPIN VCOOUT INH
10
9
6
7
8
C1A
C1B
GND
VCC
1Y2
1Y1
1-COM
1Y0
1Y3
A
B
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
2Y0
2Y2
2-COM
2Y3
2Y1
INH
GND
GND
See page 505
See page 508
4049
4053
HEX INVERTING BUFFERS
TRIPLE 2-CHANNEL ANALOG
MULTIPLEXERS/DEMULTIPLEXERS
NC
6Y
6A
NC
5Y
5A
4Y
4A
16
15
14
13
12
11
10
9
1
2
3
VCC
1Y
1A
4
5
6
7
8
2Y
2A
3Y
3A
GND
VCC
16
2-COM 1-COM
15
14
1Y1
1Y0
A
B
C
13
12
11
10
9
1
2
3
4
5
6
7
8
2Y1
2Y0
3Y1
3-COM
3Y0
INH
GND
GND
NC – No internal connection
See page 506
See page 509
103
Pin Assignments
4059
4075
CMOS PROGRAMMABLE DIVIDE-BY-N COUNTER
TRIPLE 3-INPUT OR GATES
positive logic:
Y=A+B+C
VCC
Q
J5
J6
J7
J8
J9
J10
J11
J12
Ka
Kb
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
CP
LE
J1
J2
J3
J4
J16
J15
J14
J13
Kc
GND
See page 510
See page 514
4060
4094
ASYNCHRONOUS 14-STAGE BINARY COUNTERS
AND OSCILLATORS
VCC
3C
3B
3A
3Y
2Y
2C
14
13
12
11
10
9
8
1
2
3
4
5
6
7
2A
2B
1A
1B
1C
1Y
GND
8-STAGE SHIFT AND STORE BUS REGISTER,
THREE-STATE
OUTPUTS
VCC
QJ
QH
QI
CLR
CKI
CKO
CKO
VCC
OE
Q4
Q5
Q6
Q7
QS2
QS1
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
QJ
QH
QI
CLR
CKI
CKO
QN
QF
QE
QG
QD
1
2
QL
CKO
QM
1
2
3
QL
QM
QN
4
5
6
7
8
QF
QE
QG
QD
GND
STROBE DATA
3
4
5
6
7
8
CP
Q0
Q1
Q2
Q3
GND
OUTPUTS
See page 511
See page 516
4066
4245
QUADRUPLE BILATERAL SWITCHES
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
WITH 3-STATE OUTPUTS
(3.3V) (3.3V)
VCCB VCCB
VCC
1C
4C
4A
4B
3B
3A
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
2B
2A
2C
3C
GND
I10
I11
I12
I13
I14
I15
E
S2
S3
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
COMMOMN I7
INPUT/
OUTPUT
I6
I5
I4
I3
I2
I1
I0
S2
S1
GND
See page 513
B2
B3
B4
B5
B6
B7
B8
GND
20
19
18
17
16
15
14
13
2
3
4
5
6
7
8
9
10
11
12
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
4316
I9
B1
21
DIR
See page 518
I8
OE
22
1
4067
VCC
23
(5V)
VCCA
See page 512
16-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER
104
24
QUAD ANALOG SWITCH WITH LEVEL TRANSLATION
See page 519
VCC
1S
4S
4Z
4Y
3Y
3Z
VEE
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1Z
1Y
2Y
2Z
2S
3S
E
GND
Pin Assignments
4351
4514
ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LATCH
4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS
WITH LATCHES
VCC
A2
A1
A0
A3
S0
NC
S1
S2
LE
20
19
18
17
16
15
14
13
12
11
INPUTS
1
A4
2
A6
3
NC
4
5
A
A7
COMMON
6
A5
7
E1
8
E2
9
VEE
DATA INPUTS
VCC
G
D
C
Y10
Y11
Y8
Y9
Y14
Y15
Y12
Y13
24
23
22
21
20
19
18
17
16
15
14
13
G
D
C
Y10
Y11
Y8
Y9
Y14
Y15
Y12
A
B
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
1
2
3
4
5
6
7
8
9
10
11
12
LE
A
B
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
GND
Y13
LE
10
GND
NC – No internal connection
See page 520
4352
INPUTS
DATA INPUTS
ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LATCH
VCC
A2
20
19
A
A1 COMMON A0
18
17
16
A3
NC
S0
S1
LE
15
14
13
12
11
See page 524
4515
4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS
WITH LATCHES
INPUTS
1
2
3
B0
B2
NC
5
6
7
8
9
10
B
B3
COMMON
B1
E1
E2
VEE
GND
4
DATA INPUTS
VCC
G
D
C
Y10
Y11
Y8
Y9
Y14
Y15
Y12
Y13
24
23
22
21
20
19
18
17
16
15
14
13
G
D
C
Y10
Y11
Y8
Y9
Y14
Y15
Y12
A
B
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
1
2
3
4
5
6
7
8
9
10
11
12
LE
A
B
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
GND
NC – No internal connection
See page 521
4374
Y13
LE
OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP
WITH 3-STAE OUTPUTS
1D
2D
3D
4D
VCC
5D
6D
7D
8D
CLK
20
19
18
17
16
15
14
13
12
11
DATA INPUTS
INPUTS
See page 526
4518
1
2
3
4
5
6
7
8
9
10
1Q
2Q
3Q
4Q
GND
5Q
6Q
7Q
8Q
OE
DUAL SYNCHRONOUS COUNTERS
See page 522
4511
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS
7-SEGMENT OUTPUTS
VCC
f
g
a
b
c
d
e
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
D1
D2
LT
Bt
LE
D3
D0
GND
BCD INPUTS
See page 523
VCC
2MR
2Q3
2Q2
2Q1
2Q0
2E
2CP
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1CP
1E
1Q0
1Q1
1Q2
1Q3
1MR
GND
BCD INPUTS
See page 528
105
Pin Assignments
4520
5400
DUAL SYNCHRONOUS COUNTERS
11-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
VCC
2MR
2Q3
2Q2
2Q1
2Q0
2E
2CP
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1CP
1E
1Q0
1Q1
1Q2
1Q3
1MR
GND
D1
D2
D3
D4
D5
D6
VCC
VCC
D7
D8
D9
D10
D11
OE2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Y1
Y2
Y3
Y4
Y5
Y6
GND
GND
Y7
Y8
Y9
Y10
Y11
OE1
See page 534
5401
11-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
See page 529
4538
D1
D2
D3
D4
D5
D6
VCC
VCC
D7
D8
D9
D10
D11
OE2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DUAL RETRIGGERABLE
PRECISION MONO STABLE MULTIVIBRATOR
VCC
2CX
2RXCX
1R
1A
1B
1Q
1Q
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Y1
Y2
Y3
Y4
Y5
Y6
GND
GND
Y7
Y8
Y9
Y10
Y11
OE1
See page 534
5402
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
1
2
3
4
5
6
7
8
1CX
1RXCX
1R
1A
1B
1Q
1Q
GND
D1
D2
D3
D4
D5
D6
D7
VCC
D8
D9
D10
D11
D12
OE2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
See page 530
4543
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS
Y1
Y2
Y3
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
OE1
See page 535
7-SEGMENT OUTPUTS
VCC
f
g
e
d
c
b
a
16
15
14
13
12
11
10
9
1
2
DL
D2
3
4
5
6
7
8
D1
D3
D0
PH
B1
GND
BCD INPUTS
See page 532
106
5403
11-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
D1
D2
D3
D4
D5
D6
D7
VCC
D8
D9
D10
D11
D12
OE2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Y1
Y2
Y3
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
OE1
See page 535
Pin Assignments
7001
7046
QUADRUPLE POSITIVE-AND GATES
WITH SCHMITT-TRIGGER INPUTS
PHASE-LOCKED LOOP WITH VCO AND LOCK DETECTOR
positive logic:
Y=A•B
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
VCC
GLD SIGIN PC2OUT
R2
R1 DEMOUT VCOIN
16
15
14
13
12
11
1
2
3
4
5
LD PC1OUT COMPIN VCOOUT INH
See page 536
See page 538
7002
7266
QUADRUPLE POSITIVE-NOR GATES
WITH SCHMITT-TRIGGER INPUTS
QUAD 2-INPUT EXCLUSIVE-NOR GATES
10
9
6
7
8
C1A
C1B
GND
positive logic:
Y=A⊕B
positive logic:
Y=A+B
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
See page 536
VCC
4B
4A
4Y
3Y
3B
3A
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
1Y
2Y
2A
2B
GND
VCC
2B
2A
2Y
8
7
6
5
See page 539
7032
8003
QUADRUPLE POSITIVE-OR GATES
WITH SCHMITT-TRIGGER INPUTS
DUAL 2-INPUT POSITIVE-NAND GATES
positive logic:
Y=A+B
See page 537
VCC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
1A
1B
1Y
GND
See page 539
107
Pin Assignments
16240
16-BIT BUS BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
See page 540
16241
16-BIT BUS BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
See page 541
16244
16-BIT BUS BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
See page 544
16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
See page 546
108
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
Pin Assignments
16260
12-BIT TO 24-BIT MULTIPLEXES D-TYPE LATCH
WITH 3-STATE OUTPUTS
OE2B LEA2B
56
55
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
LEA1B OE1B
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
See page 548
16269
12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
OEB2 CLKENA2 2B4
56
55
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4 CLKENA1 CLK
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
24
25
26
27
28
1B2
GND
1B3
NC
SEL
54
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
OEA
OEB1
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
29
NC – No internal connection
See page 550
16270
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
OEB CLKENA2 2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4 CLKENA1 CLK
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
27
28
OEA CLKEN1B 2B3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3 CLKEN2B SEL
See page 552
16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
OEB CLKENA2 2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4 CLKENA1 CLK
56
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
55
54
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
See page 554
109
Pin Assignments
16282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
VCC
GND
1B10
2B10
1B11
GND
2B11
1B12
2B12
VCC
1B13
2B13
1B14
2B14
GND
1B15
2B15
1B16
2B16
VCC
GND
1B17
2B17
1B18
2B18
VCC
A18
A17
A16
GND
A15
A14
A13
VCC
A12
A11
A10
GND
OE
DIR
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VCC
GND
2B9
1B9
2B8
GND
1B8
2B7
1B7
VCC
2B6
1B6
2B5
1B5
GND
2B4
1B4
2B3
1B3
VCC
GND
2B2
1B2
2B1
1B1
VCC
A1
A2
A3
GND
A4
A5
A6
VCC
A7
A8
A9
GND
CLK
SEL
See page 556
16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
CLK
A1
A2
GND
A3
A4
VCC
A5
A6
GND
A7
A8
A9
A10
GND
A11
A12
VCC
A13
A14
GND
A15
A16
LE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OE
Y1
Y2
GND
Y3
Y4
VCC
Y5
Y6
GND
Y7
Y8
Y9
Y10
GND
Y11
Y12
VCC
Y13
Y14
GND
Y15
Y16
NC
NC – No internal connection
See page 558
16344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
OE4
8B1
8B2
GND
8B3
8B4
VCC
8A
7B1
7B2
GND
7B3
7B4
7A
6A
6B1
6B2
GND
6B3
6B4
5A
VCC
5B1
5B2
GND
5B3
5B4
OE3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OE1
1B1
1B2
GND
1B3
1B4
VCC
1A
2B1
2B2
GND
2B3
2B4
2A
3A
3B1
3B2
GND
3B3
3B4
4A
VCC
4B1
4B2
GND
4B3
4B4
OE2
See page 560
16373
16-BIT TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
See page 562
110
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
Pin Assignments
16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
See page 564
16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
CLK
SELEN
1B1
GND
1B2
1B3
VCC
1B4
1B5
1B6
GND
1B7
1B8
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2B9
SEL4
SEL3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PRE
SEL0
1A1
GND
1A2
1A3
VCC
1A4
1A5
1A6
GND
1A7
1A8
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2A9
SEL1
SEL2
See page 566
16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
OEB1
OEB2
SEL0
GND
1B1
1B2
VCC
1B3
1B4
2B1
GND
2B2
2B3
2B4
3B1
3B2
3B3
GND
3B4
4B1
4B2
VCC
4B3
4B4
GND
SEL1
OEB3
OEB4
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CLKAB GND
1A
2A
3A
4A
GND CLKENAB CLKENB CLKENBA VCC
LEB3
LEB4
GND
OEA
LEAB1 LEAB2 LEBA
4
5
6
7
8
9
GND
LEB1
LEB2
VCC
CLKBA
OEB
CE_SEL0 CE_SEL1
LEAB3 LEAB3
See page 568
16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
1OEBA 1CLKBA 1CLKENBA GND
56
55
54
53
1
2
3
4
1OEAB 1CLKAB 1CLKENAB GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND 2CLKENBA 2CLKBA 2OEBA
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
26
27
28
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND 2CLKENAB 2CLKAB 2OEAB
See page 570
111
Pin Assignments
16500
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
GND CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
56
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
55
CLKBA GND
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
CLKBA GND
See page 572
16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
GND CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
56
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
55
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
See page 574
16524
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
GND
SEL
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLK
GND
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
OEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA CLKENBA
See page 576
16525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SEL
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18 CLK1BA CLK2BA
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1
2
CLKENAB OEAB
See page 578
112
30
29
28
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA CLKENAB
Pin Assignments
16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1OE2
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE1
1Y1
1Y2
GND
1Y3
1Y4
VCC
1Y5
1Y6
GND
1Y7
1Y8
2Y1
2Y2
GND
2Y3
2Y4
VCC
2Y5
2Y6
GND
2Y7
2Y8
2OE1
See page 580
16541
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1OE2
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE1
1Y1
1Y2
GND
1Y3
1Y4
VCC
1Y5
1Y6
GND
1Y7
1Y8
2Y1
2Y2
GND
2Y3
2Y4
VCC
2Y5
2Y6
GND
2Y7
2Y8
2OE1
See page 581
16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
1OEBA 1LEBA 1CEBA GND
56
55
54
53
1
2
3
4
1OEAB 1LEAB 1CEAB GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND 2CEBA 2LEBA 2OEBA
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
26
27
28
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND 2CEAB 2LEAB 2OEAB
See page 582
16600
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
CLKENAB CLKAB
56
55
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
CLKBA CLKENBA
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
See page 584
113
Pin Assignments
16601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
CLKENAB CLKAB
56
55
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
CLKBA CLKENBA
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
See page 586
16620
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
1OEBA
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OEBA
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OEAB
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2OEAB
See page 588
16623
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
1OEBA
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OEBA
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OEAB
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2OEAB
See page 590
16640
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
See page 591
114
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
Pin Assignments
16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
1OE 1CLKBA 1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
1
2
3
1DIR 1CLKAB 1SAB
2SBA 2CLKBA 2OE
31
30
29
26
27
28
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB 2CLKAB 2DIR
2SBA 2CLKBA 2OEBA
See page 592
16651
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
1OEBA 1CLKBA 1SBA
56
55
54
1
2
3
1OEAB 1CLKAB 1SAB
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
26
27
28
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB 2CLKAB 2OEAB
2SBA 2CLKBA 2OEBA
See page 594
16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
1OEBA 1CLKBA 1SBA
56
55
54
1
2
3
1OEAB 1CLKAB 1SAB
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
26
27
28
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB 2CLKAB 2OEBA
2PARITY 2ODD/EVEN 2T/R
See page 596
16657
16-BIT TRANSCEIVERS
WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
1T/R 1ODD/EVEN 1PARITY
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
56
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
55
54
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1OE
NC
1ERR
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2ERR
NC
2OE
NC – No internal connection
See page 598
115
Pin Assignments
16721
20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
CLK
D1
D2
GND
D3
D4
VCC
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
GND
D14
D15
D16
VCC
D17
D18
GND
D19
D20
CLKEN
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OE
Q1
Q2
GND
Q3
Q4
VCC
Q5
Q6
Q7
GND
Q8
Q9
Q10
Q11
Q12
Q13
GND
Q14
Q15
Q16
VCC
Q17
Q18
GND
Q19
Q20
NC
NC – No internal connection
See page 600
16722
22-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
CLK
D1
D2
GND
D3
D4
VCC
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
GND
D14
D15
D16
VCC
D17
D18
GND
D19
D20
VCC
D21
D22
GND
CLKEN
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OE
Q1
Q2
GND
Q3
Q4
VCC
Q5
Q6
Q7
GND
Q8
Q9
Q10
Q11
Q12
Q13
GND
Q14
Q15
Q16
VCC
Q17
Q18
GND
Q19
Q20
VCC
Q21
Q22
GND
NC
NC – No internal connection
See page 601
16820
10-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH DUAL OUTPUTS
CLK
D1
NC
GND
D2
NC
VCC
D3
NC
D4
GND
NC
D5
NC
D6
NC
D7
GND
NC
D8
NC
VCC
D9
NC
GND
D10
NC
NC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1OE
1Q1
1Q2
GND
2Q1
2Q2
VCC
3Q1
3Q2
4Q1
GND
4Q2
5Q1
5Q2
6Q1
6Q2
7Q1
GND
7Q2
8Q1
8Q2
VCC
9Q1
9Q2
GND
10Q1
10Q2
2OE
NC – No internal connection
See page 602
16821
20-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2CLK
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
See page 603
116
Pin Assignments
16823
18-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH DUAL OUTPUTS
1CLK 1CLKEN 1D1
GND
1D2
1D3
VCC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9 2CLKEN 2CLK
56
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
55
54
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1CLR
1OE
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2OE
2CLR
See page 604
16825
18-BIT BUS BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1OE2
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
VCC
2A6
2A7
GNA
2A8
2A9
2OE2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1OE1
1Y1
1Y2
GNA
1Y3
1Y4
VCC
1Y5
1Y6
1Y7
GNA
1Y8
1Y9
GND
GND
2Y1
2Y2
GNA
2Y3
2Y4
2Y5
VCC
2Y6
2Y7
GNA
2Y8
2Y9
2OE1
See page 605
16827
20-BIT BUS BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1OE2
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GNA
2A9
2A10
2OE2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1OE1
1Y1
1Y2
GNA
1Y3
1Y4
VCC
1Y5
1Y6
1Y7
GNA
1Y8
1Y9
1Y10
2Y1
2Y2
2Y3
GNA
2Y4
2Y5
2Y6
VCC
2Y7
2Y8
GNA
2Y9
2Y10
2OE1
See page 606
16831
1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
1Y2
2Y2
GND
3Y2
4Y2
VCC
1Y3
2Y3
GND
3Y3
4Y3
GND
1Y4
2Y4
VCC
3Y4
4Y4
GND
1Y5
2Y5
3Y5
4Y5
GND
1Y6
2Y6
VCC
3Y6
4Y6
GND
1Y7
2Y7
GND
3Y7
4Y7
VCC
1Y8
2Y8
GND
3Y8
4Y8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
34
35
36
37
38
39
40
NC
VCC
4Y9
3Y9
GND
2Y9
1Y9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
4Y1
3Y1
GND
2Y1
1Y1
VCC
NC
A1
GND
NC
A2
GND
NC
A3
VCC
NC
A4
GND
CLK
OE1
OE2
SEL
GND
A5
A6
VCC
A7
NC
GND
A8
NC
GND
A9
NC – No internal connection
See page 607
117
Pin Assignments
16832
1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
1Y2
2Y2
GND
3Y2
4Y2
VCC
1Y3
2Y3
GND
3Y3
4Y3
GND
VCC
GND
1Y4
2Y4
3Y4
4Y4
GND
1Y5
2Y5
VCC
3Y5
4Y5
GND
GND
VCC
1Y6
2Y6
GND
3Y6
4Y6
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
4Y1
3Y1
GND
2Y1
1Y1
VCC
A1
GND
A2
GND
A3
VCC
NC
GND
CLK
OE1
OE2
SEL
GND
A4
A5
VCC
GND
A6
GND
A7
VCC
4Y7
3Y7
GND
2Y7
1Y7
NC – No internal connection
See page 608
16833
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
1OEA
56
1CLR 1PARITY GND
55
54
53
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND 2PARITY 2CLR
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
2OEA
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1OEB
1CLK
1ERR
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2ERR
2CLK
2OEB
See page 610
16834
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
NC – No internal connection
See page 612
16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
NC – No internal connection
See page 613
118
Pin Assignments
16841
20-BIT BUS INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2LE
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
See page 614
16843
18-BIT BUS INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
1LE
1PRE
1D1
GND
1D2
1D3
VCC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2PRE
2LE
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1CLR
1OE
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2OE
2CLR
See page 615
16853
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
1LE
1PRE
1D1
GND
1D2
1D3
VCC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2PRE
2LE
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1CLR
1OE
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2OE
2CLR
See page 616
16861
20-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
1OEBA
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GNA
2A9
2A10 2OEBA
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1OEAB
1B1
1B2
GNA
1B3
1B4
VCC
1B5
1B6
1B7
GNA
1B8
1B9
1B10
2B1
2B2
2B3
GNA
2B4
2B5
2B6
VCC
2B7
2B8
GNA
2B9
2B10 2OEAB
See page 618
119
Pin Assignments
16863
18-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
1OEBA
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
VCC
2A6
2A7
GNA
2A8
2A9
2OEBA
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1OEAB
1B1
1B2
GNA
1B3
1B4
VCC
1B5
1B6
1B7
GNA
1B8
1B9
GND
GND
2B1
2B2
GNA
2B3
2B4
2B5
VCC
2B6
2B7
GNA
2B8
2B9
2OEAB
See page 619
16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
1CLKENBA LEBA CLKBA 1ERRB 1BPAR GND
64
63
62
61
60
59
1
2
3
4
5
6
1CLKENAB LEAB CLKAB 1ERRA 1APAR GND
1B1
1B2
1B3
VCC
1B4
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
2B5
VCC
2B6
2B7
2B8
GND 2BPAR 2ERRB OEBA ODD/EVEN 2CLKENBA
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
28
29
30
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1A1
1A2
1A3
VCC
1A4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
2A5
VCC
2B6
2A7
2B8
GND 2APAR 2ERRA OEAB
34
33
31
32
SEL 2CLKENAB
See page 620
16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
CLK
1A 11A/YERREN GND 11Y1
11Y2
VCC
2A
3A
4A
GND
12A
12Y1
12Y2
5A
6A
7A
GND
APAR
8A
YERR
VCC
9A
MODE
GND
10A
56
55
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
54
53
52
PARI/O CLKEN
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
OE
1Y1
1Y2
GND
2Y1
2Y2
VCC
3Y1
3Y2
4Y1
GND
4Y2
5Y1
5Y2
6Y1
6Y2
7Y1
GND
7Y2
8Y1
8Y2
VCC
9Y1
9Y2
GND
10Y1
10Y2 PAROE
See page 622
16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
1OEBA 1CLKBA 1CLKENBA GND
56
55
54
53
1
2
3
4
1OEAB 1CLKAB 1CLKENAB GND
See page 624
120
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND 2CLKENBA 2CLKBA 2OEBA
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
26
27
28
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND 2CLKENAB 2CLKAB 2OEAB
Pin Assignments
25244
29825
25-Ω OCTAL BUS BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
8-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
1OE
1A1
1A2
VCC
1A3
1A4
2A1
2A2
VCC
2A3
2A4
2OE
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
PRE
C
24
23
22
21
20
19
18
17
16
15
14
13
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
1Y1
GND
1Y2
1Y3
GND
1Y4
2Y1
GND
2Y2
2Y3
GND
2Y4
OC
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
See page 626
See page 630
25245
29827
29828
25-Ω OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
CLK
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
See page 627
10-BIT BUFFERS AND BUS DRIVERS
WITH 3-STATE OUTPUTS
VCC
OE3
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLKEN
CLK
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
OE1
OE2
1D
2D
3D
4D
5D
6D
7D
8D
CLR
GND
See page 631, 632
25642
29841
25-Ω OCTAL BUS TRANSCEIVER
10-BIT BUS INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
DIR
B1
B2
VCC
B3
B4
B5
B6
VCC
B7
B8
OE
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
A1
GND
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
VCC
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
OE2
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
OE1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
See page 628
See page 633
29821
29843
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
9-BIT BUS INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
DIR
B1
B2
VCC
B3
B4
B5
B6
VCC
B7
B8
OE
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
LE
24
23
22
21
20
19
18
17
16
15
14
13
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
A1
GND
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
See page 629
See page 634
121
Pin Assignments
29854
29864
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
9-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
VCC
B1
B2
B3
B4
B5
B6
B7
B8
24
23
22
21
20
19
18
17
16
PARITY OEB
15
14
LE
VCC
B1
B2
B3
B4
B5
B6
B7
B8
B9
13
24
23
22
21
20
19
18
17
16
15
OEAB2 OEAB1
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
OEA
A1
A2
A3
A4
A5
A6
A7
A8
ERR
CLR
GND
OEAB1
A1
A2
A3
A4
A5
A6
A7
A8
A9
See page 636
14
13
11
12
OEAB2 GND
See page 639
29863
9-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
VCC
B1
B2
B3
B4
B5
B6
B7
B8
B9
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
OEAB1
A1
A2
A3
A4
A5
A6
A7
A8
A9
OEAB2 OEAB1
14
13
11
12
OEAB2 GND
See page 638
32240
32-BIT BUFFER/DRIVER
GKE PACKAGE
(TOP VIEW)
1
3
4
5
6
terminal assignments
1
2
3
4
5
6
A
A
1Y2
1Y1
1OE
2OE
1A1
1A2
B
B
1Y4
1Y3
GND
GND
1A3
1A4
C
C
2Y2
2Y1
1VCC
1VCC
2A1
2A2
D
D
2Y2
2Y3
GND
GND
2A3
2A4
E
3Y2
3Y1
GND
GND
3A1
3A2
F
3Y4
3Y3
3A4
4Y2
4Y1
1VCC
GND
3A3
G
1VCC
GND
4A1
4A2
H
4Y3
4Y4
4OE
3OE
4A4
4A3
J
5Y2
5Y1
5OE
6OE
5A1
5A2
E
F
G
H
J
K
5Y4
5Y3
GND
GND
5A3
5A4
K
L
6Y2
6Y1
6Y4
6Y3
2VCC
GND
6A2
M
2VCC
GND
6A1
L
6A3
6A4
M
N
7Y2
7Y1
GND
GND
7A1
7A2
N
P
7Y4
7Y3
7A4
R
8Y2
8Y1
2VCC
GND
7A3
P
2VCC
GND
8A1
8A2
R
T
8Y3
8Y4
8OE
7OE
8A4
8A3
T
See page 640
122
2
Pin Assignments
32244
36-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
GKE PACKAGE
(TOP VIEW)
6
5
4
3
2
1
A B C D E
F G H
J
K
L M N P R T
6
1A2
1A4
2A2
2A4
3A2
3A4
4A2
4A3
5A2
5A4
6A2
6A4
7A2
7A4
8A2
5
1A1
1A3
2A1
2A3
3A1
3A3
4A1
4A4
5A1
5A3
6A1
6A3
7A1
7A3
8A1
8A4
4
2OE
GND
VCC
GND
GND
VCC
GND
3OE
6OE
GND
VCC
GND
GND
VCC
GND
7OE
3
1OE
GND
VCC
GND
GND
VCC
GND
4OE
5DIR
GND
VCC
GND
GND
VCC
GND
8DIR
2
1Y1
1Y3
2Y1
2Y3
3Y1
3Y3
4Y1
4Y4
5Y1
5Y3
6Y1
6Y3
7Y1
7Y3
8Y1
8Y4
1
1Y2
1Y4
2Y2
2Y4
3Y2
3Y4
4Y2
4Y3
5Y2
5Y4
6Y2
6Y4
7Y2
7Y4
8Y2
8Y3
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
8A3
See page 642
123
Pin Assignments
32245
36-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
1A7
1A6
GND
1A5
1A4
1A3
1A2
1A1
GND
1DIR
1OE
VCC
2OE
2DIR
GND
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
100 99
1A8
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1A9
1
75
1B9
2A1
2
74
2A1
GND
3
73
GND
2A2
4
72
2B2
2A3
5
71
2A3
2A4
6
70
2A4
2A5
7
69
2A5
GND
8
68
GND
2A6
9
67
2A6
2A7
10
66
2A7
2A8
11
65
2B8
2A9
12
64
2B9
VCC
13
63
VCC
3A1
14
62
3B1
3A2
15
61
3B2
3A3
16
60
3B3
3A4
17
59
3B4
GND
18
58
GND
3A5
19
57
3B5
3A6
20
56
3B6
3A7
21
55
3B7
3A8
22
54
3B8
GND
23
53
GND
3A9
24
52
3B9
4A1
25
51
4B1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
4A2
4A3
4A4
GND
4A5
4A6
4A7
4A8
4A9
GND
4DIR
4OE
VCC
3OE
3DIR
GND
4B9
4B8
4B7
4B6
4B5
GND
4B4
4B3
4B2
See page 644
32245
36-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
GKE PACKAGE
(TOP VIEW)
6
5
4
3
2
1
A B C D E
J
K
L M N P R T
1A2
1A4
1A6
1A8
2A2
2A4
2A6
2A7
3A2
3A4
3A6
3A8
4A2
4A4
4A6
5
1A1
1A3
1A5
1A7
2A1
2A3
2A5
2A8
3A1
3A3
3A5
3A7
4A1
4A3
4A5
4A8
4
1OE
GND
VCC
GND
GND
VCC
GND
2OE
3OE
GND
VCC
GND
GND
VCC
GND
4OE
3
1DIR
GND
VCC
GND
GND
VCC
GND
2DIR
3DIR
GND
VCC
GND
GND
VCC
GND
4DIR
2
1B1
1B3
1B5
1B7
2B1
2B3
2B5
2B8
3B1
3B3
3B5
3B7
4B1
4B3
4B5
4B8
1
1B2
1B4
1B6
1B8
2B2
2B4
2B6
2B7
3B2
3B4
3B6
3B8
4B2
4B4
4B6
4B7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
See page 644
124
F G H
6
4A7
Pin Assignments
32316
16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
A1
SELA
OEA
OEC
SELC
LEC
80
79
78
77
76
75
CLKC CLKENC
74
73
NC
VCC
GND
C16
C15
C14
C13
C12
GND
C11
C10
C9
72
71
70
69
68
67
66
65
64
63
62
61
A2
1
60
C8
A3
2
59
C7
A4
3
58
C6
GND
4
57
GND
A5
5
56
C5
A6
6
55
C4
A7
7
54
C3
A8
8
53
C2
A9
9
52
C1
VCC
10
51
VCC
GND
11
50
GND
A10
12
49
B16
A11
13
48
B15
A12
14
47
B14
A13
15
46
B13
A14
16
45
B12
GND
17
44
GND
A15
18
43
B11
A16
19
42
B10
NC
20
41
B9
21
22
CLKENA CLKA
23
24
25
26
LEA
OEB
SELB
LEB
27
28
CLKB CLKENB
29
30
31
32
33
34
35
36
37
38
39
40
NC
VCC
GND
B1
B2
B3
B4
B5
GND
B6
B7
B8
NC – No internal connection
See page 646
32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
A1
SELA
OEA
OEC
SELC
LEC
CLKC
C18
C17
VCC
GND
C16
C15
C14
C13
C12
GND
C11
C10
C9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
A2
1
60
C8
A3
2
59
C7
A4
3
58
C6
GND
4
57
GND
A5
5
56
C5
A6
6
55
C4
A7
7
54
C3
A8
8
53
C2
A9
9
52
C1
VCC
10
51
VCC
GND
11
50
GND
A10
12
49
B18
A11
13
48
B17
A12
14
47
B16
A13
15
46
B15
A14
16
45
B14
GND
17
44
GND
A15
18
43
B13
A16
19
42
B12
A17
20
41
B11
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A18
CLKA
LEA
OEB
SELB
LEB
CLKB
B1
B2
VCC
GND
B3
B4
B5
B6
B7
GND
B8
B9
B10
See page 648
125
Pin Assignments
32373
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
GKE PACKAGE
(TOP VIEW)
6
5
4
3
2
1
A B C D E
F G H
J
K
L M N P R T
6
1D2
1D4
1D6
2D2
2D4
2D6
2D7
3D2
3D4
3D6
4D2
4D4
5
1D1
1D3
1D5
1D7
2D1
2D3
2D5
2D8
3D1
3D3
3D5
3D7
4D1
4D3
4D5
4
1LE
GND
VCC
GND
GND
VCC
GND
2LE
3LE
GND
VCC
GND
GND
VCC
GND
4LE
3
1OE
GND
VCC
GND
GND
VCC
GND
2OE
3OE
GND
VCC
GND
GND
VCC
GND
4OE
2
1Q1
1Q3
1Q5
1Q7
2Q1
2Q3
2Q5
2Q8
3Q1
3Q3
3Q5
3Q7
4Q1
4Q3
4Q5
4Q8
1
1Q2
1Q4
1Q6
1Q8
2Q2
2Q4
2Q6
2Q7
3Q2
3Q4
3Q6
3Q8
4Q2
4Q4
4Q6
4Q7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1D8
3D8
4D6
See page 650
32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
GKE PACKAGE
(TOP VIEW)
1
A
B
4
5
6
terminal assignments
1
2
3
4
5
6
A
1Q2
1Q1
1OE
1CLK
1D1
1D2
1D4
B
1Q4
1Q3
GND
GND
1D3
1Q6
1Q5
VCC
VCC
1D5
1D6
D
1Q8
1Q7
GND
GND
1D7
1D8
E
2Q2
2Q1
GND
GND
2D1
2D2
F
2Q4
2Q3
VCC
VCC
2D3
2D4
G
2Q6
2Q5
GND
GND
2D5
2D6
H
2Q8
2Q7
2OE
2CLK
2D7
2D8
J
3Q2
3Q1
3OE
3CLK
3D1
3D2
K
K
3Q4
3Q3
GND
GND
3D3
3D4
L
L
3Q6
3Q5
VCC
VCC
3D5
3D6
M
M
3Q8
3Q7
GND
GND
3D7
3D8
N
N
4Q2
4Q1
GND
GND
4D1
4D2
4D4
D
E
F
G
H
J
126
3
C
C
See page 652
2
P
P
4Q4
4Q3
VCC
VCC
4D3
R
R
4Q6
4Q5
GND
GND
4D5
4D6
T
T
4Q7
4Q8
4OE
4CLK
4D8
4D7
4D7
4D8
Pin Assignments
32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
2A11
2A12
2A13
GND
2A14
2A15
2A16
2A17
2A18 2OEBA 2LEBA 2CLKBA VCC 2CLKAB 2LEAB 2OEAB 2B18
2B17
2B16
2B15
2B14
GND
2B13
2B12
2B11
100 99
98
97
96
95
94
93
92
83
82
81
80
79
78
77
76
91
90
89
88
87
86
85
84
2A10
1
75
2B10
2A9
2
74
2A9
GND
3
73
GND
2A8
4
72
2B8
2A7
5
71
2A7
2A6
6
70
2A6
2A5
7
69
2A5
GND
8
68
GND
2A4
9
67
2A4
2A3
10
66
2A3
2A2
11
65
2B2
2A1
12
64
2B1
VCC
13
63
VCC
1A1
14
62
1B1
1A2
15
61
1B2
1A3
16
60
1B3
1A4
17
59
1B4
GND
18
58
GND
1A5
19
57
1B5
1A6
20
56
1B6
1A7
21
55
1B7
1A8
22
54
1B8
GND
23
53
GND
1A9
24
52
1B9
1A10
25
51
1B10
26
27
28
29
30
31
32
33
34
42
43
44
45
46
47
48
49
50
1A11
1A12
1A13
GND
1A14
1A15
1A16
1A17
1A18 1OEBA 1LEBA 1CLKBA VCC 1CLKAB 1LEAB 1OEAB 1B18
35
36
37
38
39
40
41
1B17
1B16
1B15
1B14
GND
1B13
1B12
1B11
See page 654
32543
36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
1A8
See page 656
1A7
1A6
GND
1A5
1A4
1A3
1A2
1A1
100 99
98
97
96
95
94
93
92
1CEBA 1OEBA 1LEBA
91
90
89
VCC
88
1LEAB 1OEAB 1CEAB
87
86
85
1B1
1B1
1B3
1B4
1B5
GND
1B6
1B7
1B8
84
83
82
81
80
79
78
77
76
1A9
1
75
1B9
1A10
2
74
1B10
GND
3
73
GND
1A11
4
71
1B11
1A12
5
72
1B12
1A13
6
70
1B13
1A14
7
69
1B14
GND
8
68
GND
1A15
9
67
1B15
1A16
10
66
1B16
1A17
11
65
1B17
1A18
12
64
1B18
VCC
13
63
VCC
2A1
14
62
2B1
2A2
15
61
2B2
2A3
16
60
2B3
2A4
17
59
2B4
GND
18
58
GND
2A5
19
57
2B5
2A6
20
56
2B6
2A7
21
55
2B7
2A8
22
54
2B8
GND
23
53
GND
2A9
24
52
2B9
2A10
25
51
2B10
26
27
28
29
30
31
32
33
34
2A11
2A12
2A13
GND
2A14
2A15
2A16
2A17
2A18 2CEBA 2OEBA 2LEBA
35
36
37
38
VCC
42
43
44
45
46
47
48
49
50
2LEAB 2OEAB 2CEAB 2B18
39
40
41
2B17
2B16
2B15
GND
2B14
2B13
2B12
2B11
127
Pin Assignments
40103
8-STAGE SYNCHRONOUS DOWN COUNTERS
VCC
PE
(SYNC)
TC
P7
P6
P5
P4
PL
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
CP
MR
TE
P0
P1
P2
P3
GND
See page 658
162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
See page 659
162241
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
See page 660
162244
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
See page 661
128
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
Pin Assignments
162245
16-BIT TRANSCEIVER
WITH 3-STATE OUTPUTS
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
See page 662
162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
OE2B LEA2B
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
56
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
55
LEA1B OE1B
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
See page 664
162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
OEB CLKENA2 2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4 CLKENA1 CLK
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
27
28
OEA CLKEN1B 2B3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3 CLKEN2B SEL
See page 666
162280
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
WITH BYTE MASKS AND 3-STATE OUTPUTS
VCC
GND
1B8
2B8
1B9
GND
2B9
1B10
2B10
VCC
1B11
2B11
1B12
2B12
GND
1B13
2B13
1B14
2B14
VCC
GND
1B15
2B15
1B16
2B16
VCC
A16
A15
A14
GND
A13
A12
A11
VCC
A10
A9
A8
GND
OE
DIR
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VCC
GND
2B7
1B7
2B6
GND
1B6
2B5
1B5
VCC
2B4
1B4
2B3
1B3
GND
2B2
1B2
2B1
1B1
VCC
GND
2D2
1D2
2D1
1D1
VCC
C1
C2
A1
GND
A2
A3
A4
VCC
A5
A6
A7
GND
CLK
SEL
See page 668
129
Pin Assignments
162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
VCC
GND
1B10
2B10
1B11
GND
2B11
1B12
2B12
VCC
1B13
2B13
1B14
2B14
GND
1B15
2B15
1B16
2B16
VCC
GND
1B17
2B17
1B18
2B18
VCC
A18
A17
A16
GND
A15
A14
A13
VCC
A12
A11
A10
GND
OE
DIR
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VCC
GND
2B9
1B9
2B8
GND
1B8
2B7
1B7
VCC
2B6
1B6
2B5
1B5
GND
2B4
1B4
2B3
1B3
VCC
GND
2B2
1B2
2B1
1B1
VCC
A1
A2
A3
GND
A4
A5
A6
VCC
A7
A8
A9
GND
CLK
SEL
See page 670
162334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
CLK
A1
A2
GND
A3
A4
VCC
A5
A6
GND
A7
A8
A9
A10
GND
A11
A12
VCC
A13
A14
GND
A15
A16
LE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OE
Y1
Y2
GND
Y3
Y4
VCC
Y5
Y6
GND
Y7
Y8
Y9
Y10
GND
Y11
Y12
VCC
Y13
Y14
GND
Y15
Y16
NC
NC – No internal connection
See page 672
162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
OE4
8B1
8B2
GND
8B3
8B4
VCC
8A
7B1
7B2
GND
7B3
7B4
7A
6A
6B1
6B2
GND
6B3
6B4
5A
VCC
5B1
5B2
GND
5B3
5B4
OE3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OE1
1B1
1B2
GND
1B3
1B4
VCC
1A
2B1
2B2
GND
2B3
3B4
2A
3A
3B1
3B2
GND
3B3
3B4
4A
VCC
4B1
4B2
GND
4B3
4B4
OE2
See page 674
162373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
See page 676
130
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
Pin Assignments
162374
3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
See page 677
162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
OEB1
OEB2
SEL0
GND
1B1
1B2
VCC
1B3
1B4
2B1
GND
2B2
2B3
2B4
3B1
3B2
3B3
GND
3B4
4B1
4B2
VCC
4B3
4B4
GND
SEL1
OEB3
OEB4
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CLKAB GND
1A
2A
3A
4A
GND CLKENAB CLKENB CLKENBA VCC
LEB3
LEB4
GND
OEA
LEAB3 LEAB3
CLKBA GND
LEAB1 LEAB2 LEBA
4
5
6
7
8
9
GND
LEB1
LEB2
VCC
CLKBA
OEB
CE_SEL0 CE_SEL1
See page 678
162500
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
GND CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
56
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
55
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
See page 680
162501
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
GND CLKAB
56
55
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
CLKBA GND
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
See page 682
131
Pin Assignments
162525
16-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SEL
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18 CLK1BA CLK2BA
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1
2
CLKENAB OEAB
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
30
29
27
28
OEBA CLKENBA
See page 684
162541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1OE2
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE1
1Y1
1Y2
GND
1Y3
1Y4
VCC
1Y5
1Y6
GND
1Y7
1Y8
2Y1
2Y2
GND
2Y3
2Y4
VCC
2Y5
2Y6
GND
2Y7
2Y8
2OE1
See page 686
162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
CLKENAB CLKAB
56
55
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
CLKBA CLKENBA
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
See page 688
162721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
CLK
D1
D2
GND
D3
D4
VCC
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
GND
D14
D15
D16
VCC
D17
D18
GND
D19
D20
CLKEN
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OE
Q1
Q2
GND
Q3
Q4
VCC
Q5
Q6
Q7
GND
Q8
Q9
Q10
Q11
Q12
Q13
GND
Q14
Q15
Q16
VCC
Q17
Q18
GND
Q19
Q20
NC
NC – No internal connection
See page 690
132
Pin Assignments
162820
3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS
AND 3-STATE OUTPUTS
CLK
D1
NC
GND
D2
NC
VCC
D3
NC
D4
GND
NC
D5
NC
D6
NC
D7
GND
NC
D8
NC
VCC
D9
NC
GND
D10
NC
NC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1OE
1Q1
1Q2
GND
2Q1
2Q2
VCC
3Q1
3Q2
4Q1
GND
4Q2
5Q1
5Q2
6Q1
6Q2
7Q1
GND
7Q2
8Q1
8Q2
VCC
9Q1
9Q2
GND
10Q1
10Q2
2OE
NC – No internal connection
See page 691
162823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
1CLK 1CLKEN 1D1
GND
1D2
1D3
VCC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9 2CLKEN 2CLK
56
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
55
54
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1CLR
1OE
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2OE
2CLR
See page 692
162825
18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
1OE2
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
VCC
2A6
2A7
GND
2A8
2A9
2OE2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1OE1
1Y1
1Y2
GND
1Y3
1Y4
VCC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
GND
GND
2Y1
2Y2
GND
2Y3
2Y4
2Y5
VCC
2Y6
2Y7
GND
2Y8
2Y9
2OE1
See page 693
162827
20-BIT BUS BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1OE2
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GNA
2A9
2A10
2OE2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1OE1
1Y1
1Y2
GNA
1Y3
1Y4
VCC
1Y5
1Y6
1Y7
GNA
1Y8
1Y9
1Y10
2Y1
2Y2
2Y3
GNA
2Y4
2Y5
2Y6
VCC
2Y7
2Y8
GNA
2Y9
2Y10
2OE1
See page 694
133
Pin Assignments
162830
1-BIT to 2-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
1Y3
2Y3
GND
1Y4
2Y4
VCC
1Y5
2Y5
GND
1Y6
2Y6
GND
1Y7
2Y7
VCC
1Y8
2Y8
GND
1Y9
2Y9
1Y10
2Y10
GND
1Y11
2Y11
VCC
1Y12
2Y12
GND
1Y13
2Y13
GND
1Y14
2Y14
VCC
1Y15
2Y15
GND
1Y16
2Y16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
2Y2
1Y2
GND
2Y1
1Y1
VCC
A1
A2
GND
A3
A4
GND
A5
A6
VCC
A7
A8
GND
A9
OE1
OE2
A10
GND
A11
A12
VCC
A13
A14
GND
A15
A16
GND
A17
A18
VCC
2Y18
1Y18
GND
2Y17
1Y17
See page 695
162831
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
1Y2
2Y2
GND
3Y2
4Y2
VCC
1Y3
2Y3
GND
3Y3
4Y3
GND
1Y4
2Y4
VCC
3Y4
4Y4
GND
1Y5
2Y5
3Y5
4Y5
GND
1Y6
2Y6
VCC
3Y6
4Y6
GND
1Y7
2Y7
GND
3Y7
4Y7
VCC
1Y8
2Y8
GND
3Y8
4Y8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
4Y1
3Y1
GND
2Y1
1Y1
VCC
NC
A1
GND
NC
A2
GND
NC
A3
VCC
NC
A4
GND
CLK
OE1
OE2
SEL
GND
A5
A6
VCC
A7
NC
GND
A8
NC
GND
A9
NC
VCC
4Y9
3Y9
GND
2Y9
1Y9
NC – No internal connection
See page 696
162832
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
1Y2
2Y2
GND
3Y2
4Y2
VCC
1Y3
2Y3
GND
3Y3
4Y3
GND
VCC
GND
1Y4
2Y4
3Y4
4Y4
GND
1Y5
2Y5
VCC
3Y5
4Y5
GND
GND
VCC
1Y6
2Y6
GND
3Y6
4Y6
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
4Y1
3Y1
GND
2Y1
1Y1
VCC
A1
GND
A2
GND
A3
VCC
NC
GND
CLK
OE1
OE2
SEL
GND
A4
A5
VCC
GND
A6
GND
A7
VCC
4Y7
3Y7
GND
2Y7
1Y7
See page 697
162834
162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
NC – No internal connection
See page 698, 699
134
Pin Assignments
162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
CLK
A1
A2
GND
A3
A4
VCC
A5
A6
A7
GND
A8
A9
A10
A11
A12
A13
GND
A14
A15
A16
VCC
A17
A18
GND
A19
A20
LE
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OE
Y1
Y2
GND
Y3
Y4
VCC
Y5
Y6
Y7
GND
Y8
Y9
Y10
Y11
Y12
Y13
GND
Y14
Y15
Y16
VCC
Y17
Y18
GND
Y19
Y20
NC
NC – No internal connection
See page 700
162841
20-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2LE
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
See page 701
164245
16-BIT TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
WITH 3-STATE OUTPUTS
1OE
1A1
1A2
GND
1A3
1A4 (3.3V)VCCA 1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4 (3.3V)VCCA 2A5
2A6
GND
2A7
2A8
2OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
6
7
8
18
1
2
3
4
5
1DIR
1B1
1B2
GND
1B3
1B4 (5V)VCCB 1B5
9
10
11
12
13
14
15
16
17
19
20
21
22
23
24
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4 (5V)VCCB 2B5
2B6
GND
2B7
2B8
2DIR
See page 702
135
Pin Assignments
322374
3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
GKE PACKAGE
(TOP VIEW)
1
3
4
5
6
terminal assignments
1
2
3
4
5
6
A
1Q2
1Q1
1OE
1CLK
1D1
1D2
B
B
1Q4
1Q3
GND
GND
1D3
1D4
C
C
1Q6
1Q5
1D6
D
1Q8
1Q7
VCC
GND
1D5
D
VCC
GND
1D7
1D8
E
E
2Q2
2Q1
GND
GND
2D1
2D2
F
F
2Q4
2Q3
VCC
VCC
2D3
2D4
G
G
2Q6
2Q6
GND
GND
2D5
2D6
H
H
2Q7
2Q8
2OE
2CLK
2D8
2D7
A
J
K
L
M
N
P
R
T
See page 703
136
2
J
3Q2
3Q1
3OE
3CLK
3D1
3D2
K
3Q4
3Q3
GND
GND
3D3
3D4
L
3Q6
3Q5
VCC
VCC
3D5
3D6
M
3Q8
3Q7
GND
GND
3D7
3D8
N
4Q2
4Q1
GND
GND
4D1
4D2
P
4Q4
4Q3
VCC
VCC
4D3
4D4
R
4Q6
4Q5
GND
GND
4D5
4D6
T
4Q7
4Q8
4OE
4CLK
4D8
4D7
NC – No internal connection
FUNCTION
AND
ELECTRICAL
CHARACTERISTICS
Logic Diagram
00
QUADRUPLE 2-INPUT
POSITIVE-NAND GATES
A
Y
B
● Y = A•B
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 SN74 CD74
HC
HC HCT HCT
AC
11
10.2
0.02
0.04
0.02
0.04
0.04
0.02
0.08
0.04
mA
-2
20
-1
20
-4
4
-4
4
-4
4
-4
4
-24
24
-24
24
-24
24
-24
24
mA
mA
LV
3V
LV
5V
-6
6
0.02
-12
12
MAX or MIN
TTL
LS
S
ALS
AS
F
ICC
MAX
22
4.4
36
3
17.4
IOH
IOL
MAX
MAX
-0.4
16
-0.4
8
-1
20
-0.4
8
PARAMETER
ICC
IOH
IOL
MAX or MIN
SN74 CD74 AHC AHCT
ACT ACT
MAX
MAX
MAX
0.02
-24
24
0.08
-24
24
0.02
-8
8
0.02
-8
8
SN74 CD74 ACT
AC
AC
11
UNIT
LVC ALVC UNIT
3V
3V
0.01
-24
24
0.01
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT
tPLH
tPHL
A or B
A or B
PARAMETER INPUT
tPLH
tPHL
UNIT:ns
A or B
A or B
SN74 CD74 SN74 CD74
HC
HC HCT HCT
OUTPUT
MAX or MIN
TTL
LS
S
ALS
AS
F
Y
Y
MAX
MAX
22
15
15
15
4.5
5
11
8
4.5
4
6
5.3
OUTPUT
MAX or MIN
LV
3V
LV
5V
LVC ALVC
3V
3V
Y
Y
MAX
MAX
13
13
8.5
8.5
4.3
4.3
SN74 CD74 AHC AHCT
ACT ACT
9.5
8
10.8
13.2
8.5
8.5
9
9
23
23
27
27
25
25
30
30
AC
11
7.4
6.8
SN74 CD74 ACT
AC
AC
11
8.5
7
7.3
7.3
12.3
8.8
3
3
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
139
Logic Diagram
01
QUADRUPLE 2-INPUT
POSITIVE-NAND GATES
WITH OPEN-COLLECTOR
OUTPUTS
1A
1B
1Y
2A
2B
● Y = A•B
3A
3B
2Y
3Y
4A
4B
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
VOH
IOL
MAX or MIN
TTL
LS
ALS
HC
UNIT
MAX
MAX
MAX
22
5.5
16
4.4
5.5
8
3
5.5
8
0.02
VCC
4
mA
V
mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT
tPLH
tPHL
UNIT:ns
140
A or B
A or B
OUTPUT
MAX or MIN
TTL
LS
ALS
HC
Y
Y
MAX
MAX
55
15
32
28
54
28
31
25
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4Y
Logic Diagram
02
QUADRUPLE 2-INPUT
POSITIVE-NOR GATES
A
Y
B
● Y=A+B
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
PARAMETER
MAX or MIN
TTL
LS
S
ALS
AS
F
SN74 CD74 SN74 CD74
HC
HC HCT HCT
AC
11
CD74 ACT
AC
11
MAX
MAX
MAX
27
-0.4
16
5.4
-0.4
8
45
-1
20
4
-0.4
8
20.1
-2
20
13
-1
20
0.02
-4
4
0.04
-24
24
0.08
-24
24
CD74
AHC AHCT
ACT
LV
3V
LV
5V
LVC
3V
UNIT
MAX or MIN
ICC
IOH
MAX
MAX
0.08
-24
0.02
-8
0.02
-8
-6
0.02
-12
0.01
-24
mA
mA
IOL
MAX
24
8
8
6
12
24
mA
0.04
-4
4
0.02
-4
4
0.04
-4
4
UNIT
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
F
CD74 ACT
AC
11
OUTPUT
MAX or MIN
TTL
LS
S
tPLH
A or B
Y
MAX
22
15
5.5
12
4.5
6.5
23
27
25
32
6.9
11.5
10.6
tPHL
A or B
Y
MAX
15
15
5.5
10
4.5
5.3
23
27
25
32
6.4
11.5
8.7
PARAMETER
INPUT
OUTPUT
MAX or MIN
CD74 AHC AHCT
ACT
LV
3V
LV
5V
LVC
3V
tPLH
tPHL
UNIT: ns
A or B
A or B
Y
Y
MAX
MAX
12.2
12.2
13
13
8.5
8.5
4.4
4.4
8.5
8.5
AS
AC
11
INPUT
8.5
8.5
ALS
SN74 CD74 SN74 CD74
HC
HC HCT HCT
PARAMETER
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
141
Logic Diagram
03
A
QUADRUPLE 2-INPUT
POSITIVE-NAND GATES
WITH OPEN-COLLECTOR
OUTPUTS
Y
B
● Y = A•B
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
VOH
IOL
MAX or MIN
TTL
LS
S
MAX
MAX
MAX
22
5.5
16
4.4
8
0.1
36
5.5
20
ALS SN74 CD74 CD74 UNIT
HC
HC HCT
4
8
0.1
0.02
0.05
4
0.04
VCC
4
0.04
VCC
4
mA
V
mA
SWITCHING CHARACTERISTICS
142
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
tPLH
A or B
Y
MAX
45
32
7.5
50
31
30
36
tPHL
UNIT: ns
A or B
Y
MAX
15
28
7
13
25
30
36
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
ALS
SN74 CD74 CD74
HC
HC HCT
PARAMETER
Logic Diagram
04
HEX
INVERTERS
A
Y
● Y=A
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 SN74 CD74
HC
HC HCT HCT
AC
11
SN74 CD74 ACT
AC
AC
11
15.3
0.02
0.04
0.02
0.04
0.04
0.02
0.08
0.04
mA
-2
20
-1
20
-4
4
-4
4
-4
4
-4
4
-24
24
-24
24
-24
24
-24
24
mA
mA
LV
3V
LV
5V
MAX or MIN
TTL
LS
S
ALS
AS
F
ICC
MAX
33
6.6
54
4.2
26.3
IOH
IOL
MAX
MAX
-0.4
16
-0.4
8
-1
20
-0.4
8
PARAMETER
MAX or MIN
SN74 CD74
AHC AHCT
ACT ACT
UNIT
LVC ALVC
UNIT
3V
3V
ICC
MAX
0.02
0.08
0.02
0.02
-
0.02
0.01
0.01
mA
IOH
IOL
MAX
MAX
-24
24
-24
24
-8
8
-8
8
-6
6
-12
12
-24
24
-24
24
mA
mA
SWITCHING CHARACTERISTICS
AC
11
SN74 CD74 ACT
AC
AC
11
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
ALS
AS
tPLH
A or B
Y
MAX
22
15
4.5
11
5
6
24
26
25
29
7.1
7.5
6.5
9.7
tPHL
A or B
Y
MAX
15
15
5
8
4
5.3
24
26
25
29
6
7
6.5
9.6
PARAMETER
INPUT
OUTPUT
MAX or MIN
LV
3V
LV
5V
LVC ALVC
3V
3V
tPLH
tPHL
UNIT: ns
A or B
A or B
Y
Y
MAX
MAX
12
12
8.5
8.5
4.5
4.5
SN74 CD74 AHC AHCT
ACT ACT
9
8.5
9.3
9.3
8.5
8.5
8.5
8.5
F
SN74 CD74 SN74 CD74
HC
HC HCT HCT
PARAMETER
2.8
2.8
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
143
Logic Diagram
U04
HEX
INVERTERS
A
Y
● Y=A
● Unbuffered Output
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
SN74 CD74 AHC
HC
HC
LV
3V
LV
5V
LVC
3V
UNIT
ICC
IOH
MAX
MAX
0.02
-4
0.04
-4
0.02
-8
-6
0.02
-12
0.01
-24
mA
mA
IOL
MAX
4
4
8
6
12
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
tPLH
tPHL
UNIT: ns
A or B
A or B
Y
Y
MAX
MAX
SN74 CD74
AHC
HC
HC
20
20
21
21
8
8
LV
3V
LV
5V
LVC
3V
13
13
8
8
3.8
3.8
05
Logic Diagram
HEX INVERTERS
WITH OPEN-COLLECTOR
OUTPUTS
A
Y
● Y=A
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
VOH
IOL
MAX or MIN
TTL
LS
S
MAX
MAX
MAX
MAX
33
5.5
16
6.6
5.5
8
54
5.5
20
ALS SN74 CD74 CD74 AHC
HC
AC ACT
LV
3V
LV
5V
UNIT
4.2
5.5
8
5.5
6
0.02
5.5
12
mA
mA
V
mA
0.02
5.5
4
0.08
-24
5.5
24
0.08
-24
5.5
24
0.02
Vcc
8
SWITCHING CHARACTERISTICS
144
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
tPLH
tPHL
tPLZ
tPZL
UNIT: ns
A or B
A or B
A
A
Y
Y
Y
Y
MAX
MAX
MAX
MAX
55
15
-
32
28
-
7.5
7
-
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
ALS SN74 CD74 CD74 AHC
HC
AC ACT
54
14
-
29
21
-
8.2
6.5
9.3
10.8
8.5
8.5
LV
3V
LV
5V
12
12
-
8.5
8.5
-
Logic Diagram
06
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR
HIGH-VOLTAGE OUTPUTS
A
Y
● Y=A
RECOMMENDED OPERATING CONDITIONS
PARAMETER
LV
3V
MAX or MIN
TTL
LS
ICC
IOH
MAX
MAX
51
0.25
60
0.25
-
VOH
IOL
MAX
MAX
30
40
30
40
5.5
8
LV
5V
LVC
3V
UNIT
0.02
0.01
mA
0.0025
5.5
16
5.5
24
mA
V
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
LV
3V
LV
5V
LVC
3V
tPLH
tPHL
UNIT: ns
A or B
A or B
Y
Y
MAX
MAX
15
23
15
20
12
12
8.5
8.5
3.7
3.7
07
Logic Diagram
HEX BUFFERS/DRIVERS
WITH OPEN-COLLECTOR
HIGH-VOLTAGE OUTPUTS
A
Y
● Y=A
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
VOH
IOL
MAX or MIN
TTL
LS
LV
3V
LV
5V
LVC
3V
UNIT
MAX
MAX
MAX
MAX
41
0.25
30
40
45
0.25
30
40
5.5
8
0.02
0.01
mA
0.0025
5.5
16
5.5
24
mA
V
mA
SWITCHING CHARACTERISTICS
145
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
LV
3V
LV
5V
LVC
3V
tPLH
tPHL
UNIT: ns
A or B
A or B
Y
Y
MAX
MAX
15
26
10
30
12
12
8.5
8.5
2.9
2.9
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
145
Logic Diagram
08
QUADRUPLE 2-INPUT
POSITIVE-AND GATES
A
Y
B
● Y = A•B
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 SN74 CD74
HC
HC HCT HCT
AC
11
SN74 CD74 ACT
AC
AC
11
12.9
-1
0.02
-4
0.04
-4
0.02
-4
0.04
-4
0.04
-24
0.02
-24
0.08
-24
0.04
-24
mA
mA
20
20
4
4
4
4
24
24
24
24
mA
SN74 CD74 AHC AHCT
ACT ACT
LV
3V
LV
5V
0.02
-24
24
-6
6
0.02
-12
12
MAX or MIN
TTL
LS
S
ALS
AS
F
ICC
IOH
MAX
MAX
33
-0.8
8.8
-0.4
57
-1
4
-0.4
24
-2
IOL
MAX
16
8
20
8
PARAMETER
ICC
IOH
IOL
MAX or MIN
MAX
MAX
MAX
0.08
-24
24
0.02
-8
8
0.02
-8
8
UNIT
LVC ALVC UNIT
0.01
-24
24
0.01
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
146
SN74 CD74 SN74 CD74
HC
HC HCT HCT
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
ALS
AS
F
tPLH
tPHL
A or B
A or B
Y
Y
MAX
MAX
27
19
15
20
7
7.5
14
10
5.5
5.5
6.6
6.3
PARAMETER
INPUT
OUTPUT
MAX or MIN
LV
3V
LV
5V
tPLH
A or B
Y
MAX
10
12.9
9
9
14
9
4.1
2.9
tPHL
UNIT: ns
A or B
Y
MAX
10
12.9
9
9
14
9
4.1
2.9
SN74 CD74
AHC AHCT
ACT ACT
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
25
25
27
27
30
30
38
38
AC
11
6.9
6.5
SN74 CD74 ACT
AC
AC
11
8.5
7.5
8.7
8.7
9
8.2
LVC ALVC
146
Logic Diagram
09
QUADRUPLE 2-INPUT
POSITIVE-AND GATES
WITH OPEN-COLLECTOR
OUTPUTS
1A
1B
2A
2B
● Y = A•B
3A
3B
4A
4B
1
2
4
5
9
10
12
13
3
6
8
11
1Y
2Y
3Y
4Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 UNIT
HC
MAX or MIN
TTL
LS
S
ALS
F
ICC
IOH
MAX
MAX
33
-
8.8
0.1
57
0.25
4.2
0.1
26.3
-
15.3
-
mA
mA
VOH
IOL
MAX
MAX
5.5
16
5.5
8
5.5
20
5.5
8
5.5
20
VCC
4
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
ALS
F
SN74
HC
tPLH
tPHL
UNIT: ns
A or B
A or B
Y
Y
MAX
MAX
32
24
35
35
10
10
54
15
9.6
4.8
31
25
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
147
Logic Diagram
10
TRIPLE 3-INPUT
POSITIVE-NAND GATES
A
B
C
Y
● Y = A•B•C
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 SN74 CD74
HC
HC HCT HCT
AC
11
SN74 CD74 ACT
AC
AC
11
7.7
-1
0.02
-4
0.04
-4
0.02
-4
0.04
-4
0.04
-24
0.02
-24
0.08
-24
0.04
-24
mA
mA
20
4
4
4
4
24
24
24
24
mA
MAX or MIN
TTL
LS
S
ALS
AS
F
ICC
IOH
MAX
MAX
16.5
-0.4
3.3
-0.4
27
-1
2.2
-0.4
13
-2
IOL
MAX
16
8
20
8
20
SN74 CD74
ACT ACT
LV
3V
LV
5V
0.04
-24
24
-6
6
0.02
-12
12
PARAMETER
ICC
IOH
IOL
MAX or MIN
MAX
MAX
MAX
0.08
-24
24
UNIT
LVC ALVC UNIT
3V
0.01
-24
24
0.01
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
ALS
AS
F
A, B or C
A, B or C
Y
Y
MAX
MAX
22
15
15
15
4.5
5
11
10
4.5
4.5
6
5.3
INPUT
OUTPUT
MAX or MIN
LV
3V
LV
5V
LVC
ALVC
3V
tPLH
A, B or C
Y
MAX
10
-
13.5
9
4.9
3
tPHL
UNIT: ns
A, B or C
Y
MAX
9.5
13.5
13.5
9
4.9
3
tPLH
tPHL
PARAMETER
148
SN74 CD74
ACT ACT
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
SN74 CD74 SN74 CD74
HC
HC HCT HCT
24
24
30
30
19
19
36
36
AC
11
6.7
7
SN74 CD74 ACT
AC
AC
11
8
6.5
12.2
12.2
8.9
8.2
Logic Diagram
11
TRIPLE 3-INPUT
POSITIVE-AND GATES
A
B
C
Y
● Y = A•B•C
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 SN74 CD74
HC
HC HCT HCT
AC
11
SN74 ACT SN74
AC
11
ACT
LV
3V
LV
5V
UNIT
9.7
-1
0.02
-4
0.04
-4
0.02
-4
0.04
-4
0.04
-24
0.02
-24
0.04
-24
0.02
-24
-6
0.02
-12
mA
mA
20
4
4
4
4
24
24
24
24
6
12
mA
MAX or MIN
LS
S
ALS
AS
F
ICC
IOH
MAX
MAX
6.6
-0.4
42
-1
3
-0.4
18
-2
IOL
MAX
8
20
8
20
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
PARAMETER
tPLH
tPHL
INPUT
OUTPUT
MAX or MIN
LS
S
ALS
AS
F
A, B or C
A, B or C
Y
Y
MAX
MAX
15
20
7
7.5
13
10
6
5.5
6.6
6.5
INPUT
OUTPUT
MAX or MIN
LV
3V
LV
5V
A, B or C
A, B or C
Y
Y
MAX
MAX
14
14
9
9
SN74 CD74 SN74 CD74
HC
HC HCT HCT
25
25
30
30
21
21
42
42
AC
11
6.5
6.9
SN74 ACT SN74
AC
11
ACT
8.5
7.5
9.6
8.7
10.5
10.5
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
149
Logic Diagram
14
HEX SCHMITT-TRIGGER
INVERTERS
A
Y
● Y=A
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
SN74 CD74 SN74 CD74 SN74 CD74 SN74 CD74 AHC AHCT UNIT
HC
HC HCT HCT AC
AC ACT ACT
ICC
IOH
MAX
MAX
60
-0.8
21
-0.4
0.02
-4
0.04
-4
0.02
-4
0.04
-4
0.02
-24
0.08
-24
0.02
-24
0.08
-24
0.02
-8
0.02
-8
mA
mA
IOL
MAX
16
8
4
4
4
4
24
24
24
24
8
8
mA
MAX or MIN
LV
3V
LV
5V
MAX
MAX
MAX
-6
6
0.02
-12
12
PARAMETER
PARAMETER
ICC
IOH
IOL
LVC ALVC UNIT
3V
3V
0.01
-24
24
0.01
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
150
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
tPLH
tPHL
A or B
A or B
Y
Y
MAX
MAX
22
22
22
22
PARAMETER
INPUT
OUTPUT
MAX or MIN
tPLH
tPHL
UNIT: ns
A or B
A or B
Y
Y
MAX
MAX
AHC AHCT
12
12
9
9
SN74 CD74 SN74 CD74 SN74 CD74 SN74 CD74
HC
HC HCT HCT AC
AC ACT ACT
31
31
41
41
LV
3V
LV
5V
LVC ALVC
3V
3V
18.5
18.5
12
12
6.4
6.4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
40
40
57
57
3.4
3.4
11
9.5
10.5
10.5
12.5
11
14.5
9.5
Logic Diagram
16
HEX INVERTER
BUFFERS/DRIVERS
WITH OPEN-COLLECTOR
HIGH-VOLTAGE OUTPUTS
● Y=A
1A
1
2
1Y
2A
3
4
2Y
3A
5
6
3Y
4A
9
8
4Y
5A
11
10
5Y
6A
13
12
6Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
UNIT
ICC
VOH
MAX
MAX
51
15
mA
V
IOL
MAX
40
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
TTL
A
A
Y
Y
MAX
MAX
15
23
17
Logic Diagram
HEX BUFFERS/DRIVERS
WITH OPEN-COLLECTOR
HIGH-VOLTAGE OUTPUTS
A
Y
● Y=A
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
UNIT
MAX
MAX
MAX
41
15
40
6.6
V
mA
ICC
VOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
TTL
A
A
Y
Y
MAX
MAX
15
26
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
151
Logic Diagram
19
HEX SCHMITT-TRIGGER
INVERTERS
● Y=A
● P-N-P Input Reduce System Loading
(IIL = -0.05mA MAX)
● Excellent Noise Immunity with Typical
Hysteresis of 0.8V
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
UNIT
ICC
IOH
MAX
MAX
30
-0.4
mA
mA
IOL
MAX
8
mA
SWITCHING CHARACTERISTICS
152
PARAMETER
INPUT
OUTPUT
MAX or MIN
LS
tPLH
A or B
Y
MAX
20
tPHL
UNIT: ns
A or B
Y
MAX
30
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1A
1
2
1Y
2A
3
4
2Y
3A
5
6
3Y
4A
9
8
4Y
5Y
6Y
5A
11
10
6A
13
12
Logic Diagram
20
DUAL 4-INPUT
POSITIVE-NAND
GATES
1A
1B
1C
1D
1
2
4
5
● Y = A•B•C•D
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
2A
2B
2C
2D
9
10
12
13
6
1Y
8
2Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 CD74
HC
HC HCT
MAX or MIN
TTL
LS
S
ALS
AS
F
ICC
IOH
MAX
MAX
11
-0.4
2.2
-0.4
18
-1
1.5
-0.4
8.7
-2
5.1
-1
0.02
-4
0.04
-4
IOL
MAX
16
8
20
8
20
20
4
4
AC
11
CD74 ACT CD74
AC
11
ACT
LV
3V
LV
5V
UNIT
0.04
-4
0.04
-24
0.08
-24
0.04
-24
0.08
-24
-6
0.02
-12
mA
mA
4
24
24
24
24
6
12
mA
AC
11
CD74 ACT CD74
AC
11
ACT
6.7
7.3
12.2
12.2
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
ALS
AS
F
A, B, C or D
A, B, C or D
Y
Y
MAX
MAX
22
15
15
15
4.5
5
11
10
5
4.5
6
5.3
INPUT
OUTPUT
MAX or MIN
LV
3V
LV
5V
tPLH
A, B, C or D
Y
MAX
11.5
8
tPHL
UNIT: ns
A, B, C or D
Y
MAX
11.5
8
tPLH
tPHL
PARAMETER
SN74 CD74 CD74
HC
HC HCT
28
28
30
30
42
42
9.1
9.2
13.5
13.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
153
Logic Diagram
21
DUAL 4-INPUT
POSITIVE-AND
GATES
● Y = A•B•C•D
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
1A
1B
1C
1D
1
2
4
5
2A
2B
2C
2D
9
10
12
13
6
8
1Y
2Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 CD74
HC
HC HCT
MAX or MIN
LS
ALS
AS
F
ICC
IOH
MAX
MAX
4.4
-0.4
2.3
-0.4
12
-2
7.3
-1
0.02
-4
0.04
-4
IOL
MAX
8
8
20
20
4
4
AC
11
ACT
11
LV
3V
LV
5V
UNIT
0.04
-4
0.04
-24
0.04
-24
-6
0.02
-12
mA
mA
4
24
24
6
12
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
LS
ALS
AS
F
A, B, C or D
A, B, C or D
Y
Y
MAX
MAX
15
20
15
10
6
6
5.3
5.5
SN74 CD74 CD74
HC
HC HCT
28
28
25
33
33
41
41
AC
11
ACT
11
LV
3V
LV
5V
8.8
6.9
9.8
8.9
12
12
6
8
Logic Diagram
DUAL 4-INPUT
POSITIVE-NOR GATES
WITH STROBE
A
● Y = G (A + B + C + D)
C
B
OUTPUT
Y
D
G
X X
GATE 1 OF
SN5423/SN7423
ONLY
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL UNIT
MAX
MAX
MAX
19
-0.8
16
mA
mA
mA
SWITCHING CHARACTERISTICS
154
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
tPLH
tPHL
UNIT: ns
A or B
A or B
Y
Y
MAX
MAX
22
15
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
26
QUADRUPLE 2-INPUT
HIGH-VOLTAGE INTERFACE
POSITIVE-NAND GATES
1
1A
4
2A
9
3A
12
4A
3Y
11
13
4B
2Y
8
10
3B
1Y
6
5
2B
● Y = AB
3
2
1B
4Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
UNIT
ICC
VOH
MAX
MAX
22
15
4.4
15
mA
V
IOL
MAX
16
8
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
tPLH
tPHL
UNIT: ns
A or B
A or B
Y
Y
MAX
MAX
24
17
32
28
27
Logic Diagram
A
B
C
TRIPLE 3-INPUT
POSITIVE-NOR GATES
Y
● Y=A+B+C
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
LS
ALS
AS
F
SN74 CD74 CD74
HC
HC HCT
AC
11
ACT
11
LV
3V
LV
5V
UNIT
MAX
MAX
MAX
26
-0.8
16
6.8
-0.4
8
4
-0.4
8
17.1
-2
20
12
-1
20
0.02
-4
4
0.04
-24
24
0.04
-24
24
-6
6
0.02
-12
12
mA
mA
mA
0.04
-4
4
0.04
-4
4
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
TTL
LS
ALS
AS
F
A, B or C
A, B or C
Y
Y
MAX
MAX
15
11
15
15
15
9
5.5
4.5
5.5
4.5
SN74 CD74 CD74
HC
HC HCT
23
23
29
29
35
35
AC
11
ACT
11
LV
3V
LV
5V
7.7
8.1
10.1
9.4
14
14
9
9
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
155
Logic Diagram
30
8-INPUT
POSITIVE-NAND
GATES
1
A
2
B
3
C
4
D
● Y = A•B•C•D•E•F•G•H
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
8
5
E
Y
6
F
11
G
12
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
LS
S
ALS
AS
F
SN74 CD74 CD74
HC
HC HCT
AC
11
ACT
11
UNIT
MAX
MAX
MAX
6
-0.4
16
1.1
-0.4
8
10
-1
20
0.9
-0.4
8
4.9
-2
20
4
-1
20
0.02
-4
4
0.04
-24
24
0.04
-24
24
mA
mA
mA
0.04
-4
4
0.04
-4
4
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
ALS
AS
F
A thru H
A thru H
Y
Y
MAX
MAX
22
15
15
20
6
7
10
12
5
4.5
5.5
5
SN74 CD74 CD74
HC
HC HCT
33
33
31
A1
Delay Elements for Generating Delay Line
Inverting and Non-inverting Elements
Buffer NAND Elements Rated at IOL of 12/24mA
P-N-P Inputs Reduce Fan-In (IIL = -0.2mA MAX)
Worst Case MIN/MAX Delays Guaranteed Across
Temperature and VCC Range
A2
A3
B3
A4
B4
A5
A6
RECOMMENDED RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
156
42
42
ACT
11
7.2
7.4
8.5
8.7
Logic Diagram
DELAY ELEMENTS
●
●
●
●
●
39
39
AC
11
Y3, Y4 outputs
All other outputs
Y3, Y4 outputs
All other outputs
MAX or MIN
LS
UNIT
MAX
MAX
MAX
MAX
MAX
20
-1.2
-0.4
24
8
mA
mA
mA
mA
mA
(1)
(2)
(3)
(4)
(5)
(7)
(6)
(10)
(9)
(11)
(13)
(12)
(15)
(14)
Y1
Y2
Y3
Y4
Y5
Y6
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
INPUT
OUTPUT
MAX or MIN
A1, A6
Y1, Y6
MAX
A2, A5
Y2, Y5
MAX
A3, B3
A4, Y4
Y3, Y4
MAX
LS
65
45
80
95
15
15
Logic Diagram
32
QUADRUPLE 2-INPUT
POSITIVE-OR GATES
A
Y
B
● Y=A+B
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 SN74 CD74
HC
HC HCT HCT
AC
11
SN74 CD74 ACT
AC
AC
11
15.5
0.02
0.04
0.02
0.04
0.04
0.02
0.08
0.04
mA
-2
-1
-4
-4
-4
-4
-24
-24
-24
-24
mA
20
20
4
4
4
4
24
24
24
24
mA
LV
3V
LV
5V
MAX or MIN
TTL
LS
S
ALS
AS
F
ICC
MAX
38
9.8
68
4.9
26.6
IOH
MAX
-0.8
-0.4
-1
-0.4
IOL
MAX
16
8
20
8
PARAMETER
MAX or MIN
SN74 CD74
AHC AHCT
ACT ACT
UNIT
LVC
ALVC UNIT
3V
ICC
IOH
MAX
MAX
0.02
-24
0.08
-24
0.02
-8
0.02
-8
0.02
-6
0.02
-12
0.01
-24
0.01
-24
mA
mA
IOL
MAX
24
24
8
8
6
12
24
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
ALS
AS
F
tPLH
tPHL
A or B
A or B
Y
Y
MAX
MAX
15
22
22
22
7
7
14
12
5.8
5.8
6.6
-
PARAMETER
INPUT
OUTPUT
MAX or MIN
tPLH
tPHL
A or B
A or B
Y
Y
MAX
MAX
CD74 ACT SN74 CD74
AHC AHCT
AC
11
ACT ACT
9.5
9.5
9
8
10
10
12.1
12.1
8.5
8.5
9
9
SN74 CD74 SN74 CD74
HC
HC HCT HCT
25
25
27
27
30
30
36
36
LV
3V
LV
5V
LVC ALVC
3V
3V
13
13
8.5
8.5
3.8
3.8
AC
11
SN74
AC
6.7
5.9
8.5
7.5
2.8
2.8
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
157
Logic Diagram
33
QUADRUPLE 2-INPUT
POSITIVE-NOR BUFFERS
WITH OPEN-COLLECTOR
OUTPUTS
1A
● Y=A+B
3A
1Y
1B
2A
2Y
2B
3Y
3B
4A
4Y
4B
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
ALS
UNIT
ICC
VOH
PARAMETER
MAX
MAX
16.5
5.5
13.8
5.5
9
5.5
mA
V
IOL
MAX
48
24
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
ALS
tPLH
tPHL
A or B
A or B
Y
Y
MAX
MAX
15
18
32
28
33
12
UNIT: ns
35
Logic Diagram
HEX NONINVERTERS
WITH OPEN-COLLECTOR
OUTPUTS
1A
2A
● Y=A
3A
4A
5A
1
2
3
4
5
6
9
8
11
10
13
12
1Y
2Y
3Y
4Y
5Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ICC
VOH
IOL
6A
ALS UNIT
MAX
MAX
MAX
63
5.5
8
mA
V
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
158
INPUT
OUTPUT
MAX or MIN
ALS
A
A
Y
Y
MAX
MAX
50
14
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
6Y
Logic Diagram
37
QUADRUPLE 2-INPUT
POSITIVE-NAND BUFFERS
1A
1B
2A
● Y = A•B
2B
3A
3B
4A
4B
1
3
2
4
6
5
9
8
10
12
11
13
1Y
2Y
3Y
4Y
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
S
ALS
F
UNIT
ICC
IOH
PARAMETER
MAX
MAX
54
-1.2
12
-1.2
80
-3
7.8
-2.6
33
-15
mA
mA
IOL
MAX
48
24
60
24
64
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
ALS
F
tPLH
tPHL
A or B
A or B
Y
Y
MAX
MAX
22
15
24
24
6.5
6.5
8
7
6.5
5
UNIT: ns
38
Logic Diagram
QUADRUPLE 2-INPUT
POSITIVE-NAND BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
1A
1B
2A
2B
● Y = A•B
3A
3B
4A
4B
1
2
4
5
9
10
12
13
3
6
8
11
1Y
2Y
3Y
4Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
VOH
IOL
MAX or MIN
TTL
LS
S
ALS
F
UNIT
MAX
MAX
MAX
54
5.5
48
12
5.5
24
80
5.5
60
7.8
5.5
24
30
4.5
64
mA
V
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
ALS
F
tPLH
tPHL
UNIT: ns
A or B
A or B
Y
Y
MAX
MAX
22
18
32
28
10
10
33
12
13
5.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
159
42
4-LINE TO 10-LINE DECODERS
● All Outputs Are High for Invalid Input Conditions
● Also for Applications as
3-Line to 8-Line Decoders
4-Line to 16-Line Decoders
● Full Decoding of Valid Input Logic Ensures That All Inputs Remain Off for All Invalid Input Conditions
Logic Diagram
1
A
2
3
4
B
0
15
14
1
2
3
5
4
6
C
13
7
9
12
5
6
7
D
10
11
160
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
8
9
FUNCTION TABLE
No.
INVALID
0
1
2
3
4
5
6
7
8
9
INPUTS
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
OUTPUTS
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
0
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
3
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
4
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
5
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
6
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
7
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
8
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
SN74 CD74 CD74 UNIT
HC
HC HCT
ICC
IOH
MAX
MAX
56
-0.8
13
-0.4
0.08
-4
0.16
-4
0.16
-4
mA
mA
IOL
MAX
16
8
4
4
4
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH 2Level Logic
tPHL 2Level Logic
tPLH 3Level Logic
tPHL 3Level Logic
UNIT: ns
INTPUT
A, B, C or D
A, B, C or D
OUTPUT
0-9
0-9
0-9
0-9
MAX or MIN
MAX
MAX
TTL
LS
25
25
30
30
25
25
30
30
SN74 CD74 CD74
HC
HC HCT
38
38
38
38
45
45
45
45
53
53
53
53
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
161
45
BCD-TO-DECIMAL DECODER/DRIVER
● 80-mA Sink-Current Capability
● All Outputs Are Off for Invalid BCD Input Conditions
Logic Diagram
1
A
2
3
4
B
0
15
14
1
2
3
5
4
6
C
13
7
9
12
5
6
7
D
10
11
162
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
8
9
FUNCTION TABLE
No.
INVALID
0
1
2
3
4
5
6
7
8
9
INPUTS
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
OUTPUTS
0
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
3
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
4
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
5
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
6
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
7
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
8
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
UNIT
ICC
VO (on)
PARAMETER
MAX
MAX
70
0.9
mA
V
IOL
MAX
80
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
MAX or MIN
TTL
MAX
25
25
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
163
47
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
● Open-Collector Outputs
● Lamp-Test Provision
● Leading/Trailing Zero Suppression
Logic Diagram
(13) OUTPUT
a
INPUT (7)
A
INPUT (1)
B
(12) OUTPUT
b
INPUT (2)
C
(11) OUTPUT
c
INPUT (6)
D
BI/RBO
BLANKING
(4)
INPUT OR
RIPPLE-BLANKING
OUTPUT
LT
(3)
LAMP-TEST
INPUT
RBI
(5)
RIPPLE-BLANKING
INPUT
164
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(10) OUTPUT
d
(9)
OUTPUT
e
(15) OUTPUT
f
(14) OUTPUT
g
FUNCTION TABLE
No.
INPUTS
0
1
2
3
4
5
6
7
LT
H
H
H
H
H
H
H
H
RBI
H
X
X
X
X
X
X
X
D
L
L
L
L
L
L
L
L
C
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
8
9
10
11
12
13
14
15
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
BI
RBI
LT
X
H
L
X
L
X
X
L
X
X
L
X
X
L
X
BI/RBO
OUTPUTS
H
H
H
H
H
H
H
H
a
ON
OFF
ON
ON
OFF
ON
OFF
ON
b
ON
ON
ON
ON
ON
OFF
OFF
ON
c
ON
ON
OFF
ON
ON
ON
ON
ON
d
ON
OFF
ON
ON
OFF
ON
ON
OFF
e
ON
OFF
ON
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
ON
OFF
f
ON
OFF
OFF
OFF
ON
ON
ON
OFF
ON
ON
OFF
OFF
ON
ON
ON
OFF
g
OFF
OFF
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
OFF
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
ON
ON
OFF
OFF
OFF
ON
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
OFF
OFF
ON
ON
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
ON
ON
OFF
ON
ON
OFF
X
L
X
L
L
H
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ICC
IOH
MAX
MAX
IOL
MAX
TTL
LS
103
13
-0.2 -0.05
8
3.2
UNIT
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
toff
ton
toff
ton
UNIT: ns
INPUT
OUTPUT
MAX or MIN
TTL
LS
A
A
RBI
RBI
A to g
A to g
A to g
A to g
MAX
MAX
MAX
MAX
100
100
100
100
100
100
100
100
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
165
Logic Diagram
51
AND-OR INVERT GATES
1A
1B
1C
● '51, 'S51: Y = AB + CD
● 'F51, 'LS51: 1Y = (1A•1B•1C) + (1D•1E•1F)
● 'HC51: 2Y = (2A•2B) + (2C•2D)
1Y
1D
1E
1F
2A
2B
1Y
2C
2D
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
S
F
SN74 UNIT
HC
ICC
MAX
14
2.8
22
7.5
0.08
mA
IOH
IOL
MAX
MAX
-0.4
16
-0.4
8
-1
20
-1
20
-4
4
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
166
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
F
SN74
HC
Any
Any
Y
Y
MAX
MAX
22
15
20
20
5.5
5.5
6.5
4.5
35
35
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
64
4-2-3-2 INPUT AND-OR
INVERT GATE
A
B
C
D
● Y = ABCD + EF + GHI + JK
E
F
Y
G
H
I
J
K
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
S
F
ICC
PARAMETER
MAX
16
4.7
UNIT
mA
IOH
IOL
MAX
MAX
-1
20
-1
20
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
S
F
Any
Any
Y
Y
MAX
MAX
5.5
5.5
7
5.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
167
73
DUAL J-K FLIP-FLOPS WITH CLEAR
Logic Diagram
14 (7)
J
3(10)
K
12 (9)
Q
J
K
CL
1 (5)
CP
13 (8)
Q
CL R
2 (6)
R
CD74HC/HCT73
Q
Q
CLR
K
J
CLK
'LS73
168
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLE (SN74)
CLOCK
X
↓
↓
↓
↓
H
TRUTH TABLE (CD74)
OUTPUTS
INPUTS
CLEAR
L
H
H
H
H
H
J
X
L
H
L
H
X
K
X
L
L
H
H
X
INPUTS
Q
Q
H
L
Q0 QO
L
H
H
L
TOGGLE
Q0 Q0
OUTPUTS
R
CP
J
K
Q
Q
L
X
X
X
L
H
H
↓
L
L
No Change
H
↓
H
L
H
L
H
↓
L
H
L
H
H
↓
H
H
Toggle
H
H
X
X
No Change
NOTE:
H = High Level (Steady State)
L = Low Level (Steady State)
X = Irrelevant
↓ = High-to-Low Transition
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 CD74 UNIT
HC
HC HCT
MAX or MIN
TTL
LS
ICC
MAX
20
6
0.04
0.08
0.08
mA
IOH
IOL
MAX
MAX
16
-0.4
8
-0.4
4
-4
4
-4
4
-4
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
CLOCK"L"
CLOCK"H"
CP Pulse Wide
tsu
CLEAR "L"
CLK
th
J,K to CP
CLK
MAX or MIN
TTL
LS
MIN
15
20
47
-
30
20
-
MIN
25
MIN
MIN
J,K to CP
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT
CLEAR
Q
MAX
CLEAR
Q
MAX
CLOCK
Q or Q
MAX
CP
Q
MAX
CP
Q
MAX
0
-
SN74 CD74 CD74
HC
HC HCT
25
20
20
-
20
24
20
24
20
20
24
27
20
-
25
-
24
24
0
0
3
-
-
-
3
25
40
20
20
20
20
39
39
39
39
44
44
44
44
51
51
51
51
25
40
-
20
20
-
32
32
-
48
48
48
48
57
57
54
54
0
fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
169
74
DUAL D-TYPE POSITIVE-EDGETRIGGERED FLIP-FLOPS
WITH PRESET AND CLEAR
● 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
PRE
CLK
C
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
C
C
C
Q
CLR
170
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLE
OUTPUTS
INPUTS
PRESET
L
H
L
H
H
H
CLEAR
H
L
L
H
H
H
CLOCK
X
X
X
↓
↓
L
Q
H
L
H*
H
L
Q0
D
X
X
X
H
L
X
Q
L
H
H*
L
H
Q0
† This configuration is unstable; that is, it does not persist when
PRE or CLR returns to its inactive (high) level.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
S
ALS
AS
F
SN74 CD74 SN74 CD74
HC
HC HCT HCT
AC
11
SN74 CD74 ACT
AC
AC
11
16
UNIT
ICC
MAX
15
8
25
4
16
0.04
0.08
0.04
0.08
0.04
0.02
0.08
0.04
IOH
MAX
-0.4
-0.4
-1
-0.4
-2
-1
-4
-4
-4
-4
-24
-24
-24
-24
mA
IOL
MAX
16
8
20
8
20
20
4
4
4
4
24
24
24
24
mA
ALS
AS
F
PARAMETER
ICC
IOH
IOL
MAX or MIN
mA
SN74 CD74 AHC AHCT
ACT ACT
LV
3V
LV
5V
LVC
3V
UNIT
0.02
-24
24
-6
6
0.02
-12
12
0.01
-24
24
mA
mA
mA
MAX or MIN
TTL
LS
S
MIN
15
25
75
34
105
100
25
20
24
16
125
MIN
MIN
MIN
MIN
30
37
30
20
25
25
20
6
7.3
7
3
14.5
14.5
15
15
4
5.5
4
4.5
4
5
4
3
20
20
25
25
24
24
24
18
23
23
20
15
27
27
24
18
4
4
4
3.5
MIN
MIN
20
5
25
40
25
40
5
25
40
25
40
2
6
13.5
6
13.5
10
0
13
15
13
15
2
0
7.5
10.5
7.5
10.5
2
1
7.1
10.5
7.1
10.5
6
0
58
58
58
58
3
60
60
60
60
0
0
44
44
44
44
5
3
60
60
60
60
1
0
7.1
9
7.1
9
25
40
25
40
9
9
16
18
8
9
7.8
9.2
44
44
53
53
35
35
53
53
8.2
7.5
LV
3V
LV
5V
LVC
3V
MAX
MAX
MAX
0.08
-24
24
0.02
-8
8
0.02
-8
8
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
tsu
CLOCK"H"
CLOCK"L"
RESET or CLEAR "L"
D
PRE, CLR INACTIVE
th
tPLH
tPHL
tPLH
tPHL
RESET
CLEAR
tPLH
tPHL
PARAMETER
fmax
tw
tsu
Q
Q
Q
Q
MAX
CLOCK
Q or Q
MAX
INPUT
OUTPUT
MAX or MIN
CLOCK"H"
CLOCK"L"
RESET or CLEAR "L"
D
PRE, CLR INACTIVE
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT fmax : MHz, other : ns
MAX
RESET
CLEAR
CLOCK
Q
Q
Q
Q
Q or Q
SN74 CD74 SN74 CD74
HC
HC HCT HCT
SN74 CD74 ACT SN74 CD74
AHC AHCT
AC
AC
11
ACT ACT
MIN
MIN
MIN
MIN
125
5
5
5
110
4.5
4.5
4
85
5
5
5
125
6
6
6
85
5.7
5.7
5
75
5
5
5
65
5
5
5
45
7
7
7
75
5
5
5
100
3.3
3.3
3.3
MIN
MIN
3
0
3.5
-
4.5
2
3.5
0
4
-
5
3
5
3.5
7
5
5
3
3
2
MIN
0.5
10
10.5
10
10.5
10.5
10.5
0
10.5
11.5
10.5
11.5
10
10
0
9.6
12.5
9.6
12.5
9.4
8.8
1
11.5
12.5
11.5
12.5
14
12
9.5
11.5
12.5
11.5
12.5
9.5
9.5
0.5
11
11
11
11
10.5
10.5
0
13
13
13
13
10
10
0.5
18
18
18
18
17.5
17.5
0.5
11
11
11
11
10.5
10.5
0
5.4
5.4
5.4
5.4
5.2
5.2
MAX
MAX
MAX
AC
11
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
171
75
4-BIT BISTABLE LATCHES
Logic Diagram
DATA
Q
TO
OTHER
LATCH
Q
ENABLE
C
SN74LS75
LATCH 0
16 (10)
2 (6)
D0
D
Q
LE
LE
Q0
1 (11)
Q0
13 (4)
E
14 (8)
Q1
LE
LE
3 (7)
D
D1
15 (9)
Q1
Q
LATCH 1
5
12
VCC
GND
CD74HC/HCT75
FUNCTION TABLE
INPUTS
D
L
H
X
C
H
H
L
OUTPUTS
Q
L
H
Q0
Q
H
L
Q0
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
LS
SN74 CD74 CD74 UNIT
HC
HC HCT
MAX
MAX
MAX
53
-0.4
16
12
-0.4
8
0.04
-4
4
0.08
-4
4
0.08
-4
4
MAX or MIN
TTL
LS
20
20
5
30
25
40
15
30
15
30
15
20
20
5
27
17
20
15
27
25
30
15
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
172
INPUT
OUTPUT
MIN
MIN
D
Q
MAX
D
Q
MAX
G
Q
MAX
G
Q
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
SN74 CD74 CD74
HC
HC HCT
20
25
5
30
30
30
30
33
33
33
33
24
18
3
33
33
39
39
39
39
39
39
24
18
3
42
42
42
42
42
42
45
45
85
4-BIT MAGNITUDE COMPARATORS
Logic Diagram
A3
B3
(15)
(1)
(5)
A2
B2
(14)
(2)
AB
A1
B1
(6)
A=B
(12)
(11)
(7)
A0
B0
A>B
(13)
AB3
A3<B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 CD74
UNIT
HC
HC HCT
MAX or MIN
TTL
LS
S
MAX
MAX
MAX
88
-0.4
16
20
-0.4
8
115
-1
20
ICC
IOH
IOL
0.08
-4
4
0.16
-4
4
0.16
-4
4
mA
mA
mA
A2, B2
X
X
A2>B2
A2<B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A1, B1
X
X
X
X
A1>B1
A1<B1
A1=B1
A1=B1
A1=B1
A1=B1
A1=B1
A1=B1
A1=B1
A0, B0
X
X
X
X
X
X
A0>B0
A0<B0
A0=B0
A0=B0
A0=B0
A0=B0
A0=B0
CASCADING
INPUTS
OUTPUTS
A>B AB A<B A=B
L
H
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
L
L
L
H
H
L
L
L
H
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
INPUT
OUTPUT
Any A or B
data input
tPHL
Any A or B
data input
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
A
A
B,
B,
A
A
A B,
A B,
A
A
B
B
A
A
B
B
B
B
A
B,
A
A B,
A
A
A
A
A
A
A
A B
B
A B
B
B
B
B
B
B
B
Nunber of
Gate Levels
MAX or MIN
TTL
LS
S
3
4
3
4
1
1
2
2
1
1
MAX
MAX
MAX
MAX
26
35
30
30
11
17
20
17
11
17
36
45
30
45
22
17
20
26
22
17
16
18
16.5
16.5
7.5
8.5
10.5
7.5
7.5
8.5
MAX
MAX
MAX
SN74 CD74 CD74
HC
HC HCT
58
50
58
50
44
44
37
37
44
44
59
53
59
53
42
42
42
42
56
60
56
60
45
45
47
47
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
173
86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
● Y = A ⊕ B or Y = AB + AB
● 74AC11xxx : Product Available in Reduced-Noise Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
1A
1B
2A
2B
3A
3B
4A
4B
(1)
(3)
(2)
(4)
(6)
(5)
(9)
(8)
(10)
(12)
(11)
(13)
An exclusive-OR gate has many applications,
some of which can be represented better
by alternative logic symbols.
1Y
Exclusive OR
2Y
=1
3Y
4Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
S
ALS
AS
F
SN74 CD74 CD74
HC
HC HCT
AC
11
SN74 CD74 ACT
AC
AC
11
UNIT
ICC
MAX
50
10
75
5.9
38
28
0.02
0.04
0.04
0.04
0.02
0.08
0.04
mA
IOH
IOL
MAX
MAX
16
-0.8
8
-0.4
20
-1
8
-0.4
20
-2
20
-1
4
-4
4
-4
4
-4
24
-24
24
-24
24
-24
24
-24
mA
mA
LV
3V
LV
5V
LVC
3V
UNIT
PARAMETER
MAX or MIN
SN74 CD74
AHC AHCT
ACT ACT
ICC
IOH
MAX
MAX
0.04
24
0.08
24
0.02
8
0.02
8
6
0.02
12
0.01
24
mA
mA
IOL
MAX
-24
-24
-8
-8
-6
-12
-24
mA
OUTPUT
MAX or MIN
TTL
LS
S
ALS
AS
F
Y
Y
Y
Y
MAX
MAX
MAX
MAX
23
17
30
22
23
17
30
22
10.5
10
10.5
10
17
12
17
10
7.5
6.5
6.5
7
6.5
6.5
8
7.5
25
25
25
25
OUTPUT
MAX or MIN
LV
3V
LV
5V
LVC
3V
Y
Y
Y
Y
MAX
MAX
MAX
MAX
16.5
16.5
16.5
16.5
10
10
10
10
4.6
4.6
4.6
4.6
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
A or B
A or B
PARAMETER
tPLH Input Low
tPHL Input Low
tPLH Input High
tPHL Input High
UNIT: ns
174
INPUT
INPUT
A or B
A or B
SN74 CD74 AHC AHCT
ACT ACT
10
10.5
10
10.5
14.6
14.6
14.6
14.6
10
10
10
10
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
10
10
10
10
SN74 CD74 CD74
HC
HC HCT
36
36
36
36
48
48
48
48
AC
11
7.6
6.8
7.6
6.8
SN74 CD74 ACT
AC
AC
11
9
9.5
9
9.5
10.8
10.8
10.8
10.8
9.6
9
9.6
9
Logic Diagram
90
R9(1) (6)
R9(2) (7)
DECADE COUNTER
CKA
(14)
J Q
(12)
QA
CK
K
FUNCTION TABLE
BCD COUNT SEQUENCE
Count
0
1
2
3
4
5
6
7
8
9
J Q
BI-QUINARY
OUTPUTS
QD QC QB QA
L
L
L
L
H
L
L
L
H
L
L
L
H
H
L
L
H
L
L
L
H
H
L
L
L
L
H
H
H
H
H
L
L
L
L
H
H
L
H
L
OUTPUTS
QA QD QC QB
L
L
L
L
H
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
L
L
L
H
H
L
L
H
L
L
H
H
H
L
H
H
L
L
H
Count
0
1
2
3
4
5
6
7
8
9
CKB
(1)
H
H
X
X
L
L
X
H
H
X
L
X
X
L
L
X
H
X
L
X
L
X
L
H
L
X
L
X
QB
J Q
(8)
QC
CK
K
RESET/COUNT
FUNCTION TABLE
RESET INPUTS
R0(1) R0(2) R9(1) R9(2)
(9)
CK
K
S Q
OUTPUTS
Q D Q C Q B QA
L
L
L
L
L
L
L
L
L
L
H
H
Count
Count
Count
Count
(11)
QD
CK
R Q
R0(1) (2)
R0(2) (3)
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
ICC
PARAMETER
MAX
39
15
UNIT
mA
IOH
IOL
MAX
MAX
-0.8
16
-0.4
8
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
INPUT
OUTPUT
A
QA
B
QB
MAX or MIN
MIN
tw
A
B
RESET
MIN
tsu
RESET
INACTIVE
MIN
tPLH
A
tPHL
tPLH
A
tPHL
tPLH
B
tPHL
tPLH
B
tPHL
tPLH
B
tPHL
tPHL
Set to 0
tPLH
Set to 9
tPHL
UNIT fmax : MHz, other : ns
QA
MAX
QD
MAX
QB
MAX
QC
MAX
QC
MAX
Any
QA, QD
QB, QC
MAX
MAX
TTL
LS
32
32
16
15
30
15
16
15
30
30
25
25
16
18
48
50
16
21
32
35
32
35
40
30
40
16
18
48
50
16
21
32
35
32
35
40
30
40
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
175
Logic Diagram
92
DIVIDE-BY-12 COUNTERS
CKA
(14)
J Q
CK
(12)
QA
K
FUNCTION TABLE
COUNT
QD
L
L
L
L
L
L
H
H
H
H
H
H
0
1
2
3
4
5
6
7
8
9
10
11
OUTPUTS
QC
QB
L
L
L
L
H
L
H
L
H
L
H
L
L
L
L
L
H
L
H
L
H
L
H
L
CKB
QA
(1)
J Q
CK
L
H
L
H
L
H
L
H
L
H
L
H
J Q
CK
H
L
X
H
X
L
J Q
CK
R0(1) (6)
(7)
R0(2)
OUTPUTS
QD QC QB QA
L
L
L
L
COUNT
COUNT
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
LS
UNIT
MAX
MAX
MAX
39
-0.8
16
15
-0.4
8
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
INPUT
OUTPUT
A
B
QA
QB
MIN
A
B
RESET
MIN
tsu
RESET
INACTIVE
MIN
A
A
tPHL
tPLH
B
tPHL
tPLH
B
tPHL
tPLH
B
tPHL
tPHL
Set to 0
UNIT fmax : MHz, other : ns
176
MAX or MIN
tw
tPLH
tPHL
tPLH
QB
(9)
QC
K Q
K
RESET INPUTS
R0(1) R0(2)
(11)
K
QA
MAX
QD
MAX
QB
MAX
QC
MAX
QD
MAX
Any
MAX
TTL
LS
32
16
15
30
15
32
16
15
30
30
25
25
16
18
48
16
18
48
50
16
21
16
21
32
35
40
50
16
21
16
21
32
35
40
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(8)
QD
Logic Diagram
93
4-BIT BINARY COUNTERS
CKA
(14) [14]
J Q
CK
(12) [13]
QA
K
FUNCTION TABLE
COUNT
QD
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RESET INPUTS
R0(1) R0(2)
H
L
X
H
X
L
OUTPUTS
QC
QB
L
L
L
L
H
L
H
L
H
L
H
L
H
H
H
H
L
L
L
L
H
L
H
L
H
L
L
H
H
H
H
H
CKB
QA
(1) [8]
J Q
CK
(9) [9]
QB
K
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
J Q
CK
(8) [10]
QC
K
J Q
CK
R0(1) (2) [1]
(3) [2]
R0(2)
(11) [12]
QD
K
OUTPUTS
QD QC QB QA
L
L
L
L
COUNT
COUNT
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
LS
CD74 CD74 UNIT
HC HCT
MAX
MAX
MAX
39
-0.8
16
15
-0.4
8
0.16
-4
4
0.16
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
INPUT
OUTPUT
MAX or MIN
A
B
QA
QB
MIN
LS
32
16
15
32
16
15
20
20
24
20
20
24
MIN
30
15
30
30
MIN
25
25
16
18
70
70
16
21
32
35
51
51
40
16
18
70
70
16
21
32
35
51
51
40
24
24
38
38
41
41
56
56
74
74
-
24
24
51
51
87
87
51
51
69
69
87
87
-
A
tw
tsu
B
RESET
RESET
INACTIVE
tPLH
A
tPHL
tPLH
A
tPHL
tPLH
B
tPHL
tPLH
B
tPHL
tPLH
B
tPHL
tPHL
Set to 0
UNIT fmax : MHz, other : ns
CD74 CD74
HC HCT
TTL
QA
MAX
QD
MAX
QB
MAX
QC
MAX
QD
MAX
ANY
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
177
97
SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIER
● Perform Fixed-Rate or Variable-Rate Frequency Division
● Typical Maximum Clock Frequency: 32MHz
Logic Diagram
ENABLE
INPUT
(11)
ENABLE
OUTPUT
(7)
G
QA
T
G
QB
G
T
QA
CLEAR
QC
G
T
QB
CLEAR
QD
G
T
QC
CLEAR
QE
G
T
QD
CLEAR
QE
CLEAR
QF
CLEAR
(13)
CLEAR
(9)
CLOCK
STROBE
(10)
RATE
INPUT B5
(3)
RATE
INPUT B4
(2)
RATE
INPUT B3
(15)
RATE
INPUT B2
(14)
Y OUTPUT
(5)
Z OUTPUT
178
(1)
(6)
(12)
UNITY/CASCADE
INPUT
RATE
INPUT B1
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
QF
T
RATE
INPUT B0
(4)
FUNCTION TABLE
INPUTS
OUTPUTS
BINARY RATE
CLEAR ENABLE STROBE F E D C B A
NUMBER OF
CLOCK PULSES
UNITY/
CASCADE
LOGI LEVEL OR
NUMBER OF PULSES
Y
Z
ENABLE
H
L
L
L
L
L
L
L
L
X
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
L
L
L
L
L
L
H
H
X
L
H
L
L
L
L
L
H
X
64
64
64
64
64
64
64
64
H
H
H
H
H
H
H
H
H
L
L
1
2
4
8
16
32
63
H
H
1
2
4
8
16
32
63
H
1
1
1
1
1
1
1
1
L
L
L
L
L
L
H H H H H H
H L H L L L
64
64
L
H
H
40
63
40
1
1
X
L
L
L
L
L
H
L
H
X
L
L
L
L
H
L
L
H
X
L
L
L
H
L
L
L
H
X
L
L
H
L
L
L
L
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
UNIT
MAX
MAX
MAX
120
16
-0.4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
th
INPUT
OUTPUT
MAX or MIN
A
QA
MIN
25
MIN
MIN
MIN
MIN
MIN
20
15
25
0
0
MIN
MAX
MAX
MAX
MAX
20
20
21
18
23
MAX
MAX
MAX
MAX
MAX
39
30
18
26
10
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
14
14
10
30
33
30
33
36
23
23
23
CLK
CLR
Positive
Negative
Positive
Negative
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT
ENABLE
ENABLE
STRB
Z
CLK
Y
CLK
Z
RATE
Z
UNITY
/CAS
Y
STRB
Y
CLK
ENABLE
CLR
Y
Z
RATE
Y
TTL
fmax : MHz other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
179
107
DUAL J-K FLIP-FLOPS WITH CLEAR
Logic Diagram
Q
Q
CLR
K
J
CLK
Q
Q
CLR
K
J
CLK
180
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLES
'107
INPUTS
CLEAR
L
H
H
H
H
CLOCK
X
CLEAR
L
H
H
H
H
H
CLOCK
X
↓
↓
↓
↓
H
OUTPUTS
J
X
L
H
L
H
K
X
L
L
H
H
Q
Q
L
H
Q O QO
H
L
L
H
TOGGLE
'LS107A,'HC107
INPUTS
OUTPUTS
J
X
L
H
L
H
X
K
X
L
L
H
H
X
Q
Q
L
H
QO QO
L
H
H
L
TOGGLE
Q O QO
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
UNIT
ICC
IOH
MAX
MAX
20
-0.4
6
-0.4
0.04
-4
0.08
-4
0.08
-4
mA
mA
IOL
MAX
16
8
4
4
4
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
INPUT
OUTPUT
CLK H
CLK L
CP
CLR L (or R)
J, K
CLR INACTIVE
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
CLR (or R)
CLK
tPLH
tPHL
UNIT
Q
Q
Q
Q
CP
Q
CP
Q
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HC
MIN
MIN
MIN
15
20
47
30
20
-
25
20
20
20
-
19
-
MIN
MIN
MIN
MIN
MIN
25
0
0
0
25
20
25
0
20
25
25
0
24
25
30
3
27
36
30
5
MAX
MAX
MAX
MAX
MAX
MAX
25
40
25
40
-
20
20
20
20
-
39
39
32
32
-
47
47
51
51
57
57
65
65
MAX
MAX
-
-
-
51
51
60
60
fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
181
109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
Logic Diagram
PRE
C
J
C
TG
K
CLK
C
Q
TG
C
C
C
TG
TG
C
C
C
C
Q
CLR
182
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLE
INPUTS
PRESET
L
H
L
H
H
H
H
H
CLEAR
H
L
L
H
H
H
H
H
OUTPUTS
CLOCK
X
X
X
↑
↑
↑
↑
L
J
X
X
X
L
H
L
H
X
Q
Q
H
L
L
H
H† H†
L
H
TOGGLE
QO Q O
H
L
Q O QO
K
X
X
X
L
L
H
H
X
† The output levels in this configuration are not guaranteed to
meet the minimum levels for VOH. Furthermore, this
configuration is nonstable; that is, it will not persist when
either PRE or CLR returns to its inactive (high) level.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
CD74
AC
CD74
ACT
UNIT
ICC
MAX
15
8
4
17
17
0.04
0.08
0.08
0.08
0.08
mA
IOH
IOL
MAX
MAX
-0.8
16
-0.4
4
-0.4
8
-2
20
-1
20
-4
4
-4
4
-4
4
-24
24
-24
24
mA
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
CD74
AC
CD74
ACT
fmax
tw
CLK H
MIN
MIN
25
20
25
25
34
14.5
105
4
90
4
25
20
25
-
19
-
100
-
100
-
tsu
CLK L
CP
PRE L
CLR L
R
J, K
MIN
MIN
MIN
MIN
MIN
MIN
20
20
20
10
25
25
25
14.5
15
15
15
5.5
4
4
5.5
5
4
4
3
20
25
25
25
24
24
-
27
36
-
5
4.5
-
5
5.5
-
PRE, CLR
J, K to CP
MIN
MIN
MIN
MAX
10
6
15
5
25
10
0
13
2
0
8
2
1
8
6
0
58
30
3
-
30
5
-
5.5
0
-
5.5
1
-
MAX
MAX
MAX
MAX
MAX
MAX
35
15
25
16
28
-
40
25
40
25
40
-
15
13
15
16
18
-
10.5
8
10.5
9
9
-
10.5
8
10.5
8
9.2
-
58
58
58
44
44
-
51
65
10.3
10.3
MAX
MAX
MAX
MAX
MAX
-
-
-
-
-
-
51
51
51
47
47
65
60
60
57
57
10.3
10.3
10.3
12.2
12.2
10.3
10.3
10.3
12.2
12.2
th
tPLH
tPHL
PRE
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT
Q
CLR
Q
Q
Q
CLK
Q,Q
CP
Q
CP
Q
R
Q,Q
fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
183
112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
Logic Diagram
PRE
C
J
C
Q
TG
TG
K
C
CLK
C
C
C
TG
TG
C
C
C
C
Q
CLR
184
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLE
OUTPUTS
INPUTS
CLEAR
L
X
X
X
H
H
H
H
H
H
H
↑
↑
A1
X
H
X
X
L
L
X
X
H
↓
↓
L
X
A2
X
H
X
X
X
X
L
L
↓
↓
H
X
L
B2
X
X
X
L
H
↑
H
↑
H
H
H
H
H
B
X
X
L
X
↑
H
↑
H
H
H
H
H
H
Q
L
L†
L†
L†
Q
H
H†
H†
H†
See explanation of function table on page
† These lines of the functional tables assume that the indicated
steady-state conditions at the A and B inputs have been
set up long enough to complete any pulse started before the set up.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
S
ALS
F
SN74
HC
CD74
HC
CD74
HCT
CD74
AC
CD74
ACT
LVC
3V
UNIT
MAX
MAX
MAX
6
-0.4
8
25
-1
20
4.5
-0.4
8
19
-1
20
0.04
-4
4
0.08
-4
4
0.08
-4
4
0.08
-24
24
0.08
-24
24
0.01
-24
24
mA
mA
mA
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
INPUT
OUTPUT
PRE, CLR
CLK H
CLK L
CP
DATA
PRE INACTIVE
CLR INACTIVE
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
PRE or CLR
Q or Q
CLK
Q or Q
CP
Q or Q
S
Q or Q
R
Q or Q
MAX or MIN
LS
S
ALS
F
SN74
HC
CD74
HC
CD74
HCT
LVC
3V
MIN
MIN
MIN
30
25
20
80
8
6
30
10
16.5
100
5
5
20
25
25
20
24
-
20
27
-
150
3.3
MIN
MIN
MIN
MIN
MIN
MIN
20
25
20
0
6.5
7
0
16.5
22
20
20
0
5
5
5
5
0
25
25
25
25
0
24
24
0
24
24
3
3.3
2.3
2.4
2.4
0.7
MAX
MAX
MAX
MAX
MAX
20
20
20
20
-
7
7
7
7
-
15
18
15
19
-
7.5
7.5
7.5
7.5
-
41
41
31
31
-
53
53
4.8
4.8
5.9
5.9
-
MAX
MAX
MAX
MAX
MAX
-
-
-
-
-
53
47
47
54
54
53
48
48
56
56
-
UNIT fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
185
Logic Diagram
121
(11)
MONOSTABLE MULTIVIBRATOR
● Internal Timing Resistors (2kΩ)
● Programmable Output Pulse Width with
Rext/Cext: 40ns to 28s
(9)
(6)
A1
A2
B
FUNCTION TABLE
A2
X
L
X
H
↓
H
↓
X
L
B
H
H
L
X
H
H
H
↑
↑
Q
L
L†
L†
L†
MAX or MIN
TTL
UNIT
MAX
MAX
MAX
40
-0.4
16
mA
mA
mA
INPUT
OUTPUT
MAX or MIN
Q
MAX
Q
MAX
tw (IN)
tPLH
tPHL
tPLH
tPHL
UNIT: NS
186
MIN
A
B
A
B
C
(5)
Cext
NOTES: 1. An external capacitor may be connected between Cext (positive) and Rext / Cext.
2. To use the internal timing resistor, connect Rint to VCC. For improved pulse width
accuracy and repestability, connect an external resistor between Rext / Cext and
VCC with Rint open-circuited.
SWITCHING CHARACTERISTICS
PARAMETER
(1)
(4)
(10)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Q
Rint = 2 kΩ NOM
Q
H
H†
H†
H†
See explanation of function table on page
† These lines of the functional tables assume that the indicated
steady-state conditions at the A and B inputs have been
set up long enough to complete any pulse started before the set up.
ICC
IOH
IOL
Rint
(3)
OUTPUTS
INPUTS
A1
L
X
X
H
H
↓
↓
L
X
Rext / Cext
TTL
50
70
80
55
65
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
122
(13)
RETRIGGERABLE MONOSTABLE
MULTIVIBRATORS WITH CLEAR
A1
A2
B1
B2
● Retriggerable for Very Long Output Pulse, Up to
100% Duty Cycle
● Internal Timing Resistors (5kΩ)
CLR
Rint
(1)
(9)
(2)
(11)
(3)
(4)
(8)
(5)
R
(6)
Rext / Cext
Rint
Cext
Q
Q
Rint is nominally 10 kW for '122 and 'LS122
FUNCTION TABLE
OUTPUTS
INPUTS
CLEAR
L
X
X
X
H
H
H
H
H
H
H
↑
↑
A1
X
H
X
X
L
L
X
X
H
↓
↓
L
X
A2
X
H
X
X
X
X
L
L
↓
↓
H
X
L
B
X
X
L
X
↑
H
↑
H
H
H
H
H
H
Q
L
L†
L†
L†
B2
X
X
X
L
H
↑
H
↑
H
H
H
H
H
Q
H
H†
H†
H†
See explanation of function table on page
† These lines of the functional tables assume that the indicated
steady-state conditions at the A and B inputs have been
set up long enough to complete any pulse started before the set up.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
UNIT
ICC
IOH
PARAMETER
MAX
MAX
66
-0.8
11
-0.4
mA
mA
IOL
MAX
16
8
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
Q
MAX
Q
MAX
tw
tPLH
tPHL
tPLH
tPHL
UNIT: NS
MIN
A
B
A
B
CLEAR
Q
Q
MAX
TTL
LS
40
40
33
28
40
36
27
40
33
44
45
56
27
45
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
187
Logic Diagram
123
Rext/Cext
DUAL RETRIGGERABLE MONOSTABLE
MULTIVIBARATORS WITH CLEAR
● Retriggerable for Very Long Output Pulse, Up to
100% Duty Cycle
A
Cext
B
Q
CLR
Q
R
FUNCTION TABLE
INPUTS
CLEAR
L
X
X
H
H
↑
A (A)
X
H
X
L
↓
L
OUTPUTS
B
X
X
L
↑
H
H
Q
L
L†
L†
Q
H
H†
H†
See explanation of function table on page
† These lines of the functional tables assume that the indicated
steady-state conditions at the A and B inputs have been
set up long enough to complete any pulse started before the set up.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
LS
CD74
HC
CD74
HCT
AHC
AHCT
LV
3V
LV
5V
UNIT
MAX
MAX
MAX
66
-0.8
16
20
-0.4
8
0.16
-4
4
0.16
-4
4
0.65
-8
8
0.975
-8
8
0.28
-6
6
0.65
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
A (A)
B
Q
MAX
tPHL
A (A)
B
Q
MAX
tPLH
tPHL
CLEAR
(R)
Q
tw
tPLH
MIN
Q
MAX
TTL
LS
CD74
HC
CD74
HCT
AHCT
LV
3V
LV
5V
40
40
30
30
5
5
5
5
33
28
40
36
27
33
44
45
56
27
90
90
96
96
65
-
16
16
16
16
13
12
12
12
12
14
27.5
27.5
27.5
27.5
22
16
16
16
16
13
40
45
65
-
13
14
22
13
UNIT: NS
188
AHC
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
124
DUAL VOLTAGE-CONTROLLED OSCILLATORS WITH ENABLE INPUTS
● Frequency Spectrum: 1Hz to 60MHz
● Typical fmax: 85MHz
● Typical Power Dissipation: 525mW
Block Diagram
1 FREQUENCY CONTROL
1 RANGE
1 Cext
1 Cext
1G ENABLE
(2)
(3)
(4)
(5)
FREQCONT
RNG
Y
Cext
Cext
(6)
2 FREQUENCY CONTROL
(7)
1Y
2 RANGE
2 Cext
EN
2 Cext
2G ENABLE
(1)
(14)
(12)
(13)
FREQCONT
RNG
Y
(10)
2Y
Cext
Cext
EN
(11)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
S
UNIT
ICC
MAX
150
mA
IOH
IOL
MAX
MAX
-1
20
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fo
UNIT: NS
MAX or MIN
S
MIN
60
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
189
125
QUADRUPLE BUS BUFFER GATES WITH THREE-STATE OUTPUTS
● Y=A
Logic Diagram
1OE
1A
1
3OE
2
3
3A
1Y
9
8
3Y
13
4
4OE
2OE
2A
10
6
5
4A
2Y
11
12
4Y
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
SN64
BCT
ABT
ICC
MAX
54
20
40
0.08
0.16
0.08
0.16
49
49
30
mA
IOH
IOL
MAX
MAX
-5.2
16
-2.6
24
-15
64
-6
6
-6
6
-6
6
-6
6
-15
64
-15
64
-32
64
mA
mA
MAX or MIN
LVTH
3V
AHC
AHCT
LV
3V
LV
5V
LVC
3V
ALVC
UNIT
ICC
IOH
MAX
MAX
7
-32
0.04
-8
0.02
-8
0.02
-8
0.02
-16
0.01
-24
0.01
-24
mA
mA
IOL
MAX
64
8
8
8
16
24
24
mA
PARAMETER
PARAMETER
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: NS
190
INPUT
OUTPUT
A
Y
G
Y
INPUT
OUTPUT
A
Y
G
Y
MAX or MIN
TTL
LS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
SN64
BCT
ABT
MAX
MAX
MAX
MAX
MAX
MAX
13
18
17
25
8
12
15
18
20
25
20
20
6.5
8
8.5
9
6
6
30
30
30
30
30
30
30
30
38
38
38
38
33
33
35
35
33
33
38
38
38
38
42
42
5.7
7.7
10.3
11.7
8.9
8.6
6
8
11.1
12.8
9.4
9.9
4.9
4.9
5.9
6.8
6.2
6.2
MAX or MIN
LVTH
3V
AHC
AHCT
LV
3V
LV
5V
LVC
3V
ALVC
MAX
MAX
MAX
MAX
MAX
MAX
3.5
3.9
4
4
4.5
4.5
8.5
8.5
8
8
10
10
8.5
8.5
8
8
10
10
13
13
13
13
15
15
8.5
8.5
8
8
10
10
4.8
4.8
5.4
5.4
4.6
4.6
2.8
2.8
3.5
3.5
4
4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
126
QUADRUPLE BUS BUFFER GATES WITH THREE-STATE OUTPUTS
● Y=A
Logic Diagram
1OE
1A
2OE
2A
1
10
3OE
2
3
1Y
9
3A
4
6
2Y
3Y
13
4OE
5
8
12
4A
11
4Y
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
F
SN74
HC
CD74
HC
CD74
HCT
SN74
BCT
SN64
BCT
ABT
LVTH
3V
ICC
MAX
62
22
48
0.08
0.16
0.16
51
51
30
7
mA
IOH
IOL
MAX
MAX
-5.2
16
-2.6
24
-15
64
-6
6
-6
6
-6
6
-15
64
-15
64
-32
64
-32
64
mA
mA
MAX or MIN
AHC
AHCT
LV
3V
LV
5V
LVC
3V
ALVC
UNIT
ICC
IOH
MAX
MAX
0.04
-8
0.02
-8
0.02
-8
0.02
-16
0.01
-24
0.01
-24
mA
mA
IOL
MAX
8
8
8
16
24
24
mA
PARAMETER
PARAMETER
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
A
Y
G
Y
INPUT
OUTPUT
A
Y
G
Y
MAX or MIN
TTL
LS
F
SN74
HC
CD74
HC
CD74
HCT
SN74
BCT
SN64
BCT
ABT
LVTH
3V
MAX
MAX
MAX
MAX
MAX
MAX
13
18
18
25
16
18
15
18
25
35
25
25
7
8.5
8.5
8.5
7.5
8
30
30
30
30
30
30
30
30
38
38
38
38
36
36
38
38
42
42
6.3
7.4
7.9
10.5
10
12.3
6.3
7.4
7.9
10.5
10
12.3
6.3
5.7
6.5
6.5
6.8
6.7
3.8
3.9
5.4
5.2
3.8
5.5
MAX or MIN
AHC
AHCT
LV
5V
LV
3V
LVC
3V
ALVC
MAX
MAX
MAX
MAX
MAX
MAX
8.5
8.5
8
8
10
10
8.5
8.5
8
8
10
10
8.5
8.5
8
8
10
10
13
13
13
13
15
15
4.7
4.7
5.7
5.7
6
6
3.1
3.1
3.3
3.3
3.7
3.7
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
191
Logic Diagram
128
50-Ω LINE DRIVERS
A
Y
B
● Y=A+B
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
UNIT
ICC
PARAMETER
MAX
57
mA
IOH
IOL
MAX
MAX
-42.4
48
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
TTL
A, B
A, B
Y
Y
MAX
MAX
9
12
132
Logic Diagram
QUADRUPLE 2-INPUT POSITIVE-NAND
SCHMITT TRIGGERS
A
Y
● Y = A•B
B
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
LS
S
SN74
HC
CD74
HC
CD74
HCT
AHC
AHCT
LV
3V
LV
5V
UNIT
MAX
MAX
MAX
40
-0.8
16
14
-0.4
8
68
-1
20
0.02
-4
4
0.04
-4
4
0.04
-4
4
0.02
-8
8
0.02
-8
8
0.02
-6
6
0.02
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
192
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
SN74
HC
CD74
HC
CD74
HCT
AHC
AHCT
LV
3V
LV
5V
A, B
A, B
Y
Y
MAX
MAX
22
22
22
22
10.5
13
31
31
38
38
50
50
11
11
10
8
17.5
17.5
11
11
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
133
13-INPUT POSITIVE-NAND GATES
1
A
2
B
● Y = A•B•C•D•E•F•G•H•I•J•K•L•M
3
C
4
D
5
E
6
F
11
I
12
J
13
K
14
L
PARAMETER
ICC
IOH
IOL
15
M
MAX or MIN
S
ALS
SN74
HC
MAX
MAX
MAX
10
-1
20
0.34
-0.4
8
0.02
-4
4
UNIT
mA
mA
mA
Y
10
H
RECOMMENDED OPERATING CONDITIONS
9
7
G
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
S
ALS
SN74
HC
A to M
A to M
Y
Y
MAX
MAX
6
7
11
25
38
38
136
Logic Diagram
QUAD EXCLUSIVE-OR
GATES WITH OPEN-COLLECTOR OUTPUTS
1A
● Y = A ⊕ B = AB + AB
2B
1B
2A
3A
3B
FUNCTION TABLE
INPUTS
A
B
L
L
L
H
H
L
H
H
4A
OUTPUT
Y
L
H
H
L
4B
1Y
2Y
3Y
4Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
VOH
IOL
MAX or MIN
TTL
LS
ALS
AS
UNIT
MAX
MAX
MAX
50
5.5
16
10
5.5
8
5.9
5.5
8
31
5.5
20
mA
V
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
TTL
LS
ALS
AS
A or B
A or B
A or B
A or B
Y (Other Output = L)
Y (Other Output = L)
Y (Other Output = L)
Y (Other Output = L)
MAX
MAX
MAX
MAX
18
50
22
55
30
30
30
30
50
15
50
15
12.5
7.1
11.4
10.7
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
193
137
3-TO-8 LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES
● Incorporates Two Output Enables To Simplify Cascading
Logic Diagram
A
1
15
14
13
Select
Inputs
B
2
12
Y0
Y1
Y2
Y3
Data
Outputs
11
C
10
9
Latch
Enable
LE
4
7
Output
Enables
194
G2
G1
Y4
3
5
6
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Y5
Y6
Y7
FUNCTION TABLE
INPUTS
ENABLE
OUTPUTS
SELECT
LE
X
X
L
L
L
L
L
L
L
L
G1
X
L
H
H
H
H
H
H
H
H
G2
H
X
L
L
L
L
L
L
L
L
C
X
X
L
L
L
L
H
H
H
H
B
X
X
L
L
H
H
L
L
H
H
A
X
X
L
H
L
H
L
H
L
H
Y0
H
H
L
H
H
H
H
H
H
H
H
H
L
X
X
X
Depends upon the address previously applied
while LE was at a logic low.
Y1
H
H
H
L
H
H
H
H
H
H
Y3
H
H
H
H
H
L
H
H
H
H
Y2
H
H
H
H
L
H
H
H
H
H
Y4
H
H
H
H
H
H
L
H
H
H
Y6
H
H
H
H
H
H
H
H
L
H
Y5
H
H
H
H
H
H
H
L
H
H
Y7
H
H
H
H
H
H
H
H
H
L
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
ALS
AS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
UNIT
ICC
IOH
MAX
MAX
18
-0.4
11
-0.4
24
-2
0.08
-4
0.16
-4
0.08
-4
0.16
-4
mA
mA
IOL
MAX
8
8
20
4
4
4
4
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
A, B, C
Y (CD74: Y)
G2
Y (CD74: Y)
G1
Y (CD74: Y)
LE (CD74: LE)
Y (CD74: Y)
MAX or MIN
LS
ALS
AS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
MAX
24
20
12.5
48
54
48
57
MAX
MAX
MAX
MAX
MAX
38
21
27
21
27
20
12
15
17
15
12.5
8
8.5
10
9
48
36
36
36
36
54
44
44
44
44
48
36
36
36
36
57
56
56
53
53
MAX
MAX
27
38
22
20
13.5
14
48
48
57
57
52
52
66
66
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
195
138
3-TO-8 LINE DECODERS/DEMULTIPLEXRS
● 3 Enable Inputs to Simplify Cascading and /or Data Reception
● 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
15
A
Select
Inputs
B
C
14
13
3
12
10
Enable
Inputs
G2A
G2B
196
Y1
2
11
G1
Y0
1
6
4
5
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
9
7
Y2
Y3
Data
Outputs
Y4
Y5
Y6
Y7
FUNCTION TABLE
INPUTS
OUTPUTS
ENABLE SELECT
G1 G2* C B A
H X X X
X
X X X X
L
L L L
H
L
L L H
H
L
L H L
H
L
H
L H H
L
H
L H L L
H
L H L H
H
L H H L
H
L H H H
Y0
H
H
L
H
H
H
H
H
H
H
Y1
H
H
H
L
H
H
H
H
H
H
Y2
H
H
H
H
L
H
H
H
H
H
Y3
H
H
H
H
H
L
H
H
H
H
Y4
H
H
H
H
H
H
L
H
H
H
Y5
H
H
H
H
H
H
H
L
H
H
Y6
H
H
H
H
H
H
H
H
L
H
Y7
H
H
H
H
H
H
H
H
H
L
G2* = G2A•G2B
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
S
ALS
AS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
AC
11
ICC
MAX
10
74
10
20
20
0.08
0.16
0.08
0.16
0.04
mA
IOH
IOL
MAX
MAX
-0.4
8
-1
20
-0.4
8
-2
20
-1
20
-4
4
-4
4
-4
4
-4
4
-24
24
mA
mA
MAX or MIN
CD74
AC
ACT
11
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
LVC
3V
UNIT
ICC
IOH
MAX
MAX
0.16
-24
0.04
-24
0.16
-24
0.04
-8
0.04
-8
0.02
-6
0.02
-12
0.01
-24
mA
mA
IOL
MAX
24
24
24
8
8
6
12
24
mA
PARAMETER
PARAMETER
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
LS
S
ALS
AS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
AC
11
A, B, C
Y (CD74:Y )
MAX
MAX
27
39
12
12
22
18
10
9.5
8.5
9
45
45
45
45
45
45
53
53
8.1
8.8
MAX
MAX
MAX
MAX
26
38
26
38
11
11
11
11
17
17
17
17
7.5
8.5
10
10
8
7.5
9
8.5
39
39
39
39
53
53
53
53
42
42
42
42
53
53
53
53
8.3
8.3
7.5
7.7
MAX or MIN
CD74
AC
ACT
11
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
LVC
3V
MAX
MAX
MAX
MAX
MAX
MAX
11
11
10
10
11
11
9.8
9.7
8.9
8.9
9.3
9.8
12
12
10.5
10.5
11
11
11.5
11.5
11.5
11.5
11.5
11.5
13
13
12
12
11.5
11.5
18
18
18
18
18.5
18.5
11.5
11.5
11.5
11.5
11.5
11.5
6.7
6.7
6.5
6.5
5.8
5.8
G2
Y (CD74:Y )
G1
Y (CD74:Y )
INPUT
OUTPUT
A, B, C
Y (CD74:Y )
G2
Y (CD74:Y )
G1
Y (CD74:Y )
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
197
139
DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS
● Incorporate Two Enable Inputs to Simplify Cascading and /or Data Reception
● 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
4
1
1G
5
6
1A
1B
3
7
15
11
10
2A
2B
198
1Y1
1Y2
2
12
2G
1Y0
1Y3
2Y0
2Y1
2Y2
14
13
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
9
2Y3
FUNCTION TABLE
INPUTS
ENABLE SELECT
G
H
L
L
L
L
B
X
L
L
H
H
A
X
L
H
L
H
OUTPUTS
Y0
H
L
H
H
H
Y1
H
H
L
H
H
Y2
H
H
H
L
H
Y3
H
H
H
H
L
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
S
ALS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
CD74
AC
ACT
11
CD74
ACT
ICC
MAX
11
90
13
0.08
0.08
0.08
0.16
0.16
0.08
0.16
mA
IOH
IOL
MAX
MAX
-0.4
8
-1
20
-0.4
8
-4
4
-4
4
-4
4
-4
4
-24
24
-24
24
-24
24
mA
mA
MAX or MIN
AHC
AHCT
LV
3V
LV
5V
LVC
3V
UNIT
ICC
MAX
0.04
0.02
-
0.02
0.01
mA
IOH
IOL
MAX
MAX
-8
8
-8
8
-6
6
-12
12
-24
24
mA
mA
PARAMETER
PARAMETER
UNIT
SWITCHING CHARACTERISTICS
INPUT
OUTPUT
MAX or MIN
LS
S
ALS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
CD74
AC
ACT
11
CD74
ACT
tPLH
tPHL
tPLH
A or B
A or B
G
Y (CD74: Y)
Y (CD74: Y)
Y (CD74: Y)
MAX
MAX
MAX
29
38
24
12
12
8
14
14
14
44
44
44
44
44
41
43
43
43
51
51
51
10.5
10.5
10.5
8.5
8.5
7.9
11.5
11.5
12
tPHL
G
Y (CD74: Y)
MAX
32
10
15
44
41
43
51
10.5
7.5
12
INPUT
OUTPUT
MAX or MIN
AHC
AHCT
LV
3V
LV
5V
LVC
3V
A or B
A or B
G
Y (CD74: Y)
Y (CD74: Y)
Y (CD74: Y)
MAX
MAX
MAX
10.5
10.5
9.5
10.5
10.5
9.5
16.5
16.5
14.5
10.5
10.5
9.5
6.2
6.2
4.7
G
Y (CD74: Y)
MAX
9.5
9.5
14.5
9.5
4.7
PARAMETER
PARAMETER
tPLH
tPHL
tPLH
tPHL
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
199
Logic Diagram
140
DUAL 4-INPUT POSITIVE-NAND
50-Ω LINE DRIVERS
● Y = ABCD
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
S
UNIT
ICC
IOH
PARAMETER
MAX
MAX
44
-40
mA
mA
IOL
MAX
60
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
INPUT
OUTPUT
MAX or MIN
S
A, B, C, D
Y
MAX
MAX
6.5
6.5
UNIT: ns
200
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1A
1B
1C
1D
1Y
2A
2B
2C
2D
2Y
145
BCD-TO-DECIMAL DECODERS/DRIVERS FOR LAMPS, RELAYS, MOS
● Sink-Current Capability: 80mA
● Low Power Dissipation (SN74LS): 35mW (typ)
Logic Diagram
(1)
OUTPUT 0
(15)
INPUT A
(2)
OUTPUT 1
(3)
OUTPUT 2
(4)
(14)
INPUT B
OUTPUT 3
(5)
OUTPUT 4
(6)
OUTPUT 5
(13)
INPUT C
(7)
OUTPUT 6
(9)
OUTPUT 7
(12)
INPUT D
(10)
OUTPUT 8
(11)
OUTPUT 9
FUNCTION TABLE
INPUTS
RECOMMENDED OPERATING CONDITIONS
OUTPUTS
0
1
2
3
4
D
L
L
L
L
L
C
L
L
L
L
H
B
L
L
H
H
L
A
L
H
L
H
L
0
L
H
H
H
H
1
H
L
H
H
H
2
H
H
L
H
H
3
H
H
H
L
H
4
H
H
H
H
L
5
H
H
H
H
H
6
H
H
H
H
H
7
H
H
H
H
H
8
H
H
H
H
H
9
H
H
H
H
H
5
6
7
8
9
L
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
INVALID
No.
H
H
H
H
H
H
L
L
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
PARAMETER
ICC
Vo (OFF)
MAX or MIN
TTL
LS
UNIT
MAX
MAX
70
15
13
15
mA
mA
MAX or MIN
TTL
LS
MAX
MAX
50
50
50
50
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
201
147
10-TO-4 LINE PRIORITY ENCODER
Logic Diagram
1
2
3
4
(11)
(12)
(9)
(13)
(1)
(7)
5
6
7
8
9
202
A
(2)
B
(3)
(4)
(6)
C
(5)
(10)
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(14)
D
FUNCTION TABLE
INPUTS
1
H
X
X
X
X
X
X
X
X
L
2
H
X
X
X
X
X
X
X
L
H
3
H
X
X
X
X
X
X
L
H
H
4
H
X
X
X
X
X
L
H
H
H
5
H
X
X
X
X
L
H
H
H
H
OUTPUTS
6
H
X
X
X
L
H
H
H
H
H
7
H
X
X
L
H
H
H
H
H
H
8
H
X
L
H
H
H
H
H
H
H
9
H
L
H
H
H
H
H
H
H
H
D
H
L
L
H
H
H
H
H
H
H
C
H
H
H
L
L
L
L
H
H
H
B
H
H
H
L
L
H
H
L
L
H
A
H
L
H
L
H
L
H
L
H
L
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
UNIT
ICC
IOH
MAX
MAX
70
-0.8
20
-0.4
0.08
-4
0.16
-4
0.16
-4
mA
mA
IOL
MAX
16
8
4
4
4
mA
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
MAX
MAX
19
19
33
23
48
48
48
48
53
53
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
203
148
8-TO 3-LINE OCTAL PRIORITY ENCODERS
Logic Diagram
0
10
15
14
1
2
11
4
6
7
EI
204
A0
13
1
7
5
GS
12
9
3
EO
A1
2
3
4
6
5
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
A2
FUNCTION TABLE
OUTPUTS
INPUTS
EI
H
L
L
L
L
L
L
L
L
L
0
X
H
X
X
X
X
X
X
X
L
1
X
H
X
X
X
X
X
X
L
H
2
X
H
X
X
X
X
X
L
H
H
3
X
H
X
X
X
X
L
H
H
H
4
X
H
X
X
X
L
H
H
H
H
5
X
H
X
X
L
H
H
H
H
H
6
X
H
X
L
H
H
H
H
H
H
7
X
H
L
H
H
H
H
H
H
H
A2
H
H
L
L
L
L
H
H
H
H
A1
H
H
L
L
H
H
L
L
H
H
A0
H
H
L
H
L
H
L
H
L
H
GS
H
H
L
L
L
L
L
L
L
L
EO
H
L
H
H
H
H
H
H
H
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
SN74
HC
UNIT
ICC
MAX
60
20
0.08
mA
IOL
MAX
16
8
4
mA
IOH
MAX
-0.8
-0.4
-4
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
INPUT
OUTPUT
WAVEFORM
MAX or MIN
1 to 7
A0, A1 or A2
In-phase output
MAX
1 to 7
A0, A1 or A2
Out-of-phase
output
MAX
0 to 7
EO
Out-of-phase
output
MAX
0 to 7
GS
In-phase output
MAX
E1
A0, A1 or A2
In-phase output
MAX
E1
GS
In-phase output
MAX
E1
EO
In-phase output
MAX
TTL
LS
SN74
HC
15
14
19
19
18
25
36
29
45
45
45
45
10
25
30
25
15
18
40
55
21
25
38
38
48
48
49
15
12
15
15
30
25
17
36
21
35
49
36
36
41
41
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
205
150
1-OF-16 DATA SELECTOR
Logic Diagram
STROBE (9)
(ENABLE)
E0
E1
E2
E3
E4
E5
E6
DATA
INPUTS
E7
E8
E9
E10
E11
E12
E13
E14
E15
(8)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(10)
(23)
(22)
(21)
(20)
(19)
(18)
(17)
(16)
A
A
DATA
SELECT
(BINARY)
B
C
D
206
(15)
A
B
(14)
B
C
(13)
C
D
(11)
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
D
OUTPUTS
FUNCTION TABLE
INPUTS
SELECT
D
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
C
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
B
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
STROBE OUTPUT
W
G
H
H
E0
L
E1
L
E2
L
E3
L
E4
L
E5
L
E6
L
E7
L
E8
L
E9
L
E10
L
E11
L
E12
L
E13
L
E14
L
E15
L
NOTES:
H = High Level, L = Low Level, X = irrelevant
E0, E1 ... E15 = the complement of the level of the
respective E input
D0, D1 ... D7 = the level of the D respective input
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
UNIT
MAX
MAX
MAX
48
-0.8
16
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A, B, C or D
W
MAX
Strobe G
W
MAX
E0 thru E15 or
E0 thru D7
W
MAX
TTL
35
33
24
30
14
20
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
207
151
8-TO-1 LINE DATA SELECTORS/MULTIPLEXERS
Logic Diagram
G
D0
D1
D2
D3
Data
Inputs
D5
D6
D7
A
B
C
208
4
3
2
1
5
D4
Data
Select
(binary)
7
15
14
13
12
11
10
9
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
6
Y
W
FUNCTION TABLE
INPUTS
OUTPUTS
SELECT
C
X
L
L
L
L
H
H
H
H
B
X
L
L
H
H
L
L
H
H
A
X
L
H
L
H
L
H
L
H
G
H
L
L
L
L
L
L
L
L
Y
L
D0
D1
D2
D3
D4
D5
D6
D7
W
H
D0
D1
D2
D3
D4
D5
D6
D7
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
S
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
CD74
AC
CD74
ACT
UNIT
ICC
MAX
48
10
70
12
30
21
0.08
0.16
0.16
0.16
0.16
mA
IOH
IOL
MAX
MAX
-0.8
16
-0.4
8
-1
20
-2.6
24
-15
48
-1
24
-6
6
-4
4
-4
4
-24
24
-24
24
mA
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A, B or C
Y
MAX
A, B or C
W (CD74: Y)
MAX
D0 to D7
Y
MAX
D0 to D7
W (CD74: Y)
MAX
G
Y
MAX
G
W (CD74: Y)
MAX
INPUT
OUTPUT
MAX or MIN
A, B or C
Y
MAX
A, B or C
W (CD74: Y)
MAX
D0 to D7
Y
MAX
D0 to D7
W (CD74: Y)
MAX
G
Y
MAX
G
W (CD74: Y)
MAX
TTL
LS
S
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
38
38
26
43
30
23
18
18
15
18
24
24
14.5
15
12
12
9
9.5
63
63
63
56
56
62
62
62
65
30
20
27
14
14
32
32
26
21
20
13.5
16.5
18
13
12
23
10
15
15
15
12
10.5
11
6.5
4.5
7.5
7.5
7.5
7
5
63
49
49
49
49
62
51
51
56
56
65
57
57
54
54
33
33
21
23
42
32
24
30
12
12
7
7
18
19
19
23
14
11
6
10
10.5
7.5
7
6
32
32
32
32
42
42
44
44
44
44
54
54
CD74
AC
CD74
ACT
18.2
20.2
18.2
19.6
19.6
13.5
13.5
14.9
14.9
12.2
12.2
13.5
13.5
20.2
21.6
21.6
15.5
15.5
16.9
16.9
12.1
12.1
13.5
13.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
209
153
DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
Logic Diagram
1G
1C0
1C1
1
6
5
7
Data 1
1C2
1C3
B
Select
A
2C0
2C1
Data 2
2C2
2C3
2G
210
1Y
4
3
2
14
10
11
12
13
15
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
9
2Y
FUNCTION TABLE
SELECT INPUTS
B
X
L
L
L
L
H
H
H
H
A
X
L
L
H
H
L
L
H
H
DATA INPUTS
C0
X
L
H
X
X
X
X
X
X
C1
X
X
X
L
H
X
X
X
X
C2
X
X
X
X
X
L
H
X
X
STROBE
OUTPUTS
G
H
L
L
L
L
L
L
L
L
Y
L
L
H
L
H
L
H
L
H
C3
X
X
X
X
X
X
X
L
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
S
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
CD74
AC
CD74
ACT
UNIT
ICC
MAX
60
10
70
14
33
20
0.08
0.16
0.16
0.16
0.16
mA
IOH
IOL
MAX
MAX
-0.8
16
-0.4
8
-1
20
-2.6
24
-15
48
-1
20
-6
6
-4
4
-4
4
-24
24
-24
24
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
INPUT
OUTPUT
DATA
Y
SELECT
Y
STROBE
Y
F
SN74
HC
CD74
HC
CD74
HCT
CD74
AC
CD74
ACT
7
8
35
44
51
13.3
18
8
12.5
11
11.5
9
7.5
12
10.5
10.5
8
35
38
38
24
24
44
48
48
36
36
51
51
51
41
41
13.3
20
20
11.8
11.8
18
22
22
12.6
12.6
MAX or MIN
TTL
LS
S
ALS
AS
MAX
18
15
9
10
MAX
MAX
MAX
MAX
MAX
23
34
34
30
23
26
29
38
24
32
9
18
18
15
13.5
15
21
21
18
18
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
211
154
4-LINE TO 16-LINE DECODER/DEMULTIPLEXER
Logic Diagram
(1)
A
G1
G2
A
INPUTS
B
(22)
C
D
(2)
A
(3)
B
(18)
(19)
(23)
B
G
(4)
(5)
C
A
A
(6)
B
(7)
B
C
(21)
(8)
C
D
D
2
3
4
5
6
7
(10)
OUTPUTS
8
9
D
(11)
D
D
(13)
C
(14)
(15)
B
(16)
A
A
212
1
C
(9)
(20)
0
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
G
B
C
D
(17)
10
11
12
13
14
15
FUNCTION TABLE
OUTPUTS
INPUTS
G1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
G2
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
D
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
X
X
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
0
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
3
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
4
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
5
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
6
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
7
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
8
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
10
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
11
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
12
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
13
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
14
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
15
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
ALS
SN74
HC
CD74
HC
CD74
HCT
UNIT
MAX
MAX
MAX
56
-0.8
16
23
24
-0.4
0.08
-4
4
0.16
-4
4
0.16
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
TTL
ALS
SN74
HC
CD74
HC
CD74
HCT
A, B, C, D
0 to 15
(CD74: Y0 to Y15)
MAX
36
33
12
12
45
45
53
53
53
53
G1 to G2
0 to 15
(CD74: Y0 to Y15)
MAX
30
27
12
12
45
45
53
53
51
51
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
213
155
DECODERS/DEMULTIPLEXERS
● Individual Strobes Simplify Cascading for Decoding or Demultiplexing Lager Words
● Outputs: Totem Pole
Logic Diagram
STROBE (2)
1G
DATA
1C
214
(7) OUTPUT
1Y0
(6) OUTPUT
1Y1
(5) OUTPUT
1Y2
SELECT
B
(3)
SELECT
A
(13)
DATA
2C
(15)
(11)OUTPUT
2Y2
STROBE (14)
2G
(12)OUTPUT
2Y3
(4) OUTPUT
1Y3
(9) OUTPUT
2Y0
(10)OUTPUT
2Y1
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLES
2-LINE TO 4-LINE DECODER OR
1-LINE TO 4-LINE DEMULTIPLEXER
INPUTS
SELECT
OUTPUTS
STROBE
DATA
B
A
1G
1C
X
L
L
H
H
X
X
L
H
L
H
X
H
L
L
L
L
X
X
H
H
H
H
L
1Y0 1Y1 1Y2 1Y3
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
2-LINE TO 4-LINE DECODER OR
1-LINE TO 4-LINE DEMULTIPLEXER
INPUTS
SELECT
OUTPUTS
STROBE
DATA
B
A
2G
2C
X
L
L
H
H
X
X
L
H
L
H
X
H
L
L
L
L
X
X
L
L
L
L
H
2Y0 2Y1 2Y2 2Y3
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
3-LINE TO 8-LINE DECODER OR
1-LINE TO 8-LINE DEMULTIPLEXER
INPUTS
OUTPUTS
STROBE
or DATA
SELECT
C†
B
A
G‡
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
† C = inputs 1C and 2C connected together
‡ G = inputs 1G and 2G connected together
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
LS
ALS
UNIT
MAX
MAX
MAX
40
-0.8
16
10
-0.4
8
13
-0.4
8
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
A or B
A or B
1C
1C
OUTPUT
MAX or MIN
Y
MAX
Y
MAX
TTL
LS
ALS
32
32
24
30
26
30
27
27
14
12
12
14
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
215
156
DECODERS/DEMULTIPLEXERS
● Individual Strobes Simplify Cascading for Decoding or Demultiplexing Lager Words
● Outputs: Open-Collector
Logic Diagram
7
Strobe 1G
Data 1C
2
1
6
5
B
1Y0
1Y1
1Y2
3
4
1Y3
Select
9
A
13
10
Data 2C
Strobe 2G
216
15
11
2Y0
2Y1
2Y2
14
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
12
2Y3
FUNCTION TABLES
2-LINE TO 4-LINE DECODER OR
1-LINE TO 4-LINE DEMULTIPLEXER
INPUTS
SELECT
B
X
L
L
H
H
X
OUTPUTS
STROBE
DATA
1G
H
L
L
L
L
X
1C
X
H
H
H
H
L
A
X
L
H
L
H
X
1Y0 1Y1 1Y2 1Y3
H
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
2-LINE TO 4-LINE DECODER OR
1-LINE TO 4-LINE DEMULTIPLEXER
INPUTS
SELECT
B
X
L
L
H
H
X
OUTPUTS
STROBE
DATA
2G
H
L
L
L
L
X
2C
X
L
L
L
L
H
A
X
L
H
L
H
X
2Y0 2Y1 2Y2 2Y3
H
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
3-LINE TO 8-LINE DECODER OR
1-LINE TO 8-LINE DEMULTIPLEXER
INPUTS
C†
X
L
L
L
L
H
H
H
H
B
X
L
L
H
H
L
L
H
H
OUTPUTS
STROBE
or DATA
SELECT
A
X
L
H
L
H
L
H
L
H
G‡
H
L
L
L
L
L
L
L
L
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
† C = inputs 1C and 2C connected together
‡ G = inputs 1G and 2G connected together
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
ALS
UNIT
ICC
PARAMETER
MAX
40
10
9
mA
IOL
VOH
MAX
MAX
16
5.5
8
5.5
8
5.5
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
2C
1G or 2G
A or B
A or B
1C
1C
OUTPUT
MAX or MIN
Y
MAX
Y
MAX
Y
MAX
TTL
LS
ALS
23
30
34
34
27
33
40
51
46
51
48
48
38
22
55
25
50
23
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
217
157
QUAD 2-TO-1 LINE DATA SELECTORS/MULTIPLEXERS
Logic Diagram
G
D0
D1
D2
D3
Data
Inputs
D5
D6
D7
A
B
C
218
4
3
2
1
5
D4
Data
Select
(binary)
7
15
14
13
12
11
10
9
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
6
Y
W
FUNCTION TABLE
INPUTS
STROBE
H
L
L
L
L
SELECT
X
L
L
H
H
A
X
L
H
X
X
OUTPUT
B
X
X
X
L
H
L
L
H
L
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
S
ALS
AS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
UNIT
28
mA
ICC
MAX
48
16
78
11
23
0.08
0.16
0.08
0.16
IOH
MAX
-0.8
-0.4
-1
-0.4
-2
-1
-6
-4
-6
-4
mA
IOL
MAX
16
8
20
8
20
20
6
4
6
4
mA
MAX or MIN
CD74
AC
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
LVC
3V
UNIT
MAX
MAX
MAX
0.16
-24
24
0.16
-24
24
0.04
-8
8
0.02
-8
8
-6
6
0.0.2
-12
12
0.01
-24
24
mA
mA
mA
PARAMETER
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
DATA
Y
MAX
STROBE
Y
MAX
SELECT
Y
MAX
INPUT
OUTPUT
MAX or MIN
DATA
Y
MAX
STROBE
Y
MAX
SELECT
Y
MAX
TTL
LS
S
ALS
AS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
14
14
20
21
23
14
14
20
21
23
7.5
6.5
12.5
12
15
14
12
20
13
24
6
5.5
10.5
7.5
11
6.5
7
11
7
11
32
32
29
29
31
38
38
41
41
44
35
35
33
33
40
38
38
41
41
44
27
27
15
17
10
8
31
44
40
44
CD74
AC
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
LVC
3V
8.5
8.5
13.5
13.5
9.5
9.5
13.5
13.5
9.5
9.5
12
12
9.8
9.8
12
12
15
15
19.5
19.5
9.5
9.5
12
12
5.2
5.2
6.5
6.5
14.5
14.5
14.5
14.5
11.5
11.5
12
12
19
19
11.5
11.5
6.8
6.8
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
219
158
QUAD 2-TO-1 LINE DATA SLECTORS/MULTIPLEXERS
● Buffered Inputs and Outputs
Logic Diagram
1A
2
4
1B
2A
3
5
7
2B
3A
6
4A
10
G
A/B
220
3Y
14
12
4B
2Y
11
9
3B
1Y
13
15
1
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4Y
FUNCTION TABLE
INPUTS
STROBE
H
L
L
L
L
SELECT
X
L
L
H
H
A
X
L
H
X
X
OUTPUT
B
X
X
X
L
H
H
H
L
H
L
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
S
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
UNIT
ICC
IOH
MAX
MAX
11
-0.4
81
-1
10
-0.4
22.5
-2
15
-1
0.08
-6
0.16
-4
0.16
-4
mA
mA
IOL
MAX
8
20
8
20
20
6
4
4
mA
MAX or MIN
CD74
AC
CD74
ACT
AHC
AHCT
UNIT
ICC
IOH
MAX
MAX
0.16
-24
0.16
-24
0.04
-8
0.02
-8
mA
mA
IOL
MAX
24
24
8
8
mA
PARAMETER
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
DATA
Y
MAX
STROBE
Y
MAX
SELECT
Y
MAX
INPUT
OUTPUT
MAX or MIN
DATA
Y
MAX
STROBE
Y
MAX
SELECT
Y
MAX
LS
S
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
12
6
15
5
7
32
42
42
15
17
24
20
24
6
11.5
12
12
12
8
18
18
18
18
4.5
6.5
10
9.5
10.5
4.5
7
6.5
9.5
7
32
29
29
31
31
42
48
48
45
45
42
48
48
45
45
CD74
AC
CD74
ACT
AHC
AHCT
8
8
11.9
11.9
9.2
9.2
12.4
12.4
9.5
9.5
12
12
9.8
9.8
12
12
12.9
12.9
13.5
13.5
11.5
11.5
12
12
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
221
159
4-TO-16 LINE DECODER/DEMULTIPLEXER
Logic Diagram
(1)
A
G1
G2
A
INPUTS
B
(22)
C
D
(2)
A
(3)
B
(18)
(19)
(23)
B
G
(4)
(5)
C
A
A
(6)
B
(7)
B
C
(21)
(8)
(9)
(20)
D
2
3
4
5
6
7
(10)
OUTPUTS
8
9
D
(11)
D
D
(13)
C
(14)
(15)
B
(16)
A
A
222
1
C
C
D
0
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
G
B
C
D
(17)
10
11
12
13
14
15
FUNCTION TABLE
OUTPUTS
INPUTS
G1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
G2
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
X
X
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
0
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
3
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
4
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
5
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
6
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
7
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
8
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
10
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
11
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
12
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
13
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
14
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
15
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOL
MAX or MIN
TTL
UNIT
MAX
MAX
56
16
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
INPUT
ANY
MAX
STROBE
ANY
MAX
TTL
36
36
25
36
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
223
161
SYNCHRONOUS 4-BIT BINARY COUNTERS
● Asynchronous Clear Function
● Carry Output for n-Bit Cascading
Logic Diagram
LOAD
ENT
ENP
9
10
15
LD†
7
RCO
CK†
CLK
CLR
A
B
C
D
2
1
CK
LD
R
3
4
5
6
M1
G2
1, 2T/1C3
G4
3D
4R
M1
G2
1, 2T/1C3
G4
3D
4R
M1
G2
1, 2T/1C3
G4
3D
4R
M1
G2
1, 2T/1C3
G4
3D
4R
14
13
12
11
QA
QB
QC
QD
† For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
224
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
CD74
AC
CD74
ACT
LV
3V
LV
5V
UNIT
ICC
IOH
MAX
MAX
101
-0.8
32
-0.4
21
-0.4
53
-2
55
-1
0.08
4
0.16
-4
0.16
-4
0.08
-24
0.08
-24
-6
0.02
-12
mA
mA
IOL
MAX
16
8
8
20
20
-4
4
4
24
24
-6
12
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
CLOCK
CLEAR
tsu
INPUT A, B, C, D
ENABLE, P, T
LOAD
MAX or MIN
TTL
LS
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
MIN
25
25
40
75
90
25
20
20
MIN
25
20
25
20
15
8
7
5
20
20
24
30
24
30
20
20
15
8
5
38
18
15
20
25
20
20
15
15
8
8
11.5
11.5
43
34
15
18
20
18
20
0
25
3
10
0
8
0
2
31
0
20
3
5
35
35
25
35
35
24
20
20
15
16.5
12.5
7
15
15
9.5
54
54
51
56
56
56
63
63
59
29
16
16
38
-
27
14
14
28
-
20
13
13
24
23
13
9
8.5
13
12.5
11
8.5
8.5
13
11.5
51
49
49
53
55
56
36
36
63
63
59
48
48
75
75
MIN
CLEAR INACTIVE
th
MIN
tPLH
tPHL
tPLH
CLOCK
tPHL
tPLH
tPHL
tPHL
PARAMETER
fmax
tw
tsu
RIPPLE CARRY
MAX
CLOCK
ANY Q
MAX
ENABLE T
RIPPLE CARRY
MAX
CLEAR
ANY Q
RIPPLE CARRY
MAX
MAX
INPUT
OUTPUT
MAX or MIN
CD74
AC
CD74
ACT
LV
3V
LV
5V
MIN
103
4.8
4.4
4.4
-
91
5.4
5.3
4.4
-
50
5
5
6.5
9
85
5
5
4.5
6
5.3
0
15.2
15.2
5.3
0
15.2
15.2
9.5
2.5
1
23.5
23.5
6
1.5
1
14
14
15
15
9.4
9.4
15
15
15
15
9.8
9.8
15
15
18.5
18.5
18
18
19.5
19
11.5
11.5
11.5
11.5
12.5
12
CLOCK
CLEAR
INPUT A, B, C, D
ENABLE, P, T
MIN
MIN
LOAD
CLEAR INACTIVE
th
tPLH
tPHL
MIN
tPLH
tPHL
tPLH
tPHL
tPHL
UNIT
CLOCK
RIPPLE CARRY
MAX
CLOCK
ANY Q
MAX
ENABLE T
RIPPLE CARRY
MAX
CLEAR
ANY Q
RIPPLE CARRY
MAX
MAX
fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
225
163
SYNCHRONOUS 4-BIT BINARY COUNTERS
● Synchronous Clear Function
● Carry Output for n-Bit Cascading
Logic Diagram
LOAD
ENT
ENP
9
10
15
LD†
7
RCO
CK†
CLK
CLR
2
1
CK
LD
R
A
B
C
D
3
4
5
6
M1
G2
1, 2T/1C3
G4
3D
4R
M1
G2
1, 2T/1C3
G4
3D
4R
M1
G2
1, 2T/1C3
G4
3D
4R
M1
G2
1, 2T/1C3
G4
3D
4R
14
13
12
11
QA
QB
QC
QD
† For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
226
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
S
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
CD74
AC
CD74
ACT
LV
3V
LV
5V
UNIT
ICC
IOH
MAX
MAX
101
-0.8
32
-0.4
160
-1
21
-0.4
53
-2
55
-1
0.08
4
0.16
-4
0.16
-4
0.08
-24
0.08
-24
-6
0.02
-12
mA
mA
IOL
MAX
16
8
20
8
20
20
-4
4
4
24
24
-6
12
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
CLOCK
CLEAR
tsu
INPUT A, B, C, D
ENABLE, P, T
tPHL
tPLH
tPHL
tPLH
tPHL
PARAMETER
fmax
tw
tsu
UNIT
20
-
8
5
38
8
8
12
11.5
11.5
-
43
34
40
10
10
20
20
4
15
20
25
20
20
20
20
12
14
14
15
15
15
ALS
0
3
3
0
0
2
0
35
35
25
20
16.5
15
54
35
25
35
24
25
15
20
15
12.5
7
15
9.5
54
51
29
16
16
27
14
14
15
15
15
20
13
13
13
9
8.5
11
8.5
8.5
51
49
49
MAX or MIN
CD74
HC
CD74
HCT
CD74
AC
CD74
ACT
LV
3V
LV
5V
MIN
20
24
18
20
24
15
103
4.8
4.4
91
5.4
4.4
50
5
6.5
85
5
4.5
15
18
20
3
56
20
18
20
5
63
4.4
5.3
5.3
0
15.2
5.3
6.6
6.6
0
15.2
9
9.5
4
1
23.5
6
6
3.5
1
14
56
56
56
36
36
63
59
59
48
48
15.2
15
15
9.4
9.4
15.2
15
15
9.8
9.8
23.5
18.5
18.5
18
18
14
11.5
11.5
11.5
11.5
MAX
CLOCK
ANY Q
MAX
ENABLE T
RIPPLE CARRY
MAX
INPUT
OUTPUT
MIN
MIN
MIN
tPHL
tPLH
tPHL
tPLH
tPHL
25
7
-
40
25
20
LOAD
CLEAR
th
tPLH
90
25
25
20
RIPPLE CARRY
ENABLE, P, T
75
6.7
25
MIN
CLOCK
CLOCK
CLEAR
INPUT A, B, C, D
40
12.5
MIN
MIN
tPLH
SN74
HC
LS
LOAD
CLEAR
th
F
TTL
MIN
S
AS
MAX or MIN
CLOCK
RIPPLE CARRY
MAX
CLOCK
ANY Q
MAX
ENABLE T
RIPPLE CARRY
MAX
fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
227
164
8-BIT PARALLEL OUT SERIAL SHIFT REGISTERS
● AND-Gated (Enable/Disable) Serial Inputs
● Fully Buffered Clock and Serial Inputs
Logic Diagram
CLK
A
B
CLR
8
C1
1
2
C1
C1
C1
C1
C1
C1
1D
1D
1D
1D
1D
1D
1D
R
R
R
R
R
R
R
R
9
3
QA
228
C1
1D
4
QB
5
QC
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
6
QD
10
QE
11
QF
12
QG
13
QH
FUNCTION TABLE
INPUTS
CLEAR
L
H
H
H
H
CLOCK
X
L
↑
↑
↑
A
X
X
H
L
X
B
X
X
H
X
L
QA
OUTPUTS
QB . . . Q H
L
QA0
H
L
L
L
QB0
QAn
QAn
QAn
L
QH0
QGn
QGn
QGn
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
ALS
SN74
HC
CD74
HC
CD74
HCT
CD74
AC
CD74
ACT
LV
3V
LV
5V
UNIT
ICC
IOH
MAX
MAX
54
-0.4
27
-0.4
24
-0.4
0.08
-4
0.16
-4
0.16
-4
0.16
-24
0.16
-24
-6
0.02
-12
mA
mA
IOL
MAX
8
8
8
4
4
4
24
24
6
12
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
INPUT
OUTPUT
CLR "L"
CLK "H"
CLK "L"
DATA
CLEAR INACTIVE
th
tPHL
tPLH
tPHL
PARAMETER
fmax
tw
tsu
LS
ALS
SN74
HC
CD74
HC
CD74
HCT
CD74
AC
CD74
ACT
MIN
MIN
MIN
25
20
20
25
20
20
50
16
10
25
25
20
20
18
24
18
27
27
75
4.5
6.7
70
4.5
7.1
MIN
MIN
MIN
MIN
20
15
20
5
20
15
20
5
10
6
8
2
20
25
25
5
24
18
18
4
27
18
18
4
6.7
2.5
2.5
2.5
7.1
2.5
2.5
3
42
30
37
36
27
32
20
16
17
51
44
44
42
51
51
57
54
54
13.9
12.5
12.5
15.8
14.9
14.9
CLEAR
Q
MAX
Q
MAX
INPUT
OUTPUT
MAX or MIN
LV
3V
LV
5V
MIN
MIN
45
5
75
5
MIN
MIN
MIN
MIN
MIN
5
5
6
2.5
0
5
5
4.5
2.5
1
18.5
18.5
18.5
12.5
12.5
12.5
CLEAR INACTIVE
th
UNIT
TTL
CLOCK
CLR "L"
CLK "H"
CLK "L"
DATA
tPHL
tPLH
tPHL
MAX or MIN
CLEAR
Q
MAX
CLOCK
Q
MAX
fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
229
165
8-BIT SHIFT REGISTERS
● Complementary Outputs: Serial (QH, QH)
● Direct Overriding Load (Data) Inputs
● Parallel-to-Serial Data Conversion
Logic Diagram
A
SH/LD
CLK INH
CLK
SER
230
1
B
11
C
12
D
13
E
14
F
3
G
4
H
5
6
15
2
10
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
9
7
QH
QH
FUNCTION TABLE
INPUTS
SHIFT/
LOAD
CLOCK
INHIBIT
CLOCK
SERIAL
PARALLEL
A...H
L
H
H
H
H
X
L
L
L
H
X
L
↑
↑
X
X
X
H
L
X
a...h
X
X
X
X
INTERNAL
OUTPUTS
QA
QB
a
b
QA0
QB0
QAn
H
L
QAn
QA0
QB0
OUTPUT
QH
h
QH0
QGn
QGn
QH0
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
ALS
SN74
HC
CD74
HC
CD74
HCT
LV
3V
LV
5V
UNIT
ICC
IOH
MAX
MAX
63
-0.8
30
-0.4
24
-0.4
0.08
-4
0.16
-4
0.16
-4
-6
0.02
-12
mA
mA
IOL
MAX
16
8
8
4
4
4
6
12
mA
MAX or MIN
TTL
LS
ALS
SN74
HC
CD74
HC
CD74
HCT
LV
3V
LV
5V
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
High
Low
High
Low
CLOCK
SH/ LD "L"
tsu
MIN
20
25
45
25
20
18
50
85
MIN
MIN
MIN
MIN
25
25
15
15
30
15
25
25
17
30
11
11
12
11
20
20
20
25
24
24
24
24
27
27
30
30
7
7
9
5
4
4
6
3.5
10
20
45
0
24
10
20
45
0
25
10
10
10
4
13
25
10
20
5
38
24
24
11
50
30
30
11
60
8.5
6
6
0.5
21.5
5
4
4
1
13.5
31
31
40
17
36
25
35
35
25
30
14
20
22
13
16
38
38
38
38
38
50
53
53
45
45
60
60
60
53
53
21.5
22
22
20
20
13.5
13.5
13.5
12.5
12.5
27
27
30
25
15
16
38
38
45
45
53
53
20
20
12.5
12.5
CLK INH
DATA
SER
MIN
SH/ LD "H"
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
MIN
CLOCK
Q H or QH
MAX
SH/ LD
Q H or QH
MAX
H
QH
MAX
H
QH
MAX
tPLH
tPHL
UNIT
fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
231
166
8-BIT SHIFT REGISTERS
● Synchronous Load
● Direct Overriding Clear
● Parallel-to-Serial Conversion
Logic Diagram
A
SH/LD
SER
15
B
2
C
D
3
4
1D
C1
R
1D
C1
R
E
F
G
H
5
10
11
12
14
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1
CLK INH
CLK
CLR
6
7
1D
C1
R
9
13
QH
232
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLE
INPUTS
CLEAR
L
H
H
H
H
H
SHIFT/
LOAD
X
X
L
H
H
X
CLOCK
INHIBIT
X
L
L
L
L
H
CLOCK
SERIAL
X
L
↑
↑
↑
↑
X
X
X
H
L
X
PARALLEL
A...H
X
X
a...h
X
X
X
INTERNAL
OUTPUTS
QA
QB
L
L
QA0
QB0
a
b
H
QAn
L
QAn
QA0
QB0
OUTPUT
QH
L
QH0
h
QGn
QGn
QH0
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
ALS
F
SN74
HC
CD74
HC
CD74
HCT
LV
3V
LV
5V
UNIT
ICC
IOH
MAX
MAX
127
-0.8
32
-0.4
24
-0.4
60
-1
0.08
-4
0.16
-4
0.16
-4
-6
0.02
-12
mA
mA
IOL
MAX
16
8
8
20
4
4
4
6
12
mA
MAX or MIN
TTL
LS
ALS
F
SN74
HC
CD74
HC
CD74
HCT
LV
3V
LV
5V
MIN
25
20
25
20
45
10
110
3.5
25
20
20
24
16
30
50
7
85
4
20
30
20
0
35
30
25
30
20
0
30
25
9
16
7
3
14
13
4
4
3
0
9.5
14
25
36
20
0
30
38
30
44
24
1
48
48
53
45
24
0
60
60
7
6
6
0
18.5
21.5
5
4
4.5
1
12
13.5
26
20
12
9
38
48
60
21.5
13.5
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
th
tPHL
tPHL
tPLH
UNIT
INPUT
OUTPUT
CLOCK
MIN
CLEAR
Mode Control
DATA
MIN
CLEAR
QH
MIN
MAX
CLOCK
QH
MAX
fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
233
169
4-BIT UP/DOWN SYNCHRONOUS ONOUS BINARY COUNTERS
● Fully Synchronous Operation for Counting and Programming
● Internal Carry Look-Ahead Circuitry for Fast Counting
● Carry Output for n-Bit Cascading
Logic Diagram
LOAD
U/D
ENT
ENP
9
15
1
RCO
10
7
C1
CLK
A
2
1D
14
QA
3
C1
1D
B
13
QB
4
C1
1D
C
12
QC
5
C1
1D
D
234
6
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
11
QD
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
RCO
Q
IOL
RCO
Q
MAX or MIN
LS
S
ALS
AS
F
UNIT
MAX
MAX
45
-0.4
160
-1
25
-0.4
63
-2
52
-1
mA
mA
MAX
MAX
-1.2
8
-1
20
-0.4
8
-2
20
-1
20
mA
mA
MAX
24
20
8
20
20
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
INPUT
OUTPUT
MAX or MIN
LS
S
ALS
AS
F
MIN
20
40
40
21
40
20
75
16.5
90
17
25
25
28
15
20
15
13
13
12.5
9.5
25
15
20
7
13
CLK
RCO
MAX
CLK
ANY Q
MAX
ENT
RCO
MAX
25
20
12
25
13
16
9
9
7
9
RCO
MAX
35
25
15
22
19
19
12
13
12.5
12
tPLH
U/D
tPHL
UNIT fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
235
170
4-BY-4 REGISTER FILES
● Separate Read/Write Addressing Permits Simultaneous Reading and Writing
● Fast Access Times: Typically 20ns
● Expandable to 1024 Words of 4 Bits
Logic Diagram
D1
D2
(15)
WORD 0
WORD 1
WORD 2
WORD 3
D Q
D Q
D Q
D Q
G
G
G
G
D Q
D Q
D Q
D Q
G
G
G
G
(10)
Q1
(1)
(9)
Q2
DATA
INPUTS
OUTPUTS
D3
D4
(2)
(7)
D Q
D Q
D Q
D Q
G
G
G
G
D Q
D Q
D Q
D Q
G
G
G
G
(3)
(12)
GW
(6)
(13)
(14)
WB
WA
WRITE INPUT
236
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(11)
(4)
RB
GR
(5)
RA
READ INPUT
Q3
Q4
WRITE FUNCTION TABLE
WRITE INPUTS
OUTPUTS
WB
WA
GW
0
1
2
3
L
L
H
H
X
L
H
L
H
X
L
L
L
L
H
Q=D
QO
QO
QO
QO
QO
Q=D
QO
QO
QO
QO
QO
Q=D
QO
QO
QO
QO
QO
Q=D
QO
READ FUNCTION TABLE
OUTPUTS
READ INPUTS
RB
RA
GR
Q1
Q2
Q3
Q4
L
L
H
H
X
L
H
L
H
X
L
L
L
L
H
W0B1
W1B1
W2B1
W3B1
H
W0B2
W1B2
W2B2
W3B2
H
W0B3
W1B3
W2B3
W3B3
H
W0B4
W1B4
W2B4
W3B4
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
UNIT
ICC
VOH
MAX
MAX
150
5.5
40
5.5
mA
V
IOL
MAX
16
8
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
th
INPUT
OUTPUT
MAX or MIN
MIN
MIN
D
MIN
W
D
W
MIN
tPLH
tPHL
READ
ENABLE
Q
MAX
tPLH
tPHL
tPLH
tPHL
tPLH
READ
SELECT
Q
MAX
WRITE
ENABLE
Q
MAX
Q
MAX
DATA
tPHL
UNIT fmax : MHz, other : ns
TTL
LS
25
10
25
10
15
15
5
15
30
15
15
5
30
30
35
40
40
45
30
40
40
45
40
45
45
35
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
237
173
4-BIT D-TYPE REGISTERS
● 3-State Outputs Interface Directly
● Fully Independent Clock Virtually
Logic Diagram
Output
Control
M
N
1D
Data
Enable
G1
G2
2D
1
2
14
1D
C1
9
10
13
R
3
1Q
1D
C1
CLK
3D
7
12
4
R
2Q
1D
C1
5
R
4D
11
3Q
1D
C1
CLR
238
15
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
R
6
4Q
FUNCTION TABLE
CLEAR CLOCK
H
L
L
L
L
L
X
L
↑
↑
↑
↑
INPUTS
DATA ENABLE DATA
D
G2
G1
X
X
X
X
X
X
H
X
X
X
H
X
L
L
L
H
L
L
OUTPUT
Q
L
QO
QO
QO
L
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
UNIT
ICC
MAX
72
24
0.08
0.16
0.16
mA
IOH
MAX
-5.2
-2.6
-6
-6
-6
mA
IOL
MAX
16
24
6
6
6
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
tsu
DATA ENABLE
DATA
CLR INACTIVE
th
tPHL
tPLH
tPHL
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
MIN
MIN
25
20
17
10
10
25
25
35
17
10
25
20
25
25
23
20
24
18
18
-
13
28
18
27
-
2
10
27
43
31
0
3
35
25
30
0
0
38
38
38
0
3
53
60
60
0
0
66
60
60
30
30
14
20
23
27
20
17
38
38
38
38
45
45
45
45
45
45
-
MIN
MIN
DATA ENABLE
DATA
MIN
CLEAR
Q
MAX
CLOCK
Q
MAX
Q
MAX
Q
MAX
tPZH
ENABLE
tPZL
tPHZ
DISABLE
tPLZ
UNIT fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
239
Logic Diagram
174
HEX D-TYPE FLIP-FLOPS
CLR
● Buffered Clock and Direct Clear Inputs
● Fully Buffered Outputs for Maximum Isolation
from External Disturbances
CLK
1D
1
9
3
1D
2
C1
1Q
R
FUNCTION TABLE
CLEAR
L
H
H
L
INPUTS
CLOCK
X
↑
↑
L
To Five Other Channels
OUTPUT
Q
L
H
L
QO
D
X
H
L
X
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
S
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
UNIT
MAX
MAX
MAX
65
-0.8
16
26
-0.4
8
144
-1
20
19
-0.4
8
45
-2
20
55
-1
20
0.08
-4
4
0.16
-4
4
0.16
-4
4
mA
mA
mA
MAX or MIN
CD74
AC
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
UNIT
MAX
MAX
MAX
0.16
-24
24
0.16
-24
24
0.04
-8
8
0.04
-8
8
-6
6
0.02
-12
12
mA
mA
mA
ICC
IOH
IOL
PARAMETER
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
INPUT
OUTPUT
CLR LOW
CLK HIGH
CLK LOW
DATA INPUT
fmax
tw
tsu
S
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
CD74
AC
30
20
75
10
50
10
100
5
80
5
25
20
20
24
17
38
95
4
20
20
20
25
5
20
20
20
25
5
7
7
5
5
3
10
10
10
6
0
4
6
4
6
1
4
6
4.5
5
1
20
20
25
25
0
24
24
18
5
30
30
24
5
5.2
5.2
2
3
25
35
30
35
35
30
30
22
12
17
18
23
15
17
14
8
10
15
9
11
40
40
40
40
45
45
50
50
66
66
60
60
14.5
14.5
13.5
13.5
CLR
ANY Q
MAX
CLK
ANY Q
MAX
INPUT
OUTPUT
MAX or MIN
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
MIN
MIN
80
4
6.2
6.2
2
2.5
15.5
15.5
14
14
80
5
5
5
4.5
2.5
0.5
11
10.5
10.5
65
5
5
5
5
3.5
0
13
10
10
50
5
5
5
6
3
0
17
17
16.5
16.5
80
5
5
5
4.5
2.5
0.5
11
11
10.5
10.5
CLR LOW
CLK HIGH
CLK LOW
DATA INPUT
CLR INACTIVE
th
tPLH
CLR
tPHL
tPLH
CLK
tPHL
UNIT fmax : MHz, other : ns
240
LS
25
20
MIN
MIN
MIN
CLR INACTIVE
PARAMETER
TTL
MIN
MIN
MIN
th
tPLH
tPHL
tPLH
tPHL
MAX or MIN
MIN
MIN
MIN
MIN
ANY Q
MAX
ANY Q
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
175
QUAD D-TYPE FLIP-FLOPS
CLR
● Complementary Outputs (Q, Q)
● Buffered Clock and Direct Clear Inputs
● Asynchronous Clear Function
CLK
1D
1
9
4
2
1D
1Q
C1
3
R
1Q
FUNCTION TABLE
CLEAR
L
H
H
H
INPUTS
CLOCK
X
↑
↑
L
OUTPUTS
Q
Q
H
L
H
L
L
H
QO QO
D
X
H
L
X
To Three Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
S
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
AC
11
CD74
AC
CD74
ACT
LV
3V
LV
5V
UNIT
MAX
MAX
MAX
45
-0.8
16
18
-0.4
8
96
-1
20
14
-0.4
8
34
-2
20
34
-1
20
0.04
-4
4
0.16
-4
4
0.16
-4
4
0.08
-24
24
0.16
-24
24
0.16
-24
24
-6
6
0.02
-12
12
mA
mA
mA
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
OUTPUT
MAX or MIN
TTL
LS
S
ALS
AS
F
SN74
HC
CD74
HC
CD74
HCT
MIN
25
20
20
30
20
20
75
10
7
50
10
10
100
5
4
100
5
4
25
20
20
20
24
24
16
30
30
20
20
25
5
25
35
20
20
25
5
30
30
7
5
5
3
15
22
10
10
6
0
18
23
5
3
6
1
9
13
5
3
5
1
9
13
20
25
25
0
38
38
24
24
5
53
53
30
30
5
53
53
7.5
9.5
38
38
53
53
50
50
CLR LOW
CLK HIGH
MIN
CLK LOW
DATA INPUT
CLR INACTIVE
MIN
th
tPLH
tPHL
MIN
tPLH
tPHL
PARAMETER
fmax
tw
tsu
INPUT
CLR
ANY Q or Q
MAX
CLK
ANY Q or Q
MAX
30
35
25
25
12
17
15
17
7.5
10
INPUT
OUTPUT
MAX or MIN
AC
11
CD74
AC
CD74
ACT
LV
3V
LV
5V
MIN
125
4
4
4
5.5
5.5
0.5
6.8
9.3
6.9
9..3
100
4
5
5
2
2
12.2
12.2
12.2
12.2
114
4
5
5
2
2
13
13
11.5
11.5
45
5
5
5
5
5
1
15.5
15.5
17
17
75
5
5
5
4
5
1
9.5
9.5
10.5
10.5
CLR LOW
CLK HIGH
CLK LOW
DATA INPUT
CLR INACTIVE
th
tPLH
CLR
tPHL
tPLH
CLK
tPHL
UNIT fmax : MHz, other : ns
MIN
MIN
MIN
ANY Q or Q
MAX
ANY Q or Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
241
181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
● Full Look-Ahead for High-Speed Operations on Long Words
● Input Clamping Diodes Minimize Transmission-Line Effects
Logic Diagram
S3
S2
S1
S0
3
4
5
6
17
B3
16
A3
19
15
13
B2
A2
B1
A1
21
11
M
Cn
242
P
F3
F2
22
14
A=B
23
F1
1
9
A0
Cn + 4
20
10
B0
G
18
2
8
7
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
F0
FUNCTION TABLE (ACTIVE LOW)
S3 S2 S1 S0
FUNCTION TABLE (ACTIVE HIGH)
ACTIVE-LOW DATA
SELECTION
M=H
LOGIC
FUNCTION
Cn = L
(no carry)
Cn = H
(with carry)
L
L
L
F=A
F = A MINUS 1
F=A
L
L
L
L
H
L
L H
L
F = AB
F=A+B
F = AB MINUS 1
F = AB MINUS 1
F = AB
F = AB
L
L H H
F=1
F = MINUS 1(2's COMP)
F=0
L
L
L
H L L
H L H
H H L
F=A+B
F=B
F=A⊕B
F = A PLUS (A + B)
F = AB PLUS (A + B)
F = A MINUS B MINUS 1
L H H H
H L L L
H L L H
F=A+B
F = AB
F=A⊕B
L
L H
H
L H H
H H
H H
H H
H H
L L
L H
H L
H H
M = L; ARITHMETIC OPERATIONS
M=H
LOGIC
FUNCTION
S3 S2 S1 S0
L
H
ACTIVE-HIGH DATA
SELECTION
M = L; ARITHMETIC OPERATIONS
Cn = H
(no carry)
Cn = L
(with carry)
L
L
L
F=A
F=A
F = A PLUS 1
L
L
L
H
L
L H
L
F=A+B
F = AB
F=A+B
F=A+B
F = (A + B) PLUS 1
F = (A + B) PLUS 1
L
L H H
F=0
F = MINUS 1(2's COMPL)
F=0
F = A PLUS (A + B) PLUS 1
F = AB PLUS (A + B) PLUS 1
F = A MINUS B
L
L
L
H L L
H L H
H H L
F = AB
F=B
F=A⊕B
F = A PLUS AB
F = (A + B) PLUS AB
F = A MINUS B MINUS 1
F = A PLUS AB PLUS 1
F = (A + B) PLUS AB PLUS 1
F = A MINUS B
F=A+B
F = A PLUS (A + B)
F = A PLUS B
F = (A + B) PLUS 1
F = A PLUS (A + B) PLUS 1
F = A PLUS B PLUS 1
L H H H
H L L L
H L L H
F = AB
F=A+B
F=A⊕B
F = AB MINUS 1
F = A PLUS AB
F = A PLUS B
F = AB
F = A PLUS AB PLUS 1
F = A PLUS B PLUS 1
F=B
F = (A + B) PLUS AB
F = (A + B) PLUS AB PLUS 1
F = AB
F=1
F=A+B
F = AB MINUS 1
F = A PLUS A*
F = (A + B) PLUS A
F = AB
F = A PLUS A PLUS 1
F = (A + B) PLUS A PLUS 1
F=A+B
F=A
F = (A + B) PLUS A
F = A MINUS 1
F = (A + B) PLUS A PLUS 1
F=A
F=B
F = AB PLUS (A + B)
F = AB PLUS (A + B) PLUS 1
H
L H
F=A+B
F=0
F = AB
F = (A + B)
F = A PLUS A*
F = AB PLUS A
F = (A + B) PLUS 1
F = A PLUS A PLUS 1
F = AB PLUS A PLUS 1
H
L H H
F = AB
F=A
F = AB PLUS A
F=A
F = AB PLUS A PLUS 1
F = A PLUS 1
H H
H H
H H
H H
L
L L
L H
H L
H H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
All outputs except
A=B
G
All outputs except
G
MAX or MIN
TTL
LS
S
AS
UNIT
MAX
150
37
220
200
mA
-0.8
-0.4
-1
-2
mA
-
-
-
-3
mA
16
8
20
20
mA
16
8
20
48
mA
MAX
MAX
G
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
Cn
Cn 4
MAX
18
19
27
20
10.5
10.5
9
9
43
41
19
18
42
38
38
26
20
32
18.5
18.5
12
12
16.5
12
12
9
9
9.5
32
20
16.5
8
A, B
Cn 4
MAX
Cn
F
MAX
A i , Bi
Fi
MAX
AS
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
243
182
LOOK-AHEAD CARRY GENERATORS
Logic Diagram
(7)
(10)
P or X
G or Y
(6)
P3 or X3
(5)
G3 or Y3
(9)
(15)
P2 or X2
(14)
G2 or Y2
(11)
(2)
P1 or X1
(1)
G1 or Y1
(4)
P0 or X0
(3)
G0 or Y0
(13)
Cn or Cn
244
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(12)
Cn+z
or
Cn+z
Cn+y
or
Cn+y
Cn+x
or
Cn+x
FUNCTION TABLE
G OUTPUTS
Cn+x OUTPUTS
P OUTPUTS
INPUTS
OUTPUT
INPUTS
G3 G2 G1 P3 P2 P1 P0
G
L X X X X X X
L
X L X X L X X
L
L
X X L X L L X
L
X X X L L L L
All other combinations
H
P3 P2 P1 P0
L L L L
All other
combinations
Cn+y OUTPUTS
OUTPUT
P
L
H
INPUTS OUTPUT
Cn+x
G0 P0 Cn
L
X
X
H
X
L
H
H
All other
L
combinations
Cn+z OUTPUTS
INPUTS
OUTPUT
Cn+y
G0 P1 P0 Cn
X X X X
H
L L X X
H
X L L H
H
All other
L
combinations
G1
L
X
X
INPUTS
OUTPUT
Cn+z
G2 G1 G0 P2 P1 P0 Cn
L X X X X X X
H
X L X L X X X
H
X X L L L X X
H
X X X L L L H
H
L
All other combinations
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
S
AS
UNIT
MAX
MAX
MAX
72
-0.8
16
109
-1
20
36
-2
20
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
Cn
Cn + X, Cn + Y
or Cn + Z
MAX
P or G
Cn + X, Cn + Y
or Cn + Z
MAX
P or G
G
MAX
P
P
MAX
TTL
S
AS
10
10.5
7
7
10
10.5
7
7
10
9.5
10.5
6
7.5
10.5
6.5
10
7.5
10.5
6.5
10
12
8
7.5
6
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
245
190
SYNCHRONOUS UP/DOWN DECADE COUNTER
Logic Diagram
P0
P1
15
1
14
CP
B
5
C
U/D
11
D
E
F
G
H
I
PL
P
PL
T
P
Q
PL
T
Q
CL Q
CL Q
FF0
FF1
J
K
L
M
N
O
CE
4
P
3
2
Q0
Q1
P3
P2
9
10
13
B
RC
C
D
E
F
G
H
I
12
TC
P
J
T
PL
P
Q
PL
T
Q
CL Q
CL Q
FF2
FF3
K
L
M
N
O
P
6
7
Q2
246
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Q3
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
ALS
SN74
HC
CD74
HC
UNIT
ICC
MAX
105
35
22
0.08
0.16
mA
IOH
IOL
MAX
MAX
-0.8
16
-0.4
8
-0.4
8
-4
4
-4
4
mA
mA
MAX or MIN
TTL
LS
ALS
SN74
HC
CD74
HC
MIN
20
20
25
17
25
MIN
25
35
25
35
20
20
30
30
20
25
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
CLK (CP)
LOAD (PL)
Data , high or low
tsu
th
Data hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT
fmax : MHz
MIN
MIN
LOAD
(PL)
Q
MAX
DATA
Q
MAX
CLK
(CP)
RCO
(RC)
MAX
CLK
(CP)
Q
MAX
CLK
(CP)
MAX/MIN
(TC)
MAX
D/U
(U/D)
RCO
(RC)
MAX
D/U
(U/D)
MAX/ MIN
(TC)
MAX
20
0
20
5
20
5
38
5
15
2
33
33
30
66
49
50
50
30
66
49
22
50
32
40
21
21
60
60
44
44
20
24
24
36
42
20
24
24
36
42
20
20
18
18
31
30
30
48
48
63
31
31
43
43
53
52
45
45
33
33
52
45
45
33
33
31
37
28
25
25
63
57
57
48
48
53
38
38
41
41
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
247
191
SYNCHRONOUS UP/DOWN COUNTERS
● Count Enable Control Input
● Ripple Clock Output for Cascading
● Asynchronously Presentable with Load Control
Logic Diagram
12
CTEN
D/U
4
13
5
CLK
14
LOAD
11
A
15
S
3
C1
1D
R
B
2
C1
1D
R
6
C1
1D
R
QB
QC
9
S
C1
1D
R
248
QA
10
S
D
RCO
1
S
C
MAX/MIN
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
7
QD
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
ALS
SN74
HC
CD74
HC
CD74
HCT
UNIT
ICC
IOH
MAX
MAX
105
-0.8
35
-0.4
22
-0.4
0.08
-4
0.16
-4
0.16
-4
mA
mA
IOL
MAX
16
8
8
4
4
4
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
MAX or MIN
TTL
LS
ALS
SN74
HC
CD74
HC
CD74
HCT
MIN
20
20
30
17
25
25
tw
CLK
LOAD
MIN
25
35
25
35
16.5
20
30
30
20
25
20
25
tsu
DATA
MIN
20
20
20
38
15
15
th
tPLH
DATA
MIN
0
33
5
33
5
30
5
66
2
49
2
50
50
22
50
20
24
50
32
40
20
24
30
21
21
20
20
66
60
60
30
30
49
44
44
31
31
50
48
48
34
34
24
36
42
52
45
24
36
42
52
45
18
18
31
31
37
48
48
63
63
57
43
43
53
53
38
44
44
53
53
38
45
33
33
45
33
33
28
25
25
57
48
48
38
41
41
38
48
48
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
LOAD
QA, QB
QC, QD
MAX
DATA
A, B, C, D
QA, QB
QC, QD
MAX
CLK
RIPPLE
CLK
MAX
CLK
QA, QB
QC, QD
MAX
CLK
MAX or MIN
MAX
D/U
RIPPLE
CLK
MAX
MAX or MIN
MAX
tPHL
tPLH
D/U
tPHL
UNIT fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
249
192
PRESETTABLE SYNCHRONOUS 4-BITUP/DOWN COUNTERS
Logic Diagram
(13)
(12)
DATA
INPUT A
DOWN
UP
DATA
INPUT B
BO
CO
(15)
(4)
(5)
S
(3)
OUTPUT QA
T
R
(1)
S
(2)
OUTPUT QB
T
R
DATA
INPUT C
(10)
S
(6)
OUTPUT QC
T
R
DATA
INPUT D
CLR
(9)
(14)
S
T
R
LOAD
250
(11)
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(7)
OUTPUT QD
FUNCTION TABLE
CLOCK UP
CLOCK
DOWN
RESET
PARALLEL
LOAD
↑
H
L
H
Count Up
FANCTION
H
↑
L
H
Count Down
X
X
H
X
Reset
X
X
L
L
Load Preset inputs
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care, ↑ = Transition from Low to High Level
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
CD74
UNIT
HC
ICC
MAX
0.16
IOH
MAX
-4
mA
mA
IOL
MAX
4
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN CD74
HC
CPU, CPD
tw
PL
MR
MIN
tsu
Pn to PL
Pn to PL
CPD to CPU, CPD to CPU
MIN
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
UNIT:ns
MIN
CPU
TCU
MAX
CPD
TCD
MAX
CPD
Qn
MAX
CPD
Qn
MAX
PL
Qn
MAX
MR
Qn
MAX
35
24
30
24
0
24
38
38
38
38
65
65
65
65
66
66
60
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
251
193
SYNCHRONOUS UP/DOWN DUAL CLOCKCOUNTERS
● Parallel Asynchronous Load for Modulo-N Count Lengths
● Asynchronous Clear
Logic Diagram
12
13
CLR
UP
DOWN
LOAD
A
5
4
11
15
S
R
S
3
2
C1
1D
R
6
C1
1D
R
QC
9
S
C1
1D
R
252
QB
10
S
D
QA
1
S
C
BO
14
C1
1D
R
B
CO
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
7
QD
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
ALS
F
SN74
HC
CD74
HC
CD74
HCT
UNIT
ICC
IOH
MAX
MAX
102
-0.4
34
-0.4
22
-0.4
54
-1
0.08
-4
0.16
-4
0.16
-4
mA
mA
IOL
MAX
16
8
8
20
4
4
4
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
ALS
F
SN74
HC
CD74
HC
CD74
HCT
fmax
MIN
25
25
30
85
17
17
15
tw
tsu
DATA
MIN
MIN
20
20
20
20
20
20
4
3.5
30
28
30
24
35
22
th
DATA
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
MIN
0
5
5
2.5
5
0
0
UP
CO
MAX
26
24
26
24
16
18
9
9
41
41
38
38
41
41
DOWN
BO
MAX
UP or
DOWN
ANY Q
MAX
LOAD
ANY Q
MAX
24
24
38
47
40
24
24
38
47
40
16
18
19
17
30
9
9
9
13
11
41
41
63
63
65
38
38
65
65
66
41
41
60
60
69
ANY Q
MAX
40
35
40
35
28
17
13
12
65
60
66
60
69
65
tPHL
tPHL
CLR
UNIT fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
253
194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
● Direct Overriding Clear
● Parallel-to-Serial, Serial-to-Parallel Conversions
● Left or Right Shifts
Logic Diagram
Parallel Inputs
A
S1
S0
SR SER
10
D
3
6
9
2
7
Two
Identical
Channels
Not
Shown†
1S
CLK
CLR
C1
1R
R
R
11
1
15
12
QA
QD
Parallel Outputs
† I/O ports not shown: QB (14) and QC (13)
254
1S
C1
1R
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
SL SER
FUNCTION TABLE
INPUTS
MODE
SERIAL
CLEAR
CLOCK
S1 S0
LEFT RIGHT
L
X X
X
X
X
H
X
X X
L
X
H
↑
X
H H
X
H
↑
X
H
L H
H
L H
↑
X
L
H
X
H L
↑
H
H L
H
X
↑
L
L L
H
X
X
X
OUTPUTS
PARALLEL
A B C D
X X X X
X X X X
a b c d
X X X X
X X X X
X X X X
X X X X
X X X X
QA QB QC QD
L
QA0
a
H
L
QBn
QBn
QA0
L
QB0
b
QAn
QAn
QCn
QCn
QB0
L
QC0
c
QBn
QBn
QDn
QDn
QC0
L
QD0
d
QCn
QCn
H
L
QD0
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
S
AS
SN74
HC
CD74
HC
CD74
HCT
UNIT
ICC
MAX
63
23
135
53
0.1
0.16
0.16
mA
IOH
IOL
MAX
MAX
-0.8
16
-0.4
8
-1
20
-2
20
-4
4
-4
4
-4
4
mA
mA
MAX or MIN
TTL
LS
S
AS
SN74
HC
CD74
HC
CD74
HCT
MIN
25
20
25
20
70
12
80
4.5
25
20
20
24
18
24
MIN
20
20
30
20
25
20
20
30
20
25
7
7
11
5
9
4
7
9.5
4
6
20
20
25
25
-
24
24
24
21
-
24
24
30
21
-
0
30
22
26
0
30
22
26
3
18.5
12
16.5
0.5
12
7
7
0
38
36
36
0
42
53
53
0
60
56
56
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
INPUT
OUTPUT
CLR
CLK "H"
CLK "H"
Mode Control
DATA
CLR INACTIVE
th
tPHL
tPLH
tPHL
UNIT fmax : MHz, other : ns
MIN
CLEAR
ANY
MIN
MAX
CLOCK
ANY
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
255
195
4-BIT PARALLEL-ACCESS SHIFT REGISTERS
● Direct Overriding Clear
● Parallel-to-Serial, Serial-to-Parallel Conversions
Logic Diagram
Serial Inputs
J
2
SH/ LD
CLK
CLR
Parallel Inputs
K
3
B
A
4
C
5
D
6
7
9
10
1
R
1R
R
1R
C1
R
1R
C1
1S
C1
1S
15
QA
R
1R
C1
1S
14
QB
1S
13
QC
Parallel Outputs
256
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
12
QD
11
QD
FUNCTION TABLE
INPUTS
SERIAL
SHIFT/
CLEAR LOAD CLOCK
J K
X
L
X
X X
H
L
↑
X X
L
X X
H
H
↑
L H
H
H
H
H
↑
L L
H
H
↑
H H
H
H
↑
H L
OUTPUTS
PARALLEL
A
X
a
X
X
X
X
X
B
X
b
X
X
X
X
X
C
X
c
X
X
X
X
X
QA QB QC QD QD
D
L
L
X L
c
b
d a
X QA0 QB0 QC0
X QA0 QA0 QBn
X L QAn QBn
X H QAn QBn
X QAn QAn QBn
L
d
QD0
QCn
QCn
QCn
QCn
H
d
QD0
QCn
QCn
QCn
QCn
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
S
AS
SN74
HC
CD74
HC
UNIT
ICC
MAX
63
21
109
57
0.1
0.16
mA
IOH
IOL
MAX
MAX
-0.8
16
-0.4
8
-1
20
-2
20
-4
4
-4
4
mA
mA
MAX or MIN
TTL
LS
S
MIN
30
16
30
16
12
25
20
25
10
12
25
15
25
20
0
30
22
26
0
30
22
26
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
INPUT
OUTPUT
CLOCK
MIN
CLEAR
tsu
Shift / Load
Serial & Pararel Data
Clear Inactive Data
TRELEASE
th
tPHL
tPLH
tPHL
UNIT fmax : MHz, other : ns
MIN
MAX
MIN
MAX
CLEAR
CLOCK
QA, QD
MAX
AS
SN74
HC
CD74
HC
70
7
70
4
25
20
20
24
12
11
5
9
6
7.2
8
3.5
6
-
20
25
25
25
-
24
30
30
30
-
3
18.5
12
16.5
1
11.5
8.5
10.5
0
38
36
36
45
53
53
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
257
221
DUAL MONOSTABLE MULTIVIBRATORS
● Overriding Clear Terminates Outputs Pulse
Logic Diagram
Rext/Cext
A
Cext
B
Q
CLR
258
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
R
Q
FUNCTION TABLE
INPUTS
CLEAR
L
X
X
H
H
↑
OUTPUTS
A
X
H
X
L
↓
L
Q
L
L†
L†
B
X
X
L
↑
H
H
Q
H
H†
H†
See explanation of function table on page
† These lines of the functional tables assume that the indicated
steady-state conditions at the A and B inputs have been
set up long enough to complete any pulse started before the set up.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CD74 CD74
HC HCT
MAX or MIN
TTL
LS
ICC
IOH
MAX
MAX
80
-0.8
27
-0.4
0.16
-4
IOL
MAX
16
8
4
LV
3V
LV
5V
UNIT
0.16
-4
0.28
-6
0.65
-12
mA
mA
4
6
12
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
tPLH
A (HC, LV: A)
B
Q
MAX
tPHL
A (HC, LV: A)
B
Q
MAX
tPHL
tPLH
UNIT: ns
Clear
Q
Q
MAX
TTL
LS
70
55
80
70
55
80
CD74 CD74
HC HCT
63
63
51
LV
3V
LV
5V
63
63
51
27.5
27.5
27.5
16
16
16
65
65
51
51
27.5
16
27
40
55
65
48
54
57
56
22
22
13
13
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
259
237
3-TO-8 LINE DECODER DEMULTIPLEXER WITH ADDRESS LATCHES
Logic Diagram
GL
A
(4)
(1)
TG
(15)
TG
(14)
Y0
Y1
TG
(13)
B
(2)
TG
(12)
TG
C
(3)
TG
(11)
(10)
(9)
G1
G2
260
Y2
Y3
Y4
Y5
Y6
(6)
(7)
(5)
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Y7
FUNCTION TABLE
INPUTS
LE
X
X
L
L
L
L
L
L
L
L
H
OE0
X
L
H
H
H
H
H
H
H
H
H
OUTPUTS
A2
X
X
L
L
L
L
H
H
H
H
X
OE1
H
X
L
L
L
L
L
L
L
L
L
A0
X
X
L
H
L
H
L
H
L
H
X
A1
X
X
L
L
H
H
L
L
H
H
X
Y7
Y5
Y6
Y1
Y4
Y3
Y2
Y0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
Depends upon the address previously applied while LE was at a logic low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
SN74 CD74 CD74
UNIT
HC
HC HCT
ICC
MAX
0.08
0.16
0.16
IOH
MAX
-4
-4
-4
mA
mA
IOL
MAX
4
4
4
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
LE Pulse Width
An to LE
An to LE
MAX or MIN
MIN
MIN
MIN
An
Y
MAX
OE
Y
MAX
SN74 CD74 CD74
HC
HC HCT
20
19
5
15
15
9
15
15
5
48
48
44
44
48
48
44
44
57
57
60
60
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
261
238
3-TO-8-LINE DECODERS/DEMULTIPLEXERS
Logic Diagram
E3
E2
E1
(6)
(5)
(15)
(4)
(14)
A0
A1
(1)
(13)
(2)
(12)
A2
Y0
Y1
Y2
Y3
(11)
(3)
Y4
(10)
Y5
(9)
Y6
(7)
262
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Y7
FUNCTION TABLE
INPUTS
E2
X
X
H
L
L
L
L
L
L
L
L
OUTPUTS
ADDRESS
ENABLE
E3
X
L
X
H
H
H
H
H
H
H
H
E1
H
X
X
L
L
L
L
L
L
L
L
A2
X
X
X
L
L
L
L
H
H
H
H
A1
X
X
X
L
L
H
H
L
L
H
H
A0
X
X
X
L
H
L
H
L
H
L
H
Y1
L
L
L
L
H
L
L
L
L
L
L
Y0
L
L
L
H
L
L
L
L
L
L
L
Y2
L
L
L
L
L
H
L
L
L
L
L
Y3
L
L
L
L
L
L
H
L
L
L
L
Y4
L
L
L
L
L
L
L
H
L
L
L
Y5
L
L
L
L
L
L
L
L
H
L
L
Y6
L
L
L
L
L
L
L
L
L
H
L
Y7
L
L
L
L
L
L
L
L
L
L
H
Note: H = High Voltage Level, L = Low Volltage Level, X = Don’t Care
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN CD74 CD74 CD74 CD74 UNIT
HC HCT AC ACT
ICC
IOH
MAX
MAX
0.16
-4
0.16
-4
0.16
-24
0.16
-24
mA
mA
IOL
MAX
4
4
24
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT:ns
MAX or MIN CD74 CD74 CD74 CD74
HC HCT AC ACT
INPUT
OUTPUT
Address
Y
MAX
E1, E2
Y
MAX
E3
Y
MAX
45
45
-
53
53
-
15
15
11.9
11.9
16.6
15
15
11.9
11.9
16.6
-
-
16.6
16.6
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
263
240
OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
●
●
●
●
3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
PNP Inputs Reduce DC Loading
74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
1OE
1A1
1A2
1A3
1A4
264
1
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
S
ALS
ALS
A-1
AS
F
ICCH
MAX
27
135
11
11
17
29
0.08
0.16
0.08
0.16
31
ICCL
ICCZ
MAX
MAX
44
50
150
150
23
25
23
25
75
38
75
63
0.08
0.08
0.16
0.16
0.08
0.08
0.16
0.16
71
9
IOH
MAX
-15
-15
-15
-15
-15
-15
-6
-6
-6
-6
IOL
MAX
24
64
24
48
64
64
6
6
6
PARAMETER
PARAMETER
MAX or MIN LVTH
3V
AC
11
SN74 CD74 SN74 CD74 SN74 ABT
HC
HC HCT HCT BCT
SN74 CD74 ACT SN74 CD74 AHC AHCT
AC
AC
11
ACT ACT
LVT
3V
UNIT
0.25
0.19
mA
30
0.25
5
0.19
mA
mA
-15
-32
-32
mA
6
64
64
64
mA
LV
3V
LV
5V
LVC
3V
LVCZ UNIT
3V
ICCH
ICCL
MAX
MAX
0.19
5
0.08
0.08
0.04
0.04
0.16
0.16
0.08
0.08
0.04
0.04
0.16
0.16
0.04
0.04
0.04
0.04
-
0.02
0.02
0.01
0.01
0.1
0.1
mA
mA
ICCZ
MAX
0.19
0.08
0.04
0.16
0.08
0.04
0.16
0.04
0.04
-
0.02
0.01
0.1
mA
IOH
IOL
MAX
MAX
-32
64
-24
24
-24
24
-24
24
-24
24
-24
24
-24
24
-8
8
-8
8
-8
8
-16
16
-24
24
-24
24
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
LS
S
ALS
ALS
A-1
AS
F
14
18
23
30
7
7
10
15
9
9
13
18
9
9
13
18
6.5
6.5
6.4
9
8
5.7
6.1
10
25
25
38
38
30
30
-
32
32
44
44
33
33
-
5.6
4
8.8
10.5
4.8
4.8
5.2
6.2
3.8
4
4.6
4.4
MAX
25
20
9
15
10
12
10
12
5
9.5
6.3
9.5
38
38
-
44
44
-
8.1
9.5
6.4
5.8
4.4
4.3
OUTPUT
MAX or MIN
LVTH
3V
AC
11
LV
3V
LV
5V
LVC
3V
LVCZ
3V
Y
MAX
3.8
4
8.4
7.2
7
6.5
7.2
7.2
10.6
8.7
9.5
8.5
8.6
8.6
8.5
8.5
9.5
9.5
12.5
12.5
8.5
8.5
6.5
6.5
6.5
6.5
4.6
4.4
4.4
4.3
9.2
8.7
6.6
7.7
8
8.5
9.5
9.5
12
12
12
12
12.5
12.3
10
10.8
9.5
10.5
10.5
10.5
13.4
13.4
13.4
13.4
10.5
10.5
10.5
10.5
13
13
13
13
16
16
17
17
10.5
10.5
15.5
15.5
8
8
7
7
8
8
7
7
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
G
Y
MAX
G
Y
INPUT
A
G
Y
MAX
G
Y
MAX
SN74 CD74 SN74 CD74 SN74 ABT
HC
HC HCT HCT BCT
SN74 CD74 ACT SN74 CD74
AHC AHCT
AC
AC
11
ACT ACT
LVT
3V
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
265
241
OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
● 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
● PNP Inputs Reduce DC Loading
Logic Diagram
1OE
1A1
1A2
1A3
1A4
266
1
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 CD74 SN74 ABT LVTH SN74 UNIT
HC
HC HCT BCT
3V
AC
MAX or MIN
LS
S
ALS
AS
F
ICCH
MAX
27
160
18
35
60
0.08
0.16
0.16
43
0.25
0.19
0.04
mA
ICCL
ICCZ
MAX
MAX
46
54
180
180
26
30
90
56
90
90
0.08
0.08
0.16
0.16
0.16
0.16
85
10
30
0.25
5
0.19
0.04
0.04
mA
mA
IOH
MAX
-15
-15
-15
-15
-15
-6
-6
-6
-15
-32
-32
-24
mA
IOL
MAX
24
64
24
64
64
6
6
6
64
64
64
24
mA
PARAMETER
MAX or MIN SN74 CD74 UNIT
ACT ACT
ICCH
ICCL
MAX
MAX
0.04
0.04
0.16
0.16
mA
mA
ICCZ
MAX
0.04
0.16
mA
IOH
IOL
MAX
MAX
-24
24
-24
24
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
1G
Y
MAX
1G
Y
MAX
2G
Y
MAX
2G
Y
MAX
INPUT
OUTPUT
A
Y
MAX
1G
Y
MAX
1G
Y
MAX
2G
Y
MAX
2G
Y
MAX
SN74 CD74 CD74 SN74 ABT LVTH SN74
HC
HC HCT BCT
3V
AC
LS
S
ALS
AS
F
18
18
23
30
25
9
9
12
15
9
11
10
21
21
10
6.2
6.2
9
7.5
6
6.2
6.5
6.7
8
7
29
29
38
38
38
33
33
-
38
38
-
4.9
5.9
8.7
9.4
8.1
4.6
4.6
6.8
6.8
7.1
3.5
3.4
4.5
4.4
4.5
7.5
7.5
9.5
9.5
10.5
20
23
30
25
20
15
12
15
9
15
15
21
21
10
15
9
10.5
8.5
7
12
7
6.7
8
7
7
38
38
38
38
38
-
-
9.9
8.7
9.4
8.1
9.9
5.9
6.8
6.8
7.1
5.9
4.7
4.5
4.4
4.5
4.7
10.5
9.5
9.5
10.5
10.5
MAX or MIN SN74 CD74
ACT ACT
9.5
8.5
9.5
10.5
9.6
9.6
13.4
13.4
10.5
10.5
9.5
10.5
10.5
13.4
13.4
13.4
13.4
13.4
10.5
13.4
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
267
243
QUADRUPLE BUS TRANSCEIVERS
● Two-Way Asynchronous Communication Between Data Buses
● PNP Inputs Reduce DC Loading
Logic Diagram
OEAB
A1
A2
A3
A4
268
1
13
3
11
4
10
5
9
6
8
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OEBA
B1
B2
B3
B4
FUNCTION TABLE
INPUTS
OPERATION
GAB
GBA
L
H
H
L
L
H
L
H
A to B
B to A
Isolation
Latch A and B (A = B)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 CD74
UNIT
HC
HC HCT
MAX or MIN
LS
ALS
AS
ICCH
MAX
38
25
44
0.08
0.16
0.16
mA
ICCL
MAX
50
30
74
0.08
0.16
0.16
mA
ICCZ
IOH
MAX
MAX
54
-15
32
-15
56
-
0.08
-
0.16
-6
0.16
-6
mA
mA
IOL
MAX
24
24
64
6
6
6
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
SN74 CD74 CD74
HC
HC HCT
INPUT
OUTPUT
MAX or MIN
LS
ALS
AS
A or B
A or B
A or B
A or B
MAX
MAX
GAB
B
MAX
18
18
23
30
11
11
20
20
7.5
6.5
9
7.5
25
25
38
38
27
27
45
45
33
33
51
51
GAB
B
MAX
GAB
A
MAX
GAB
A
MAX
25
20
23
30
25
14
22
20
20
14
6.5
9
10.5
8.5
7
38
38
38
38
38
45
45
45
45
45
53
53
51
51
53
20
22
11
38
45
53
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
269
244
OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
●
●
●
●
3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
PNP Inputs Reduce DC Loading
74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
1OE
1A1
1A2
1A3
1A4
270
1
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
S
ALS
ALS
C-1
AS
F
ICCH
MAX
27
160
17
17
34
60
0.08
0.16
0.08
0.16
40
40
0.25
0.19
0.19
0.19 0.225
mA
ICCL
ICCZ
MAX
MAX
46
54
180
180
24
27
24
27
90
54
90
90
0.08
0.08
0.16
0.16
0.08
0.08
0.16
0.16
80
10
80
10
30
0.25
5
0.19
5
0.19
12
15
0.19 0.225
mA
mA
IOH
MAX
-15
-15
-15
-15
-15
-15
-6
-6
-6
-6
-15
-15
-32
-32
-32
-32
-32
mA
IOL
MAX
24
64
24
48
64
64
6
6
6
6
64
64
64
64
64
64
64
mA
MAX or MIN
AC
11
LV
3V
LV
5V
LVC LVCH LVCZ ALVC ALVCH UNIT
3V
3V
3V
3V
3V
ICCH
ICCL
MAX
MAX
0.08
0.08
0.04
0.04
0.16
0.16
0.08
0.08
0.04
0.04
0.16
0.16
0.04
0.04
0.04
0.04
-
0.02
0.02
0.01
0.01
0.01
0.01
0.1
0.1
0.01
0.01
0.01
0.01
mA
mA
ICCZ
MAX
0.08
0.04
0.16
0.08
0.04
0.16
0.04
0.04
-
0.02
0.01
0.01
0.1
0.01
0.01
mA
IOH
IOL
MAX
MAX
-24
24
-24
24
-24
24
-24
24
-24
24
-24
24
-8
8
-8
8
-8
8
-16
16
-24
24
-24
24
-24
24
-24
24
-24
24
mA
mA
PARAMETER
PARAMETER
SN74 CD74 SN74 CD74 SN74 SN64 ABT
HC
HC HCT HCT BCT BCT
SN74 CD74 ACT SN74 CD74 AHC AHCT
AC
AC
11
ACT ACT
LVT
3V
LVTH LVTT LVTZ UNIT
3V
3V
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
G
Y
MAX
G
Y
MAX
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
G
Y
MAX
G
Y
MAX
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
G
Y
MAX
G
Y
MAX
LS
S
ALS
ALS
C-1
AS
F
18
18
23
30
25
9
9
12
15
9
10
10
20
20
10
10
10
20
20
10
6.2
6.2
9
7.5
6
6.2
6.5
6.7
8
7
29
29
38
38
38
33
33
-
35
35
44
44
44
38
38
-
5
5.5
8.7
8.9
7.7
5.3
6
9
9.4
8
4.6
4.6
5.1
6.1
6.6
20
15
13
13
9
7
38
-
44
-
8.9
9.8
5.7
LVT
3V
LVTH LVTT LVTZ
3V
3V
AC
11
SN74 CD74 SN74 CD74 SN74 SN64 ABT
HC
HC HCT HCT BCT BCT
SN74 CD74 ACT SN74 CD74 AHC AHCT
AC
AC
11
ACT ACT
LV
3V
3.5
3.3
4.5
3.5
3.3
4.5
4.1
4.1
5.2
4.1
4.1
5.2
7.3
6.9
8.5
7.5
7.5
8
8.2
8.2
12
9.9
9.2
12.5
10
10
9.5
9.6
9.6
13.4
8.5
8.5
10.5
9.5
9.5
13
13.5
13.5
16
4.4
4.4
4.4
4.4
4.4
4.4
5.2
5.6
5.1
5.2
5.6
5.1
8.5
7.3
8.2
8.5
9.5
9.5
12
12
12
11.4
10.4
11.2
10.5
10.5
10.5
13.4
13.4
13.4
10.5
10.5
10.5
13
13
13
16
18
18
LV
5V
LVC LVCH LVCZ ALVC ALVCH
3V
3V
3V
3V
3V
8.5
5.9
5.9
5.9
2.8
2.8
8.5
10.5
10.5
15.5
15.5
5.9
7.6
7.6
6.5
6.5
5.9
7.6
7.6
5.8
5.8
5.9
7.6
7.6
6.5
6.5
2.8
4.5
4.5
4.2
4.2
2.8
4.5
4.5
4.2
4.2
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
271
Logic Diagram
245
OCTAL BUS TRANSCEIVERS
DIR
1
19
● 3-State Outputs Drive Bus Lines Directly
● PNP Inputs Reduce DC Loading on Bus Lines
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
A1
OE
2
18
B1
To Seven Other Channels
FUNCTION TABLE
ENABLE
G
DIRECTION
CONTROL
DIR
OPERATION
L
L
H
L
H
X
B data to A bus
A data to B bus
Isolation
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
ALS
ALS
C-1
ICCH
MAX
70
45
45
97
90
0.08
0.16
0.08
0.16
57
57
0.25
0.25
0.19
0.19
0.19
mA
ICCL
ICCZ
IOH (A port)
IOH (B port)
IOL (A port)
MAX
MAX
MAX
MAX
MAX
90
95
-15
-15
24
55
58
-15
-15
24
55
58
-15
-15
48
143
123
-15
-15
64
120
110
-3
-15
24
0.08
0.08
-6
6
-6
0.16
0.16
-4
-4
4
0.08
0.08
-6
-6
6
0.16
0.16
-4
-4
4
90
15
-3
-15
24
90
15
-3
-15
24
30
0.25
-32
-32
64
30
0.25
-32
-32
64
5
0.19
-32
-32
64
5
0.19
-32
-32
64
12
0.19
-12
-32
32
mA
mA
mA
mA
mA
IOL (B port)
MAX
24
24
48
64
64
6
4
6
4
64
64
64
64
64
64
32
mA
MAX or MIN
AC
11
LV
3V
LV
5V
LVC LVCH LVCZ ALVC ALVCH UNIT
3V
3V
3V
3V
3V
ICCH
ICCL
ICCZ
MAX
MAX
MAX
0.08
0.08
0.08
0.04
0.04
0.04
0.16
0.16
0.16
0.08
0.08
0.08
0.04
0.04
0.04
0.16
0.16
0.16
0.04
0.04
0.04
0.04
0.04
0.04
-
0.02
0.02
0.02
0.01
0.01
0.01
0.01
0.01
0.01
0.1
0.1
0.1
0.01
0.01
0.01
0.01
0.01
0.01
mA
mA
mA
IOH (A port)
IOH (B port)
IOL (A port)
IOL (B port)
MAX
MAX
MAX
MAX
-24
-24
24
24
-24
-24
24
24
-24
-24
24
24
-24
-24
24
24
-24
-24
24
24
-24
-24
24
24
-8
-8
8
8
-8
-8
8
8
-8
-8
8
8
-16
-16
16
16
-24
-24
24
24
-24
-24
24
24
-24
-24
24
24
-24
-24
24
24
-24
-24
24
24
mA
mA
mA
mA
PARAMETER
PARAMETER
272
AS
F
SN74 CD74 SN74 CD74 SN74 SN64
LVT
ABT ABTH
HC
HC HCT HCT BCT BCT
3V
SN74 CD74 ACT SN74 CD74 AHC AHCT
AC
AC
11
ACT ACT
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
LVTH LVTR
UNIT
3V
3V
SWITCHING CHARACTERISTICS
PARAMETER
LS
ALS
ALS
C-1
AS
F
SN74 CD74 SN74 CD74 SN74 SN64 ABT ABTH
HC
HC HCT HCT BCT BCT
12
10
10
7.5
7
26
33
28
39
7
7
3.6
3.6
12
40
10
20
10
20
7
9
7
8
26
58
33
45
28
58
39
48
7
10.9
7
10.9
3.9
5.6
3.9
5.6
58
48
11.6
11.6
6.2
6.2
50
50
45
45
9.3
9.1
9.3
9.1
5.9
4.5
5.9
4.5
LV
3V
LV
5V
LVC
3V
INPUT
OUTPUT
MAX or MIN
A, B
B, A
MAX
G
A, B
MAX
40
20
20
8.5
9
58
45
G
A, B
MAX
28
25
10
15
10
15
5.5
9.5
7.5
7.5
50
50
45
45
INPUT
OUTPUT
MAX or MIN
LVT
3V
LVTH
3V
AC
11
A, B
B, A
MAX
tPZH
tPZL
G
A, B
tPHZ
tPLZ
G
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tPLH
tPHL
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tPLH
tPHL
SN74 CD74 ACT SN74 CD74
AHC AHCT
AC
AC
11
ACT ACT
3.5
3.5
9.5
7
8.5
10
8
10
8.5
9.5
13.5
8.5
6.3
3.5
3.5
6.9
7
8.5
9.1
9
10
8.5
9.5
13.5
8.5
6.3
MAX
5.5
5.5
5.5
5.5
11.4
9.5
9
9.5
14
14
13.2
12.9
11
12
14
14
12
12
16
16
19
19
12
12
8.5
8.5
A, B
MAX
5.9
5
5.9
5
9.5
10.4
10
10
14
14
12.9
13.9
11
11
14.4
14.4
11
11
16.5
16.5
22
22
16
16
7.5
7.5
INPUT
OUTPUT
MAX or MIN
A, B
B, A
MAX
G
A, B
MAX
G
A, B
MAX
INPUT
OUTPUT
MAX or MIN
A
B
A
B
A
B
B
A
B
A
B
A
B
tPZH
G
tPZL
G
tPHZ
G
tPLZ
G
A
B
A
MAX
MAX
MAX
MAX
MAX
MAX
LVCH LVCZ ALVC ALVCH
3V
3V
3V
3V
6.3
6.3
6.3
6.3
3.4
3.4
3.4
3.4
8.5
8.5
7.5
7.5
8.5
8.5
7.5
7.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
LVTR
3V
4.2
4.4
4.6
4.1
5.5
6
6.6
6.4
6.1
5.8
5.2
5.2
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
273
247
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS WITH RIPPLE BLANKING
● Open-Collector Outputs Drive Indicators Directly
● Lamp-Test Provision
● Leading/Trailing Zero Suppression
Logic Diagram
(13) OUTPUT
a
INPUT (7)
A
INPUT (1)
B
INPUT (2)
C
INPUT (8)
D
BI/RBO
(4)
BLANKING
INPUT OR
RIPPLE-BLANKING
OUTPUT
(12) OUTPUT
b
(11) OUTPUT
c
(10) OUTPUT
d
(9) OUTPUT
e
(15) OUTPUT
f
LAMP TEST (3)
INPUT
(5)
RBI
RIPPLE-BLANKING
INPUT
274
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(14) OUTPUT
g
FUNCTION TABLE
DECIMAL
OR
FUNCTION
INPUTS
OUTPUTS
BI/RBO
0
1
2
3
LT
H
H
H
H
RBI
H
X
X
X
D
L
L
L
L
C
L
L
L
L
B
L
L
H
H
A
L
H
L
H
H
H
H
H
a
ON
OFF
ON
ON
4
5
6
7
H
H
H
H
X
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
OFF ON
ON OFF
ON OFF
ON ON
8
9
10
11
12
13
14
15
BI
RBI
LT
H
H
H
H
H
H
H
H
X
H
L
X
X
X
X
X
X
X
X
X
L
X
H
H
H
H
H
H
H
H
X
L
X
L
L
L
L
H
H
H
H
X
L
X
L
L
H
H
L
L
H
H
X
L
X
L
H
L
H
L
H
L
H
X
L
X
H
H
H
H
H
H
H
H
L
L
H
ON
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
b
ON
ON
ON
ON
g
f
e
d
c
ON ON ON ON OFF
ON OFF OFF OFF OFF
OFF ON ON OFF ON
ON ON OFF OFF ON
ON
ON
ON
ON
ON ON
ON ON
OFF OFF
OFF ON
ON OFF
OFF OFF
OFF OFF
OFF OFF
OFF OFF
OFF OFF
ON ON
OFF OFF ON
ON OFF ON
ON ON ON
OFF OFF OFF
ON ON ON
ON OFF ON
ON ON OFF
ON OFF OFF
OFF OFF ON
ON OFF ON
ON ON ON
OFF OFF OFF
OFF OFF OFF
OFF OFF OFF
ON ON ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
ON
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
VO (off)
IO (on)
IOH
IOL
a thru g
BI/RBO
MAX or MIN
TTL
LS
UNIT
MAX
MAX
MAX
MAX
103
15
40
-0.2
13
15
24
-0.05
mA
V
mA
mA
MAX
8
3.2
mA
TTL
LS
100
100
100
100
100
100
100
100
SWITCHING CHARACTERISTICS
PARAMETER
toff
ton
toff
ton
UNIT: ns
MAX or MIN
INPUT A
MIN
INPUT RBI
MIN
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
275
250
1-OF-16 DATA SELECTOR/MULTIPLEXER
● 4-Line to 1-Line Multiplexers That Can Select 1-of-16 Data Inputs
● Applications:
Boolean Function Generator
Parallel-to-Serial Converter
Data Source Selector
● Buffered 3-State Bus Driver Inputs Permit Multiplexing From n Lines to One Line
● 3-State Outputs
Logic Diagram
E0
E1
E2
E3
E4
E5
E6
E7
Data
Inputs
E8
E9
E10
E11
E12
E13
E14
E15
A
8
7
6
5
4
3
2
1
10
23
22
21
20
19
18
17
16
15
A
A
Data
Selects
B
14
B
B
C
13
C
C
D
11
D
D
OE
276
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
W
FUNCTION TABLE
INPUTS
G
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
OUTPUT
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
Ei
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
X
W
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
AS
UNIT
ICC
IOH
MAX
MAX
50
-15
mA
mA
IOL
MAX
48
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
AS
DATA
W
MAX
8
7
SELECT
W
MAX
G
W
MAX
G
W
MAX
13
10.5
7
9
6
6.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
277
251
DATA SELECTORS/MULTIPLEXERS
●
●
●
●
3-State Version of '151
3-State Outputs Interface Directly with System Bus
Perform Parallel-to-Serial Conversion
Complementary Outputs Provide True and Inverted Data
Logic Diagram
OE
D0
D1
D2
D3
Data
Inputs
D5
D6
D7
A
B
C
278
4
3
2
1
5
D4
Data
Select
(binary)
7
15
14
13
12
11
10
9
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
6
Y
W
FUNCTION TABLE
INPUTS
SELECT
STROBE
G
C
B
A
X
H
X
X
L
L
L
L
L
L
L
H
L
L
H
L
H
L
L
H
L
H
L
L
H
L
H
L
L
L
H
H
H
H
H
L
OUTPUTS
Y
W
Z
D0
D1
D2
D3
D4
D5
D6
D7
Z
D0
D1
D2
D3
D4
D5
D6
D7
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
S
ALS
F
SN74 CD74 CD74 SN74 CD74
UNIT
HC
HC HCT AC
AC
ICC
MAX
62
12
85
14
24
0.08
0.16
0.16
0.16
0.16
mA
IOH
IOL
MAX
MAX
-5.2
16
-2.6
8
-6.5
20
-2.6
24
-3
24
-6
6
-4
4
-4
4
-24
24
-24
24
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A, B, C
Y
MAX
A, B, C
W (CD74: Y)
MAX
ANY D
Y
MAX
ANY D
W (CD74: Y)
MAX
G
Y
MAX
G
W (CD74: Y)
MAX
G
Y
MAX
G
W (CD74: Y)
MAX
SN74 CD74 CD74 SN74 CD74
HC
HC HCT AC
AC
TTL
LS
S
ALS
F
45
45
33
33
28
45
45
33
33
28
18
19.5
15
13.5
12
18
24
24
23
10
9.5
7.5
12.5
9
7
51
51
51
51
49
74
74
74
74
53
63
63
63
63
53
18.2
18.2
19.6
19.6
13.5
18.2
18.2
19.6
19.6
13.5
28
15
15
27
40
28
15
15
45
40
12
7
7
19.5
21
15
15
15
15
15
5
8
8
7
6.5
49
49
49
36
36
53
53
53
42
42
53
53
53
45
45
13.5
14.9
14.9
13.5
13.5
13.5
14.9
14.9
13.5
13.5
27
40
8
23
8
27
40
45
25
55
19.5
21
8.5
14
8.5
15
15
10
10
10
6
4.5
8.5
8
5.5
36
36
49
49
49
42
42
42
42
42
45
45
45
45
45
13.5
13.5
13.5
13.5
13.5
13.5
13.5
13.5
13.5
13.5
23
25
14
10
4.5
49
42
45
13.5
13.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
279
253
DUAL DATA SELECTORS/MULTIPLEXERS
● 3-State Version of '153
● Perform Parallel-to-Serial Conversion
Logic Diagram
1OE
1C0
1C1
1
6
5
7
Data 1
1C2
1C3
B
Select
A
2C0
2C1
Data 2
2C2
2C3
2OE
280
1Y
4
3
2
14
10
11
12
13
15
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
9
2Y
FUNCTION TABLE
SELECT
INPUTS
DATA INPUTS
OUTPUT
CONTROL
OUTPUT
B
A
C0
C1
C2
C3
G
Y
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
H
L
L
L
L
L
L
L
L
Z
L
H
L
H
L
H
L
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
ALS
AS
F
SN74 CD74 CD74 CD74 CD74
UNIT
HC
HC HCT AC ACT
ICC
MAX
14
14
33
23
0.08
0.16
0.16
0.16
0.16
mA
IOH
MAX
-2.6
-2.6
-15
-3
-6
-6
-4
-24
-24
mA
IOL
MAX
8
24
48
24
6
6
4
24
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
INPUT
OUTPUT
MAX or MIN
DATA
Y
MAX
SELECT
Y
MAX
G
Y
MAX
G
Y
MAX
SN74 CD74 CD74 CD74 CD74
HC
HC HCT AC ACT
LS
ALS
AS
F
25
20
45
10
14
21
7.5
8
13.5
8
7
13
35
35
38
53
53
53
57
57
60
13.3
13.3
20
18
18
22
32
28
23
41
27
21
14
16
10
14
11.5
12.5
11.5
6
7
10
9
9
6
7
38
25
25
38
38
53
33
33
45
45
60
45
45
45
45
20
11.5
11.5
11.5
11.5
22
12.6
12.6
12.6
12.6
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
281
257
QUAD DATA SELECTORS/MULTIPLEXERS
● 3-State Outputs Interface Directly with System Bus
● Provides Bus Interface from Multiple Sources in High-Performance Systems
Logic Diagram
OE
A/B
1A
1B
2A
2B
3A
3B
4A
4B
282
15
1
2
4
1Y
3
5
7
2Y
6
11
9
3Y
10
14
12
13
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4Y
FUNCTION TABLE
INPUTS
OUTPUT
OUTPUT
CONTROL
SELECT
A
B
Y
H
L
L
L
L
X
L
L
H
H
X
L
H
X
X
X
X
X
L
H
Z
L
H
L
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 SN74 CD74
HC
HC HCT HCT
AC
11
CD74 ACT CD74
AC
11
ACT
MAX or MIN
LS
S
ALS
AS
F
ICC
IOH
MAX
MAX
19
-2.6
87
-6.5
14
-2.6
31.9
-15
23
-3
0.08
-6
0.16
-6
0.08
-6
0.16
-6
0.08
-24
0.16
-24
0.08
-24
IOL
MAX
24
20
24
48
24
6
6
6
6
24
24
24
LVC
3V
UNIT
0.16
-24
0.01
-24
mA
mA
24
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
LS
S
DATA
ANY
MAX
13
15
21
24
30
30
30
25
SELECT
ANY
MAX
G
Y
MAX
G
Y
MAX
SN74 CD74 SN74 CD74
HC
HC HCT HCT
AC
11
CD74 ACT CD74
AC
11
ACT
LVC
3V
ALS
AS
F
7.5
6.5
10
12
5.5
6
7
6.5
25
25
45
45
38
38
50
50
6.4
7.2
9.3
9.3
6.9
8.7
10.7
10.7
4.6
4.6
15
15
19.5
21
8.5
18
22
16
18
10
11
10
7.5
9.5
6.5
15
9.5
8.5
8.5
7
25
25
38
38
38
53
53
45
45
45
38
38
38
38
38
57
57
45
45
45
7.2
7.9
6.5
8.6
7.6
13.4
13.4
14.7
14.7
14.7
8.2
9.4
7.3
9.6
8.4
15.4
15.4
16.1
16.1
16.1
6.4
6.4
5.6
5.6
4.3
14
15
7
7
38
45
38
45
7.6
14.7
8.5
16.1
4.3
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
283
258
QUAD DATA SELECTORS/MULTIPLEXERS
● 3-State Outputs Interface Directly with System Bus
● Provides Bus Interface from Multiple Sources in High-Performance Systems
Logic Diagram
OE
A /B
1A
1B
2A
2B
3A
3B
4A
4B
284
15
1
2
4
1Y
3
5
7
2Y
6
11
9
3Y
10
14
12
13
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4Y
FUNCTION TABLE
INPUTS
OUTPUT
CONTROL
H
L
L
L
L
SELECT
A
B
X
L
L
H
H
X
L
H
X
X
X
X
X
L
H
OUTPUT
Z
H
L
H
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SN74 CD74 CD74 CD74 UNIT
HC
HC HCT ACT
MAX or MIN
LS
S
ALS
AS
F
ICC
IOH
MAX
MAX
16
-2.6
87
-6.5
13
-2.6
25.2
-15
23
-3
0.08
-6
0.16
-6
0.16
-6
0.16
-24
mA
mA
IOL
MAX
8
20
24
48
24
6
6
6
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
DATA
Y
MAX
SELECT
Y
MAX
G
Y
MAX
G
Y
MAX
SN74 CD74 CD74 CD74
HC
HC HCT ACT
LS
S
ALS
AS
F
12
17
21
24
6
6
12
12
8
7
25
20
5
4
9.5
10
6
5.5
9.5
11
25
25
29
29
24
24
35
35
34
34
43
43
10.7
10.7
15.4
15.4
30
30
30
25
19.5
21
8.5
14
18
18
10
18
8
10
6
6.5
8.5
8.5
7
7
38
38
38
38
35
35
38
38
35
35
38
38
16.1
16.1
16.1
16.1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
285
259
8-BIT ADDRESSABLE LATCHES
●
●
●
●
●
●
8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion with Storage
Asynchronous Parallel Clear
Active-High Decoder
Enable/Disable Input Simplifies Expansion
Expandable for n-Bit Applications
Four Distinct Functional Modes
Logic Diagram
G
D
14
4
5
S0
7
10
12
286
Q3
Q4
Q5
3
11
CLR
Q2
2
9
S2
Q1
1
6
S1
Q0
13
15
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Q6
Q7
FUNCTION TABLE
LATCH SELECTION
SELECT
INPUTS
C
B
A
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
INPUTS
LATCH
ADDRESSED
L
H
L
H
L
H
L
H
CLEAR
0
1
2
3
4
5
6
7
G
OUTPUT OF
EACH
ADDRESSED OTHER
LATCH
OUTPUT
L
H
L
H
H
H
L
L
Qi0
Qi0
L
L
D
Qi0
D
L
FUNCTION
Addressable latch
Memory
8-line demultiplexer
Clear
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ALS SN74 CD74 CD74 UNIT
HC
HC HCT
MAX or MIN
TTL
LS
ICC
MAX
90
36
22
0.08
0.16
0.16
mA
IOH
IOL
MAX
MAX
16
-0.8
8
-0.4
8
-0.4
4
-4
4
-4
4
-4
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
UNIT: ns
INPUT
OUTPUT
G
CLR
DATA
MAX or MIN
MIN
MIN
ADDRESS
DATA
ADDRESS
MIN
CLEAR
Any Q
MAX
DATA
Any Q
MAX
ADDRESS
Any Q
MAX
ENABLE
Any Q
MAX
ALS SN74 CD74 CD74
HC
HC HCT
TTL
LS
15
15
15
17
10
20
15
10
15
20
20
19
21
21
24
27
27
26
5
0
20
25
17
0
0
18
15
0
0
12
19
5
5
38
24
0
0
47
26
0
0
59
24
20
28
30
20
27
19
12
22
33
33
50
56
56
56
59
59
61
28
20
20
20
24
24
12
20
13
50
43
43
56
51
51
61
57
57
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
287
Logic Diagram
260
DUAL 5-INPUT POSITIVE-NOR GATES
A
B
C
D
E
● Y=A+B+C+D+E
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
S
F
UNIT
ICC
MAX
45
9.5
mA
IOH
IOL
MAX
MAX
-1
20
-1
20
mA
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
288
INPUT
A, B, C, D, E
OUTPUT
Y
MAX or MIN
S
F
MAX
5.5
6
6.5
4.5
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Y
Logic Diagram
265
QUAD COMPLEMENTARY-OUTPUT ELEMENTS
ELEMENTS 1 and 4
A
Y
W
B
W
A
● Y = A, W = A
● Y = AB, W = AB
ELEMENTS 2 and 3
Y
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
UNIT
ICC
MAX
34
mA
IOH
IOL
MAX
MAX
-0.8
16
mA
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
tPLH
tPHL
tPLH
tPHL
Y
A or B
A or B
Y
MAX
MAX
18
18
Y
A or B
A or B
Y
MAX
MAX
18
18
tPLH
-tPHL
Y
tPHL
-tPLH Y
UNIT: ns
A or B
with
respect Y
MAX
3
A or B
with
respect Y
MAX
3
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
289
Logic Diagram
266
QUAD 2-INPUT
EXCLUSIVE-NOR GATES WITH
OPEN-COLLECTOR OUTPUTS
A
B
● Y=A⊕B
FUNCTION TABLE
INPUTS
A
B
L
L
L
H
H
L
H
H
OUTPUT
Y
H
L
L
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
HC
UNIT
ICC
VOH
MAX
MAX
13
5.5
0.02
Vcc
mA
V
IOL
MAX
8
4
mA
SWITCHING CHARACTERISTICS
INPUT
OUTPUT
MAX or MIN
LS
SN74
HC
tPLH
A or B
Other Input
Low
Y
MAX
30
31
tPHL
A or B
Other Input
Low
Y
MAX
30
25
tPLH
A or B
Other Input
High
Y
MAX
30
31
tPHL
A or B
Other Input
High
Y
MAX
30
25
PARAMETER
UNIT: ns
290
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Y
273
OCTAL D-TYPE FLIP-FLOPS
● Contain Eight Flip-Flops with Single-Rail Outputs
● Buffered Clock and Direct-Clear Inputs
Logic Diagram
CLK
1D
2D
3D
4D
3
4
7
8
1D
1D
C1
1D
C1
R
CLR
5D
6D
13
7D
14
8D
17
18
11
1D
C1
R
1D
C1
R
R
1D
C1
R
1D
1D
C1
C1
C1
R
R
R
1
2
5
6
9
1Q
2Q
3Q
4Q
12
15
5Q
16
6Q
19
7Q
8Q
FUNCTION TABLE
INPUTS
CLEAR
CLOCK
D
OUTPUT
Q
L
H
H
H
X
↑
↑
L
X
H
L
X
L
H
L
Q0
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
ALS SN74 CD74 SN74 CD74 ABT LVTH CD74 CD74 AHC AHCT
HC
HC HCT HCT
3V
AC ACT
LV
3V
LV
5V
UNIT
MAX
MAX
MAX
94
-0.8
16
27
-0.4
8
29
-2.6
24
-6
6
0.02
-12
12
mA
mA
mA
ICC
IOH
IOL
0.08
-4
4
0.16
-4
4
0.08
-4
4
0.16
-4
4
30
-32
64
5
-32
64
0.16
-24
24
0.16
-24
24
0.04
-8
8
0.04
-8
8
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
ALS
CLEAR
ANY Q
MIN
MIN
MIN
MIN
MIN
MAX
CLOCK
ANY Q
MAX
30
16.5
20
25
5
27
27
27
30
20
20
25
5
27
27
27
35
14
10
15
0
18
12
15
INPUT
OUTPUT
LV
3V
LV
5V
45
6.5
6.5
2.5
2
19.5
19.5
19.5
70
5
4.5
2
1
12
12.5
12.5
fmax
t
tsu
DATA INPUT
CLR INACVIVE
th
tPHL
tPLH
tPHL
PARAMETER
fmax
t
tsu
ANY Q
MIN
MIN
MIN
MIN
MIN
MAX
ANY Q
MAX
DATA INPUT
CLR INACVIVE
th
tPHL
CLEAR
tPLH
CLOCK
tPHL
UNIT fmax : MHz, other : ns
MAX or MIN AHCT
45
6.5
5
2.5
0
12.6
9.8
11
SN74 CD74 SN74 CD74
LVTH CD74 CD74
ABT
AHC
HC
HC HCT HCT
3V
AC ACT
21
20
25
25
0
40
40
40
20
24
18
3
45
45
45
16
25
25
25
0
42
42
42
16
30
18
3
48
45
45
150
3.3
2.5
2
1.2
7.4
6.5
7.3
150
3.3
2.3
2.3
0
4.9
4.8
4.3
100
5
2
2
13.5
13.5
13.5
85
6
2
2
13.5
13.5
13.5
70
5
4.5
2
1
12
12.5
12.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
291
276
QUAD J-K FLIP-FLORS
● Separate Negative-Edge-Triggered Clocks
● Fully Buffered Outputs
Logic Diagram
2Q
(6)
1Q
(5)
Q
Q
CLR
J
CK
(2)
(1)
1J
3Q
(15)
PR
CLR
K
J
(3)
1CLK
(4)
1K
CK
(9)
2J
(8)
2CLK
4Q
(16)
Q
PR
CLR
K
J
(7)
2K
Q
CK
(12)
3J
PR
CLR
K
J
(13)
3CLK
(14)
3K
PR
CK
(19)
4J
K
(18)
4CLK
(17)
4K
FUNCTION TABLE
COMMON INPUTS
PRESET
CLEAR
L
H
L
H
H
H
H
H
INPUTS
K
CLOCK J
X
X
X
↓
↓
↓
↓
H
H
L
L
H
H
H
H
H
X
X
X
L
H
L
H
X
X
X
X
H
H
L
L
X
OUTPUT
Q
H
L
H†
Q0
H
L
TOGGLE
Q0
† The output levels in this configuration are not guaranteed to
meet the minimum levels for VOH. Furthermore, this
configuration is nonstable; that is, it will not persist when
either PRE or CLR returns to its inactive (high) level.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
UNIT
MAX
MAX
MAX
81
-0.8
16
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
INPUT
OUTPUT
CLOCK high
CLOCK low
J, K
CLR, PR
th
tPLH
PRESET
tPHL
CLEAR
tPLH
CLOC
tPHL
UNIT fmax : MHz, other : ns
292
(11)
PRESET
CLEAR
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
MAX or MIN
TTL
MIN
35
13.5
15
3
10
10
25
30
30
30
MIN
MIN
Q
Q
MIN
MAX
MAX
Q
MAX
Logic Diagram
279
QUAD S-R LATCHES
(latches 1 and 3)
(latches 2 and 4)
R
S1
S2
R
Q
Q
S
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
LS
UNIT
ICC
IOH
MAX
MAX
30
-0.8
7
-0.4
mA
mA
IOL
MAX
16
8
mA
SWITCHING CHARACTERISTICS
PARAMETER
t
tPLH
tPHL
tPHL
UNIT: ns
INPUT
S
R
OUTPUT
Q
MAX or MIN
TTL
LS
MIN
20
22
15
27
20
22
21
27
MAX
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
293
280
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
● Generate Either Odd or Even Parity for Nine Data Lines
● Cascadable for n-Bit Parity
Logic Diagram
A
B
C
8
9
10
5
D
E
F
11
12
13
6
G
H
I
294
Σ EVEN
1
2
4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Σ ODD
FUNCTION TABLE
NO. OF INPUTS
A–I
THAT ARE HIGH
OUTPUTS
Σ EVEN Σ ODD
H
L
0, 2, 4, 6, 8
1, 3, 5, 7, 9
L
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
S
ALS
AS
SN74 CD74 CD74 CD74 CD74 UNIT
HC
HC HCT AC ACT
F
ICC
MAX
27
105
16
35
35
0.08
0.16
0.16
0.16
0.16
mA
IOH
IOL
MAX
MAX
-0.4
8
-1
20
-2.6
24
-2
20
-1
20
-4
4
-4
4
-4
4
-24
24
-24
24
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
DATA
S
EVEN
MAX
DATA
S
ODD
MAX
LS
S
ALS
AS
F
50
45
35
50
21
18
21
18
20
20
20
22
12
11
12
11.5
10
11
10
11
SN74 CD74 CD74 CD74 CD74
HC
HC HCT AC ACT
52
52
52
52
60
60
60
60
63
63
68
68
20
20
21
21
21.6
21.6
21.6
21.6
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
295
283
4-BIT BINARY FULL ADDERS
● Full-Carry Look-Ahead Across the Four Bits
Logic Diagram
9
B4
A4
B3
A3
B2
11
12
10
B1
14
13
C0
296
Σ3
2
Σ2
3
6
4
A1
Σ4
15
1
A2
C4
5
7
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Σ1
FUNCTION TABLE
OUTPUTS
WHEN C0 = L
INPUTS
WHEN C0 = H
WHEN C2 = L
WHEN C2 = H
A1
B1
A2
B2
Σ1
Σ2
C2
Σ1
Σ2
C2
A3
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
B3
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A4
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
B4
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Σ3
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
Σ4
L
L
L
H
H
H
H
L
H
H
H
L
L
L
L
H
C4
L
L
L
L
L
L
L
H
L
L
L
H
H
H
H
H
Σ3
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
Σ4
L
H
H
H
H
L
L
L
H
L
L
L
L
H
H
H
C4
L
L
L
L
L
H
H
H
L
H
H
H
H
H
H
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
MAX
MAX
MAX
MAX
MAX
ICC
IOH
IOL
Any output except C4
C4
Any output except C4
C4
CD74 CD74 CD74 CD74 UNIT
HC HCT AC ACT
LS
S
F
110
39
160
55
0.16
0.16
0.16
0.16
-0.8
-0.4
16
8
-0.4
-0.4
8
8
-1
-0.5
20
10
-1
-1
20
20
-4
-4
4
4
-4
-4
4
4
-24
-24
24
24
-24
-24
24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
INPUT
OUTPUT
C0
S
Ai or Bi
Si
C0
C4
Ai or Bi
CD74 CD74 CD74 CD74
HC HCT AC ACT
MAX or MIN
TTL
LS
S
F
MAX
MAX
MAX
21
21
24
24
24
24
18
18
18
10.5
10.5
10.5
69
69
63
47
47
69
17.6
17.6
18.2
17.6
17.6
18.2
MAX
MAX
MAX
MAX
MAX
24
14
16
14
16
24
17
22
17
17
18
11
11
12
12
10.5
8.5
8
8.5
8
63
59
59
59
59
69
80
80
72
72
18.2
17.6
17.6
17.6
17.6
18.2
17.6
17.6
17.6
17.6
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
297
286
9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORT
●
●
●
●
●
Generate Either Odd or Even Parity for Nine Data Lines
Cascadable for n-Bit Parity
Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port
74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
A
B
C
D
E
F
G
H
I
PARITY I/O
XMIT
298
8
9
10
11
12
13
5
1
2
4
6
3
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
PARITY
ERROR
FUNCTION TABLE
NUMBER OF INPUTS
(A–I) THAT
ARE HIGH
XMIT
PARITY
I/O
PARITY
ERROR
0, 2, 4, 6, 8
l
H
H
1, 3, 5, 7, 9
l
L
H
0, 2, 4, 6, 8
h
h
h
l
H
L
1, 3, 5, 7, 9
h
h
h
l
L
H
h = high input level
H = high output level
l = low input level
L = low output level
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ICC
IOH
IOL
MAX
AS
AC
11
ACT
11
UNIT
50
0.08
0.08
mA
Parity error
MAX
-2
-24
-24
mA
Parity I/O
Parity error
MAX
MAX
-15
20
-24
24
-24
24
mA
mA
Parity I/O
MAX
48
24
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
AS
AC
11
ACT
11
A to I
Parity I/O
MAX
15
14
9
107
10.4
12
A to I
Parity error
MAX
Parity I/O
Parity error
MAX
16.5
16.5
9
9
13
10
12
6.2
7.9
5.3
11.3
12.9
7.7
9.1
7.3
XMIT
Parity I/O
MAX
16
11.5
10
8.9
6.5
6.3
11.4
8.5
7.8
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
299
292
PROGRAMMABLE FREQUENCY DIVIDER/DIGITAL TIMER
● Digitally Programmable from 22 to 231
● Easily Expandable
● Applications:
Frequency Division
Digital Timing
Logic Diagram
CLR
CLK1
CLK2
(11)
(4)
(5)
R
R
T
T
R
X/Y
T
2D R
2T
0
28
R
T
M2
(3)
26
TP1
24
2D R
R
T
2T
22
M2
20
A
B
C
D
(1)
(15)
(14)
(6)
18
(10)
16
2
4
2D R
8
R
2T
E
(2)
16
14
T
M2
2D R
12
2T
10
8
(13)
TP3
M2
R
T
2D
2T
6
M2
R
T
2D R
2T
4
2
S
3D
3T
M2
M3
300
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(7)
Q
TP2
FUNCTION TABLE
CLEAR
CLK 1
CLK 2
Q OUTPUT MODE
L
H
H
H
H
X
≠
L
H
X
X
L
≠
X
H
Cleared to L
Count
Count
Inhibit
Inhibit
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
UNIT
ICC
MAX
75
mA
IOH (Q only)
IOL (Q only)
MAX
MAX
-1.2
24
V
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tPLH
tPHL
tPHL
UNIT fmax :
INPUT
CLK
CLK
CLK
CLR
Hz, other : ns
OUTPUT
MAX or MIN
LS
Q
MIN
MAX
30
90
Q
Q
MAX
MAX
120
65
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
301
293
4-BIT BINARY COUNTERS
Logic Diagram
INPUT A
INPUT B
(10)
(1)
J Q
(9)
QA
CK
K
J Q
(5)
QB
CK
K
J Q
(4)
QC
CK
K
J Q
CK
K
R0(1) (12)
R0(2) (13)
302
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(8)
QD
COUNT SEQUENCE
COUNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
QD
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
OUTPUTS
QC
QB
L
L
L
L
H
L
H
L
H
L
H
L
H
H
H
H
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
QA
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
NOTE: Output QA is connected to input B.
RESET/COUNT FUNCTION TABLE
RESET INPUTS
R0(1)
R0(2)
H
H
L
X
X
L
QD
L
OUTPUTS
QC QB QA
L
L
L
COUNT
COUNT
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
ICC
PARAMETER
MAX
39
15
UNIT
mA
IOH
IOL
MAX
MAX
-0.8
16
-0.4
8
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
INPUT
OUTPUT
MAX or MIN
TTL
LS
A
B
QA
QB
MIN
MIN
32
16
15
32
16
15
MIN
30
15
25
16
18
30
15
25
16
18
70
70
16
21
32
35
51
51
70
70
16
21
32
35
51
51
A
B
Reset
tsu
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT fmax :
A, B
MIN
A
QA
MAX
A
QB
MAX
B
QB
MAX
B
QC
MAX
B
QD
MAX
Hz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
303
294
PROGRAMMABLE FREQUENCY DIVIDER/DIGITAL TIMER
● Digitally Programmable from 22 to 215
● Easily Expandable
● Applications
Frequency Division
Digital Timing
Logic Diagram
CLR
CLK1
CLK2
(11)
(4)
(5)
R
R
T
T
X/Y
0
1
14
2D R
2T
M2
13
12
11
10
A
B
C
D
(2)
(1)
(15)
(14)
(3)
9
1
8
2
4
8
2D R
2T
7
M2
6
5
4
3D S
3T
3
2
304
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
M3
(7)
Q
TP
FUNCTION TABLE
PROGRAMMING INPUTS
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
BINARY
Inhibit
Inhibit
22
23
24
25
26
27
28
29
210
211
212
213
214
215
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
FREQUENCY DIVISION
Q
TP
DECIMAL
DECIMAL
BINARY
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
29
4
512
8
512
29
9
2
16
512
29
32
512
29
64
512
128
Disabled Low
2
256
2
4
512
23
8
1024
24
16
2048
25
32
4096
26
64
8192
27
128
16384
28
256
32768
29
512
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
UNIT
ICC
MAX
50
mA
IOH
IOL
MAX
MAX
-1.2
24
V
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tPLH
tPHL
tPLH
UNIT fmax :
INPUT
OUTPUT
CLK
CLK 1 or 2
CLR
CLK 1 or 2
CLR
Hz, other : ns
MAX or MIN
LS
MIN
MIN
MIN
30
16
35
Q
MAX
Q
MAX
90
120
65
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
305
297
DIGITAL PHASE-LOCKED-LOOP FILTERS
Logic Diagram
K COUNTER
(2)
A
(1)
B
(15)
C
(14)
D
KCLK
D/U
ENCTR
1
2
4
8
X/Y
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TO MODE CONTROLS 12-2 (11-STAGES NOT SHOWN)
(4)
(6)
(3)
C20
20D
R
R
T
T
14D R
14T
M14
13D R
13T
M13
1DR
1T
M1
R
C20
20D
T
T
R
R
M14
14T
14D
R
M13
13T
13D
R
M1
1T
1D
R
T
T
R
POWER-UP RESET
I=1
1
DECREMENT
INCREMENT
I/D CLK
I/D CIRCUIT
(5)
(7)
I/D OUT
21D
21D
C21
21D
C21
C21
21D
21J
C21
C21
C21
C21
21D
C21
21D
C21
21K
21D
21D
φA1
EXCLUSIVE-OR PHASE DETECTOR
(9)
(11) XORPD
OUT
φB
(10)
EDGE CONTROLLED PHASE DETECTOR
φA2
306
(13)
S
S
R
R
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(12) ECPD
OUT
FUNCTION TABLES
K COUNTER FUNCTION TABLE
(DIGITAL CONTROL)
D
C
B
A
MODULO
(K)
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Inhibited
22
24
25
26
27
28
29
210
211
212
213
214
215
216
217
EXCLUSIVE OR PHASE DETECTOR
φ A1
φB
XORPD OUT
L
H
H
L
L
H
L
H
L
L
H
H
EDGE-CONTROLLED PHASE DETECTOR
φ A2
φB
ECPD OUT
H
H or L
↓
↓
H or L
L
H or L
↑
No change
↑
H or L
No change
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
ICC
IOH (I/D OUT)
IOH (XOR, ECPD)
IOL (I/D OUT)
IOL (XOR, ECPD)
MAX
MAX
MAX
MAX
MAX
120
-1
-0.4
24
8
CD74 CD74 CD74 UNIT
HC HCT ACT
0.16
-6
-6
6
6
0.16
-4
-4
4
4
0.08
-24
-24
24
24
mA
mA
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
INPUT
OUTPUT
MAX or MIN
K CLK
I/D CLK
I/D OUT
I/D OUT
MIN
K CLK
MIN
I/D CLK
tsu
D/U
ENCLR
MIN
th
D/U
ENCLR
MIN
tPLH
tPHL
I/D CLK
tPLH
A1 or
B
tPHL
A1 or
B
tPLH
tPHL
UNIT
other input low
other input high
other input low
other input high
B
A2
I/D OUT
MAX
X or OUT
MAX
X or OUT
ECPD OUT
ECPD OUT
MAX
LS
CD74 CD74 CD74
HC HCT ACT
32
16
16
20
13
24
20
13
24
45
35
8
33
30
31
0
0
25
38
30
30
0
0
53
38
30
30
0
0
53
9
17
16
7
6
24
35
15
25
25
25
30
30
53
45
45
45
45
60
60
53
45
45
45
45
60
60
24
22
22
22
22
30
30
fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
307
298
QUAD 2-INPUT MULTIPLEXERS WITH STORAGE
● Outputs Storage Register
Logic Diagram
A1
WS
A2
B1
3
10
1S
2
C1
15
QA
1R
4
1S
B2
C1
1
C1
14
QB
1R
9
1S
C2
D1
5
C1
13
QC
1R
7
1S
D2
6
C1
1R
CLK
308
11
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
12
QD
FUNCTION TABLE
INPUTS
OUTPUTS
WORD
SELECT
CLOCK
QA
QB
QC
QD
L
H
X
↓
↓
H
A1
A2
QA0
B1
B2
QB0
C1
C2
QC0
D1
D2
QD0
† a1, a2, etc. = the level of steady-state input at A1, A2, etc.
QA0, QB0, etc. = the level of QA, QB, etc. entered
on the most recent O transition of CLK
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
TTL
65
LS
AS
SN74
UNIT
HC
ICC
MAX
21
36
0.08
mA
IOL
MAX
16
8
20
4
mA
IOH
MAX
-0.8
-0.4
-2
-4
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
t
tsu
th
Data
Word Select
Data
Word Select
tPLH
tPHL
UNIT: ns
MAX or MIN
TTL
LS
AS
SN74
HC
MIN
20
15
25
5
0
20
15
25
5
0
8
4.5
13
3.5
1
27
21
21
0
0
27
32
27
32
9
11
31
31
MIN
MIN
CLK
GA to GD
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
309
299
8-BIT BIDIRECTIONAL UNIVERSAL SHIFT/STORAGE REGISTERS
● Multiplexed I/O Ports Provide Improved Bit Density
● Four Modes of Operation:
Hold (Store)
Shift Right
Shift Left
Load Data
● Operate with Outputs Enabled or at High Impedance
● 3-State Outputs Drive Bus Lines Directly
● Can Be Cascaded for n-Bit Word Lengths
Logic Diagram
S0
S1
SR
(shift right
serial input)
CLK
1
19
18
11
Six
Identical
Channels
Not
Shown†
12
1D
1D
C1
C1
R
QA′
CLR
OE1
OE2
R
17
8
9
2
3
7
1
A /QA
† I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4).
310
SL
(shift left
serial input)
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
6
H /QH
QH′
FUNCTION TABLE
MODE
Clear
Hold
Shift
Right
Shift
Left
Load
CLR
L
L
L
H
H
H
H
H
H
H
S1
X
L
H
L
X
L
L
H
H
H
S0
L
X
H
L
X
H
H
L
L
H
INPUTS
OE1 †
OE2 †
L
L
L
L
X
X
L
L
L
L
L
L
L
L
L
L
L
L
X
X
CLK
X
X
X
X
L
SL
X
X
X
X
X
X
X
H
L
X
↑
↑
↑
↑
↑
SR
X
X
X
X
X
H
L
X
X
X
A/Q A
L
L
X
Q A0
Q A0
H
L
Q Bn
Q Bn
a
B/Q B
L
L
X
Q B0
Q B0
Q An
Q An
Q Cn
Q Cn
b
C/Q C
L
L
X
Q C0
Q C0
Q Bn
Q Bn
Q Dn
Q Dn
c
I/O PORTS
D/Q D
E/Q E
L
L
L
L
X
X
Q D0
Q E0
Q D0
Q E0
Q Cn
Q Dn
Q Cn
Q Dn
Q En
Q Fn
Q En
Q Fn
d
e
F/Q F
L
L
X
Q F0
Q F0
Q En
Q En
Q Gn
Q Gn
f
G/Q G
L
L
X
Q G0
Q G0
Q Fn
Q Fn
Q Hn
Q Hn
g
H/Q H
L
L
X
Q H0
Q H0
Q Gn
Q Gn
H
L
h
OUTPUTS
Q A'
Q H'
L
L
L
L
L
L
Q A0
Q H0
Q A0
Q H0
H
Q Gn
L
Q Gn
Q Bn
H
Q Bn
L
a
h
NOTE: a...h=the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputsare isolated from the I/O terminals.
† When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operationor clearing of the register is not affected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
MAX
ICC
Q A thru QH
IOH
MAX
Q A' or QH'
Q A thru QH
Q A' or QH'
IOL
MAX
LS
S
ALS
F
CD74 CD74 CD74 CD74
UNIT
HC HCT AC ACT
53
225
40
95
0.16
0.16
0.16
0.16
-2.6
-6.5
-2.6
-3
-6
-4
-24
-24
-0.4
24
-0.5
20
-0.4
24
-1
24
-4
6
-4
4
-24
24
-24
24
mA
8
6
8
20
4
4
24
24
MAX or MIN
LS
S
ALS
F
MIN
20
30
50
10
30
16.5
70
7
20
24
16
30
95
5.2
90
5.5
MIN
10
20
20
10
10
7
16.5
10
16
7
7
5.5
24
15
36
30
22
30
5.2
5
4.5
5.5
5
4.5
20
35
20
0
10
33
5
15
10
5
5
20
6
20
15
0
0
15
5.5
8.5
7
2
0
10
36
36
0
0
60
30
41
0
0
68
4.5
9
0
0
12.9
4.5
9
0
0
12.9
39
25
39
40
40
21
30
20
15
20
21
21
21
24
18
18
12
12
18
13
19
22
22
16
22
8
15
9.5
10
12
10.5
15
9
11
7
6.5
60
60
60
60
60
47
39
56
47
68
68
68
69
69
48
45
56
48
12.9
13.5
13.5
11.2
13.9
14.9
14.9
14.9
14.9
12.9
14.5
14.5
12.2
18.6
14.9
14.9
14.9
14.9
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
t
CLK high
CLK low
CLR
DATA "H"
tsu
th
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
DATA "L"
SELECT
MIN
CLR INACTIVE
DATA
SELECT
MIN
CLK
Q A' or QB'
MAX
CLK
Q A thru QH
MAX
CLR
CLR
Q A' or QH'
Q A thru QH
MAX
OE1, OE2
Q A thru QH
MAX
OE1, OE2
Q A thru QH
MAX
CD74 CD74 CD74 CD74
HC HCT AC ACT
fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
311
321
CRYSTAL-CONTROLLED OSCILLATOR
● Crystal-Controlled Oscillator Operation from 1MHz to 20MHz
● Complementary Outputs
Logic Diagram
FFD
TANK 1
TANK 2
XTAL 1
(5)
(4)
1D
(1)
(2)
(14)
FFQ
C1
(7)
OSC
(12)
F
F
VCC
XTAL 2
(15)
DRIVER
SECTION
(10)
(9)
(6)
'LS321
ONLY
T
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
F
F/4
T
(13)
312
F
F/2
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
MAX or MIN
LS
UNIT
MAX
75
mA
IOH
F' or F'
F, F, F/2, F/4
MAX
MAX
-24
-0.4
mA
mA
IOL
F' or F'
F, F, F/2, F/4
MAX
MAX
24
8
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
fmax
tr
tf
OUTPUT
MAX or MIN
LS
F/2
MIN
10
F/4
ANY
MAX
MIN
5
20
F',F'
ANY
MAX
MAX
14
40
F',F'
MAX
10
ANY
MAX
20
UNIT fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
313
323
8-BIT BIDIRECTIONAL SHIFT/STORAGE REGISTERS
● Multiplexed I/O Ports Provide Improved Bit Density
● Four Modes of Operation:
Hold (Store)
Shift Right
Shift Left
Load Data
● 3-State Outputs Drive Bus Lines Directly
● Can Be Cascaded for n-Bit Word Lengths
Logic Diagram
CLR
S0
S1
SR
(shift right
serial input)
CLK
9
1
19
18
11
Six
Identical
Channels
Not
Shown†
12
1D
1D
C1
QA′
OE1
OE2
C1
17
8
2
3
7
1
A/QA
† I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4).
314
SL
(shift left
serial input)
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
6
H/QH
QH′
FUNCTION TABLE
Hold
Shift
Right
Shift
Left
Load
S1
X
L
L
X
L
L
H
H
H
L
L
H
H
H
H
H
H
H
S0
L
X
L
X
H
H
L
L
H
OUTPUTS
I/O BORD
CLK
→→
Clear
SELECT
CLR
X
L
→ →→ →→
MODE
INPUTS
OUTPUT
CONTROL
OE1† OE2†
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
SEREAL
SL
X
X
X
X
X
X
H
L
X
SR
X
X
X
X
H
L
X
X
X
A/QA B/QB C/QC C/QD C/QE C/QF C/QG H/QH
QA'
QH'
L
L
QA0
QA0
H
L
QBn
QBn
a
L
L
QA0
QA0
H
L
QBn
QBn
a
L
L
QH0
QH0
QGn
QGn
H
L
h
L
L
QA0
QB0
QAn
QAn
QCn
QCn
b
L
L
QC0
QC0
QBn
QBn
QDn
QDn
c
L
L
QD0
QD0
QCn
QCn
QEn
QEn
d
L
L
QE0
QE0
QDn
QDn
QFn
QFn
e
L
L
QF0
QF0
QEn
QEn
QGn
QGn
f
L
L
QG0
QG0
QFn
QFn
QHn
QHn
g
L
L
QH0
QH0
QGn
QGn
H
L
h
† a ...h=t he level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop
outputsare isolated from the I/O terminals.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
MAX
ICC
IOH
IOL
Q A' or QH'
Q A thru QH
Q A' or QH'
Q A thru QH
MAX
MAX
ALS
CD74
AC
CD74
ACT
225
40
0.16
0.16
mA
-0.5
-6.5
6
20
-0.4
-2.6
8
24
-24
-24
24
24
-24
-24
24
24
mA
mA
mA
mA
LS
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
th
INPUT
OUTPUT
CLK
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT fmax : MHz, other : ns
ALS
CD74
AC
CD74
ACT
MIN
25
30
20
17
16.5
-
95
5.2
5
90
5.5
5
20
20
0
16
6
20
20
0
0
4.5
4.5
9
5.5
0
0
4.5
4.5
9
5.5
0
0
33
39
25
39
21
15
18
13
19
16
12.9
12.9
13.5
13.5
14.9
12.9
12.9
14.5
14.5
14.9
30
20
15
21
30
20
15
22
8
15
16
22
8
15
14.9
14.9
14.9
14.9
14.9
14.9
14.9
14.9
14.9
14.9
14.9
14.9
14.9
14.9
MIN
CLR
SELECT
DATA
tPHL
tPLH
tPHL
tPZH
tPZL
LS
MIN
CLR
DATA H
DATA L
SELECT
tPLH
MAX or MIN
MIN
CLK
Q A' or QB'
MAX
CLK
Q A thru QH
MAX
OE1
Q A thru QH
MAX
OE1
Q A thru QH
MAX
OE2
Q A thru QH
MAX
OE2
Q A thru QH
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
315
348
8-LINE TO 3-LINE PRIORITY ENCODER
● 3-State Outputs Drive Bus Lines Directly
● Encodes 8 Data Lines to 3-Line Binary (Octal)
Logic Diagram
E1
0
(5)
(10)
(15)
(14)
1
2
4
(12)
6
7
316
A0
(13)
(1)
(7)
5
GS
(11)
(9)
3
EO
(2)
A1
(3)
(4)
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(6)
A2
FUNCTION TABLE
E1
H
L
L
L
L
L
L
L
L
L
0
X
H
X
X
X
X
X
X
X
L
1
X
H
X
X
X
X
X
X
L
H
INPUTS
2 3 4
X X X
H H H
X X X
X X X
X X X
X X L
X L H
L H H
H H H
H H H
5
X
H
X
X
L
H
H
H
H
H
6
X
H
X
L
H
H
H
H
H
H
7
X
H
L
H
H
H
H
H
H
H
OUTPUTS
A2 A1 A0 GS
Z Z Z
H
Z Z Z
H
L L L
L
L
L L H
L
L H L
L
L H H
H L L
L
H L H
L
H H L
L
H H H
L
E0
H
L
H
H
H
H
H
H
H
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
MAX or MIN
LS
MAX
25
UNIT
mA
IOH
A0, A1, A2
E0, ES
MAX
MAX
-2.6
-0.4
mA
mA
IOL
A0, A1, A2
E0, ES
MAX
MAX
24
8
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
INPUT
OUTPUT
1 to 7
A0, A1, A2
0 to 7
E0
0 to 7
GS
MAX or MIN
LS
MAX
35
MAX
MAX
MAX
MAX
MAX
35
18
40
55
21
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
317
354
8-INPUT MULTIPLEXER/REGISTER WITH 3-STATE OUTPUTS
Logic Diagram
15
OE1
ENABLE LOGIC
16
OE2
17
OE3
E
9
8
D0
7
D1
6
D2
5
D3
4
D4
3
D5
2
D
A
T
A
O
F
R
E
G
I
S
T
E
R
S
S
E
L
E
C
T
O
R
1
D6
1
D7
11
LE
14
S0
13
S1
12
S2
318
A
D
D
R
E
S
S
R
E
G
I
S
T
E
R
19
8
ADDRESS
DECODE
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Y
18
Y
BUFFERS
FUNCTION TABLE (SN74)
TRUTH TABLE
INPUTS
SELECT†
DC
S2 S1 S0
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
OUTPUT
ENABLES
G1 G2 G3
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
INPUTS
OUTPUTS
ENABLE
DATA
SELECT (NOTE 3)
W
Y
Z
Z
Z
D0
D0n
D1
D1n
D2
D2n
D3
D3n
D4
D4n
D5
D5n
D6
D6n
D7
D7n
Z
Z
Z
D0
D0n
D1
D1n
D2
D2n
D3
D3n
D4
D4n
D5
D5n
D6
D6n
D7
D7n
NOTES:
H = High Voltage Level (Steady State), L = Low
Voltage Level (Steady State), X = Don’t Care, Z =
High Impedance State (Off State), D0n ... D7n =
the level of steady-state inputs D0 through D7,
respectively, before the most recent low-to-high
transition of data control.
† This column shows the input address setup with
LE low.
OUTPUT ENABLES
OUTPUTS
S2
S1
S0
E
OE1
OE2
OE3
Y
Y
X
X
X
X
H
X
X
Z
Z
X
X
X
X
X
H
X
Z
Z
X
X
X
X
X
X
L
Z
Z
L
L
L
L
L
L
H
D0
D0
D0n
L
L
L
H
L
L
H
D0n
L
L
H
L
L
L
H
D1
D1
L
L
H
H
L
L
H
D1n
D1n
L
H
L
L
L
L
H
D2
D2
L
H
L
H
L
L
H
D2n
D2n
L
H
H
L
L
L
H
D3
D3
L
H
H
H
L
L
H
D3n
D3n
H
L
L
L
L
L
H
D4
D4
H
L
L
H
L
L
H
D4n
D4n
H
L
H
L
L
L
H
D5
D5
H
L
H
H
L
L
H
D5n
Dn 5
H
H
L
L
L
L
H
D6
D6
H
H
L
H
L
L
H
D6n
D6n
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LS
SN74
HC
CD74
HC
SN74
HCT
UNIT
MAX
MAX
MAX
46
-2.6
24
0.08
-6
6
0.16
-6
6
0.16
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
D0 thru D7
Y
D0 thru D7
W
(CD74: Y)
DC
(CD74: E)
Y
DC
(CD74: E)
W
(CD74: Y)
MAX or MIN
LS
SN74
HC
CD74
HC
SN74
HCT
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
15
15
36
35
27
44
42
39
33
50
19
5
59
59
59
59
68
68
68
68
15
14
63
63
63
63
75
75
75
75
15
14
71
71
71
71
81
81
81
81
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
319
356
SYNCHRONOUS UP/DOWN DECADE COUNTER
Logic Diagram
15
OE1
ENABLE LOGIC
16
OE2
17
OE3
CP
9
8
D0
7
D1
6
D2
5
D3
4
D4
3
D5
2
D
A
T
A
O
F
R
E
G
I
S
T
E
R
S
S
E
L
E
C
T
O
R
1
D6
1
D7
11
LE
14
S0
13
S1
12
S2
320
A
D
D
R
E
S
S
R
E
G
I
S
T
E
R
19
8
ADDRESS
DECODE
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Y
18
Y
BUFFERS
TRUTH TABLE
FUNCTION TABLE (SN74)
INPUTS
SELECT†
CLK
C2 C1 C0
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
OUTPUT
ENABLES
G1 G2 G3
X
X
X
↑
H or L
↑
H or L
↑
H or L
↑
H or L
↑
H or L
↑
H or L
↑
H or L
↑
H or L
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
INPUTS
OUTPUTS
SELECT (NOTE 3)
W
Y
Z
Z
Z
D0
D0n
D1
D1n
D2
D2n
D3
D3n
D4
D4n
D5
D5n
D6
D6n
D7
D7n
Z
Z
Z
D0
D0n
D1
D1n
D2
D2n
D3
D3n
D4
D4n
D5
D5n
D6
D6n
D7
D7n
NOTES:
H = High Voltage Level (Steady State), L = Low
Voltage Level (Steady State), ↑ = Transition form
Low to High Level, X = Don’t Care, Z = High
Impedance State (Off State), D0n ... D7n = the
level of steady-state inputs D0 through D7,
respectively, before the most recent low-to-high
transition of data control.
† This column shows the input address setup with
LE low.
CLOCK
OUTPUTS
OUTPUT ENABLES
S2
S1
S0
CP
OE1
OE2
OE3
Y
Y
X
X
X
X
H
X
X
Z
Z
X
X
X
X
X
H
X
Z
Z
X
X
X
X
X
X
L
Z
Z
L
L
L
↑
L
L
H
D0
D0
L
L
L
H or L
L
L
H
D0n
D0n
L
L
H
↑
L
L
H
D1
D1
L
L
H
H or L
L
L
H
D1n
D1n
L
H
L
↑
L
L
H
D2
D2
L
H
L
H or L
L
L
H
D2n
D2n
L
H
H
↑
L
L
H
D3
D3
L
H
H
H or L
L
L
H
D3n
D3n
H
L
L
↑
L
L
H
D4
D4
H
L
L
H or L
L
L
H
D4n
D4n
H
L
H
↑
L
L
H
D5
D5
H
L
H
H or L
L
L
H
D5n
D5n
H
H
L
↑
L
L
H
D6
D6
H
H
L
H or L
L
L
H
D6n
D6n
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LS
SN74
HC
CD74
HCT
UNIT
MAX
MAX
MAX
46
-2.6
24
0.08
-6
6
0.16
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
D0 thru D7
D0 thru D7
MAX or MIN
LS
SN74
HC
CD74
HCT
MIN
MIN
15
0
27
50
36
27
45
48
54
45
19
5
64
64
64
64
71
71
71
71
14
77
77
77
77
89
89
89
89
CLK
Y
MAX
CLK
W
(CD74 : Y )
MAX
S0, S1, S2
Y
MAX
S0, S1, S2
W
(CD74 : Y )
MAX
11
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
321
Logic Diagram
365
HEX BUS DRIVERS
OE1
OE2
A1
1
15
2
3
To Five Other Channels
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
UNIT
ICC
IOH
MAX
MAX
85
-5.2
24
-2.6
0.08
-6
0.16
-6
0.16
-4
mA
mA
IOL
MAX
32
24
6
6
4
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
322
INPUT
OUTPUT
A
Y
G
Y
G
Y
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
MAX
MAX
MAX
16
22
35
15
18
35
24
24
48
32
32
45
38
38
53
MAX
MAX
MAX
37
11
27
45
32
35
48
48
48
45
45
45
53
53
53
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Y1
366
HEX BUS DRIVERS HEX BUFFERS/LINE DRIVERS 3-STATE
Logic Diagram
VCC
16
ONE OF SIX IDENTICAL CIRCUITS
2
1A
3
(NOTE)
1Y
GND
8
1
OE1
2A
15
4
5
2Y
OE2
3A
6
7
3Y
10
4A
9
4Y
12
5A
11
5Y
14
6A
13
6Y
NOTE: Inverter not included in HC/HCT365.
FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT365 AND HC366 (OUTPUTS FOR HC/HCT365 ARE COMPLEMENTS OF THOSE
SHOWN, i.e., 1Y, 2Y, ETC.)
FUNCTION TABLE
INPUTS
G1
L
L
X
H
G2
L
L
H
X
A
L
H
X
X
OUTPUT
Y
H
L
Z
Z
NOTES:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Ompedance (OFF) State
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
UNIT
MAX
MAX
MAX
77
-5.2
32
21
-2.6
24
0.08
-6
6
160
-6
6
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
INPUT
OUTPUT
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
A
Y
(CD74 : Y )
G
(CD74 : OE )
Y
(CD74 : Y )
G
(CD74 : OE )
Y
(CD74 : Y )
MAX
MAX
MAX
MAX
MAX
MAX
17
16
35
37
11
27
15
18
35
45
32
35
24
24
48
48
48
48
33
33
45
45
45
45
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
323
Logic Diagram
367
HEX BUS DRIVERS
1
1OE
2
1A1
15
2OE
3
1Y1
12
2A1
To Three Other Channels
11
2Y1
To One Other Channel
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
AHC
AHCT
LV
3V
LV
5V
ICC
MAX
85
24
0.08
0.16
0.16
0.04
0.04
-
0.02
mA
IOH
IOL
MAX
MAX
-5.2
32
-2.6
24
-6
6
-6
6
-4
4
-8
8
-8
8
-8
8
-16
16
mA
mA
PARAMETER
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
A
Y
G
Y
G
Y
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
AHC
AHCT
LV
3V
LV
5V
MAX
MAX
MAX
MAX
MAX
16
22
35
47
11
16
22
35
40
30
24
24
48
48
48
32
32
45
45
45
38
38
53
53
53
9
9
10.5
10.5
10.5
6.5
6.5
9.5
8.5
9.5
13.5
13.5
16
16
15.5
9
9
10.5
10.5
10.5
MAX
27
35
48
45
53
10.5
8.5
15.5
10.5
368
Logic Diagram
HEX BUS DRIVERS
1OE
1A1
1
2OE
2
3
1Y1
2A1
To Three Other Channels
ICC
IOH
IOL
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
UNIT
MAX
MAX
MAX
77
-5.2
32
21
-2.6
24
0.08
-6
6
0.16
-6
6
0.16
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
324
INPUT
OUTPUT
A
Y
G
Y
G
Y
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
MAX
MAX
MAX
MAX
MAX
MAX
17
16
35
37
11
27
15
18
35
45
32
35
24
24
48
48
48
48
32
32
45
45
45
45
45
45
53
53
53
53
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
12
11
2Y1
To One Other Channel
RECOMMENDED OPERATING CONDITIONS
PARAMETER
15
Logic Diagram
373
OCTAL D-TYPE LATCHES
OE
● 3-State Bus-Driving True Outputs
● Buffered Control Inputs
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
LE
1
11
C1
3
1D
2
1D
1Q
To Seven Other Channels
FUNCTION TABLE
OUTPUT
CONTROL
L
L
L
H
INPUTS
LE
H
H
L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
S
ALS
AS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
LVTH
ICC
MAX
40
190
27
100
55
0.08
0.16
0.08
0.16
60
30
5
mA
IOH
IOL
MAX
MAX
-2.6
24
-6.5
20
-2.6
24
-15
48
-3
24
-6
6
-6
6
-6
6
-6
6
-15
64
-32
64
-32
64
mA
mA
MAX or MIN
AC
11
SN74
AC
CD74
AC
ACT
11
SN74
ACT
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
LVC
3V
ALVCH
3V
UNIT
ICC
IOH
MAX
MAX
0.08
-24
0.04
-24
0.16
-24
0.08
-24
0.04
-24
0.16
-24
0.04
-8
0.04
-8
-8
0.02
-16
0.01
-24
0.02
-24
mA
mA
IOL
MAX
24
24
24
24
24
24
8
8
8
16
24
24
mA
PARAMETER
PARAMETER
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
tw
INPUT
OUTPUT
High
Low
tsu
th
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
D
Q
MAX or MIN
LS
S
ALS
AS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
LVTH
MIN
MIN
MIN
MIN
MAX
MAX
MAX
15
15
5
20
18
18
30
6
7.3
0
10
12
12
14
10
10
7
12
16
22
4.5
2
3
6
6
11.5
6
2
3
8
6
13
20
13
12
38
38
44
24
15
5
45
45
53
25
13
10
44
44
44
24
20
15
48
48
53
7.5
2
5.5
9.3
9.5
9.3
3.3
1.9
1
5.9
6.2
6.6
3
1.1
1.4
3.9
3.9
4.2
MAX
MAX
MAX
30
28
36
18
15
18
23
18
20
7.5
6.5
9.5
8
12
8.5
44
38
38
53
45
45
44
44
44
53
53
53
8.8
11.8
12
7.2
5.2
6.7
4.2
4.8
4.8
LE
Q
OE
Q
OE
Q
MAX
MAX
25
20
9
12
10
12
6.5
7
7.5
6
38
38
45
45
44
44
53
53
7
7.4
6.9
6.5
4.6
4.5
INPUT
OUTPUT
MAX or MIN
AC
11
SN74
AC
CD74
AC
ACT
11
SN74
ACT
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
LVC
3V
ALVCH
3V
MIN
MIN
MIN
MIN
MAX
4
3.5
2
10.3
4.5
4.5
1
10.5
4
4
2
3
8.5
5
3.5
3.5
11.8
8
8
1
11.5
4
4
2
3
10.4
5
4
1
10.5
6.5
1.5
3.5
10.5
5
4
1
17
5
4
1
10.5
3.3
2
1.5
6.8
3.3
0.5
1.2
3.6
MAX
MAX
MAX
8.4
11.3
10.2
10.5
10.5
10.5
8.5
12
12
10
13
12.2
11.5
11.5
11.5
10.4
12.5
12.5
10.5
10.5
10.5
10.5
14.5
14.5
17
16.5
16.5
10.5
10.5
10.5
6.8
7.6
7.6
3.6
3.3
3.3
MAX
MAX
MAX
10.8
9.7
11.1
9.5
9.5
12.5
10.5
10.5
11.5
12.5
12
12.2
10.5
10.5
12.5
13.5
13.5
12.5
11.5
11.5
10.5
13.5
13.5
12
17
17
15
11.5
11.5
10.5
7.7
7.7
7
4.8
4.8
4.4
MAX
8.7
10
11.5
10.1
10
12.5
10.5
12
15
10.5
7
4.4
High
Low
D
Q
LE
Q
OE
Q
OE
Q
UNIT fmax : MHz, other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
325
Logic Diagram
374
OCTAL D-TYPE FLIP-FLOPS
OE
● Buffered Control Inputs
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
CLK
1
11
C1
1D
3
2
1D
1Q
To Seven Other Channels
FUNCTION TABLE
INPUTS
OUTPUT
CONTROL
CLK
L
L
L
H
↑
↑
L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
PARAMETER
ICC
IOH
IOL
MAX or MIN
LS
S
ALS
AS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
LVTH
3V
UNIT
MAX
MAX
MAX
40
-2.6
24
160
-6.5
20
31
-2.6
24
128
-15
48
86
-3
24
0.08
-6
6
0.16
-6
6
0.08
-6
6
0.16
-6
6
60
-15
64
30
-32
64
5
-32
64
mA
mA
mA
MAX or MIN
AC
11
SN74
AC
CD74
AC
ACT
11
SN74
ACT
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
LVC
3V
ALVCH
3V
UNIT
MAX
MAX
MAX
0.08
-24
24
0.04
-24
24
0.16
-24
24
0.08
-24
24
0.04
-24
24
0.16
-24
24
0.04
-8
8
0.04
-8
8
-8
8
0.02
-16
16
0.01
-24
24
0.01
-24
24
mA
mA
mA
MAX or MIN
LS
S
ALS
AS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
LVTH
3V
MIN
MIN
35
15
75
6
35
14
125
4
70
7
24
20
20
24
25
20
20
24
70
7
150
3.3
150
3.3
MIN
MIN
15
20
7.3
5
14
10
3
2
6
2
20
25
24
18
20
25
24
18
6.5
3.3
1.9
3.3
1.5
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
INPUT
OUTPUT
High
Low
tsu
th
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
fmax
tw
CLK
Q
OE
Q
OE
Q
INPUT
OUTPUT
High
Low
tsu
th
tPLH
CLK
tPHL
tPZH
OE
tPZL
tPHZ
OE
tPLZ
UNIT fmax : MHz, other : ns
326
Q
Q
Q
MIN
MAX
0
28
2
15
0
12
2
8
2
10
5
45
5
50
10
45
5
50
0
10.6
2.1
6.2
0.8
4.5
MAX
MAX
MAX
MAX
MAX
28
26
28
28
20
17
15
18
9
12
16
17
18
10
18
9
6
10
6
6
10
12.5
8.5
8
6.5
45
38
38
38
38
50
45
45
41
41
45
38
38
38
38
50
42
42
45
45
10
12.3
12.7
6.8
6.8
7.1
5.2
6.7
6.7
6.5
4.2
4.7
4.7
4.6
4.5
MAX or MIN
AC
11
SN74
AC
CD74
AC
ACT
11
SN74
ACT
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
LVC
3V
ALVCH
3V
MIN
MIN
MIN
MIN
95
5
5
2.5
100
4.5
4.5
4.5
12.5
4
4
2
55
9
9
3
90
5
5
5.5
110
4.5
4.5
2
75
5
5
3
75
6.5
6.5
2.5
50
5.5
5.5
4.5
75
5
5
3
100
3.3
3.3
2
150
3.3
3.3
1.8
MIN
MAX
MAX
MAX
MAX
MAX
MAX
3.5
10.2
10.1
9.1
9.4
11.2
9.2
1.5
10.5
10
9.5
9.5
12.5
10
2
10.8
10.8
14.5
14.5
14.5
14.5
5.5
12.4
13
12.3
12.3
13.2
10.8
1.5
11.5
11
10.5
10.5
12.5
10
3
11.2
11.2
14.5
14.5
14.5
14.5
2
11.5
11.5
11
11
10
10
2.5
11.5
11.5
12.5
12.5
12
12
2
18.5
18.5
16.5
16.5
16
16
2
11.5
11.5
11
11
10
10
1.5
7
7
7.5
7.5
6.5
6.5
0.5
3.6
3.6
5.2
5.2
4.5
4.5
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
375
DATA
4-BIT BISTABLE LATCHES
TO OTHER
LATCH
Q
Q
● Complementary Outputs (Q, Q)
ENABLE
FUNCTION TABLE
INPUTS
D
L
H
X
C
H
H
L
OUTPUTS
Q
L
H
Q0
H
L
Q0
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LS
SN74
HC
UNIT
MAX
MAX
MAX
12
-0.4
8
0.04
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
D
Q
D
Q
C
Q
C
Q
MAX or MIN
LS
SN74
HC
MIN
MIN
MIN
MAX
MAX
20
20
0
27
17
20
25
5
30
30
MAX
MAX
MAX
MAX
MAX
20
15
27
25
30
30
30
33
33
33
MAX
15
33
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
327
377
OCTAL D-TYPE FLIP-FLOPS
● Individual Data Input to Each Flip-Flop
● 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
11
CLK
1
CLKEN
3
1D
2
1D
1Q
C1
To Seven Other Channels
FUNCTION TABLE
INPUTS
OUTPUTS
CLKEN
CLOCK
DATA
Q
Q
H
L
L
X
X
↑
↑
L
X
H
L
X
Q0
H
L
Q0
Q0
L
H
Q0
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
ABT
AC
11
UNIT
MAX
MAX
MAX
28
-0.4
8
90
-1
20
0.08
-4
4
0.16
-4
4
0.08
-4
4
0.16
-4
4
30
-32
64
0.08
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
INPUT
OUTPUT
DATA
CLKEN ACTIVE
CLKEN INACTIVE
th
tPLH
tPHL
UNIT fmax : MHz, other : ns
328
CLK
Q
MAX or MIN
LS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
ABT
AC
11
MIN
MIN
MIN
MIN
MIN
MIN
MAX
MAX
30
20
20
25
10
5
27
27
110
5
2
2.5
4.5
1
10
10.5
20
25
25
25
25
5
40
40
20
24
18
18
3
53
53
17
25
15
15
15
3
45
45
16
30
18
18
3
57
57
150
3.3
2.5
3
3
1.8
6.5
7.3
100
5
4
6
6
0
11.3
12.9
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
378
HEX D-TYPE FLIP-FROPS
Logic Diagram
D
CLOCK
CK
EN
D
TO 7('LS377)
5('LS378)
3('LS379)
OTHER FILIP-FLOPS
CK
Q
Q
Q
('LS379
ONLY)
Q
ENABLE
G
FUNCTION TABLE
INPUTS
G
H
L
L
X
CLOCK
X
↑
↑
L
OUTPUTS
Q
Q0
H
L
Q0
DATA
X
H
L
X
Q
Q0
L
H
Q0
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LS
F
SN74
HC
UNIT
MAX
MAX
MAX
22
-0.4
8
45
-1
20
0.08
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
INPUT
OUTPUT
CLK H
CLK L
DATA
G ACTIVE
G INACTIVE
th
tPLH
tPHL
UNIT fmax : MHz, other : ns
CLK
Q
MAX or MIN
LS
F
SN74
HC
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MAX
MAX
30
20
20
20
25
10
110
4
6
5
3.5
5
0
6.7
6.1
20
25
25
25
25
25
5
40
40
5
27
27
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
329
390
DUAL DECADE COUNTERS
●
●
●
●
Individual Clock for A and B Flip-Flops Provide Dual ÷ 2 and ÷ 5 Counters
All Have Direct Clear for Each 4-Bit Counter
Typical maximum Count Frequency: 35MHz
Buffered Outputs Reduce Possibility of Collector Commutation
Logic Diagram
4(12)
nCP1
Q
1(15)
nCP0
Q
Φ
R
2(14)
nMR
Q
Φ
Q
Φ
R
Φ
R
R
VCC = 16
GND = 8
3(13)
nQ0
5(11)
nQ1
6(10)
nQ2
RECOMMENDED OPERATING CONDITIONS
FUNCTION TABLE
BCD COUNT SEQUENCE
COUNT
0
1
2
3
4
5
6
7
8
9
OUTPUTS
QD QC QB
L
L
L
L
L
L
L
L
H
L
L
H
H
L
L
H
L
L
H
H
L
H
H
L
H
L
L
H
L
L
PARAMETER
QA
L
H
L
H
L
H
L
H
L
H
ICC
IOH
IOL
0
1
2
3
4
5
6
7
8
9
330
OUTPUTS
QA QD QC
L
L
L
L
L
L
L
L
H
L
L
H
H
L
L
L
H
L
L
L
H
L
H
H
H
L
H
H
H
L
PARAMETER
fmax
QB
L
H
L
H
L
L
H
L
H
L
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
UNIT
MAX
MAX
MAX
69
-0.8
16
26
-0.4
8
0.08
-4
4
0.16
-4
4
0.16
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
BI-QUINARY
COUNT
7(9)
nQ3
tw
INPUT
OUTPUT
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
A
B
QA
QB
MIN
MIN
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
25
20
20
25
20
25
20
20
60
60
21
21
39
39
21
21
39
25
12.5
20
40
20
25
20
20
60
60
21
21
39
39
21
21
39
25
25
20
20
20
5
30
30
72
72
33
33
46
46
33
33
41
20
20
24
24
15
53
53
56
56
74
74
54
54
57
18
18
29
29
20
60
60
126
126
65
65
83
83
63
63
63
A
B
CLR H
tsu
tPLH
A
tPHL
tPLH
A
tPHL
tPLH
B
tPHL
tPLH
B
tPHL
tPLH
B
tPHL
tPHL
CLR
UNIT fmax : MHz, other : ns
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
QA
QC
QB
QC
QD
Q
Logic Diagram
393
R
CLR
DUAL 4-BIT BINARY
COUNTERS
CLK
●
●
●
●
Q
QA
Q
QB
Q
QC
Q
QD
T
Dual 4-Bit Binary Counter with Individual Clock
All Have Direct Clear for Each 4-Bit Counter
Typical maximum Count Frequency: 35MHz
Buffered Outputs Reduce Possibility of Collector
Commutation
R
T
R
FUNCTION TABLE
T
INPUTS
COUNT
QD QC QB QA
0
L
L
L
L
H
L
L
L
1
H
L
L
L
2
H
H
3
L
L
H
4
L
L
L
H
L
H
L
5
H
H
L
6
L
H
7
H
H
L
L
8
L
H
L
9
H
H
L
L
10
H
L
H
L
11
L
H
H
H
12
H
L
L
H
13
H
L
H
H
H
14
H
H
L
15
H
H
H
H
R
T
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
LV
3V
LV
5V
UNIT
MAX
MAX
MAX
64
-0.8
16
26
-0.4
8
0.08
-4
4
0.16
-4
4
0.16
-4
4
-6
6
0.02
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
INPUT
OUTPUT
A
B
CLR H
tsu
tPLH
A
tPHL
tPLH
B
tPHL
tPHL
CLR
UNIT fmax : MHz, other : ns
QA
QD
Q
MAX or MIN
TTL
LS
SN74
HC
CD74
HC
CD74
HCT
LV
3V
LV
5V
MIN
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
MAX
25
20
25
20
25
20
20
60
60
39
25
20
40
20
25
20
20
60
60
39
25
20
20
20
5
30
30
72
72
41
20
24
24
24
59
59
86
86
41
18
29
29
24
48
48
93
93
48
35
5
5
5
5
19
19
26.5
26.5
18
75
5
5
5
4
12
12
16.5
16.5
11.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
331
395
CASCADABLE UNIVERSAL SHIFT REGISTERS
● 3-State Outputs
● Parallel-In, Parallel-Out Registers
● Low Power Dissipation: 75mW Typical (Enable)
Logic Diagram
DATA INPUTS
A
B
(3)
C
(4)
D
(6)
(5)
(7)
LD/SH
(2)
SER
(10)
CLK
S
Q
S
Q
S
Q
S
Q
CK
CK
CK
CK
R Q
CLR
R Q
CLR
R Q
CLR
R Q
CLR
(1)
CLR
(9)
OC
(15)
QA
(14)
QB
3-STATE OUTPUTS
332
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(13)
QC
(12)
QD
(11)
QD'
CASCADE
OUTPUT
FUNCTION TABLE
INPUTS
CLEAR
L
H
H
H
H
H
X
H
H
L
L
L
X
H
↓
H
↓
↓
QA
QB
QC
QD
CASCADE
OUTPUT
QD
L
QA0
a
QA0
H
L
L
QB0
b
QBn
QAn
QAn
L
QC0
c
QCn
QBn
QBn
L
QD0
d
QDn
QCn
QCn
L
QD0
d
QDO
QCn
QCn
3-STATE OUTPUTS
LOAD/SHIFT
CLOCK SERIAL
CONTROL
X
X
X
X
H
L
PARALLEL
B
X
X
b
X
X
X
A
X
X
a
X
X
X
C
X
X
c
X
X
X
D
X
X
d
X
X
X
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
UNIT
MAX
34
mA
QA, QB, QC, QD
MAX
-2.6
mA
QD'
QA, QB, QC, QD
MAX
MAX
-0.4
24
mA
mA
MAX
8
mA
PARAMETER
ICC
IOH
IOL
QD'
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
INPUT
OUTPUT
LD/SH
OTHER
th
tPLH
CLK
tPHL
UNIT fmax : MHz, other : ns
Q
MAX or MIN
LS
MIN
MIN
MIN
MIN
30
16
40
20
MIN
MAX
MAX
10
30
30
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
333
399
QUAD 2-INPUT MULTIPLEXER WITH STORAGE
● Single-Rail Outputs (Q, Q)
● Select One of Two 4-Bit Data Sources and Stores Data Synchronously with System Clock
Logic Diagram
A1
WORD
SELECT
1S
QA
C1
A2
1R
B1
QB
1S
C1
B2
1R
C1
1S
QC
C1
C2
1R
D1
QD
1S
C1
D2
1R
CLOCK
RECOMMENDED OPERATING CONDITIONS
FUNCTION TABLE
INPUTS
OUTPUTS
PARAMETER
WORD
SELECT
CLOCK
L
H
X
↑
↑
L
QA
QB
QC
MAX or MIN
LS
UNIT
MAX
MAX
MAX
13
-0.4
8
mA
mA
mA
QD
C1
D1
B1
A1
B2
C2
D2
A2
QA0 QB0 QC0 QD0
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
th
OUTPUT
DATA
WORD SELECT
DATA
WORD SELECT
tPLH
tPHL
UNIT: ns
334
INPUT
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLK
Q
MAX or MIN
LS
MIN
MIN
MIN
MIN
MIN
MAX
MAX
20
25
45
0
0
27
32
423
RE-TRIGGERABLE MONO-STABLE MULTIVIBRATOR
● Will Not Trigger from Clear
Logic Diagram
Rext/Cext
Cext
A
Q
B
CLR
FUNCTION TABLE
INPUTS
CLR
A
L
X
X
H
X
X
H
L
H
↓
B
X
X
L
↑
H
OUTPUTS
Q
Q
H
L
H
L
H
L
R
Q
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LS
CD74
HC
CD74
HCT
UNIT
MAX
MAX
MAX
20
-0.4
8
0.16
-4
4
0.16
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
LS
CD74
HC
CD74
HCT
MIN
Q
MAX
Q
MAX
40
33
44
45
30
90
90
96
30
-
Q
MAX
MAX
56
27
45
96
65
65
-
t
tPLH
tPHL
tPLH
tPHL
UNIT: ns
A
B
A
B
CLR
Q
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
335
442
QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS
Logic Diagram
CS
GA
GB
GC
S0
COMMON
CONTROLS
S1
A
B
C
336
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
TRANSCEIVERS
FUNCTION TABLE
CS
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
S1
X
H
X
L
L
H
L
L
H
L
L
H
L
L
H
INPUTS
S0
GA
X
X
X
H
H
X
L
X
H
H
L
H
X
L
L
H
L
L
L
X
H
H
L
L
X
L
L
H
H
L
GB
X
X
H
H
X
H
L
X
L
L
X
H
H
X
L
TRANSFERS
BUSES
None
None
None
None
None
None
A → B, A → C
B → C, B → A
C → A, C → B
A→B
B→C
C→A
A→C
B→A
C→B
GC
X
X
H
H
H
X
L
L
X
H
L
X
L
H
X
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
UNIT
ICC
IOH
MAX
MAX
95
-15
mA
mA
IOL
MAX
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
LS
tPLH
A
B
C
B or C
A or C
A or B
MAX
14
tPHL
A
B
C
B or C
A or C
A or B
MAX
tPZL
Any G
S0, S1
A, B, C
MAX
42
36
A, B, C
A, B, C
A, B, C
MAX
MAX
MAX
32
35
25
CS
tPZH
tPLZ
tPHZ
UNIT:ns
G, S, CS
G, S, CS
G, S, CS
20
33
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
337
465
OCTAL BUFFERS 3-STATE OUTPUTS
Logic Diagram
1
G1 19
G2
A1
A2
A3
A4
A5
A6
A7
A8
2
3
4
5
6
7
8
9
12
11
14
13
16
15
18
17
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
338
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
ALS
UNIT
ICC
MAX
37
33
mA
IOH
IOL
MAX
MAX
-2.6
24
-15
24
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
tPLH
tPHL
A
tPZH
tPZL
G
tPHZ
tPLZ
UNIT:ns
OUTPUT
Y
Y
G
MAX or MIN
LS
ALS
MAX
15
18
13
12
MAX
40
45
23
25
MAX
40
10
45
18
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
339
518
8-BIT IDENTITY COMPARATOR
● Open-Collector Outputs
● 20-kΩ Pullup Resistors on Q Inputs
Logic Diagram
P7
Q7
P6
Q6
P5
Q5
P4
Q4
17
18
15
16
13
14
11
12
19
P3
Q3
P2
Q2
P1
Q1
P0
Q0
G
340
8
9
6
7
4
5
2
3
1
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
P=Q
FUNCTION TABLE
DATA
P, Q
INPUTS
ENABLE
G
P=Q
P>Q
P<Q
X
OUTPUT
P=Q
H
L
L
L
L
L
L
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALS
UNIT
ICC
IOL
PARAMETER
MAX
MAX
17
24
mA
mA
VOH
MAX
5.5
V
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
P or Q
P=Q
MAX
G
P=Q
MAX
ALS
33
15
33
15
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
341
520
8-BIT IDENTITY COMPARATOR
● 20-kΩ Pullup Resistors on Q Inputs
● 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
P7
Q7
P6
Q6
P5
Q5
P4
Q4
17
18
15
16
13
14
11
12
19
P3
Q3
P2
Q2
P1
Q1
P0
Q0
G
342
8
9
6
7
4
5
2
3
1
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
P=Q
FUNCTION TABLE
DATA
P, Q
INPUTS
ENABLE
OE
P=Q
P>Q
P<Q
X
OUTPUT
P=Q
L
H
H
H
L
L
L
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALS
F
AC
11
ICC
MAX
19
32
8
mA
IOH
MAX
-2.6
-1
-24
mA
IOL
MAX
24
20
24
mA
PARAMETER
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
INPUT
OUTPUT
MAX or MIN
P or Q
P=Q
MAX
OE
P=Q
MAX
ALS
F
AC
11
12
20
12
22
8.7
10.3
6.4
10.4
12.6
11.3
7.4
7.8
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
343
521
8-BIT IDENTITY COMPARATOR
● 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
P7
Q7
P6
Q6
P5
Q5
P4
Q4
17
18
15
16
13
14
11
12
19
P3
Q3
P2
Q2
P1
Q1
P0
Q0
G
344
8
9
6
7
4
5
2
3
1
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
P=Q
FUNCTION TABLE
DATA
P, Q
INPUTS
ENABLE
G
P=Q
P>Q
P<Q
X
OUTPUT
P=Q
L
H
H
H
L
L
L
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALS
F
AC
11
ICC
MAX
19
32
0.08
mA
IOH
IOL
MAX
MAX
-2.6
24
-1
20
-24
24
mA
mA
PARAMETER
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
UNIT: ns
F
AC
11
12
20
11
11
13
11.4
12
22
7.5
10
7.9
8.1
INPUT
OUTPUT
MAX or MIN
ALS
P or Q
P=Q
MAX
MAX
G
P=Q
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
345
Logic Diagram
533
OCTAL D-TYPE TRANSPARENT
LATCHES
1
OE
11
LE
● 3-State Bus-Driving Inverting Outputs
● Functionally Equivalent to '373, Except for Having
Inverted Outputs
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
2
C1
3
1D
1Q
1D
To Seven Other Channels
FUNCTION TABLE
OC
INPUTS
ENABLE
C
D
L
L
L
H
H
H
L
X
H
L
X
X
OUTPUT
Q
L
H
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
ABT
AC
11
SN74
AC
ACT
11
SN74
ACT
UNIT
MAX
MAX
MAX
28
-2.6
24
110
-15
48
0.08
-6
6
0.16
-6
6
0.08
-6
6
0.16
-6
6
30
-32
64
0.08
-24
24
0.04
-24
24
0.08
-24
24
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
t
tsu
th
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
346
MAX or MIN
ALS
AS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
ABT
AC
11
SN74
AC
ACT
11
SN74
ACT
MIN
MIN
MIN
15
15
7
2
2
3
20
13
5
24
15
11
25
13
5
24
15
12
3.3
2.1
2.1
4
3.5
2
5
4.5
1
5
3.5
3.5
6
4
2.5
19
13
7.5
7
38
38
50
50
44
44
51
51
6.4
6.6
9.8
8
11
10.5
11.3
9.5
11.5
11
23
18
17
9
8
6.5
44
44
38
53
53
45
44
44
44
57
57
53
7.3
7.3
5.7
11.3
10.3
10.8
11.5
11
10.5
13
12.2
12.5
11.5
11.5
11
18
10
16
9.5
6.5
7
38
38
38
45
45
45
44
44
44
53
45
45
6.7
6.9
6.5
9.7
10.5
11
11
12
11
11.4
8.9
12.8
10.3
11
11
D
Q
MAX
LE
(CD74: LE)
Q
MAX
OE
Q
MAX
OE
Q
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
534
OCTAL D-TYPE EDEGTRIGGERED FLIP-FLOPS
1
OE
11
CLK
● 3-State Bus-Driving Inverting Outputs
● '534 Have Inverted Outputs, But Otherwise Are
Functionally Equivalent to '374
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
2
C1
3
1D
1Q
1D
To Seven Other Channels
FUNCTION TABLE
OC
L
L
L
H
INPUTS
CLK
↑
↑
L
X
D
H
L
X
X
OUTPUT
Q
L
H
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
ABT
AC
11
SN74
AC
CD74
AC
ACT
11
SN74
ACT
UNIT
MAX
MAX
MAX
31
-2.6
24
128
-15
48
0.08
-6
6
0.16
-6
6
0.08
-6
6
0.16
-6
6
30
-32
64
0.08
-24
24
0.04
-24
24
0.16
-24
24
0.08
-24
24
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
CLK "H"
tw
CLK "L"
AS
SN74
HC
MIN
35
14
125
4
25
20
14
10
0
3
2
2
20
25
5
12
16
17
18
8
9
6
10
45
45
38
38
6
6
38
38
MIN
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
CLK
(CD74: CP)
Q
MAX
OE
Q
MAX
OE
Q
MAX
10
14
INPUT
OUTPUT
MAX or MIN
ACT
11
SN74
ACT
MIN
55
9
9
3
5.5
14.5
15
13.3
120
3.5
3.5
4
1.5
12.5
12
12.5
13.5
13.5
12
11.5
13.5
10.5
fmax
tsu
th
tPLH
tPHL
ALS
MIN
tsu
th
tw
MAX or MIN
CLK "H"
CLK "L"
MIN
MIN
CLK
(CD74: CP)
tPZH
OE
tPZL
tPHZ
OE
tPLZ
UNIT fmax : MHz, other : ns
Q
MAX
Q
MAX
Q
MAX
CD74
HC
SN74
HCT
20
25
20
24
24
18
5
50
50
45
45
45
45
20
25
5
45
45
37
37
37
37
CD74
HCT
ABT
AC
11
SN74
AC
CD74
AC
16
125
3.5
75
6.5
140
4
125
3.5
1.6
2
6.5
3.5
4.5
4
4
1.5
6.7
7.6
5
6.8
11.7
12.1
10.4
10.4
12
11
11.5
11.5
7.3
6.5
11.6
9.2
12.5
11
30
30
30
5
53
53
53
53
45
45
4
4
2
2
11.3
11.3
14.5
14.5
14.5
14.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
347
Logic Diagram
540
OCTAL BUFFERS AND
LINE DRIVERS
1
OE1
19
OE2
● 3-State Outputs Drive Bus Lines or Buffer Memory
Address Registers
● P-N-P Inputs Reduce D-C Loading
● Schmitt-Triggered Inputs (SN74LS540)
2
A1
18
Y1
To Seven Other Channels
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
ALS
ALS
A-1
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
LVTH
3V
CD74
AC
CD74
ACT
AHC
AHCT
UNIT
MAX
MAX
MAX
52
-15
24
22
-15
24
22
-15
48
0.08
-6
6
0.16
-6
6
0.08
-6
6
0.16
-6
6
71
-15
64
30
-32
64
5
-32
64
0.16
-24
24
0.16
-24
24
0.04
-8
8
0.04
-8
8
mA
mA
mA
MAX or MIN
LV
3V
LV
5V
LVC
3V
UNIT
ICC
MAX
-
0.02
0.01
mA
IOH
IOL
MAX
MAX
-8
8
-16
16
-24
24
mA
mA
PARAMETER
ICC
IOH
IOL
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
348
INPUT
OUTPUT
MAX or MIN
LS
ALS
ALS
A-1
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
LVTH
3V
A
Y
(CD74: Y)
MAX
15
15
12
9
12
9
25
25
33
33
25
25
36
36
6.9
4
4.8
4.8
3.8
3.8
OE
Y
(CD74: Y)
MAX
OE
Y
(CD74: Y)
MAX
25
38
25
18
15
20
10
12
15
20
10
12
38
38
38
38
48
48
48
48
38
38
38
38
53
53
53
53
10.1
11.3
9
8.5
5.9
6.4
7.3
6.2
5.2
5.3
5.6
5
INPUT
OUTPUT
MAX or MIN
CD74
AC
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
LVC
3V
A
Y
(CD74: Y)
MAX
OE
Y
(CD74: Y)
MAX
OE
Y
(CD74: Y)
MAX
68
68
12
12
12
12
7.2
7.2
13.4
13.4
13.4
13.4
8
8
10.5
10.5
10
10
10
10
12
12
12
12
12
12
16
16
17.5
17.5
8
8
10.5
10.5
10
10
5.3
5.3
6.6
6.6
7.4
7.4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
541
OCTAL BUFFERS AND
LINE DRIVERS
1
OE1
19
OE2
● 3-State Outputs Drive Bus Lines or Buffer Memory
Address Registers
● P-N-P Inputs Reduce D-C Loading
● Schmitt-Triggered Inputs (SN74LS541)
2
A1
18
Y1
To Seven Other Channels
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
ALS
ALS
A-1
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
LVTH
3V
CD74
AC
CD74
ACT
AHC
UNIT
MAX
MAX
MAX
55
-15
24
25
-15
24
25
-15
48
75
-15
64
0.08
-6
6
0.16
-6
6
0.08
-6
6
0.16
-6
6
72
-15
64
30
-32
64
5
-32
64
0.16
-24
24
0.16
-24
24
0.04
-8
8
mA
mA
mA
MAX or MIN
AHCT
LV
3V
LV
5V
LVC
3V
UNIT
ICC
MAX
0.04
-
0.02
0.01
mA
IOH
IOL
MAX
MAX
-8
8
-8
8
-16
16
-24
24
mA
mA
PARAMETER
ICC
IOH
IOL
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
LS
ALS
ALS
A-1
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
15
18
14
10
14
10
6
6
29
29
35
35
29
29
42
42
6
8.2
3.6
3.9
32
38
29
18
15
20
10
12
15
20
10
12
9.5
9.5
6.5
6
38
38
38
38
48
48
48
48
38
38
38
38
53
53
53
53
10.7
11.5
8.6
8.6
4
5.9
5.8
4.4
LVTH
3V
CD74
AC
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
LVC
3V
3.5
3.5
5.2
5.3
5.6
5
7.8
7.8
12
12
12
12
8.2
8.2
13.4
13.4
13.4
13.4
8
8
10.5
10.5
10
10
9.5
9.5
12
12
12
12
12
12
16
16
17.5
17.5
8
8
10.5
10.5
10
10
5.1
5.1
7
7
7
7
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
349
543
OCTAL REGISTERED TRANSCEIVERS
● Back-to-Back Registers for Storage
● 3-State True Outputs
● 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
A1
2
23
1
13
11
14
C1
3
1D
C1
1D
To Seven Other Channels
350
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
22
B1
FUNCTION TABLE†
INPUTS
CEAB
LEAB
OEAB
A
OUTPUT
B
H
X
X
X
Z
X
X
H
X
Z
L
H
L
X
L
L
L
L
B0‡
L
L
L
L
H
H
† A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA, LEBA, and OEBA.
‡ Output level before the indicated steady-state
input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
F
SN74
BCT
ABT
LVTH
3V
ACT
11
LVC
3V
MAX
100
8
0.25
0.19
0.08
0.01
mA
MAX
MAX
125
125
71
15
30
0.25
5
0.19
0.08
0.08
0.01
0.01
mA
mA
MAX
MAX
MAX
MAX
-3
-15
24
64
-15
-15
64
64
-32
-32
64
64
-32
-32
64
64
-24
-24
24
24
-24
-24
24
24
mA
mA
mA
mA
ICCH
ICCL
ICCZ
A
B
A
B
IOH
IOL
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
t
tsu
th
LE before
LE before
CE before
CE before
LE
LE
CE
CE
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
after
after
after
after
MAX or MIN
F
SN74
BCT
ABT
LVTH
3V
ACT
11
LVC
3V
MIN
5
3.5
3.5
-
7
4.5
4.5
-
3.5
3.5
3
3.5
3
3.3
0.4
1
0.2
0.7
4
2.5
2.5
3
3
3.3
1.6
1.6
1.6
1.6
3.5
3.5
8.5
7.5
12.5
1.5
1.5
8.8
9.6
12.9
0.5
0.5
0.5
0.5
6.9
6.9
6.6
1.5
1.3
1.6
1.4
3.7
3.7
4.7
2
2
1.5
1.5
10.2
12.1
11.2
2.1
2.1
2.1
2.1
7
7
8.5
12.5
12.5
12.5
10
12
9
8.5
10
12
9
8.5
12.7
12.9
12.7
10.7
12.3
8.1
7.2
12
13.5
8.5
7.6
7.1
6.6
7.1
6.4
7.5
8.4
8
6.4
7.5
8.4
8
4.7
4.7
4.7
4.9
4.9
5.3
5.3
5.3
5.3
5.4
5.4
13.2
11.2
13.2
11.5
15.3
10.4
10.5
12.2
16
11
11.1
8.5
8.5
8.5
7.7
7.7
7
7
8
8
7
7
"H"
"L"
"H"
"L"
MIN
"H"
"L"
"H"
"L"
MIN
A or B
B or A
MAX
LEBA
A
MAX
LEAB
B
MAX
OE
A or B
MAX
OE
A or B
MAX
CE
A or B
MAX
CE
A or B
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
351
561
SYNCHRONOUS 4-BIT COUNTER
● 3-State Outputs
● Choice of Asynchronous or Synchronous Clearing and Loading
● Internal Look-Ahead Circuitry for Fast Cascading
Logic Diagram
OE
ENT
ENP
SCLR
SLOAD
CLK
ACLR
ALOAD
A
17
12
7
18
9
11
19
RCO
2
8
1
3
R
S
C1
1D
B
CCO
16
QA
4
R
S
C1
1D
C
15
QB
5
R
S
C1
1D
D
14
QC
6
R
S
C1
1D
352
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
13
QD
FUNCTION TABLE
INPUTS
OE
H
L
L
L
L
L
L
L
ENP CLK
X
X
X
X
X
X
↑
X
↑
X
↑
H
X
X
L
X
ACLR ALOAD SCLR SLOAD ENT
X
X
X
X
X
L
X
X
X
X
H
L
X
X
X
H
H
L
X
X
H
H
H
L
X
H
H
H
H
H
H
H
H
H
L
H
H
H
H
X
OPERATION
Q outputs disabled
Asynchronous clear
Asynchronous load
Synchronous clear
Synchronous load
Count
Inhibit counting
Inhibit counting
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALS
UNIT
MAX
36
mA
ICC
IOH
OUTPUT Q
CCO & RCO
MAX
MAX
-2.6
-0.4
mA
mA
IOL
OUTPUT Q
CCO & RCO
MAX
MAX
24
8
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
INPUT
OUTPUT
CLK "H"
CLK "L"
MAX or MIN
ALS
MIN
30
16.5
16.5
MIN
H
L
A, B, C, D
L
SCLR
H
ENP or
ENT
SLOAD
MIN
L
H
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
UNIT fmax : MHz, other : ns
MIN
CLK
Q
MAX
CLK
RCO
MAX
ALOAD
Q
MAX
ALOAD
CCO
MAX
ENT
RCO
MAX
ACLR
Q
MAX
20
20
20
15
30
15
30
0
12
18
29
24
35
23
55
33
16
14
22
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
353
Logic Diagram
563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH INVERTED OUTPUTS
1
OE
11
LE
● 3-State Buffer-Type Outputs Drive Bus Lines
Directly
● Bus-Structured Pinout
C1
2
1D
19
1D
To Seven Other Channels
FUNCTION TABLE
OE
INPUTS
ENABLE
LE
D
OUTPUT
Q
L
L
L
H
H
H
L
X
H
L
X
X
L
H
Q0
Z
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
AC
CD74
AC
SN74
ACT
UNIT
ICC
IOH
MAX
MAX
29
-2.6
0.08
-6
0.16
-6
0.08
-6
0.16
-6
0.08
-24
0.16
-24
0.04
-24
mA
mA
IOL
MAX
24
6
6
6
6
24
24
24
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
t
tsu
th
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
354
INPUT
OUTPUT
MAX or MIN
MIN
D
Q
MAX
LE
(CD74: LE)
Q
MAX
OE
Q
MAX
OE
Q
MAX
ALS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
AC
CD74
AC
SN74
ACT
15
10
10
18
14
20
13
5
44
44
24
15
4
45
45
25
13
10
44
44
24
15
5
45
45
5
2.5
2
11.5
11
4
2
3
10.5
10.5
3
4.5
0
12.5
11
22
21
18
18
10
15
44
44
38
38
38
38
50
50
45
45
45
45
44
44
44
44
44
44
53
53
53
53
53
53
11
9.5
10
9.5
12
9
12
12
10.5
10.5
11.5
11.5
11.5
10.5
10
9.5
11.5
8.5
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1Q
Logic Diagram
564
OCTAL D-TYPE EDGETRIGGERED FLIP-FLOPS
OE
CLK
● 3-State Buffer-Type Inverting Outputs Drive Bus
Lines Directly
● Bus-Structured Pinout
1
11
C1
1D
2
19
1Q
1D
To Seven Other Channels
FUNCTION TABLE
OE
L
L
L
H
INPUTS
CLK
↑
↑
L
X
D
H
L
X
X
OUTPUT
Q
L
H
Q0
Z
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
AC
SN74
ACT
UNIT
ICC
IOH
MAX
MAX
30
-2.6
0.08
-6
0.16
-6
0.08
-6
0.16
-6
0.04
-24
0.04
-24
mA
mA
IOL
MAX
24
6
6
6
6
24
24
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
CLK H
CLK L
CLK
tsu
CLK
th
tPLH
CLK
tPHL
tPZH
OE
tPZL
tPHZ
OE
tPLZ
UNIT fmax : MHz, other : ns
MAX or MIN
ALS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
AC
SN74
ACT
MIN
30
14
14
15
0
25
20
20
25
5
20
24
24
18
5
25
20
20
25
5
16
30
30
30
3
85
5
5
2.5
2
75
3.5
3.5
3
1
14
14
18
18
10
15
45
45
38
38
38
38
50
50
45
45
41
41
45
45
38
38
38
38
53
53
53
53
45
45
11.5
10.5
9.5
9.5
11.5
9
11.5
10.5
9.5
9.5
11.5
8.5
MIN
Q
MAX
Q
MAX
Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
355
569
SYNCHRONOUS 4-BIT UP/DOWN COUNTERS
●
●
●
●
3-State Q Outputs Drive Bus Lines Directly
Fully Synchronous Clear, Count, and Load
Asynchronous Clear Is Also Provided
Fully Cascadable
Logic Diagram
OE
U/D
CLK
ENT
ENP
17
1
2
12
18
19
SCLR
LOAD
ACLR
A
9
8
3
15
QB
14
QC
6
C1
1D
R
356
QA
5
C1
1D
R
D
16
4
C1
1D
R
C
RCO
11
C1
1D
R
B
CCO
7
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
13
QD
FUNCTION TABLE
INPUTS
OE
H
L
L
L
L
L
L
L
ACLR SCLR LOAD ENT
X
L
H
H
H
H
H
H
X
X
L
H
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
X
L
L
H
X
ENP
U/D
CLK
X
X
X
X
L
L
X
H
X
X
X
X
H
L
X
X
X
X
↑
↑
↑
↑
X
X
OPERATION
Q outputs disabled
Asynchronous clear
Synchronous clear
Load
Count up
Count down
Inhibit count
Inhibit count
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
OUTPUT Q
IOL
CCO & RCO
OUTPUT Q
MAX or MIN
ALS
UNIT
MAX
32
-2.6
-0.4
mA
mA
mA
24
8
mA
mA
MAX
MAX
CCO & RCO
SWITCHING CHARACTERISTICS
INPUT
PARAMETER
fmax
tw
tsu
OUTPUT
ACLR, LOAD
CLK "H"
CLK "L"
Data at A, B, C, D
High
ENP, ENT
Low
High
SCLR
Low
LOAD
MAX or MIN
ALS
MIN
MIN
30
15
16.5
MIN
16.5
20
30
20
15
30
MIN
15
30
30
10
0
High
Low
UD
ACLR
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT fmax : MHz, other : ns
CLK
ANY Q
MAX
CLK
RCO
MAX
ENT
RCO
MAX
ACLR
Q
MAX
OE
Q
MAX
OE
Q
MAX
13
16
28
19
15
13
20
18
24
10
13
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
357
Logic Diagram
573
OCTAL D-TYPE TRANSPARENT
LATCHES
OE
LE
● 3-State Buffer-Type Outputs Drive Bus Lines
Directly
● Bus-Structured Pinout
1
11
C1
1D
2
19
1D
1Q
To Seven Other Channels
FUNCTION TABLE
OE
INPUTS
ENABLE
LE
D
L
L
L
H
H
H
L
X
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
LVTH
3V
SN74
AC
CD74
AC
SN74
ACT
UNIT
MAX
MAX
MAX
27
-2.6
24
106
-15
48
55
-3
24
0.08
-6
6
0.16
-6
6
0.08
-6
6
0.16
-6
6
62
-15
64
30
-32
64
5
-32
64
0.04
-24
24
0.16
-24
24
0.04
-24
24
mA
mA
mA
MAX or MIN
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
LVC
3V
UNIT
MAX
MAX
MAX
0.16
-24
24
0.04
-8
8
0.04
-8
8
-8
8
0.02
-16
16
0.01
-24
24
mA
mA
mA
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
SWITCHING CHARACTERISTICS
PARAMETER
t
tsu
th
tPLH
tPHL
tPLH
ALS
AS
10
4.5
6
20
24
25
24
4
3.3
3.3
MIN
10
7
14
14
20
2
3
8
7
13
2
3
8
6
13
13
5
44
44
44
15
12
53
53
53
13
5
44
44
44
20
15
53
53
53
1
4
8.4
9.6
8.1
1.9
1.8
5.9
6.2
6.6
0.7
1.5
3.9
3.9
4.2
19
18
18
10
15
7.5
6.5
9.5
6.5
7
8
12
8.5
7.5
6
44
38
38
38
38
53
45
45
45
45
44
44
44
44
44
53
53
53
53
53
7.8
10.4
11
6
6
7.2
5.2
6.7
7.1
6.5
4.2
5.1
5.1
4.9
4.6
SN74
AC
CD74
AC
SN74
ACT
CD74
ACT
AHC
AHCT
LV
5V
LV
3V
LVC
3V
5
3.5
2
11.5
11
11
10
10
9.5
12
9
4
2
3
8.5
8.5
12
12
10.5
10.5
11.5
11.5
4
3.5
0
12
12
12
10.5
11
10.5
12.5
9.5
4
2
3
10.4
10.4
12.5
12.5
13.5
13.5
12.5
12.5
5
3.5
1.5
10
10
11
11
11
11
11
11
5
3.5
1.5
7.5
10
8.5
10
8
11
12
10.5
5
3.5
1.5
10
10
11
11
11
11
11
11
5
3.5
1.5
16.5
16.5
17.5
17.5
17
17
16.5
16.5
3.3
2
1.5
6.9
6.9
7.7
7.7
7.5
7.5
6.5
6.5
D
Q
MAX
LE
Q
MAX
OE
Q
MAX
OE
Q
MAX
INPUT
OUTPUT
MAX or MIN
LE
MIN
LE
LE
D
Q
MAX
LE
(CD74AC/ACT: LE)
Q
MAX
OE
Q
MAX
OE
Q
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
F
LVTH
3V
MAX or MIN
LE
PARAMETER
358
OUTPUT
LE
LE
tPHL
tPZH
tPZL
tPHZ
tPLZ
t
tsu
th
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
Logic Diagram
574
OCTAL D-TYPE EDGETRIGGERED FLIP-FLOPS
OE
CLK
● 3-State Buffer-Type Noninverting Outputs Drive
Bus Lines Directly
● Bus-Structured Pinout
1
11
C1
1D
2
OE
L
L
L
H
↑
↑
L
X
1Q
To Seven Other Channels
FUNCTION TABLE
INPUTS
CLK
19
1D
OUTPUT
Q
H
L
Q0
Z
D
H
L
X
X
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
LVTH
3V
SN74
AC
CD74
AC
SN74
ACT
UNIT
MAX
MAX
MAX
28
-2.6
24
134
-15
48
86
-3
24
0.08
-6
6
0.16
-6
6
0.08
-6
6
0.16
-6
6
62
-15
64
30
-32
64
5
-24
24
0.04
-24
24
0.16
-24
24
0.04
-24
24
mA
mA
mA
MAX or MIN
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
LVC
3V
UNIT
MAX
MAX
MAX
0.16
-24
24
0.04
-8
8
0.04
-8
8
-8
8
0.02
-16
16
0.01
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
tsu
th
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
MAX or MIN
ALS
AS
F
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
LVTH
3V
MIN
MIN
MIN
35
14
15
125
5.5
5.5
100
7
2
24
20
25
20
24
18
24
20
25
20
24
18
77
6.5
6
150
3.3
1.5
150
3.3
2
MIN
0
14
14
18
18
10
12
0
8
9
6
10
6
6
2
10
10
12.5
8.5
8
6.5
5
45
45
38
38
38
38
5
50
50
45
45
41
41
5
45
45
38
38
38
38
5
50
50
45
45
42
42
0
10
8.9
10.4
10.9
7.5
6.4
1.8
6.8
7.1
5.1
6.7
7
6.5
0.3
4.5
4.5
4.8
4.8
4.8
4.4
SN74
AC
CD74
AC
SN74
ACT
CD74
ACT
AHC
AHCT
LV
3V
LV
5V
LVC
3V
85
5
2
1.5
11
9.5
9
9
10.5
8.5
125
4
2
2
10.8
10.8
14.5
14.5
14.5
14.5
85
4
2.5
0
12
11
10
10
11.5
9
110
4.5
2
3
11.2
11.2
14.5
14.5
14.5
14.5
75
5
3
1.5
12
12
12.5
12.5
11.5
11.5
75
5.5
3.5
1.5
12
12
12.5
12.5
11.5
11.5
45
5
3.5
1.5
19
19
18.5
18.5
17
17
75
5
3.5
1.5
12
12
12.5
12.5
11.5
11.5
100
3.3
2
1.5
7
7
7.5
7.5
6.4
6.4
CLK
Q
MAX
OE
Q
MAX
OE
Q
MAX
INPUT
OUTPUT
MAX or MIN
fmax
tw
tsu
th
tPLH
CLK
tPHL
tPZH
OE
tPZL
tPHZ
OE
tPLZ
UNIT fmax : MHz, other : ns
MIN
MIN
MIN
MIN
Q
MAX
Q
MAX
Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
359
Logic Diagram
575
OCTAL D-TYPE EDGETRIGGERED FLIP-FLOPS
OE
CLK
● 3-State Buffer-Type Noninverting Outputs Drive
Bus Lines Directly
● Bus-Structured Pinout
● Synchronous Clear
CLR
2
14
1
C1
1D
3
1D
To Seven Other Channels
FUNCTION TABLE
OE
L
L
L
L
H
INPUTS
CLR CLK
L
↑
H
↑
H
↑
H
L
X
X
D
X
H
L
X
X
OUTPUT
Q
L
H
L
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
UNIT
MAX
MAX
MAX
30
-2.6
24
142
-15
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tsu
CLK
H
CLK
L
DATA
th
L
CLR
DATA
tw
CLR
tPLH
CLK
tPHL
tPZH
OC
tPZL
tPHZ
OC
tPLZ
UNIT fmax : MHz, other : ns
360
MAX or MIN
ALS
AS
MIN
30
90
5.5
5.5
16.5
MIN
15
0
Q
MAX
Q
MAX
Q
MAX
14
14
18
18
10
13
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
5.5
6.5
3
0
8
9
6
10
6
6
22
1Q
Logic Diagram
576
OCTAL D-TYPE EDGETRIGGERED FLIP-FLOPS
OE
CLK
● 3-State Buffer-Type Inverting Outputs Drive Bus
Lines Directly
● Bus-Structured Pinout
● Functionally Equivalent to '576, Except for Having
Inverted Outputs
1
11
C1
1D
2
19
1Q
1D
To Seven Other Channels
FUNCTION TABLE
OE
L
L
L
H
INPUTS
CLK
↑
↑
L
X
D
H
L
X
X
OUTPUT
Q
L
H
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
UNIT
MAX
MAX
MAX
30
-2.6
24
135
-15
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
H
L
DATA
tsu
DATA
th
tPLH
CLK
tPHL
tPZH
OE
tPZL
tPHZ
OE
tPLZ
UNIT fmax : MHz, other : ns
MAX or MIN
ALS
AS
MIN
30
125
4
2
16.5
MIN
Q
MAX
Q
MAX
Q
MAX
15
0
14
14
18
18
10
15
2
2
8
9
6
10
6
6
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
361
Logic Diagram
577
OCTAL D-TYPE EDGETRIGGERED FLIP-FLOPS
2
OE
14
CLK
● 3-State Buffer-Type Inverting Outputs Drive Bus
Lines Directly
● Bus-Structured Pinout
● Synchronous Clear
1
CLR
C1
3
1D
1D
To Seven Other Channels
FUNCTION TABLE
OE
L
L
L
L
H
INPUTS
CLK
CLR
L
H
H
H
X
↑
↑
↑
L
X
D
X
H
L
X
X
OUTPUT
Q
H
L
H
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
UNIT
MAX
MAX
MAX
30
-2.6
24
142
-15
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
MAX or MIN
ALS
AS
MIN
30
16.5
15
0
125
4
2
2
14
14
18
18
10
15
8
9
6
10
6
6
t
DATA
tsu
th
CLR
tPLH
CLK
tPHL
tPZH
OE
tPZL
tPHZ
OE
tPLZ
UNIT fmax : MHz, other : ns
362
MIN
Q
MAX
Q
MAX
Q
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
22
1Q
Logic Diagram
580
OCTAL D-TYPE TRANSPARENT
LATCHES WITH INVERTED
OUTPUTS
OE
LE
1
11
C1
● 3-State Buffer-Type Outputs Drive Bus Lines
Directly
● Inverting-Logic Outputs
● Bus-Structured Pinout
1D
2
19
1Q
1D
To Seven Other Channels
FUNCTION TABLE
OE
L
L
L
H
INPUTS
ENABLE
LE
H
H
L
X
OUTPUT
Q
D
H
L
X
X
L
H
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
UNIT
MAX
MAX
MAX
29
-2.6
24
115
-15
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
t
tsu
th
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
C
MIN
C
C
D
Q
MAX
LE
Q
MAX
OE
Q
MAX
OE
Q
MAX
ALS
AS
15
10
10
18
2
2
3
7.5
14
22
21
18
18
10
15
7
9
8
6.5
9.5
6.5
7
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
363
590
8-BIT BINARY COUNTER WITH OUTPUT REGISTER
●
●
●
●
Parallel Register Outputs
Counter Has Direct Clear
3-State Outputs
Guaranteed Counter Frequency: DC to 20MHz
Logic Diagram
OE
14
RCLK
13
CCKEN
12
CCLK
11
CCLR
10
9
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
R
R
R
R
R
R
R
R
364
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
15
1
2
3
4
5
6
7
RCO
QA
QB
QC
QD
QE
QF
QG
QH
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
RCO
Q
IOL
RCO
Q
MAX or MIN
LS
SN74
HC
MAX
65
MAX
MAX
MAX
-1
-2.6
16
0.08
-4
MAX
24
UNIT
mA
-6
4
mA
mA
mA
6
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
INPUT
OUTPUT
MAX or MIN
LS
SN74
HC
CCK
RCO
MIN
20
13
MIN
25
20
31
25
CCK
CCLR
RCK
tsu
CCLR
bofore CCK
tPHL
tPLH
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT fmax : MHz, other : ns
31
20
25
MIN
CCK
bofore RCK
tPLH
20
CCK
RCO
MAX
CCLR
RCO
MAX
RCK
Q
MAX
G
Q
MAX
G
Q
MAX
40
25
22
45
30
45
45
39
18
33
38
42
42
37
45
30
38
37
37
37
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
365
592
8-BIT BINARY COUNTER WITH INPUT REGISTER
● Parallel Register Inputs
● Counter Has Directly Overriding Load and Clear
● Accurate Counter Frequency: DC to 20MHz
Logic Diagram
(10)
CCLR
(12)
CCKEN
(9)
(11)
CCK
(14)
CLOAD
RCK
A
(13)
(15)
S
1D
T
C1
R
B
(1)
S
1D
T
C1
R
C
(2)
S
1D
T
C1
R
D
(3)
S
1D
T
C1
R
E
(4)
S
1D
T
C1
R
F
(5)
S
1D
T
C1
R
G
(6)
S
1D
T
C1
R
H
(7)
S
1D
T
C1
R
366
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
RCO
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
UNIT
ICC
IOH
PARAMETER
MAX
MAX
60
-1
mA
mA
IOL
MAX
16
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
INPUT
CCK
OUTPUT
MAX or MIN
LS
RCO
MIN
20
CCK
CCLR
RCK
tsu
MIN
CLOAD
CCLR
bofore CCK
20
MIN
30
20
th
tPLH
tPLH
tPHL
UNIT fmax : MHz, other : ns
20
40
20
CLOAD
bofore CCK
RCK
bofore CLOAD
A to H
bofore RCK
tPLH
tPHL
tPLH
tPHL
25
20
MIN
CCK
RCO
MAX
CLOAD
RCO
MAX
CCLR
RCO
MAX
RCK
RCO Q
MAX
0
23
30
47
17
45
53
45
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
367
593
8-BIT BINARY COUNTER WITH INPUT REGISTER
●
●
●
●
Parallel 3-State I/O: Register Inputs/Counter Outputs
Counter Has Directly Overriding Load and Clear
Accurate Counter Frequency: DC to 20MHz
74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
(19)
G
(18)
G
CCLR
CCKEN
CCKEN
CCK
CLOAD
(12)
(15)
(14)
(11)
(13)
(17)
RCKEN
RCK
Gating for RCK
is similar in detail
to that shown for
CCK.
(9)
(16)
(1)
A/QA
1
G2
2
S
1D
T
C1
R
B/QB
(2)
S
1D
T
C1
R
C/QC
(3)
S
1D
T
C1
R
D/QD
(4)
S
1D
T
C1
R
E/QE
(5)
S
1D
T
C1
R
F/QF
(6)
S
1D
T
C1
R
G/QG
(7)
S
1D
T
C1
R
H/QH
(8)
S
1D
T
C1
R
368
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
RCO
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
RCO
Q
IOL
RCO
Q
MAX or MIN
LS
ACT
11
UNIT
MAX
85
0.08
mA
MAX
MAX
MAX
-1
-2.6
16
-24
-24
24
mA
mA
mA
MAX
24
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
OUTPUT
MAX or MIN
LS
CCK
RCO
MIN
20
52
25
20
9.6
7.6
20
40
5.8
6.2
20
1.2
20
5.1
30
7.4
CCK
CCLR
RCK
tsu
MIN
CLOAD
CCLR
bofore CCK
CLOAD
bofore CCK
RCK
bofore CLOAD
A to H
bofore RCK
th
tPLH
ACT
11
INPUT
CCK
tPHL
tPLH
CLOAD
tPHL
tPHL
CCLR
UNIT fmax : MHz, other : ns
MIN
MIN
Q
MAX
Q
MAX
Q
MAX
20
2.4
0
21
0.8
15.1
39
51
42
38
15
19.1
21.7
16
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
369
594
8-BIT SHIFT REGISTER WITH OUTPUT LATCHE
●
●
●
●
8-Bit Serial-In, Parallel-Out Shift Registers with Storage
Independent Direct Overriding Clears on Shift and Storage Registers
Independent Clocks for Shift and Storage Registers
Guaranteed Shift Frequency: DC to 20MHz
Logic Diagram
RCLR
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
1D Q
C1
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
R
3D Q
C3
15
R
3D Q
C3
1
R
3D Q
C3
2
R
3D Q
C3
R
3D Q
C3
3
4
R
3D Q
C3
5
R
3D Q
C3
6
R
3D Q
C3
7
9
370
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
QA
QB
QC
QD
QE
QF
QG
QH
QH′
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
SN74
HC
AHC
AHCT
LV
3V
LV
5V
UNIT
QH'
MAX
MAX
65
-1
0.08
-4
0.04
-8
0.02
-8
-6
0.02
-12
mA
mA
Q
QH'
MAX
MAX
-2.6
16
-6
4
-8
8
-8
8
-6
6
-12
12
mA
mA
QA to QH
MAX
24
6
8
8
6
12
mA
PARAMETER
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
tw
SRCK
RCK
tsu
SRCLR
to SRCK
SER
INPUT
OUTPUT
MAX or MIN
LS
SN74
HC
AHC
AHCT
LV
3V
LV
5V
MIN
25
20
20
20
5
5
5.5
5.5
5.5
5.5
5
5
20
10
3.3
3.3
4.8
3.3
20
22
3
3
3.5
3
5
5
8.5
5
to SRCK
SRCK
to RCK
th
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
UNIT: ns
40
22
SRCLR
to RCK
MIN
40
13
5
5
9
5
RCLR
to RCK
20
5
3.7
3.8
5.3
3.7
0
18
23
5
37
37
2
9.1
10.1
2
9.1
10.1
1.5
12.4
13.9
2
9.1
10.1
18
30
33
37
37
37
8.3
9.7
10.7
8.3
9.7
10.1
11.1
13.1
14
8.3
9.7
10.1
57
31
10.1
10.7
14.4
10.7
MIN
SRCK
QH'
MAX
RCK
QA to QH
MAX
SRCLR
RCLR
QH'
QA to QH
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
371
595
8-BIT SHIFT REGISTER WITH OUTPUT LATCHE
●
●
●
●
8-Bit Serial-In, Parallel-Out Shift Registers with Storage
3-State Outputs
Shift Register Has Direct Clear
Accurate Shift Frequency: DC to 20MHz
Logic Diagram
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
1D Q
C1
R
3D
C3 Q
15
2D Q
C2
R
3D
C3 Q
1
2D Q
C2
R
3D
C3 Q
2
2D Q
C2
R
3D
C3 Q
3
2D Q
C2
R
3D
C3 Q
4
2D Q
C2
R
3D
C3 Q
5
2D Q
C2
R
3D
C3 Q
6
2D Q
C2
R
3D
C3 Q
7
9
372
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
QA
QB
QC
QD
QE
QF
QG
QH
QH′
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
SN74
HC
AHC
AHCT
LV
3V
LV
5V
UNIT
QH'
MAX
MAX
65
-1
0.08
-4
0.04
-8
0.04
-8
-8
0.02
-16
mA
mA
QA to QH
QH'
MAX
MAX
-26
16
-6
4
-8
8
-8
8
-8
8
-16
16
mA
mA
QA to QH
MAX
24
6
8
8
8
16
mA
PARAMETER
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
tw
SRCK
RCK
tsu
SRCLR
to SRCK
SER
INPUT
OUTPUT
to SRCK
SRCK
to RCK
MAX or MIN
LS
HC
AHC
AHCT
LV
3V
LV
5V
MIN
25
20
20
20
5
5
5.5
5.5
5.5
5.5
5
5
20
12
2.5
3.8
3
2.5
20
25
3
3
3.5
3
40
19
5
5
8.5
5
40
13
5
5
9
5
0
18
25
18
35
35
0
40
40
37
37
44
2
11.4
11.4
10.5
10.5
11.1
2
11.4
11.4
10.5
10.5
11.1
1.5
18.5
18.5
17
17
17.2
2
11.4
11.4
10.5
10.5
11.1
MIN
SRCLR
to RCK
th
tPLH
tPHL
tPLH
tPHL
tPHL
UNIT: ns
MIN
SRCK
QH'
MAX
RCK
QA to QH
MAX
SRCLR
QH'
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
373
596
8-BIT SHIFT REGISTER WITH OUTPUT LATCHE
●
●
●
●
8-Bit Serial-In, Parallel-Out Shift Registers with Storage
Open-Collector Parallel Outputs
Shift Register Has Direct Clear
Accurate Shift Frequency: DC to 20MHz
Logic Diagram
G
RCK
SRCLR
SRCK
SER
(13)
(12)
(10)
(11)
(14)
1R
C1
R
2S
2R
C2
R
2S
2R
C2
R
2S
2R
C2
R
2S
2R
C2
R
2S
2R
C2
R
2S
2R
C2
R
2S
2R
C2
R
374
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
3R
(15)
QA
C3
3S
3R
(1)
QB
C3
3S
3R
(2)
QC
C3
3S
3R
(3)
QD
C3
3S
3R
(4)
QE
C3
3S
3R
(5)
QF
C3
3S
3R
(6)
QG
C3
3S
3R
(7)
QH
C3
3S
(9)
QH'
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
UNIT
QH'
MAX
MAX
55
16
mA
mA
IOL
Q
QH'
MAX
MAX
24
-1
mA
mA
VOH
QA to QH
MAX
5.5
V
ICC
IOH
SWITCHING CHARACTERISTICS
PARAMETER
tw
SRCK
RCK
tsu
SRCLR
to SRCK
SER
INPUT
OUTPUT
MAX or MIN
LS
MIN
25
20
20
20
to SRCK
SRCK
to RCK
MIN
40
SRCLR
to RCK
th
tPLH
tPHL
tPLH
tPHL
tPHL
UNIT: ns
40
MIN
SRCK
QH'
MAX
RCK
QA to QH
MAX
SRCLR
QH'
MAX
0
21
30
42
35
35
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
375
597
8-BIT SHIFT REGISTER WITH INPUT LATCHE
● 8-Bit Parallel Storage Registers Inputs
● Shift Register Has Direct Overriding Load and Clear
● Accurate Shift Frequency: DC to 20MHz
Logic Diagram
SRCLR
SRCK
SRLOAD
RCK
SER
A
(10)
(11)
(13)
(12)
(14)
(15)
C2
1D
C1
B
(1)
(2)
(3)
(4)
(5)
(6)
(7)
3R
R
S
3R
R
S
3R
R
S
3R
R
C3 3S
1D
C1
376
S
C3 3S
1D
C1
H
3R
R
C3 3S
1D
C1
G
S
C3 3S
1D
C1
F
3R
R
C3 3S
1D
C1
E
S
C3 3S
1D
C1
D
2D
R
C3 3S
1D
C1
C
S
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
S
R
3R
(9)
QH'
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
CD74
HC
CD74
HCT
UNIT
ICC
IOH
MAX
MAX
53
-1
0.16
-4
0.16
-4
mA
mA
IOL
MAX
16
4
4
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
INPUT
OUTPUT
SRCK
SRCK
MIN
RCK
SRCLR
tsu
MAX or MIN
MIN
SRLOAD
SRCLR
to SRCK
CD74
HC
CD74
HCT
20
20
16
35
24
30
20
20
18
24
20
27
40
21
24
25
-
-
30
-
-
40
-
-
MIN
SRLOAD
to SRCK
RCK
to SRLOAD
SER
MIN
to SRCK
DATA
to RCK
th
tPLH
tPHL
tPLH
LS
SRCK
SRLOAD
tPHL
tPHL
SRCLR
tPLH
RCK
tPHL
UNIT fmax : MHz, other : ns
20
15
15
MIN
20
15
15
MIN
0
23
30
57
3
53
53
60
3
57
57
72
44
36
60
48
60
53
72
72
72
66
84
84
QH'
MAX
QH'
MAX
QH'
MAX
QH'
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
377
598
8-BIT SHIFT REGISTERS
Logic Diagram
G
SRCLR
SRCKEN
SRCK
SRLOAD
DS
(16)
(12)
(14)
(13)
(9)
(19)
SER0
SER1
RCK
A/QA
(18)
(17)
(15)
(1)
C2
1D
C1
B/QB
(2)
C/QC
(4)
(5)
(6)
(7)
(8)
S
3R
R
S
3R
R
S
3R
R
S
3R
R
C3 3S
1D
C1
378
3R
R
C3 3S
1D
C1
H/QH
S
C3 3S
1D
C1
G/QG
R
C3 3S
1D
C1
F/QF
3R
C3 3S
1D
C1
E/QE
S
C3 3S
1D
C1
D/QD
2D
R
C3 3S
1D
C1
(3)
S
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
S
R
3R
(11)
QH'
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
UNIT
ICC
MAX
85
mA
IOH
IOL
MAX
MAX
-2.6
24
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
INPUT
OUTPUT
MAX or MIN
LS
MIN
20
SRCK
QH'
MAX
17
23
SRLOAD
QH'
MAX
SRCLR
QH'
MAX
RCK
QH'
MAX
SRCK
Q
MAX
SRLOAD
Q
MAX
SRCLR
Q
MAX
G
Q
MAX
Q
MAX
SRCK
G
tPLZ
UNIT fmax : MHz, other : ns
42
30
27
48
36
18
28
48
40
38
31
43
38
30
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
379
Logic Diagram
620
OCTAL BUS TRANSCEIVERS
OEBA
● Local Bus-Latch Capability
● 3-State Inverting Outputs
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
OEAB
A1
19
1
2
18
To Seven Other Channels
FUNCTION TABLE
ENABLE INPUTS
OEBA
OEAB
L
L
H
H
H
L
L
OPERATION
B data to Abus
A data to B bus
Isoration
B data to Abus
A data to B bus
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
ALS
AS
SN74
HC
SN74
BCT
ABT
AC
11
ACT
11
UNIT
ICCZ
ICCL
IOH (A port)
IOH (B port)
IOL (A port)
MAX
MAX
MAX
MAX
MAX
95
90
-15
-15
24
47
44
-15
-15
24
77
122
-15
-15
64
0.08
0.08
-6
-6
6
10
84
-3
-15
24
0.25
30
-32
-32
64
0.08
0.08
-24
-24
24
0.008
0.008
-24
-24
24
mA
mA
mA
mA
mA
IOL (B port)
IOL*
*620-1
MAX
MAX
24
-
24
48
64
-
6
-
64
-
64
-
24
-
24
-
mA
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
380
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OEBA
A
MAX
OEBA
A
MAX
OEAB
B
MAX
OEAB
B
MAX
LS
ALS
AS
SN74
HC
SN74
BCT
ABT
AC
11
ACT
11
10
15
10
15
40
40
25
25
40
40
25
25
10
10
10
10
17
25
12
18
18
25
12
18
7
6
7
6
8
9
6
12
8
9
6
13
26
26
26
26
53
53
38
38
53
53
38
38
5.8
3.6
6.9
3.9
10.6
11.1
10
7.8
7.4
9
8.1
5.9
4.8
4.8
4.8
4.8
5.5
7.1
7
5.8
6.8
6.4
6.5
5.6
7.4
7.1
7.4
7.1
8.9
8.5
8.1
8.7
8.8
8.8
8.2
8.6
9.4
8.6
9.4
8.6
10.3
10.1
10.4
10.9
11.3
11
9.4
9.6
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
Logic Diagram
621
OCTAL BUS TRANSCEIVERS
OEBA
● Local Bus-Latch Capability
● Open-Collector True Outputs
● Schmitt-Triggered Inputs (SN74LS621)
OEAB
FUNCTION TABLE
L
1
18
A1
ENABLE INPUTS
OEBA
OEAB
L
L
H
H
H
L
19
2
B1
To Seven Other Transceivers
OPERATION
B data to Abus
A data to B bus
Isoration
B data to Abus
A data to B bus
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
VOH
IOL
MAX or MIN
LS
ALS
ALS
A-1
AS
UNIT
MAX
MAX
MAX
90
5.5
24
48
5.5
24
48
5.5
48
189
5.5
64
mA
V
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OEBA
A
MAX
OEAB
B
MAX
LS
ALS
ALS
A-1
AS
25
25
25
25
33
20
33
20
33
20
33
20
24
21
7.5
7.5
40
50
40
50
39
35
39
35
39
35
39
35
21
9
22
10
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
381
Logic Diagram
623
OCTAL BUS TRANSCEIVERS
19
OEBA
1
OEAB
●
●
●
●
Local Bus-Latch Capability
3-State True Outputs
Schmitt-Triggered Inputs (SN74LS623)
74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
2
A1
18
B1
To Seven Other Channels
FUNCTION TABLE
ENABLE INPUTS
OEAB
OEBA
L
L
H
H
H
L
L
OPERATION
B data to Abus
A data to B bus
Isoration
B data to Abus
A data to B bus
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
ALS
AS
F
SN74
HC
SN74
HCT
SN74
BCT
ABT
AC
11
ACT
11
CD74
AC
CD74
ACT
UNIT
ICCZ
ICCL
IOH (A port)
MAX
MAX
MAX
95
90
-15
55
50
-15
116
189
-15
130
140
-3
0.08
0.08
-6
0.08
0.08
-6
11
92
-3
0.25
30
-32
0.08
0.08
-24
0.04
0.04
-24
0.16
0.16
-24
0.16
0.16
-24
mA
mA
mA
IOH (B port)
IOL (A port)
MAX
MAX
-15
24
-15
24
-15
64
-15
24
-6
6
-6
6
-15
24
-32
64
-24
24
-24
24
-24
24
-24
24
mA
mA
IOL (B port)
MAX
24
24
64
64
6
6
64
64
24
24
24
24
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
382
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OEBA
A
MAX
OEBA
A
MAX
OEAB
B
MAX
OEAB
B
MAX
LS
ALS
AS
F
SN74
HC
SN74
HCT
SN74
BCT
ABT
AC
11
ACT
11
CD74
AC
CD74
ACT
15
13
9
6.5
26
28
5.2
4.6
7.8
8.5
9.6
10.6
15
15
15
40
40
25
25
40
40
25
25
11
13
11
22
22
16
19
22
22
16
19
8
9
8.5
11
10
7.5
11.5
11.5
11
7
9
7.5
6.5
7.5
12
10
7.5
7
11.5
9.5
10
10
26
26
26
53
53
38
38
53
53
38
38
28
28
28
53
53
38
38
53
53
38
38
7.4
6.7
8
10.6
10.7
9.8
7.8
7.6
8.9
7.7
7.1
4.6
4.6
4.6
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.1
7.8
7.1
9
9.1
8.3
8.8
9.2
9.4
8.3
8.8
7.9
8.5
7.9
9.7
10
10.9
11.5
10.7
10.9
9.5
10
9.6
9.6
9.6
13.4
13.4
13.4
13.4
13.4
13.4
13.4
13.4
10.6
10.6
10.6
14.4
14.4
14.4
14.4
14.4
14.4
14.4
14.4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
624
VOLTAGE-CONTROLLED OSCILLATOR
● This Voltage Oscillators (VCOs) is Improved Versions of The Original VCO Family:
SN74124, 324, 325, 326, 327
● Separate Supply Voltage Pins for Isolation of Frequency Control Inputs and Oscillators from Outputs
Circuitry
● Highly Stable Operation over Specified Temperature and / or Supply Voltage Ranges
Logic Diagram
G
Cx
Z
FC
FC
RC
RC
EN
( ’LS624,
’LS628,
’LS629 only)
Y
T
R
EN
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOL
IOH
MAX or MIN
LS
UNIT
MAX
MAX
MAX
35
24
-1.2
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fo
UNIT: MHz
MAX or MIN
LS
MAX
25
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
383
628
VOLTAGE-CONTROLLED OSCILLATOR
● This Voltage Oscillators (VCOs) is Improved Versions of The Original VCO Family:
SN74124, 324, 325, 326, 327
● Separate Supply Voltage Pins for Isolation of Frequency Control Inputs and Oscillators from Outputs
Circuitry
● Highly Stable Operation over Specified Temperature and / or Supply Voltage Ranges
● Two Rexternal Pins Can Offer More Precise Temprature Compensation
Logic Diagram
G
Cx
Z
FC
FC
RC
RC
EN
( ’LS624,
’LS628,
’LS629 only)
Y
T
R
EN
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LS
UNIT
MAX
MAX
MAX
35
-1.2
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fo
UNIT: MHz
384
MAX or MIN
LS
MAX
25
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
629
VOLTAGE-CONTROLLED OSCILLATOR
● This Voltage Oscillators (VCOs) is Improved Versions of The Original VCO Family:
SN74124, 324, 325, 326, 327
● Separate Supply Voltage Pins for Isolation of Frequency Control Inputs and Oscillators from Outputs
Circuitry
● Highly Stable Operation over Specified Temperature and / or Supply Voltage Ranges
Logic Diagram
G
Cx
Z
FC
FC
RC
RC
EN
( ’LS624,
’LS628,
’LS629 only)
Y
T
R
EN
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LS
UNIT
MAX
MAX
MAX
55
-1.2
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fo
UNIT: MHz
MAX or MIN
LS
MAX
25
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
385
Logic Diagram
638
OE
OCTAL BUS TRANSCEIVERS
●
●
●
●
Bidirectional Bus Tranceivers
Inverting Logic
Outputs A-Bus: Open-Collector 3-State
Schmitt-Triggered Inputs (SN74LS638)
DIR
A1
19
1
2
18
To Seven Other Transceivers
FUNCTION TABLE
CONTROL INPUTS
OE
DIR
L
L
L
H
H
X
OPERATION
B data to A bus
A data to B bus
Isoration
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICCZ
MAX or MIN
MAX
LS
ALS
95
AS
UNIT
30
61
mA
ICCL
MAX
90
41
122
mA
IOH (B)
VOH (A)
MAX
MAX
-15
5.5
-15
5.5
-15
5.5
mA
V
IOL
MAX
24
24
64
mA
IOL*
*638-1
MAX
-
48
-
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
386
INPUT
OUTPUT
MAX or MIN
LS
ALS
AS
10
15
12
12
7
6.5
25
25
40
25
30
25
20
7
19
60
40
40
25
25
45
20
22
10
15
9
8
10
7
10
A
B
MAX
B
A
MAX
OE
A
MAX
OE
B
MAX
OE
B
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
Logic Diagram
639
OCTAL BUS TRANSCEIVERS
●
●
●
●
OE
Bidirectional Bus Tranceivers
True Logic
Outputs A-Bus: Open-Collector 3-State
Schmitt-Triggered Inputs (SN74LS638)
DIR
A1
19
1
2
18
B1
To Seven Other Transceivers
FUNCTION TABLE
CONTROL INPUTS
OE
DIR
L
L
L
H
H
X
OPERATION
B data to A bus
A data to B bus
Isoration
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
ALS
AS
UNIT
ICCZ
ICCL
IOH (B)
MAX
MAX
MAX
95
90
-15
54
50
-15
100
154
-15
mA
mA
mA
VOH (A)
IOL
IOL*
*639-1
MAX
MAX
MAX
5.5
24
-
5.5
24
48
5.5
64
-
V
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OE
A
MAX
OE
B
MAX
OE
B
MAX
LS
ALS
AS
15
15
25
25
40
50
40
40
25
25
12
12
30
22
30
35
21
25
10
16
9.5
9
22
9
21.5
11.5
10.5
10.5
7
10.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
387
Logic Diagram
640
OCTAL BUS TRANSCEIVERS
●
●
●
●
●
19
OE
Bidirectional Bus Tranceivers
Inverting Logic
3-State Outputs
Schmitt-Triggered Inputs (SN74LS640, 640-1)
74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
1
DIR
2
A1
18
B1
To Seven Other Transceivers
FUNCTION TABLE
CONTROL INPUTS
OE
DIR
L
L
L
H
H
X
OPERATION
B data to A bus
A datato B bus
Isoration
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
ALS
AS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
ACT
11
UNIT
ICCZ
MAX
95
50
80
0.08
0.16
0.08
0.16
11
0.25
0.08
mA
ICCL
IOH (A port)
IOH (B port)
IOL (A port)
IOL (B port)
MAX
MAX
MAX
MAX
MAX
90
-15
-15
24
24
55
-15
-15
24
24
123
-15
-15
64
64
0.08
-6
-6
6
6
0.16
-6
-6
6
6
0.08
-6
-6
6
6
0.16
-6
-6
6
6
94
-3
-15
24
64
30
-32
-32
64
64
0.08
-24
-24
24
24
mA
mA
mA
mA
mA
IOL*
*640-1
MAX
48
48
-
-
-
-
-
-
-
-
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
388
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OE
A
MAX
OE
A
MAX
OE
B
MAX
OE
B
MAX
LS
ALS
AS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
ACT
11
10
15
10
15
40
40
25
25
40
40
25
25
11
10
11
10
21
24
10
15
21
24
10
15
7
6
7
6
8
10
8
13
8
10
8
13
26
26
26
26
58
58
38
38
58
58
38
38
27
27
27
27
45
45
45
45
45
45
45
45
28
28
28
28
58
58
50
50
58
58
50
50
33
33
33
33
45
45
45
45
45
45
45
45
6.5
3.7
6.5
3.7
10.2
10.7
10.2
7.8
10.2
10.7
10.2
7.8
4.9
4.9
4.9
4.9
5.8
7.3
6.8
5.5
5.8
7.3
6.8
5.5
10.5
9.5
10.5
9.5
13.4
13.6
13.9
14.2
13.4
13.6
13.9
14.2
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
641
OCTAL BUS TRANSCEIVERS
OE
●
●
●
●
DIR
Bidirectional Bus Tranceivers
True Logic
3-State Outputs
Schmitt-Triggered Inputs (SN74LS641)
A1
19
1
18
2
B1
To Seven Other Transceivers
FUNCTION TABLE
CONTROL INPUTS
G
DIR
L
L
L
H
H
X
OPERATION
B data to A bus
A datato B bus
Isoration
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
ALS
AS
UNIT
ICCZ
MAX
95
-
-
mA
ICCL
VOH
IOL
IOL*
*641-1
MAX
MAX
MAX
MAX
90
5.5
24
48
47
5.5
24
48
136
5.5
64
-
mA
V
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
A
OUTPUT
MAX or MIN
B
MAX
B
A
MAX
OE
A,B
MAX
DIR
A,B
MAX
LS
ALS
AS
25
25
25
25
18
25
21
7.5
21
25
40
50
40
50
18
30
30
32
32
7.5
21
9
22
10
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
389
Logic Diagram
642
OE
OCTAL BUS TRANSCEIVERS
●
●
●
●
Bidirectional Bus Tranceivers
Inverting Logic
3-State Outputs
Schmitt-Triggered Inputs (SN74LS642)
DIR
A1
19
1
18
2
To Seven Other Transceivers
FUNCTION TABLE
CONTROL INPUTS
OE
DIR
L
L
H
OPERATION
L
H
X
B data to A bus
A data to B bus
Isoration
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
ALS
AS
ICCZ
PARAMETER
MAX
95
-
-
UNIT
mA
ICCL
VOH
IOL
IOL*
*642-1
MAX
MAX
MAX
MAX
90
5.5
24
48
28
5.5
24
48
104
5.5
64
-
mA
V
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
390
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OE, DIR
A
MAX
OE, DIR
B
MAX
LS
ALS
AS
25
25
25
30
22
30
24
7.5
24
25
40
60
40
60
22
30
38
30
38
7.5
23.5
11.5
23.5
11.5
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
Logic Diagram
645
OCTAL BUS TRANSCEIVERS
OE
●
●
●
●
DIR
Bidirectional Bus Tranceivers
True Logic
3-State Outputs
Schmitt-Triggered Inputs (SN74LS645, 645-1)
19
1
2
A1
18
B1
To Seven Other Transceivers
FUNCTION TABLE
CONTROL INPUTS
OE
L
L
H
OPERATION
DIR
L
H
X
B data to A bus
A data to B bus
Isoration
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
ALS
AS
SN74
HC
SN74
HCT
UNIT
ICCZ
ICCL
IOH
MAX
MAX
MAX
95
90
-15
58
55
-15
123
149
-15
0.08
0.08
-6
0.08
0.08
-6
mA
mA
mA
IOL
IOL*
*645-1
MAX
MAX
24
48
24
48
64
-
6
-
6
-
mA
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OE
A
MAX
OE
A
MAX
OE
B
MAX
OE
B
MAX
LS
ALS
AS
SN74
HC
SN74
HCT
15
15
15
15
40
40
25
25
40
40
25
25
10
10
10
10
20
20
10
15
20
20
10
15
9.5
9
9.5
9
11
10
7
12
11
10
7
12
26
26
26
26
58
58
50
50
58
58
50
50
28
28
28
28
58
58
50
50
58
58
50
50
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
391
646
OCTAL BUS TRANSCEIVERS AND REGISTERS
●
●
●
●
●
●
●
Bidirectional Bus Tranceivers
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
True Data Paths
3-State Outputs
74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
OE
DIR
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
One of Eight Channels
1D
C1
A1
4
20
1D
C1
To Seven Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
IOL*
PARAMETER
ICC
IOH
IOL
IOL*
MAX or MIN
LS
ALS
AS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
ABT
Ver.A
LVTH
3V
UNIT
MAX
MAX
MAX
MAX
165
-15
24
-
88
-15
24
48
211
-15
48
-
0.08
-6
6
-
0.16
-6
6
-
0.08
-6
6
-
0.08
-6
6
-
67
-15
64
-
30
-32
64
-
30
-32
64
-
5
-32
64
-
mA
mA
mA
mA
MAX or MIN
AC
11
CD74
AC
ACT
11
CD74
ACT
LVC
3V
UNIT
MAX
MAX
MAX
MAX
0.08
-24
24
-
0.08
-24
24
-
0.08
-24
24
-
0.08
-24
24
-
0.01
-24
24
-
mA
mA
mA
mA
*646-1
392
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
FUNCTION TABLE
INPUTS
DATA I/O†
OPERATION OR FUNCTION
OE
H
H
DIR
X
X
CLKAB
H to L
↑
CLKBA
H to L
↑
SAB
X
X
SBA
X
X
A1–A8
Input
Input
B1–B8
Input
Input
L
L
L
L
X
X
X
H to L
X
X
L
H
Output
Output
Input
Input
Real-time B data to A bus
Stored B data to A bus
L
L
H
H
X
H to L
X
X
L
H
X
X
Input
Input
Output
Output
Real-time A data to B bus
Stored A data to B bus
Isolation
Store A and B data
† The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled;
i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
MIN
CLKBA,CLKAB "H"
CLKBA,CLKAB "L"
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
DATA
CLKBA,CLKAB "H"
CLKBA,CLKAB "L"
CLKBA,CLKAB
tsu
MIN
MIN
MIN
LS
27
25
27
20
83
5
19
20
19
31
6
6
-
19
-
20
-
19
-
31
-
6
-
15
15
0
25
10
10
0
30
6
6
0
8.5
25
25
5
45
15
15
9
55
25
25
5
45
15
15
5
55
6
6
0.5
11.2
35
18
20
40
35
17
20
12
25
20
9
9
7
11
9
45
34
34
48
48
55
34
34
43
43
45
34
34
48
48
55
46
46
58
58
10.6
9.5
10.5
13.8
9.1
50
25
55
65
35
35
20
17
20
10
11
9
9
14
9
48
48
61
61
61
43
43
44
44
44
48
48
61
61
61
58
58
56
56
44
12
12.9
13.2
14.4
10.9
35
45
60
30
30
16
30
25
10
16
9
16
18
10
10
61
61
61
61
61
44
44
44
44
44
61
61
61
61
61
44
56
56
44
44
10.5
13.1
14.6
12.6
11.8
AC
11
CD74
AC
ACT
11
CD74
ACT
LVC
3V
100
5
5
4.5
4.5
1
11
12.2
8.8
9.8
9.4
10.7
9.9
11
12
13.1
8.9
8.3
12.6
13.7
8.7
8.1
125
4
4
2.5
2.5
2
13.5
13.5
11
11
12
12
12
12
13.5
13.5
13.5
13.5
13.5
13.5
13.5
13.5
105
4.8
4.8
4.5
4.5
2.5
13.5
14.9
11.5
12
11.5
13.5
12.4
13.1
14.4
15.3
11.6
10.6
15.3
16.5
11.3
10.3
110
4.5
4.5
2.5
2.5
2
15.5
15.5
12.5
12.5
14.5
14.5
14.5
14.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
150
3.3
3.3
1.5
1.5
1.7
8.4
8.4
7.4
7.4
8.6
8.6
8.6
8.6
8.2
8.2
7.5
7.5
8.3
8.3
7.9
7.9
A,B
MAX
SAB,SBA
(sored data low)
A,B
MAX
OE
A,B
MAX
OE
A,B
MAX
DIR
A,B
MAX
DIR
A,B
MAX
INPUT
OUTPUT
MAX or MIN
ABT
MIN
125
4
4
3.5
3
0
7.8
8.4
6.9
6.9
7.1
7.9
7.1
7.9
6.3
8.8
8.3
7.5
6.7
9.5
7.7
8.2
MIN
B,A
MAX
A,B
MAX
A,B
MAX
A,B
MAX
A,B
MAX
A,B
MAX
A,B
MAX
SN74
BCT
90
SAB,SBA
(sored data high)
MAX
CD74
HCT
40
MAX
A,B
SN74
HCT
12.5
-
B,A
MIN
CD74
HC
12.5
A,B
th
tPLH
CLOCK
tPHL
tPLH
A,B
tPHL
tPLH
SAB,SBA
(sored data high)
tPHL
tPLH
SAB,SBA
(sored data low)
tPHL
tPZH
OE
tPZL
tPHZ
OE
tPLZ
tPZH
DIR
tPZL
tPHZ
DIR
tPLZ
UNIT fmax : MHz other : ns
SN74
HC
-
MAX
MIN
AS
30
30
A,B
CLKBA,CLKAB "H"
CLKBA,CLKAB "L"
DATA
CLKBA,CLKAB "H"
CLKBA,CLKAB "L"
CLKBA,CLKAB
ALS
15
CLOCK
fmax
tw
MAX or MIN
ABT LVTH
3V
A Ver.
125
4
4
3
3
0
5.6
5.6
4.8
5.4
6.5
5.9
6.5
5.9
6.3
8.8
5
4.5
6.7
9.5
5.7
6
150
3.3
3.3
1.2
1.6
0.8
4.7
4.7
3.5
3.5
4.9
4.9
4.9
4.9
5.2
5.2
5.5
5.5
5.2
5.2
5.6
5.6
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
393
647
OCTAL BUS TRANSCEIVERS AND REGISTERS
●
●
●
●
●
Bidirectional Bus Tranceivers
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
True Data Paths
Open-Collector Outputs
Logic Diagram
G
(21)
(3)
DIR
(23)
CBA
(22)
SBA
(1)
CAB
(2)
SAB
I OF 8 CHANNELS
1D
C1
A1
(4)
(20)
1D
C1
TO 7 OTHER CHANNELS
394
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
FUNCTION TABLE
INPUTS
CAB
CBA
H to L
H to L
↑
↑
G
H
H
DIR
X
X
L
L
L
L
X
X
L
L
H
H
X
H to L
SAB
X
X
SBA
X
X
X
H to L
X
X
X
X
L
H
DATA I/O†
A1–A8
B1–B8
OPERATION OR FUNCTION
Input
Input
Input
Input
Isolation
Store A and B data
L
H
Output
Output
Input
Input
Real-time B data to A bus
Stored B data to A bus
X
X
Input
Input
Output
Output
Real-time A data to B bus
Stored A data to B bus
† The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
UNIT
ICC
MAX
150
mA
VOH
IOL
MAX
MAX
5.5
24
V
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
INPUT
OUTPUT
A,B
A,B
MAX or MIN
LS
MIN
MIN
MIN
30
15
0
35
45
CLOCK
A,B
MAX
A,B
B,A
MAX
SAB,SBA
(With Bus Input High)
A,B
MAX
SAB,SBA
(With Bus Input Low)
A,B
MAX
G
A,B
MAX
DIR
A,B
MAX
26
27
50
45
60
30
40
50
35
40
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
395
648
OCTAL BUS TRANSCEIVERS AND REGISTERS
●
●
●
●
●
Bidirectional Bus Tranceivers
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
Inverting Data Paths
3-State Outputs
Logic Diagram
OE
DIR
21
3
23
CLKBA
SBA 22
CLKAB 1
SAB
2
One of Eight Channels
A1
1D
C1
4
20
1D
C1
To Seven Other Channels
396
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
FUNCTION TABLE
INPUTS
CLKAB
CLKBA
DATA I/O†
A1–A8
B1–B8
OPERATION OR FUNCTION
SAB
SBA
H to L
↑
X
X
X
X
Input
Input
Input
Input
Isolation
Store A and B data
X
X
X
H to L
X
X
L
H
Output
Output
Input
Input
Real-time B data to A bus
Stored B data to A bus
X
H to L
X
X
L
H
X
X
Input
Input
Output
Output
Real-time A data to B bus
Stored A data to B bus
OE
H
H
DIR
X
X
H to L
↑
L
L
L
L
L
L
H
H
† The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled;
i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
ALS
AS
SN74
HC
SN74
HCT
UNIT
ICC
IOH
MAX
MAX
180
-15
88
-15
195
-15
0.08
-6
0.08
-6
mA
mA
IOL
MAX
24
24
48
6
6
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
MAX or MIN
LS
ALS
AS
SN74
HC
SN74
HCT
CLKAB, CLKBA "H"
CLKAB, CLKBA "L"
DATA
MIN
MIN
MIN
MIN
15
30
30
40
12.5
12.5
-
90
5
6
-
27
19
19
-
27
19
19
-
CLKAB, CLKBA
CLKAB, CLKBA
MIN
MIN
15
0
25
40
18
10
0
33
20
17
6
0
8.5
9
8
25
5
45
45
34
25
5
45
45
34
25
55
40
40
40
10
25
21
39
22
7
11
9
11
9
34
48
48
48
48
34
48
48
48
48
50
55
45
35
40
22
22
10
15
27
9
15
9
9
16
61
61
61
61
61
61
61
61
61
61
45
35
30
19
14
15
18
10
10
61
61
61
61
61
61
INPUT
OUTPUT
fmax
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
CLOCK
A,B
MAX
A,B
B,A
MAX
SAB,SBA
(With Bus Input High)
A,B
MAX
SAB,SBA
(With Bus Input Low)
A,B
MAX
OE
A,B
MAX
OE
A,B
MAX
DIR
A,B
MAX
A,B
MAX
tPZL
tPHZ
DIR
tPLZ
UNIT fmax : MHz other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
397
651
OCTAL BUS TRANSCEIVERS AND REGISTERS
●
●
●
●
●
Bus Tranceivers / Registers
Independent Registers and Enables for A and B Buses
Multiplexed Real-Time and Stored Data
Inverting Data Paths
3-State Outputs
Logic Diagram
OEBA
OEAB
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
One of Eight Channels
1D
C1
A1
4
20
1D
C1
To Seven Other Channels
398
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
FUNCTION TABLE
DATA I/O
INPUTS
OEAB OEBA
L
H
L
H
OPERATION OR FUNCTION
CLKAB
H to L
↑
CLKBA
H to L
↑
SAB
X
X
SBA
X
X
A1–A8
Input
Input
B1–B8
Input
Input
Input
Input
Unspecified
Output
Isolation
Store A and B data
Store A, hold B
Store A in both registers
X
H
H
H
↑
↑
H to L
↑
X
X
X
X
L
L
X
L
H to L
↑
↑
↑
X
X
X
X
L
L
L
L
X
X
X
H to L
X
X
L
H
H
H
H
H
X
H to L
X
X
L
H
X
X
Input
Input
Output
Output
Real-time A data to B bus
Stored A data to B bus
H
L
H to L
H to L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
Unspecified
Output
Output
Output
Input
Input
Hold A, store B
Store B in both registers
Input
Input
Real-time B data to A bus
Stored B data to A bus
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
ALS
AS
SN74
HC
SN74
HCT
SN74
BCT
ABT
CD74
ACT
UNIT
ICC
IOH
MAX
MAX
165
-15
82
-15
195
-15
0.08
-6
0.08
-6
62
-15
30
-32
160
-24
mA
mA
IOL
IOL*
*651-1
MAX
MAX
24
-
24
48
48
-
6
-
6
-
64
-
64
-
24
-
mA
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
MAX or MIN
LS
ALS
AS
SN74
HC
SN74
HCT
SN74
BCT
ABT
CD74
ACT
CLKBA, CLKAB "H"
CLKBA, CLKAB "L"
DATA
MIN
MIN
MIN
MIN
15
15
15
40
12.5
12.5
-
90
5
6
-
27
19
19
-
20
25
25
-
85
4.8
7
-
125
4
4
-
110
4.5
4.5
-
A,B
A,B
MIN
MIN
15
0
24
35
18
10
0
32
17
18
6
0
8.5
9
9
25
5
45
45
34
19
5
45
45
34
6
1
11.7
11.8
12.6
3
0
5.6
5.6
6.2
2.5
2
15.5
15.5
12.5
30
47
33
35
30
10
38
21
25
21
7
11
9
11
9
34
48
48
48
48
34
48
48
48
48
9.8
9.8
15.5
14.6
12.8
5.4
6.5
5.9
6.5
5.9
12.5
15.5
15.5
15.5
15.5
44
60
38
30
29
40
38
30
20
18
9
12
22
21
12
14
10
16
9
9
11
16
10
11
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
12
13.1
10.2
9.6
8.3
9.7
15
12.3
5.8
8.5
5
4.1
6.5
7.4
5.5
5.1
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
INPUT
OUTPUT
fmax
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
CLOCK
A,B
MAX
A,B
B,A
MAX
SAB,SBA
(With Bus Input High)
A,B
MAX
SAB,SBA
(With Bus Input Low)
A,B
MAX
A
MAX
A
MAX
B
MAX
B
MAX
tPZH
OEBA
tPZL
tPHZ
OEBA
tPLZ
tPZH
OEAB
tPZL
tPHZ
OEAB
tPLZ
UNIT fmax : MHz other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
399
652
OCTAL BUS TRANSCEIVERS AND REGISTERS
●
●
●
●
●
●
●
Bus Tranceivers / Registers
Independent Registers and Enables for A and B Buses
Multiplexed Real-Time and Stored Data
True Data Paths
3-State Outputs
74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
OEBA
OEAB
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
One of Eight Channels
1D
C1
A1
4
20
1D
C1
To Seven Other Channels
FUNCTION TABLE
DATA I/O
INPUTS
OEAB OEBA
L
H
L
H
CLKBA
H to L
↑
SAB
X
X
SBA
X
X
A1–A8
Input
Input
H to L
↑
X
X
X
X
Input
Input
X
X
X
H
H
H
↑
↑
L
L
X
L
H to L
↑
↑
↑
X
X
L
L
L
L
X
X
X
H to L
X
X
L
H
H
H
H
H
X
H to L
X
X
L
H
X
X
H
400
CLKAB
H to L
↑
L
H to L
H to L
H
H
Unspecified
Output
B1–B8
Input
Input
Unspecified
Output
OPERATION OR FUNCTION
Isolation
Store A and B data
Store A, hold B
Store A in both registers
Input
Input
Hold A, store B
Store B in both registers
Output
Output
Input
Input
Real-time B data to A bus
Stored B data to A bus
Input
Input
Output
Output
Real-time A data to B bus
Stored A data to B bus
Output
Stored A data to B bus and
stored B data to A bus
Output
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
ALS
AS
SN74
HC
CD74
HC
SN74
HCT
CD74
HCT
SN74
BCT
ABT
ABT
Ver.A
ICC
IOH
MAX
MAX
180
-15
88
-15
211
-15
0.08
-6
0.16
-6
0.08
-6
0.16
-6
69
-15
30
-32
30
-32
mA
mA
IOL
MAX
24
24
48
6
6
6
6
64
64
64
mA
MAX or MIN
LVTH
3V
AC
11
CD74
AC
ACT
11
CD74
ACT
LVC
3V
UNIT
SN74
HC
CD74
HC
SN74
HCT
PARAMETER
PARAMETER
ICC
MAX
5
0.08
0.16
0.08
0.16
0.01
mA
IOH
IOL
MAX
MAX
-32
64
-24
24
-24
24
-24
24
-24
24
-24
24
mA
mA
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
CLKBA, CLKAB "H"
CLKBA, CLKAB "L"
tsu
tsu
A,B High
A,B Low
DATA
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
A,B
tPLH
tPHL
tPLH
ALS
AS
CD74
HCT
SN74
BCT
-
40
90
27
20
20
17
77
MIN
15
12.5
5
19
24
25
38
6.5
MIN
MIN
MIN
MIN
15
15
15
15
12.5
10
10
6
6
6
19
25
25
24
18
18
25
19
19
38
18
18
6.5
5
5
MIN
0
25
36
0
30
17
0
8.5
9
5
45
45
11
66
66
5
45
45
5
66
66
1
10.5
9.9
18
20
18
12
9
7
34
34
41
41
34
34
56
56
8.9
9.8
35
32
50
35
20
25
11
9
11
48
48
48
51
51
51
48
48
48
69
69
69
13.1
8.5
11.3
23
45
20
17
9
10
48
61
51
53
48
61
69
68
12.5
10.6
54
18
16
61
53
61
68
12
38
30
10
16
9
9
61
61
53
53
61
61
53
53
10
9.5
30
22
11
61
53
61
68
8.1
38
38
18
10
16
10
61
61
53
53
61
61
68
53
9.3
11.6
30
16
11
61
53
61
53
11.3
A,B
MAX
A,B
B,A
MAX
SAB,SBA
(With Bus Input High)
A,B
MAX
SAB,SBA
(With Bus Input Low)
A,B
MAX
OEBA
A
MAX
OEBA
A
MAX
OEAB
B
MAX
OEAB
B
MAX
INPUT
OUTPUT
MAX or MIN
ABT
ABT
Ver.A
LVTH
3V
AC
11
CD74
AC
ACT
11
CD74
ACT
LVC
3V
MIN
125
125
150
105
125
105
110
100
MIN
MIN
MIN
MIN
MIN
MIN
4
4
3.5
3.5
0
4
4
3
3
0
3.3
3.3
1.2
1.6
0.8
4.8
4.8
4.5
4.5
1
4
4
2.5
2.5
2
4.8
4.8
4
4
2.5
4.5
4.5
2.5
2.5
2
3.3
3.3
1.9
1.9
1.7
7.8
8.4
6.7
5.6
5.6
4.8
4.7
4.7
3.5
10.7
12
8.6
13.5
13.5
11
13.1
14.4
11.1
15.5
15.5
12.5
8
8
7.4
6.7
6.9
7.7
6.9
7.7
5.8
8.5
8.2
6.8
6.5
7.4
6.9
6.2
5.4
6.5
5.9
6.5
5.9
5.8
8.5
5
4.1
6.5
7.4
5.5
5.1
3.5
4.9
4.9
4.9
4.9
5.2
5.2
5.5
5.5
4.7
4.7
5.6
5.6
9.6
9.1
10.7
9.9
10.9
10.9
12.2
7.6
7.1
11.3
12.3
7.6
7.2
11
12
12
12
12
13.5
13.5
13.5
13.5
13.5
13.5
13.5
13.5
11.6
11
13.3
12.2
12.6
12.6
13.8
9.9
9.3
15.2
16.1
10.3
9.3
12.5
14.5
14.5
14.5
14.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
7.4
8.7
8.7
8.7
8.7
7.4
7.4
7.5
7.5
7.1
7.1
7.4
7.4
CLKBA, CLKAB "H"
tsu
tsu
th
LS
MIN
CLOCK
fmax
tw
MAX or MIN
CLKBA, CLKAB "L"
DATA
A,B High
A,B Low
A,B
CLOCK
A,B
tPHL
tPLH
SAB,SBA
(With Bus Input High)
tPHL
tPLH
SAB,SBA
(With Bus Input Low)
tPHL
tPZH
OEBA
tPZL
tPHZ
OEBA
tPLZ
tPZH
OEAB
tPZL
tPHZ
OEAB
tPLZ
UNIT fmax : MHz other : ns
A,B
MAX
B,A
MAX
A,B
MAX
A,B
MAX
A
MAX
A
MAX
B
MAX
B
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
401
653
OCTAL BUS TRANSCEIVERS AND REGISTERS
●
●
●
●
●
Bus Tranceivers / Registers
Independent Registers and Enables for A and B Buses
Multiplexed Real-Time and Stored Data
Inverting Data Paths
Outputs
A Bus: Open-Collector
B Bus: 3-State
Logic Diagram
OEBA
OEAB
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
One of Eight Channels
1D
C1
A1
4
20
1D
C1
To Seven Other Channels
402
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
FUNCTION TABLE
INPUTS
OEAB OEBA CLKAB CLKBA
L
H or L
H
H or L
↑
↑
L
H
DATA I/O†
B1–B8
OPERATION OR FUNCTION
SAB
X
X
SBA
X
X
A1–A8
Inpu
Input
Isolation
Store A and B data
X
X
Input
Input
Unspeciffied‡
Output
Store A, hold B
Store A in both registers
Unspeciffied‡
Output
Input
Input
Hold A, store B
Store B in both registers
Real-time B data to A bus
Stored B data to A bus
X
H
H
H
↑
H or L
↑
↑
X
X‡
L
L
X
L
H or L
↑
↑
↑
X
X
X
X‡
L
L
L
L
X
X
X
H or L
X
X
L
H
Output
Input
H
H
H
H
X
H or L
X
X
L
H
X
X
Input
Output
Real-time A data to B bus
Stored A data to B bus
Output
Stored A data to B bus and
stored B data to A bus
H
L
H or L
H or L
H
H
Output
NOTES:
† The data output functions can be enabled or dissabled by a variety of level combinations at GAB or GBA. Data input functions always are enabled;
i.e., data at the bus teminals is storedd on evry low-to-high transition on the clock inputs.
‡ Select control = L: clocks can occur simultaneously.
Select control = H: clock must be staggered to load both registers.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LS
ALS
UNIT
MAX
MAX
MAX
165
-15
24
88
-15
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
INPUT
OUTPUT
CLK "H"
CLK "L"
DATA
A, B
A, B
MAX or MIN
LS
ALS
MIN
MIN
MIN
MIN
MIN
15
30
30
15
0
14.5
14.5
10
0
38
39
23
36
18
64
22
30
17
18
30
32
24
57
39
51
35
48
33
36
30
35
55
29
38
39
29
15
56
15
62
25
62
25
35
22
25
22
30
24
22
22
14
16
CLKBA
A
MAX
CLKAB
B
MAX
A
B
MAX
B
A
MAX
A
MAX
A
MAX
B
MAX
SBA
(B "H")
SBA
(B "L")
SAB
(A "H")
SAB
(A "L")
B
MAX
OEBA
A
MAX
OEAB
B
MAX
OEAB
B
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
403
654
OCTAL BUS TRANSCEIVERS AND REGISTERS
●
●
●
●
●
Bus Tranceivers / Registers
Independent Registers and Enables for A and B Buses
Multiplexed Real-Time and Stored Data
True Data Paths
Outputs
A Bus: Open-Collector
B Bus: 3-State
Logic Diagram
OEBA
OEAB
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
One of Eight Channels
1D
C1
A1
4
20
1D
C1
To Seven Other Channels
404
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
FUNCTION TABLE
DATA I/O
INPUTS
OEAB OEBA
L
H
L
H
CLKAB
H to L
↑
CLKBA
H to L
↑
SAB
X
X
SBA
X
X
A1–A8
Input
Input
Input
Input
OPERATION OR FUNCTION
B1–B8
Input
Input
Isolation
Store A and B data
Unspecified
Output
Store A, hold B
Store A in both registers
X
H
H
H
↑
↑
H to L
↑
X
X
X
X
L
L
X
L
H to L
↑
↑
↑
X
X
X
X
L
L
L
L
X
X
X
H to L
X
X
L
H
H
H
H
H
X
H to L
X
X
L
H
X
X
Input
Input
Output
Output
Real-time A data to B bus
Stored A data to B bus
H
L
H to L
H to L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
Unspecified
Output
Output
Output
Input
Input
Hold A, store B
Store B in both registers
Input
Input
Real-time B data to A bus
Stored B data to A bus
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LS
ALS
UNIT
MAX
MAX
MAX
180
-15
24
88
-15
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
CLKBA, CLKAB "H"
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
CLKBA, CLKAB "L"
DATA
A,B
A,B
MAX or MIN
LS
ALS
MIN
MIN
MIN
15
30
30
14.5
14.5
-
MIN
MIN
15
0
33
10
0
64
36
21
33
18
30
22
30
17
18
15
27
21
48
32
54
56
21
62
25
62
29
35
27
45
21
35
53
29
33
39
29
25
25
22
35
22
30
24
22
22
14
16
CLKBA
A
MAX
CLKAB
B
MAX
A
B
MAX
B
A
MAX
SBA (B "H")
A
MAX
SBA (B "L")
A
MAX
SAB (A "H")
B
MAX
SAB (A "L")
B
MAX
OEBA
A
MAX
OEAB
B
MAX
OEAB
B
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
405
657
OCTAL BUS TRANSCEIVERS WITH 8-BIT PARITY GENERATORS/CHECKERS
● Combines SN74F245 and SN74F280B Functions in One Package
● 3-State Outputs
● 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
Logic Diagram
T/R
1
24
OE
2
A1
A2
A3
A4
A5
A6
A7
A8
ODD/EVEN
23
3
22
4
21
5
20
6
17
8
16
9
15
10
14
11
B1
B2
B3
B4
B5
B6
B7
B8
13
12
406
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
PARITY
ERR
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
F
SN74
BCT
ABT
ACT
11
UNIT
ICCH
ICCL
MAX
MAX
125
150
2
90
0.25
40
0.08
0.08
mA
mA
ICCZ
IOH A1-A9
MAX
MAX
145
-3
1
-3
0.25
-32
0.08
-24
mA
mA
IOH B1-B9,
PARITY, ERR
MAX
-12
-15
-32
-24
mA
IOL A1-A8
MAX
24
24
64
24
mA
IOL B1-B8,
PARITY, ERR
MAX
64
64
64
24
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
A,B
B,A
A
PARITY
ODD/EVEN
PARITY, ERR
B
ERR
PARITY
ERR
OE
A, B, PARITY
OE
ERR
OE
A, B, PARITY, ERR
MAX or MIN
F
SN74
BCT
ABT
ACT
11
MAX
8
6.6
4.6
9.4
MAX
8
9
4.3
9.4
MAX
MAX
16
16
15.4
15.9
8.1
7.7
14.4
15
MAX
MAX
MAX
MAX
MAX
12
12.5
22.5
22.5
16.5
7.1
9
15.3
15.5
13.2
4.9
4.9
7.9
7.8
7.7
10.7
11.3
23.6
24.6
14.6
MAX
MAX
MAX
MAX
MAX
17
9
11
9
11
13.9
9.1
16.3
9.1
16.3
7.5
6.5
6.5
6.6
9.2
14.7
12.1
13.8
12.1
13.8
MAX
MAX
8
6.5
9.1
8
6.2
7.8
12.1
11.6
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
407
666
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
● 3-State I/O-Type Read-Back Inputs
● True Outputs
● Bus-Structured Pinout
Logic Diagram
OE1
OE2
OERB
PRE
CLR
LE
1D
2
23
1
14
11
13
S
3
1D
C1
R
To Seven Other Channels
408
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
22
1Q
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALS
UNIT
Q
MAX
MAX
73
-2.6
mA
mA
D
Q
MAX
MAX
-0.4
24
mA
mA
D
MAX
8
mA
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
ALS
CLR "L"
MIN
MIN
10
10
PRE "L"
DATA (LE)
MIN
MIN
10
10
DATA (OERB)
DATA (LE)
MIN
MIN
10
5
LE "H"
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
ten
tdis
ten
tdis
UNIT: ns
D
Q
MAX
LE
Q
MAX
CLR
Q
D
MAX
PRE
Q
D
MAX
OERB
D
MAX
OE1 , OE2
Q
MAX
14
18
21
27
29
32
22
28
21
14
21
14
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
409
667
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
● 3-State I/O-Type Read-Back Inputs
● Inverted Outputs
● Bus-Structured Pinout
Logic Diagram
OE1
OE2
OERB
PRE
CLR
LE
1D
2
23
1
14
11
13
S
3
1D
C1
R
To Seven Other Channels
410
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
22
1Q
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALS
UNIT
Q
MAX
MAX
79
-2.6
mA
mA
D
Q
MAX
MAX
-0.4
24
mA
mA
D
MAX
8
mA
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
ALS
CLR "L"
MIN
MIN
10
10
PRE "L"
DATA (LE)
MIN
MIN
10
10
DATA (OERB)
DATA (LE)
MIN
10
LE "H"
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
ten
tdis
ten
tdis
UNIT: ns
MIN
D
Q
MAX
LE
Q
MAX
CLR
Q
D
MAX
PRE
Q
D
MAX
OERB
D
MAX
OE1 , OE2
Q
MAX
5
20
15
28
22
24
26
25
28
21
14
21
14
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
411
669
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
● Fully Synchronous Operation for Counting and Programming
● Internal Look-Ahead for Fast Counting
● Carry Output for n-Bit Cascading
Logic Diagram
CLOCK
U/D
(2)
(1)
1D
(14)
QA
C1
LOAD
(9)
ENABLE (7)
P
ENABLE (10)
T
DATA A
(3)
1D
(13)
QB
C1
DATA B
(4)
(12)
1D
QC
C1
DATA C
(5)
1D
(11)
QD
C1
DATA D
(6)
(15)
412
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
RCO
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
UNIT
ICC
IOH
PARAMETER
MAX
MAX
34
-0.4
mA
mA
IOL
MAX
8
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
tsu
tPHL
tPLH
tPHL
tPLH
tPHL
LS
MIN
MIN
25
20
A,B,C,D
MIN
25
ENP,ENT
LOAD
MIN
MIN
40
30
U/D
MIN
MIN
45
0
th
tPLH
tPHL
tPLH
MAX or MIN
CLOCK
RCO
MAX
CLOCK
Q
MAX
ENT
RCO
MAX
U/D
RCO
MAX
40
60
27
27
17
45
35
40
UNIT fmax : MHz other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
413
670
4-BY-4 REGISTER FILE
●
●
●
●
Separate Read / Write Addressing Permits Simultaneous Reading and Writing
Organized as 4 Words of 4 Bits
Expandable to 512 Words of n-Bits
3-State Outputs
Logic Diagram
D1
WORD 0
D Q
WORD 1
D Q
WORD 2
D Q
(10)
WORD 3
D Q
G
G
G
G
D Q
D Q
D Q
D Q
G
G
G
G
D Q
D Q
D Q
D Q
G
G
G
G
D Q
D Q
D Q
D Q
G
G
G
G
(1)
(9)
Q1
Q2
OUTPUTS
DATA INPUTS
D2
(15)
D3
D4
(2)
(7)
(3)
(6)
(12)
GW
(13)
(14)
WA
WB
WRITE INPUT
414
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(4)
RB
(11)
GR
(5)
RA
READ INPUT
Q3
Q4
FUNCTION TABLE
WRITE INPUTS
WB
L
L
H
H
X
WA
L
H
L
GW
L
L
L
H
X
L
H
WORD
3
2
0
1
Q0
Q0
Q0
Q=D
Q=D
Q0
Q0
Q0
Q=D
Q0
Q0
Q0
Q0
Q0
Q0
Q=D
Q0
Q0
Q0
Q0
READ INPUTS
RB
L
L
H
H
X
RA
L
H
L
GR
L
L
L
H
X
L
H
OUTPUTS
Q1
W0B1
W1B1
W2B1
W3B1
Z
Q4
Q2
Q3
W0B2 W0B3 W0B4
W1B2 W1B3 W1B4
W2B2 W2B3 W2B4
W3B2 W3B3 W3B4
Z
Z
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LS
CD74
HC
CD74
HCT
UNIT
MAX
MAX
MAX
50
-2.6
8
0.16
-6
6
0.16
-6
6
mA
mA
mA
SWITCHING CHARACTERISTICS
MAX or MIN
LS
CD74
HC
CD74
HCT
tw
tsu (D)
tsu (W)
MIN
MIN
MIN
25
10
15
24
18
18
30
18
30
th (D)
th (W)
tlatch
tPLH
tPHL
MIN
MIN
MIN
15
5
25
40
45
5
5
30
59
59
5
5
38
53
53
45
50
45
40
35
75
75
75
75
45
75
75
75
75
57
40
50
35
45
45
45
57
53
53
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
Read
Select
Q
MAX
Write
Enable
Q
MAX
Data
Q
MAX
Read
Enable
Q
MAX
Read
Disable
Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
415
673
16-BIT SHIFT REGISTER
● 16-Bit Serial-In, Serial-Out Shift Register with 16-Bit Parallel-Out Storage Register
● Performs Serial-to-Parallel Conversion
Logic Diagram
SER/Q15
(6)
CS
16
(1)
PE†
P0-P15 Q0-Q15
(7-11, 13-23)
D0-D15
Y0-Y15
16
SH CLK
(2)
SER IN
Q15
CLR
R/W
MODE/STRCLK
STRCLR
(3)
16-BIT SHIFT REGISTER
(5)
(4)
† When PE is active, data synchronously parallel loaded into the
shift registers form the 16 P inputs and no shifting takes place.
416
16 Y0-Y15
CLK
CLK
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
16BIT
STORAGE
REGISTER
FUNCTION TABLE
SHIFT REGISTER FUNCTIONS
INPUTS
H
X
X
X
X
X
X
L
Z
NO
L
L
L
L
L
L
H
H
H
H
→
X
X
X
L
H
X
X
L
X
X
Z
Q15
Q14n
L
Y15n
YES
→ → →
L
L
X
H
→
SER/
Q15
MODE/
STRCLK
X
X
Z
CS R/W
SH CLK
STRCLR
X
SHIFT
STORAGE REGISTER
FUNCTIONS
READ FROM WRITE INTO PARALLEL
SERIAL INPUT SERIAL INPUT LOAD
CLEAR
LOAD
NO
NO
NO
NO
YES
NO
YES
YES
YES
YES
YES
NO
NO
YES
NO
NO
NO
NO
YES
YES
NO
YES;
NO
NO
NO
NO
NO
NO
YES
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
UNIT
MAX
80
mA
SER/Q15
MAX
-2.6
mA
Y0-Y15
SER/Q15
MAX
MAX
-0.4
24
mA
mA
Y0-Y15
MAX
8
mA
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
INPUT
MAX or MIN
LS
CLK
CLR
MIN
MIN
MIN
20
20
20
SER/Q15
Y0-Y15
Mode
MIN
MIN
MIN
20
20
35
R/W,CS
SER/Q15
Y0-Y15
Mode
35
0
0
0
40
PARAMETER
OUTPUT
fmax
tw
tsu
th
tPLH
tPLH
tPHL
tPLH
tPHL
UNIT fmax : MHz other : ns
STRCLR
Y0-Y15
MIN
MIN
MIN
MIN
MAX
MODE/
STRCLK
Y0-Y15
MAX
SH CLK
SER/Q15
MAX
45
45
33
40
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
417
674
16-BIT SHIFT REGISTER
● 16-Bit Parallel-In, Serial-Out Shift Register
● Performs Parallel-to-Serial Conversion
Logic Diagram
P0-P15
MODE
CS
CLK
(7-11, 13-23)
(5)
(1)
(2)
16
PE†
P0-P15
CLK
SER IN
Q15
16-BIT SHIFT REGISTER
R/W
(3)
† When PE is active, data synchronously parallel loaded into the
shift registers form the 16 P inputs and no shifting takes place.
418
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(6)
SER/Q15
FUNCTION TABLE
CS
H
INPUTS
R/W MODE
X
X
CLK
X
SER/
Q15
H
L
Q14n
H
H
→
parallel load
Z
→
Shift and read
→
Do nothing
Shift and write
（serial load）
X
P15
L
L
L
L
OPERATION
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
UNIT
MAX
40
mA
SER/Q15
MAX
-2.6
mA
P0-P15
SER/Q15
MAX
MAX
-0.4
24
mA
mA
P0-P15
MAX
8
mA
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
INPUT
PARAMETER
OUTPUT
fmax
CLK
CLR
tw
th
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
20
20
20
MIN
MIN
P0-P15
Mode
tPLH
tPHL
LS
MIN
MIN
SER/Q15
P0-P15
Mode
R/W,CS
SER/Q15
tsu
MAX or MIN
CLK
SER/Q15
MAX
CS, R/W
SER/Q15
MAX
CS, R/W
SER/Q15
MAX
20
20
35
35
0
0
0
33
40
45
45
40
40
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
419
679
ADDRESS COMPARATOR
● 12-Bit Address Comparator with Enable
Logic Diagram
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
1
2
3
4
5
6
7
8
9
11
A11 12
A12
P0
P1
P2
P3
13
14
15
16
17
G 19
420
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
18
Y
FUNCTION TABLE
INPUTS
A4
A5
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
G
L
L
L
L
L
L
L
L
P3
L
L
L
L
L
L
L
L
P2
L
L
L
L
H
H
H
H
P1
L
L
H
H
L
L
H
H
P0
L
H
L
H
L
H
L
H
A1
H
L
L
L
L
L
L
L
A2
H
H
L
L
L
L
L
L
A3
H
H
H
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
OUTPUT
Y
L
L
L
L
L
L
L
L
A6
H
H
H
H
H
H
L
L
A7
H
H
H
H
H
H
H
L
A8
H
H
H
H
H
H
H
H
A9
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
H
L
L
H
H
H
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
A10 A11 A12
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
All other combinations
H
H
Any combination
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
SN74
HC
UNIT
MAX
MAX
MAX
28
-2.6
24
0.08
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
Any P
Y
MAX
Any A
Y
MAX
G
Y
MAX
ALS
SN74
HC
25
35
22
30
13
375
375
78
78
31
25
31
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
421
682
8-BIT IDENTITY COMPARATOR
● Totem-Pole Outputs
● Hysteresis at P and Q Inputs
● 20kΩ Pullup Resistors on the Q Inputs
Logic Diagram
19
P0
Q0
P1
Q1
P2
Q2
P3
Q3
P4
Q4
P5
Q5
P6
Q6
P7
Q7
422
P=Q
2
3
4
5
6
7
8
9
11
12
1
13
14
15
16
17
18
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
P>Q
FUNCTION TABLE
DATA
INPUT
OUTPUTS
P, Q
P=Q
P>Q
P=Q
L
H
P>Q
H
L
P<Q
H
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
SN74
HC
UNIT
ICC
MAX
70
0.11
mA
IOH
IOL
MAX
MAX
-0.4
24
-4
4
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
P
P=Q
MAX
Q
P=Q
MAX
P
P>Q
MAX
Q
P>Q
MAX
LS
SN74
HC
25
25
25
25
30
69
69
69
69
69
30
30
30
69
69
69
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
423
684
8-BIT IDENTITY COMPARATOR
● Totem-Pole Outputs
● Hysteresis at P and Q Inputs
Logic Diagram
19
P0
Q0
P1
Q1
P2
Q2
P3
Q3
P4
Q4
P5
Q5
P6
Q6
P7
Q7
424
P=Q
2
3
4
5
6
7
8
9
11
12
1
13
14
15
16
17
18
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
P>Q
FUNCTION TABLE
DATA
INPUT
P, Q
P=Q
P>Q
P<Q
OUTPUTS
P=Q
P>Q
L
H
H
L
H
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
SN74
HC
UNIT
ICC
MAX
65
0.08
mA
IOH
MAX
-0.4
-4
mA
IOL
MAX
24
4
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
P
P=Q
MAX
Q
P=Q
MAX
P
P>Q
MAX
Q
P>Q
MAX
LS
SN74
HC
25
25
25
25
30
69
69
69
69
69
30
30
30
69
69
69
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
425
686
8-BIT IDENTITY COMPARATOR
● Totem-Pole Outputs
● Hysteresis at P and Q Inputs
Logic Diagram
P7
Q7
P6
Q6
P5
Q5
P4
Q4
P3
Q3
P2
Q2
P1
Q1
P0
Q0
(17)
(18)
(15)
(16)
(13)
(14)
(11)
(12)
(8)
(19)
(6)
(7)
(4)
(5)
(2)
(3)
(1)
426
P=Q
(9)
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
P>Q
FUNCTION TABLE
DATA
INPUTS
ENABLE
OUTPUTS
P=Q
P>Q
L
H
H
L
L
H
H
H
H
H
P, Q
P=Q
P>Q
G1
L
L
G2
L
L
P<Q
L
X
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
UNIT
ICC
IOH
PARAMETER
MAX
MAX
75
-0.4
mA
mA
IOL
MAX
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
P
P=Q
MAX
Q
P=Q
MAX
G1
P=Q
MAX
P
P>Q
MAX
Q
P>Q
MAX
G2
P>Q
MAX
LS
25
30
25
30
20
30
30
30
30
30
30
25
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
427
688
8-BIT IDENTITY COMPARATOR
● Totem-Pole Outputs
● Hysteresis at P and Q Inputs
Logic Diagram
OE
P0
Q0
P1
Q1
P2
Q2
P3
Q3
P4
Q4
P5
Q5
P6
Q6
P7
Q7
428
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
19
P=Q
FUNCTION TABLE
DATA
P, Q
INPUTS
ENABLE
OUTPUT
P=Q
P=Q
P>Q
G
L
L
P<Q
L
H
X
H
H
L
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LS
ALS
SN74
HC
CD74
HC
CD74
HCT
UNIT
ICC
MAX
65
19
0.08
0.16
0.16
mA
IOH
IOL
MAX
MAX
-0.4
24
-2.6
24
-4
4
-4
4
-4
4
mA
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
INPUT
OUTPUT
MAX or MIN
P
P=Q
MAX
Q
P=Q
MAX
G
P=Q
MAX
LS
ALS
SN74
HC
CD74
HC
CD74
HCT
18
12
53
51
51
23
18
23
18
20
20
12
20
12
22
53
53
53
30
30
51
51
51
36
36
51
51
51
36
36
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
429
697
SYNCHRONOUS UP/DOWN COUNTER WITH OUTPUT REGISTER, MULTIPLEXED
THREE-STATE OUTPUT
● Multiplexed Outputs for Counter or Latched Data
● 3-State Outputs Drive Bus Lines Directly
● Binary Counter, Direct Clear
Logic Diagram
G
R/C
RCK
CCLR
U/D
LOAD
ENP
ENT
CCK
A
(12)
(11)
(9)
(8)
1D
C1
(1)
(18)
C2
QA
(13)
(7)
(14)
1D
C1
(2)
2D
(17)
QB
C2
R
(3)
1D
B
2D
R
(4)
C1
2D
(16)
C2
QC
R
C
(5)
1D
C1
2D
(15)
C2
QD
R
D
(6)
(19)
430
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
RCO
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LS
UNIT
MAX
70
-2.6
mA
mA
-0.4
24
mA
mA
8
mA
ICC
Q
IOH
MAX
RCO
Q
IOL
MAX
RCO
SWITCHING CHARACTERISTICS
PARAMETER
tw
INPUT
OUTPUT
CCK
MAX or MIN
MIN
RCK
MIN
ENT, ENP
tPLH
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
UNIT: ns
25
30
35
U/D
th
tPLH
tPHL
tPLH
tPHL
25
30
A thru D
tsu
LS
MIN
CCK
ENT
RCO
MAX
RCO
MAX
CCK
Q
MAX
RCK
Q
MAX
CCLR
Q
MAX
Q
MAX
R/C
0
40
40
20
20
20
25
20
25
40
25
25
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
431
699
SYNCHRONOUS UP/DOWN COUNTER WITH OUTPUT REGISTER, MULTIPLEXED
THREE-STATE OUTPUT
● Multiplexed Outputs for Counter or Latched Data
● 3-State Outputs Drive Bus Lines Directly
● Binary Counter, Synchronous Clear
Logic Diagram
G
R/C
RCK
CCLR
U/D
LOAD
ENP
ENT
CCK
A
(12)
(11)
(9)
(8)
1D
C1
(1)
C
1D
C1
(2)
2D
(17)
QB
C2
(3)
(4)
C1
2D
(16)
C2
QC
(5)
C1
2D
(15)
C2
QD
(6)
(19)
432
QA
(7)
(14)
1D
D
(18)
C2
(13)
1D
B
2D
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
RCO
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ICC
IOH
IOL
LS
UNIT
Q
MAX
MAX
70
-2.6
mA
mA
RCO
Q
MAX
MAX
-0.4
24
mA
mA
RCO
MAX
8
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw
INPUT
OUTPUT
CCK
MAX or MIN
MIN
RCK
ENT, ENP
MIN
U/D
CCLR
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
25
25
30
A thru D
tsu
LS
MIN
RCO
MAX
RCO
MAX
CCK
Q
MAX
RCK
Q
MAX
Q
MAX
CCK
ENT
R/C
30
35
30
0
40
40
20
20
20
25
20
25
25
25
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
433
756
OCTAL BUFFER/LINE DRIVER/LINE RECEIVER WITH OPEN-COLLECTOR OUTPUTS
● Eliminate the Need for 3-State Overlap Protection
● pnp Inputs Reduce dc Loading
● Open-Collector Versions of SN74AS240A
Logic Diagram
1OE
1A1
1A2
1A3
1A4
1
2OE
18
2
16
4
14
6
12
8
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
AS
SN74
BCT
UNIT
ICC
MAX
80
86
mA
VOH
IOL
MAX
MAX
5.5
64
5.5
64
V
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
AS
SN74
BCT
19
6
19.5
7.5
11.3
4.2
16.5
10.3
UNIT:ns
434
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
19
11
13
15
17
9
7
5
3
2Y1
2Y2
2Y3
2Y4
757
OCTAL BUFFER/LINE DRIVER/LINE RECEIVER WITH OPEN-COLLECTOR OUTPUTS
● Eliminate the Need for 3-State Overlap Protection
● pnp Inputs Reduce dc Loading
● Open-Collector Versions of SN74AS241
Logic Diagram
1OE
1A1
1A2
1A3
1A4
1
2OE
2
18
4
16
14
6
12
8
1Y1
1Y2
1Y3
1Y4
2A1
2A2
2A3
2A4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
VOH
IOL
MAX or MIN
AS
SN74
BCT
SN64
BCT
UNIT
MAX
MAX
MAX
95
5.5
64
77
5.5
64
77
5.5
64
mA
V
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
1OE
1Y
MAX
2OE
2Y
MAX
AS
SN74
BCT
SN64
BCT
18.5
10.1
10.1
6
20
7
21
7.5
6.6
19.7
6.9
18
8.5
6.6
19.7
6.9
18
8.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
435
760
OCTAL BUFFER/LINE DRIVER/LINE RECEIVER WITH OPEN-COLLECTOR OUTPUTS
● Open-Collector Outputs Drive Bus Lines or Buffer Memory Address Registers
● pnp Inputs Reduce dc Loading
● Open-Collector Versions of SN74ALS244 and SN74AS244
Logic Diagram
1
1OE
1A1
1A2
1A3
1A4
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
19
11
9
13
7
15
5
17
3
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
VOH
IOL
MAX or MIN
ALS
AS
SN74
BCT
UNIT
MAX
MAX
MAX
19
5.5
24
94
5.5
64
76
5.5
64
mA
V
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
UNIT:ns
436
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
ALS
AS
SN74
BCT
15
12
16
13
18.5
6
18.5
7
10
7.2
17.5
9.9
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2Y1
2Y2
2Y3
2Y4
804
HEX 2-INPUT NAND DRIVERS
● Y = A•B
● High Capacitive-Drive Capability
Logic Diagram
1A
1B
2A
2B
3A
3B
4A
4B
5A
5B
6A
6B
1
3
2
4
6
5
7
9
8
12
11
13
15
14
16
18
17
19
1Y
2Y
3Y
4Y
5Y
6Y
FUNCTION TABLE
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
SN74
HC
UNIT
MAX
MAX
MAX
12
-15
24
27
-48
48
0.08
-6
6
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
ALS
AS
SN74
HC
A, B
Y
MAX
MAX
7
8
4
4
25
25
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
437
Logic Diagram
805
1A
HEX 2-INPUT NOR DRIVERS
1B
● Y=A+B
● High Capacitive-Drive Capability
2A
2B
3A
3B
FUNCTION TABLE
INPUTS
B
A
H
X
L
4A
OUTPUT
Y
X
H
L
4B
L
L
H
5A
5B
6A
6B
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALS
AS
SN74
HC
UNIT
ICC
IOH
MAX
MAX
14
-15
32
-48
0.08
-6
mA
mA
IOL
MAX
24
48
6
mA
PARAMETER
1
3
2
4
6
5
7
9
8
12
11
13
15
14
16
18
17
19
1Y
2Y
3Y
4Y
5Y
6Y
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
ALS
AS
SN74
HC
A, B
Y
MAX
MAX
7
8
4.3
4.3
24
24
808
Logic Diagram
HEX 2-INPUT AND DRIVERS
1A
1B
● Y=A+B
● High Capacitive-Drive Capability
2A
2B
3A
FUNCTION TABLE
INPUTS
A
B
H
L
X
3B
OUTPUT
Y
H
X
L
4A
4B
H
L
L
5A
5B
6A
6B
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
SN74
HC
AS
UNIT
MAX
MAX
MAX
0.08
-6
6
33
-48
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
438
INPUT
A, B
OUTPUT
MAX or MIN
SN74
HC
AS
Y
MAX
MAX
25
25
6
6
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1
2
4
5
7
8
12
13
15
16
18
19
3
6
9
11
14
17
1Y
2Y
3Y
4Y
5Y
6Y
Logic Diagram
821
10-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUT
OE
CLK
● Outputs Have Undershoot-Protection Circuitry
● Power-Up High-Impedance State
1
13
C1
1D
2
23
1Q
1D
To Nine Other Channels
FUNCTION TABLE
OE
L
L
L
H
INPUTS
CLK
↑
↑
L
X
OUTPUT
Q
H
L
Q0
Z
D
H
L
X
X
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
AS
ABT
LVC
UNIT
MAX
MAX
MAX
113
-24
48
38
-32
64
0.01
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
High
Low
tw
tsu
th
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
MAX or MIN
AS
ABT
LVC
3V
MIN
MIN
MIN
8
8
6
2.9
3.8
2.1
3.3
3.3
1.9
MIN
0
7.5
13
11
12
8
8
1.3
6.2
6.7
5.8
6.3
6.7
6.5
1.5
7.3
7.3
7.6
7.6
6.2
6.2
CLK
Q
MAX
OE
Q
MAX
OE
Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
439
823
9-BIT BUS INTERFACE FLIP-FLOP WITH 3-STATE OUTPUT
● Functionally Equivalent to AMD’s AM29823 and AM29824
● Outputs Have Undershoot-Protection Circuitry
● Power-Up High-Impedance State
Logic Diagram
OE
CLR
CLKEN
CLK
1
11
14
13
R
C1
1D
2
1D
To Eight Other Channels
440
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
23
1Q
FUNCTION TABLE
OE
L
L
L
L
H
CLR
L
H
H
H
X
INPUTS
CLKEN
X
L
L
H
X
CLK
X
↑
↑
X
X
OUTPUT
Q
L
H
L
Q0
Z
D
X
H
L
X
X
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
AS
ABT
LVC
3V
UNIT
ICC
IOH
MAX
MAX
103
-24
38
-32
0.01
-24
mA
mA
IOL
MAX
48
64
24
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
INPUT
OUTPUT
CLR "L"
CLK "H"
CLK "L"
CLR
DATA
MAX or MIN
AS
ABT
LVC
3V
MIN
6.5
8
8
5.5
2.9
3.8
3.3
3.3
3.3
8
6
7.5
-
2.5
2.1
2
3.3
1.3
1
1.3
1.8
1.8
2
0
1
2
1.3
7.5
13
15.5
6.8
6.7
7.1
8
8
7.9
11
6
7.2
12
8
8
6.5
7.5
6.9
7.2
6
6
MIN
CLKEN "H"
CLKEN "L"
DATA
th
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
MIN
CLKEN "H"
CLKEN "L"
CLK
Q
MAX
CLR
Q
MAX
OE
Q
MAX
OE
Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
441
825
8-BIT BUS INTERFACE FLIP-FLOP WITH 3-STATE OUTPUT
● Improved IOH Specifications (Max: -24mA)
● Outputs Have Undershoot-Protection Circuitry
● Power-Up High-Impedance State
Logic Diagram
OE1
OE2
OE3
CLR
CLKEN
CLK
1
2
23
11
14
13
R
C1
1D
3
1D
To Seven Other Channels
442
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
22
1Q
FUNCTION TABLE
OE
L
L
L
L
H
CLR
L
H
H
H
X
INPUTS
CLKEN
X
L
L
H
X
CLK
X
↑
↑
X
X
OUTPUT
Q
L
H
L
Q0
Z
D
X
H
L
X
X
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
AS
UNIT
ICC
IOH
PARAMETER
MAX
MAX
95
-24
mA
mA
IOL
MAX
48
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
th
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
INPUT
OUTPUT
CLR "L"
CLK "H"
CLK "L"
CLR
MAX or MIN
MIN
DATA
CLKEN
AS
4
8
8
8
MIN
6
6
MIN
0
7.5
13
15.5
CLK
Q
MAX
CLR
Q
MAX
OE
Q
MAX
OE
Q
MAX
11
12
8
8
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
443
Logic Diagram
827
10-BIT BUFFERS/BUS DRIVERS
OE1
OE2
● 3-State Outputs Drive Bus Lines or Buffer Memory
Address Registers
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
OE1
L
L
X
H
A
H
L
X
X
13
2
23
Y1
To Nine Other Channels
RECOMMENDED OPERATING CONDITIONS
FUNCTION TABLE
INPUTS
OE2
L
L
H
X
A1
1
OUTPUT
Y
H
L
Z
Z
MAX or MIN
ABT
AC
11
ACT
11
LVC
3V
UNIT
ICC
MAX
40
0.08
0.08
0.01
mA
IOH
IOL
MAX
MAX
-32
64
-24
24
-24
24
-24
24
mA
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
tPLH
tPHL
tPZH
tPZL
tPHZ
OUTPUT
A
MAX
OE
Y
MAX
OE
tPLZ
UNIT: ns
MAX
828
ABT
AC
11
ACT
11
LVC
3V
4.8
4.7
5.9
6.9
6.8
8.7
9.7
9.7
13
9.1
9.2
11.2
11.3
14
12
6.7
6.7
7.3
7.3
6.7
6.9
8.8
11.6
6.7
Logic Diagram
10-BIT BUFFERS/BUS DRIVERS
OE1
OE2
● 3-State Outputs Drive Bus Lines or Buffer Memory
Address Registers
● 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
INPUTS
OE2
L
L
X
H
A
H
L
X
X
A1
1
13
2
23
Y1
To Nine Other Channels
RECOMMENDED OPERATING CONDITIONS
FUNCTION TABLE
OE1
L
L
H
X
MAX or MIN
OUTPUT
Y
L
H
Z
Z
PARAMETER
ICC
IOH
IOL
MAX or MIN
AC
11
ACT
11
LVC
3V
UNIT
MAX
MAX
MAX
0.08
-24
24
0.08
-24
24
0.01
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
444
INPUT
OUTPUT
A
OE
OE
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
MAX or MIN
MAX
Y
MAX
MAX
AC
11
ACT
11
LVC
3V
9.5
10.4
10.7
13.2
9.6
9.2
10.2
11.7
12.1
14.7
12.3
11.7
6.7
6.7
7.3
7.3
6.7
6.7
Logic Diagram
832
HEX 2-INPUT OR DRIVERS
1A
1B
● Y=A+B
● High Capacitive-Drive Capability
2A
2B
3A
3B
FUNCTION TABLE
INPUTS
A
B
H
X
L
4A
OUTPUT
Y
X
H
L
4B
H
H
L
5A
5B
6A
6B
1
2
4
5
7
8
12
3
6
9
11
13
15
16
18
19
14
17
1Y
2Y
3Y
4Y
5Y
6Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
SN74
HC
UNIT
MAX
MAX
MAX
16
-15
24
36
-48
48
0.08
-6
6
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
A, B
Y
MAX or MIN
ALS
AS
SN74
HC
MAX
9
6.3
25
MAX
8
6.3
25
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
445
833
10-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
Logic Diagram
A1–A8
2–9
8x
8
16–23
8
B1–B8
EN
8x
8
EN
OEB
OEA
14
15
1
8
PARITY
8
1 MUX
1
1
9
2k
P
1
G1
1D
CLK
CLR
446
13
11
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C1
R
10 ERR
FUNCTION TABLE
INPUTS
OEB
OEA
L
H
H
L
X
X
H
H
L
L
INPUTS
CLR
CLK
H
H
H
L
↑
↑
↑
X
OUTPUTS AND I/O
Ai
Bi
CLR CLK
Σ OF H’s Σ OF H’s
Odd
NA
X
X
Even
Odd
H
NA
↑
Even
L
X
X
X
No ↑
H
X
L
No ↑
X
X
H
Odd
↑
H
Even
↑
Odd
NA
X
X
Even
INTERNAL
OUTPUT
TO DEVICE PRE-STATE
POINT P
ERRn-1†
H
H
X
L
X
L
X
X
A
B PARITY ERR
NA
A
L
H
B
NA
NA
X
NA
NA
Z
Z
Z
A
H
L
NA
OUTPUT
ERR
H
H
L
H
NA
H
L
H
NC
H
H
L
NA
FUNCTION
A data to B bus and
generate parity
B data to A bus and
check parity
Check error flag register
Isolation
A data to B bus and
generate inverted parity
FUNCTION
Sample
Clear
† The state of ERR before any changes at CLR, CLK, or point P
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
UNIT
MAX
MAX
MAX
38
-32
64
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
ABT
A or B
B or A
MAX
5.3
5.3
A
PARITY
MAX
OE
PARITY
MAX
CLR
CLK
ERR
MAX
OE
A,B, or PARITY
MAX
OE
A,B, or PARITY
MAX
11.2
11
10.5
10
5.2
6.2
6.5
6.5
7.9
8.1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
447
841
10-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
●
●
●
●
3-State Buffer-Type Outputs Drive Bus Lines Directly
Bus-Structured Pinout
Provide Extra Bus-Driving Latches Necessary for Wider Address/Data Paths or Buses with Parity
Power-Up High-Impedance State
Logic Diagram
OE
LE
1
13
2
1D
C1
1D
To Nine Other Channels
448
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
23
1Q
FUNCTION TABLE
OE
L
L
L
H
INPUTS
LE
H
H
L
X
OUTPUT
Q
L
H
Q0
Z
D
H
L
X
X
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALS
AS
ABT
LVC
3V
UNIT
ICC
MAX
62
94
38
0.01
mA
IOH
MAX
-2.6
-24
-32
-24
mA
IOL
MAX
24
48
64
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
tw
tsu
tsu
th
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
OUTPUT
High
Low
MAX or MIN
ALS
AS
ABT
LVC
3V
MIN
20
10
10
5
4
2.5
2.5
2.5
3.3
2.5
1.5
1.5
3.3
2.1
2.1
1
13
13
21
26
12
6.5
10.5
12
12
14
6.2
6.2
6.5
6.7
5.3
6.7
6.7
7.6
7.6
7.2
12
10
12
16
8
8
6.3
7.1
6.5
7.2
5.9
5.9
D
Q
MAX
LE
Q
MAX
OE
Q
MAX
OE
Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
449
843
9-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
●
●
●
●
3-State Buffer-Type Outputs Drive Bus Lines Directly
Bus-Structured Pinout
Provides Extra Bus-Driving Latches Necessary for Wider Address/Data Paths or Buses with Parity
Power-Up High-Impedance State
Logic Diagram
OE
PRE
CLR
LE
1
14
11
13
S2
C1
1D
2
1D
R
To Eight Other Channels
450
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
23
1Q
FUNCTION TABLE
PRE
L
H
L
H
H
H
X
CLR
H
L
L
H
H
H
X
INPUTS
OE
L
L
L
L
L
L
H
LE
X
X
X
H
H
L
X
OUTPUT
D
X
X
X
L
H
X
X
H
L
H
L
H
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALS
AS
ABT
UNIT
ICC
MAX
67
92
34
mA
IOH
MAX
-2.6
-24
-32
mA
IOL
MAX
24
48
64
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
CLR "L"
PRE "L"
LE "H"
LE "L"
MAX or MIN
MIN
LE "L"
LE "H"
PRE inactive
CLR inactive
LE "L"
LE "H"
MIN
MIN
D
Q
MAX
LE
Q
MAX
CLR
Q
MAX
PRE
Q
MAX
OE
Q
MAX
OE
Q
MAX
ALS
AS
ABT
35
35
20
4
4
4
5.5
4.5
-
10
10
-
4
2.5
2.5
15
14
3.4
2.5
3
1.6
2
5
5
2.5
2.5
1
1.5
13
18
21
6.5
9
12
6.7
7.2
7.2
26
23
22
-
12
13
10
-
6.9
7.1
8
7.4
7.2
12
14
10
12
10.5
13.5
8
8
5.7
6.5
6.8
5.9
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
451
853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
Logic Diagram
A1– A8
2–9
8x
8
8
23–16
B1–B8
EN
8x
8
EN
OEB
14
15
1
OEA
8
PARITY
8
1
MUX
1
1
9
2k
P
1
G1
13
LE
CLR
452
11
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
10
ERR
FUNCTION TABLE
INPUTS
OEB
OEA
CLR
LE
OUTPUT AND I/Os
Ai
Σ OF H
Odd
Even
L
H
X
X
H
L
H
L
NA
H
X
L
X
H
H
H
L
H
L
H
H
H
H
H
H
L
L
X
X
X
X
L Odd
H Even
Odd
Even
L
L
INPUTS
CLR
LE
L
L
H
L
X
X
Bi†
Σ OF H
NA
Odd
Even
X
X
X
L
H
H
H
X
NA
A
B
NA
NA
X
X
NA
NA
NA
NA
Z
Z
Z
A
H
L
OUTPUT
ERR
L
H
L
L
H
H
L
H
X
L
H
X
L
H
B PARITY ERR‡
L
H
NA
NA
INTERNAL
OUTPUT
TO DEVICE PRE-STATE
POINT P
ERRn-1†
L
X
H
L
X
H
X
A
NA
H
L
NC
H
NC
H
H
L
NA
FUNCTION
A data to B bus and
generate parity
B data to A bus and
check parity
Store error flag
Clear error flag register
Isolation§
(parity check)
A data to B bus and
generate inverted parity
FUNCTION
Pass
Sample
Clear
Store
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ABT
UNIT
ICC
PARAMETER
MAX
38
mA
IOH
IOL
MAX
MAX
-32
64
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
A
PARITY
MAX
OE
PARITY
MAX
CLR
ERR
MAX
LE
ERR
MAX
B or RARITY
ERR
MAX
OE
A or B
or PARITY
MAX
OE
A or B
or PARITY
MAX
ABT
5.3
5.3
11.2
11
10.5
10
6.2
6
6.6
11.7
12.8
6.7
6.7
7.9
8.1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
453
857
HEX 2-TO-1 UNIVERSAL MULTIPLEXERS
●
●
●
●
●
Select True or Complementary Data
Perform AND/NAND (Masking) of A or B Operand
Cascadable to Expand Number of Operands
Detect Zeros on A or B Operands
3-State Outputs Interface Directly with System Bus
Logic Diagram
S0
S1
COMP
1A
1
23
13
2
4
1B
2A
2B
3A
3B
4A
4B
5A
5B
6A
5
7
6
8
9
16
15
19
18
10
Details of
Four Identical Channels
Not Shown
14
17
3Y
4Y
5Y
6Y
21
11
454
2Y
22
20
6B
1Y
3
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OPER = 0
FUNCTION TABLE
INPUTS
OUTPUTS
COMP
S1
S0
Y
OPER = 0
L
L
L
A
H = all A inputs L
L
L
H
B
H = all B inputs L
L
H
L
A•B
Z
L
H
H
L
L
H
L
L
A
H = all A inputs L
H
L
H
B
H = all B inputs L
H
H
L
A•B
Z
H
H
H
Z
Z
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALS
AS
UNIT
ICCZ
MAX
36
135
mA
ICCL
MAX
33
175
mA
Y
MAX
-2.6
-15
mA
OPER = 0
Y
MAX
MAX
-2.6
24
-2
48
mA
mA
OPER = 0
MAX
24
20
mA
PARAMETER
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
ALS
AS
tpd
A or B
(COMP = "H")
Y
inverting
MAX
14
12
tpd
A or B
(COMP = "L")
Y
non-inverting
MAX
14
10
tpd
tpd
tpd
tpd
S0 or S1
COMP
A or B
S0 to S1
Y
Y
OPER = 0
OPER = 0
MAX
33
18
37
23
13
13
14
18
S0 to S1
Y
MAX
COMP
Y
MAX
S0
OPER = 0
MAX
35
23
24
21
20
12
11
12
9
12
S1
OPER = 0
MAX
COMP
OPER = 0
MAX
27
25
19
25
20
9
12
9
13
9
ten
tdis
ten
tdis
ten
tdis
ten
tdis
ten
tdis
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
455
Logic Diagram
861
10-BIT TRANSCEIVERS
WITH 3-STATE OUTPUTS
OEBA
OEAB
A1
1
13
2
23
FUNCTION TABLE
INPUTS
OEAB OEBA
L
H
H
L
H
H
L
L
To Nine Other Channels
OPERATION
A data to B bus
B data to A bus
Isolation
Latch A and B
(A = B)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
LVC
3V
UNIT
MAX
MAX
MAX
38
-32
64
0.01
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
OEAB or OEBA
B or A
MAX
OEAB or OEBA
B or A
MAX
ABT
LVC
3V
5.2
6.4
4.9
5.9
6.9
7.5
7.1
6.4
7
7
5.9
5.9
UNIT: ns
456
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
Logic Diagram
863
OEBA1
9-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
OEBA2
OEAB1
● 3-State Outputs
OEAB2
A1
1
11
13
14
2
23
B1
FUNCTION TABLE
OEAB1
L
L
L
H
X
H
H
X
X
INPUTS
OEAB2 OEBA1
L
L
H
L
X
L
X
L
L
H
X
H
X
X
X
H
H
H
OPERATION
OEBA2
L
X
H
L
L
X
H
H
X
Latch A and B
A to B
To Eight Other Channels
B to A
Isolation
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
LVC
3V
UNIT
MAX
MAX
MAX
38
-32
64
0.01
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
ABT
LVC
3V
A or B
B or A
MAX
5.7
3.9
6.1
6.1
OE
A or B
MAX
OE
A or B
MAX
5.5
5.4
6.7
6.9
7.2
7.2
6.3
6.3
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
457
867
8-BIT SYNCHRONOUS BIDIRECTIONAL COUNTER
● Fully Programmable with Synchronous Counting and Loading
● Asynchronous Clear
● Ripple-Carry Output for n-Bit Cascading
Logic Diagram
14
CLK
1
S0
S1 2
SN74ALS867A Only
(asynchronous clear)
ENP 23
A 3
1D
C1
R
B 4
1D
C1
R
C 5
1D
C1
R
D 6
1D
C1
R
E 7
1D
C1
R
F 8
1D
C1
R
G 9
1D
C1
R
H 10
1D
C1
R
22 Q
A
21 Q
B
20 Q
C
19 Q
D
18 Q
E
17 Q
F
16 Q
G
15 Q
H
13
ENT 11
458
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
RCO
FUNCTION TABLE
S1
L
L
H
H
S0
L
H
L
H
FUNCTION
Clear
Count down
Load
Count up
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALS
AS
UNIT
ICC
IOH
MAX
MAX
45
-0.4
195
-2
mA
mA
IOL
MAX
8
20
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
fmax
tw
OUTPUT
CLK (clock)
S0 and S1 (clear)
Data input A-H
tsu
ENP or ENT
S0 low and S1 high (load)
S0 and S1 low (clear)
S0 high and S1 low (count down)
S0 and S1 high (count up)
th
S0 high after S1 or S1
high after S0
MAX or MIN
ALS
AS
MIN
35
14
10
10
15
12
-
50
10
10
4
8
10
10
12
12
40
40
MIN
MIN
MIN
Data input A-H
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
CLK
RCO
MAX
CLK
Any Q
MAX
ENT
RCO
MAX
3
-
0
14
14
16
0
22
16
11
16
14
9
-
15
10
17
14
17
ENP
RCO
MAX
tPHL
S0, S1
(clear mode)
Any Q
MAX
26
-
tPLH
tPHL
S0 or S1
(count up/down)
RCO
MAX
16
16
-
tPHL
S0 or S1
(clear mode)
RCO
MAX
16
21
UNIT fmax : MHz other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
459
869
8-BIT SYNCHRONOUS BIDIRECTIONAL COUNTER
● Fully Programmable with Synchronous Counting and Loading
● Synchronous Clear
● Ripple-Carry Output for n-Bit Cascading
Logic Diagram
14
CLK
1
S0
S1 2
SN74ALS867A Only
(asynchronous clear)
ENP 23
A 3
1D
C1
R
B 4
1D
C1
R
C 5
1D
C1
R
D 6
1D
C1
R
E 7
1D
C1
R
F 8
1D
C1
R
G 9
1D
C1
R
H 10
1D
C1
R
22 Q
A
21 Q
B
20 Q
C
19 Q
D
18 Q
E
17 Q
F
16 Q
G
15 Q
H
13
ENT 11
460
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
RCO
FUNCTION TABLE
S1
L
L
H
H
S0
L
H
L
H
FUNCTION
Clear
Count down
Load
Count up
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALS
AS
UNIT
ICC
IOH
MAX
MAX
45
-0.4
195
-2
mA
mA
IOL
MAX
8
20
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
tsu
CLK
Data input A-H
ENP or ENT
S0 low and S1 high (load)
S0 and S1 low (clear)
MAX or MIN
ALS
AS
MIN
35
45
MIN
14
10
15
13
13
11
5
9
11
11
13
13
50
50
MIN
S0 high and S1 low (count down)
S0 and S1 high (count up)
th
S0 high after S1 or S1
high after S0
MIN
Data input A-H
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
CLK
RCO
MAX
CLK
Any Q
MAX
ENT
RCO
MAX
ENP
RCO
MAX
S1
(count up/down)
RCO
MAX
RCO
MAX
tPLH
S0
(clear/load)
tPHL
UNIT fmax : MHz other : ns
3
-
0
0
14
14
16
16
14
35
18
11
15
15
9
15
15
16
12
17
19
18
-
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
461
870
DUAL 16-BY 4-BIT REGISTER FILES
● 3-State Buffer-Type Outputs Drive Bus Lines Directly
● Each Register File Has Individual Write-Enable Controls and Address Lines
Logic Diagram
Decoder
2
1A0
3
1A1
4
1A2
5
1A3
1
S0
S1
S2
S3
1W
2W
Decoder
BIN/Y
1
0 16
2
15
3
16
4
BIN/Y
1
0
2
15 3
4
19
20
21
22
2A0
2A1
2A2
2A3
23
7
17
6
18
REG1
RAM 16×1
0
A 15 A
A,D
DQA1
8
13
REG2
RAM 16×1
0
A 15 A
A,D
16
16
Three Identical Channels Not Shown
462
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
DQB1
FUNCTION TABLE
S0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
FILE SELECT
S1
FILE SEL
L
1R to A, 1R to B
L
2R to A, 1R to B
H
1R to A, 2R to B
H
2R to A, 2R to B
A to 1R, 1R to B
L
A to 2R, 1R to B
L
H
A to 1R, 2R to B
A to 2R, 2R to B
H
1R to A, B to 1R
L
L
2R to A, B to 1R
H
1R to A, B to 2R
H
2R to A, B to 2R
B to 1R
L
A to 2R, B to 1R
L
A to 1R, B to 2R
H
H
B to 2R
INPUT/OUTPUT
S2 S3
I/O SEL
L
L
A out B A out, B out
H
L
A in B A in, B out
L
H
A out B A out, B in
H
H
A in Bin A in, B
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALS
AS
UNIT
ICC
PARAMETER
MAX
110
190
mA
IOL
IOH
MAX
MAX
24
-2.6
48
-15
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
th
ta(A)
ta(S)
tdis
ten
tpd
INPUT
OUTPUT
write
Address before write
Data before write
Select before write
Address before write
Data before write
Select before write
Any A
Any DQ
S0
S1
S2
S3
S2
Any
Any
Any
Any
Any
DQA
DQB
DQA
DQB
DQA
S3
Any DQB
W
DA
DQB
Any DQ
DQB
DQA
MAX or MIN
ALS
AS
MIN
12
5
15
12
0
0
12
19
12
5
15
12
0
0
12
15
15
15
14
14
17
13
13
11
11
12
17
23
12
19
26
26
22
22
MIN
MIN
MAX
MAX
MAX
MAX
MAX
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
463
Logic Diagram
873
DUAL 4-BIT D-TYPE LATCHES
OE
● 3-State Buffer-Type Outputs Drive Bus Lines
Directly
● Bus-Structured Pinout
● Asynchronous Clear
LE
CLR
R
C1
D1
R
C1
D2
FUNCTION TABLE
OE
INPUTS
ENABLE
LE
X
L
H
H
H
H
H
L
X
X
CLR
L
L
L
L
H
D
OUTPUT
L
H
L
Q0
Z
X
H
L
X
X
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
UNIT
MAX
MAX
MAX
31
-2.6
24
129
-15
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw
OUTPUT
CLR low
LE high
tsu
th
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
464
INPUT
MAX or MIN
MIN
D
Q
MAX
LE
Q
MAX
CLR
Q
MAX
OE
Q
MAX
OE
Q
MAX
ALS
AS
15
10
5
5
10
7
14
14
22
21
20
2
4.5
9.5
7.5
13
7.5
9
18
18
10
15
6.5
10.5
7.5
7.5
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Q3
1D
R
C1
D4
Q2
1D
R
C1
D3
Q1
1D
1D
Q4
Logic Diagram
874
DUAL 4-BIT D-TYPE EDGETRIGGERD FLIP-FLOPS
OE
CLK
● 3-State Buffer-Type Outputs Drive Bus Lines
Directly
● Bus-Structured Pinout
● Asynchronous Clear
CLR
R
C1
D1
Q1
1D
R
C1
D2
Q2
1D
R
C1
D3
R
FUNCTION TABLE
OE
L
L
L
L
H
INPUTS
CLR
CLK
L
X
H
↑
H
↑
H
L
X
X
D
X
H
L
X
X
Q3
1D
C1
D4
OUTPUTS
Q4
1D
L
H
L
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
UNIT
MAX
MAX
MAX
32
-2.6
24
160
-15
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
INPUT
OUTPUT
PRE or CLR low
CLK "H"
CLK "L"
Data
PRE or CLR inactive
th
tPLH
CLK
Q
tPHL
Q
tPHL
CLR
tPZH
OE
Q
tPZL
tPHZ
OE
Q
tPLZ
UNIT fmax : MHz other : ns
MAX or MIN
ALS
AS
MIN
30
10
16.5
16.5
15
10
0
14
14
17
125
2
3
4
2
4
1
8.5
10.5
9.5
18
18
10
12
7
10.5
6
7.5
MIN
MIN
MIN
MAX
MAX
MAX
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
465
876
DUAL 4-BIT D-TYPE FLIP-FLOPS
● 3-State Buffer-Type Outputs Drive Bus Lines Directly
● Bus-Structured Pinout
● Asynchronous Clear
Logic Diagram
OE
CLK
PRE
S
C1
D1
Q1
1D
S
C1
D2
Q2
1D
S
C1
D3
Q3
1D
S
C1
D4
466
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1D
Q4
FUNCTION TABLE
(each filip-flop)
OE
L
L
L
L
H
INPUTS
PRE CLK
L
X
H
↑
H
↑
H
L
X
X
OUTPUT
Q
L
L
H
Q0
Z
D
X
H
L
X
X
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALS
AS
ICC
PARAMETER
MAX
31
160
UNIT
mA
IOH
MAX
-2.6
-15
mA
IOL
MAX
24
48
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
tsu
PRE "L"
CLK "H"
CLK "L"
MAX or MIN
ALS
AS
MIN
30
10
16.5
16.5
80
4.5
6.2
6.2
15
10
4.5
5
0
14
14
19
2
8.5
10.5
9.5
MIN
Data
MIN
PRE inactive
th
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT fmax : MHz, other : ns
MIN
CLK
Q
MAX
PRE
Q
MAX
OE
Q
MAX
OE
Q
MAX
18
7
18
10
13
11
7
7
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
467
885
8-BIT MAGNITUDE COMPARATOR
●
●
●
●
SN54AS885 Latchable P-Input Ports with Power-Up Clear
Choice of Logical or Arithmetic (Two's Complement) Comparison
Data and PLE Inputs Utilize pnp Input Transistors to Reduce dc Loading Effects
Cascadable to n Bits While Maintaining High Performance
Logic Diagram
PLE
P7
P6
P5
P4
P3
P2
P1
P0
23
P7 = Q7
C1
P7
22
1D
P6 = Q6
P7
21
P6
20
P6
P5
P5 = Q5
P5
19
P4
18
P4
P3
17
P3
P2
P3 = Q3
P2 = Q2
P1 = Q1
14
P < QOUT
P2
16
P1
15
P1
P0
P0 = Q0
P0
Q7
Q6
4
Q7
5
Q7
Q6
Q6
Q5
Q5 6
Q3
Q4
Q3
8
Q3
Q2
Q2 9
Q1 10
Q0 11
P > QIN 3
P < QIN 2
1
L/A
468
13
P > QOUT
Q5
Q4
Q4 7
4MSB =
Q2
Q1
Q1
Q0
Q0
ARITH
LOGIC
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLE
INPUTS
OUTPUTS
L/A
DATA
P0–P7,
Q0–Q7
P > QIN
P < QIN
P > QOUT
Logical
H
P>Q
X
X
H
Logical
Logical†
H
P<Q
X
X
L
H
H
P=Q
H or L
H or L
H or L
H or L
Arithmetic
L
P AG Q
X
X
H
L
Arithmetic
Arithmetic†
L
Q AG P
X
X
L
H
COMPARISON
P < QOUT
L
L
P=Q
H or L
H or L
H or L
H or L
† In these cases, P > QOUT follows P > QIN and P < QOUT follows P < QIN.
AG = arithmetically greater than
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
AS
UNIT
MAX
MAX
MAX
210
-2
20
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
Data before PLE
Data after PLE
MAX or MIN
MIN
L/A
P < QOUT,
P > QOUT
MAX
P < QIN,
P > QIN
P < QOUT,
P > QOUT
MAX
Any P or Q
data input
P < QOUT,
P > QOUT
MAX
AS
2
4
13
13
8
8
17.5
15
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
469
990
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
● 3-State I/O-Type Read-Back Inputs
● True Logic Outputs
● Bus-Structured Pinout
Logic Diagram
1
OERB
11
LE
2
1D
1D
C1
To Seven Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALS
UNIT
MAX
70
-2.6
-0.4
24
mA
mA
mA
mA
8
mA
ICC
Q
D
Q
IOH
IOL
MAX
MAX
D
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
ten
tdis
UNIT: ns
470
INPUT
OUTPUT
LE high
Data before LE
MAX or MIN
ALS
MIN
10
10
10
5
17
24
26
26
21
19
MIN
Data before OERB
Data after LE
MIN
D
Q
MAX
LE
Q
MAX
OERB
D
MAX
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
19
1Q
992
9-BIT D-TYPE TRANSPARENT
●
●
●
●
3-State I/O-Type Read-Back Inputs
True Logic Outputs
Bus-Structured Pinout
Designed with Nine Bits for Parity Applications
Logic Diagram
OEQ
OERB
CLR
LE
1D
14
1
11
13
2
23
1D
1Q
C1
R
To Eight Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
Q
IOH
ALS
UNIT
MAX
80
-2.6
mA
mA
-0.4
24
8
mA
mA
mA
MAX
D
Q
D
IOL
MAX or MIN
MAX
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
tw
C "H"
CLR "L"
tsu
th
tPLH
tPHL
tPLH
tPHL
tPHL
ten
tdis
ten
tdis
UNIT:ns
OUTPUT
MAX or MIN
MIN
Data befor LE
MIN
Data befor OERB
Data affter LE
MIN
D
Q
MAX
LE
Q
MAX
CLR
Q
D
MAX
OERB
D
MAX
OEQ
Q
MAX
ALS
10
10
10
10
5
14
16
20
25
20
26
21
14
18
14
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
471
994
10-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
● 3-State I/O-Type Read-Back Inputs
● True Logic Outputs
● Bus-Structured Pinout
Logic Diagram
OERB
LE
1D
1
13
2
1D
C1
To Nine Other Channels
472
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
23
1Q
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
PARAMETER
ICC
Q
D
IOH
Q
IOL
ALS
UNIT
MAX
82
mA
MAX
-2.6
-0.4
mA
mA
24
mA
8
mA
MAX
D
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
tw
OUTPUT
C "H"
Data befor LE
tsu
MAX or MIN
ALS
MIN
10
MIN
Data befor OERB
th
tPLH
tPHL
tPLH
tPHL
ten
tdis
UNIT:ns
MIN
Data affter LE
D
Q
MAX
LE
Q
MAX
OERB
D
MAX
10
10
5
14
18
21
27
21
16
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
473
996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
● 3-State I/O-Type Read-Back Inputs
● True Logic Outputs
● T/C Determines True or Complementary Data at Q Outputs
Logic Diagram
OE
T/C
CLR
RD
EN
CLK
1D
15
14
13
10
9
11
1
1D
C1
R
To Seven Other Channels
474
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
23
1Q
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALS
UNIT
MAX
85
mA
24
mA
8
-2.6
mA
mA
-0.4
mA
ICC
Q
IOL
MAX
D
Q
IOH
MAX
D
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
tw
OUTPUT
CLR low
CLK low
MAX or MIN
ALS
MIN
10
14.5
CLK high
14.5
15
tsu
Data before CLK
th
CLR high (inactive) before CLK
Data after CLK
EN low before CLK
*1
CLK high before EN
EN low after CLK
RD high after CLK * 2
tPLH
tPHL
CLK
( T/C = H or L )
tPLH
tPHL
tPLH
tPHL
tPHL
CLR ( T/C = L )
MIN
MIN
Q
MAX
Q
MAX
Q
MAX
CLR ( T/C = H )
T/C
ten* 3
tdis* 4
ten* 3
4
tdis*
ten* 3
tdis* 4
UNIT: ns
CLR
D
MAX
RD
D
MAX
EN
D
MAX
OE
Q
MAX
10
15
10
0
5
5
28
28
27
23
23
23
30
16
19
16
19
15
10
* 1 This setup time ensures that EN will not false clock the date register.
* 2 This hold time ensures that there will be no conflict on the input date bus.
* 3 = t PZH or t PZL
* 4 = t PHZ or t PLZ
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
475
Logic Diagram
1000
QUAD 2-INPUT NAND
BUFFERS/DRIVERS
1
1A
4
2A
● Buffer Version of SN74ALS00A
● Driver Version of SN74AS00
● High Capacitive-Drive Capability
9
3A
OUTPUT
Y
L
H
H
8
10
3B
12
11
13
4B
INPUTS
A
B
H
H
L
X
X
L
6
5
2B
4A
FUNCTION TABLE
3
2
1B
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALS
AS
UNIT
ICC
MAX
7.8
19
mA
IOH
IOL
MAX
MAX
-2.6
24
-48
48
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
tPLH
tPHL
UNIT: ns
OUTPUT
A or B
MAX or MIN
ALS
AS
MAX
8
7
4
4
Y
1004
Logic Diagram
HEX INVERTING DRIVERS
1A
● Driver Version of SN74ALS04B and SN74AS04
● High Capacitive-Drive Capability
2A
3A
FUNCTION TABLE
INPUT
A
H
L
4A
OUTPUT
Y
L
H
5A
6A
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
UNIT
MAX
MAX
MAX
12
-15
24
27
-48
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
476
INPUT
OUTPUT
MAX or MIN
ALS
AS
A or B
Y
MAX
7
6
4
4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1
2
3
4
5
6
9
8
11
10
13
12
1Y
2Y
3Y
4Y
5Y
6Y
1Y
2Y
3Y
4Y
Logic Diagram
1005
HEX INVERTING BUFFER GATES
WITH OPEN-COLLECTOR OUTPUTS
1A
2A
● Buffer Version of SN74ALS05A
3A
4A
FUNCTION TABLE
INPUT
A
H
L
OUTPUT
Y
L
H
5A
6A
1
2
3
4
5
6
9
8
11
10
13
12
1Y
2Y
3Y
4Y
5Y
6Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALS
UNIT
ICC
MAX
12
mA
VOH
IOL
MAX
MAX
5.5
24
V
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
ALS
A
Y
MAX
30
10
tPLH
tPHL
UNIT: ns
1008
Logic Diagram
QUADRUPLE 2-INPUT POSITIVEAND BUFFERS/DRIVERS
1A
● Buffer Version of SN74ALS08
● Driver Version of SN74AS08
2A
1B
2B
3A
FUNCTION TABLE
INPUTS
A
B
H
H
L
X
X
L
3B
OUTPUT
Y
H
L
L
4A
4B
1
3
2
4
6
5
1Y
2Y
9
8
10
12
13
11
3Y
4Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
UNIT
MAX
MAX
MAX
9.3
-2.6
24
22
-48
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
INPUT
A or B
OUTPUT
Y
MAX or MIN
ALS
AS
MAX
9
9
6
6
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
477
Logic Diagram
1032
QUAD 2-INPUT OR BUFFERS/DRIVERS
1A
1B
● Y=A+B
● Driver Version of SN74AS32
● High Capacitive-Drive Capability
2A
2B
3A
3B
4A
4B
1
3
2
4
6
5
9
8
10
12
11
13
1Y
2Y
3Y
4Y
FUNCTION TABLE
(each gate)
INPUTS
A
B
H
X
L
OUTPUT
Y
X
H
L
H
H
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SWITCHING CHARACTERISTICS
MAX or MIN
ALS
AS
UNIT
ICC
MAX
10.6
24
mA
tPLH
PARAMETER
IOH
IOL
MAX
MAX
-2.6
24
-48
48
mA
mA
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
ALS
A or B
Y
MAX
9
6.3
or B
Y
MAX
12
6.3
1034
Logic Diagram
HEX DRIVERS
1A
● SN74AS1034A Offer High Capacitive-Drive
Capability
● Noninverting Drivers
2A
3A
4A
FUNCTION TABLE
INPUT
A
H
L
OUTPUT
Y
H
L
5A
6A
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
UNIT
MAX
MAX
MAX
14
-15
24
35
-48
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
478
AS
INPUT
A
OUTPUT
Y
MAX or MIN
ALS
AS
MAX
8
8
6
6
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1
2
3
4
5
6
9
8
11
10
13
12
1Y
2Y
3Y
4Y
5Y
6Y
Logic Diagram
1035
HEX BUFFERS WITH
OPEN-COLLECTOR OUTPUTS
1A
2A
● Noninverting Buffers with Open-Collector Outputs
3A
FUNCTION TABLE
INPUT
A
H
L
4A
OUTPUT
Y
H
L
5A
6A
1
2
3
4
5
6
9
8
11
10
13
12
1Y
2Y
3Y
4Y
5Y
6Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
VOH
IOL
MAX or MIN
ALS
UNIT
MAX
MAX
MAX
14
5.5
24
mA
V
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
ALS
A
Y
MAX
30
12
1240
Logic Diagram
OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
● Low-Power Versions of SN74ALS240A
● 3-State Outputs Drive Bus Lines or Buffer Memory
Address Registers
● 3-State Outputs Drive Bus Lines or Buffer Memory
Address Registers
1OE
1A1
1A2
1A3
1
2
18
4
16
6
14
8
12
1Y1
1Y2
1Y3
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICCZ
ICCL
IOH
IOL
MAX or MIN
ALS
UNIT
MAX
MAX
MAX
MAX
13
14
-15
16
mA
mA
mA
mA
1A4
2OE
2A1
1Y4
19
11
9
13
7
15
5
17
3
2Y1
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
A
Y
OE
Y
OE
Y
MAX or MIN
ALS
MAX
13
13
20
22
10
13
MAX
MAX
2A2
2A3
2A4
2Y2
2Y3
2Y4
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
479
Logic Diagram
1244
OCTAL BUFFERS/LINE
DRIVERS/LINE RECEIVERS
1
1OE
● 3-State Outputs Drive Bus Lines or Buffer Memory
Address Registers
● pnp Inputs Reduce dc Loading
● Low-Power Versions of SN74ALS244 Series
1A1
1A2
1A3
2
18
4
16
6
14
8
12
1Y1
1Y2
1Y3
RECOMMENDED OPERATING CONDITIONS
1A4
PARAMETER
MAX or MIN
ALS
UNIT
ICCZ
MAX
20
mA
ICCL
IOH
MAX
MAX
17
-15
mA
mA
IOL
MAX
16
mA
1Y4
19
2OE
2A1
11
9
13
7
15
5
17
3
2Y1
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
ALS
14
14
22
22
13
16
MAX
2A2
2A3
2A4
2Y2
2Y3
2Y4
UNIT: ns
1245
Logic Diagram
OCTAL BUS TRANSCEIVERS
OE
● Low-Power Versions of 4ALS245 Series
DIR
A1
19
1
2
18
FUNCTION TABLE
CONTROL INPUTS
DIR
OE
L
L
L
H
H
X
OPERATION
B data to A bus
A data to B bus
Isolation
To Seven Other Transceivers
SWITCHING CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICCZ
ICCL
IOH
IOL
480
MAX or MIN
MAX
MAX
MAX
MAX
ALS
36
33
-15
16
UNIT
mA
mA
mA
mA
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
OE
A or B
MAX
OE
A or B
MAX
ALS
13
13
25
25
12
18
B1
Logic Diagram
1640
OE
OCTAL BUS TRANSCEIVERS
● Lower-Power Versions of SN74ALS640B
● Inverting Logic
● 3-State Outputs
DIR
A1
19
1
2
18
B1
FUNCTION TABLE
CONTROL INPUTS
DIR
OE
L
L
L
H
H
X
OPERATION
B data to A bus
A data to B bus
Isolation
To Seven Other Transceivers
SWITCHING CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALS
UNIT
MAX
MAX
MAX
32
-15
16
mA
mA
mA
ICC
IOH
IOL
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
OE
A or B
MAX
OE
A or B
MAX
ALS
15
10
20
22
10
13
UNIT: ns
1645
Logic Diagram
OCTAL BUS TRANSCEIVERS
OE
● Lower-Power Versions of SN74ALS645A
● 3-State Outputs
DIR
A1
19
1
2
18
B1
FUNCTION TABLE
CONTROL INPUTS
DIR
OE
L
L
L
H
H
X
OPERATION
B data to A bus
A data to B bus
Isolation
To Seven Other Transceivers
SWITCHING CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
UNIT
MAX
MAX
MAX
38
-15
16
mA
mA
mA
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
OE
A or B
MAX
OE
A or B
MAX
ALS
13
13
25
25
12
18
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
481
2240
OCTAL BUFFERS AND LINE DRIVERS / MOS DRIVERS WITH 3-STATE OUTPUTS
● I/O Ports Have 25-Ω Series Resistors, So No External Resistors Are Required (SN74ALS2240, SN74ABT2240A)
● Output Ports Have Equivalent 33-Ω Series Resistors, So No External Resistors Are Required (SN74BCT2240)
Logic Diagram
1OE
1A1
1A2
1A3
1A4
1
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
19
11
9
13
7
15
5
17
3
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICCZ
ICCL
IOH
IOL
MAX or MIN
ALS
BCT
ABT
UNIT
MAX
MAX
MAX
MAX
20
23
-15
15
8
76
-12
12
0.25
30
-32
12
mA
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
482
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
ALS
BCT
ABT
10
10
17
20
10
15
5.7
4.4
9.3
12.4
8.7
10.6
4.8
5.4
5.2
6.8
6.4
6.2
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2Y1
2Y2
2Y3
2Y4
2241
OCTAL BUFFERS AND LINE DRIVERS / MOS DRIVERS WITH 3-STATE OUTPUTS
● Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required (SN74ABT2241A)
● Output Ports Have Equivalent 33-Ω Series Resistors, So No External Resistors Are Required (SN74BCT2241)
Logic Diagram
1OE
1A1
1A2
1A3
1A4
1
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
SN74
BCT
ABT
ICCZ
MAX
9
0.25
mA
ICCL
IOH
IOL
MAX
MAX
MAX
76
-12
12
30
-32
12
mA
mA
mA
PARAMETER
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
1OE
Y
MAX
1OE
Y
MAX
2OE
Y
MAX
2OE
Y
MAX
SN74
BCT
ABT
4.9
6.9
8.9
10.3
8.7
11.3
8.9
10.3
8.7
11.3
4.7
5.6
5.8
8.4
6.6
6.4
5.8
8.4
6.6
6.4
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
483
2244
OCTAL BUFFERS AND LINE DRIVERS / MOS DRIVERS WITH 3-STATE OUTPUTS
● Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required (SN74ABT2244A)
● Output Ports Have Equivalent 33-Ω Series Resistors, So No External Resistors Are Required (SN74BCT2244)
● Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required (SN74LVC2244A)
Logic Diagram
1
1OE
1A1
1A2
1A3
1A4
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
19
11
9
13
7
15
5
17
3
FUNCTION TABLE
INPUTS
A
X
L
H
OE
H
L
L
OUTPUT
Y
Z
L
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALS
SN74
BCT
ABT
LVC
3V
UNIT
ICCZ
ICCL
MAX
MAX
23
22
10
77
0.25
30
0.01
0.01
mA
mA
IOH
IOL
MAX
MAX
-15
15
-12
12
-32
12
-12
12
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
484
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
ALS
SN74
BCT
ABT
LVC
3V
16
17
17
14
9
9
4.9
6.7
8.7
10.4
7.8
9.8
4.7
5.6
5.5
8.3
6.6
5.8
5.5
5.5
7.1
7.1
6.8
6.8
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2Y1
2Y2
2Y3
2Y4
Logic Diagram
2245
OCTAL TRANSCEIVER AND LINE/
MOS DRIVERS WITH 3-STATE OUTPUTS
DIR
1
19
● B Port Has Equivalent 33-Ω Series Resistors, So
No External Resistors Are Required
(SN74BCT2245)
● B-Port Outputs Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are Required
(SN74ABT2245)
● Outputs Have Equivalent 25-Ω Series Resistors, So
No External Resistors Are Required
(SN74ABTR2245)
● All Outputs Have Equivalent 26-Ω Series Resistors,
So No External Resistors Are Required
(SN74LVCR2245)
● B-Port Outputs Have Equivalent 22-Ω Series
Resistors, So No External Resistors Are Required
(SN74LVTH2245)
A1
OE
2
18
B1
To Seven Other Channels
FUNCTION TABLE
INPUTS
DIR
OE
L
L
L
H
H
X
OPERATION
B data to A bus
A data to B bus
Isolation
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
SN74
BCT
ABT
ABTR
LVCR
3V
LVTH
3V
UNIT
ICCZ
ICCL
IOH (A port)
IOH (B port)
IOL (A port)
MAX
MAX
MAX
MAX
MAX
15
100
-3
-12
24
0.25
32
-32
-12
64
0.25
32
-12
-12
12
0.01
0.01
-12
-12
12
0.19
5
-32
-12
64
mA
mA
mA
mA
mA
IOL (B port)
MAX
12
12
12
12
12
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OE
B
MAX
OE
B
MAX
OE
A
MAX
OE
A
MAX
SN74
BCT
ABT
ABTR
LVCR
3V
LVTH
3V
5.8
7.8
7
7.7
9.9
12.2
8.2
9.2
11.1
11.4
9.4
7.6
3.8
4.5
3.6
4
6.1
6.3
5.3
4.8
5.5
5.7
5.6
4.5
3.8
4.5
3.8
4.5
6.1
6.3
5.3
4.8
6.1
6.3
5.3
4.8
6.3
6.3
6.3
6.3
8.2
8.2
7.8
7.8
8.2
8.2
7.8
7.8
4.4
4.4
3.5
3.5
6.2
6.2
5.9
5.4
5.5
5.5
5.9
5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
485
2373
25-Ω OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
● 3-State True Outputs with 25-Ω Sink Resistors
● Full Parallel Access for Loading
● Buffered Control Inputs
Logic Diagram
OE
LE
1
11
C1
1D
3
1D
To Seven Other Channels
486
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2
1Q
FUNCTION TABLE
(each latch)
OE
L
L
L
H
INPUTS
LE
H
H
L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
F
UNIT
MAX
MAX
MAX
66
-3
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
INPUT
OUTPUT
LE high
Data before LE
Data after LE
MAX or MIN
F
MIN
MIN
MIN
6
2
6
9
7
13
8
12
9.5
7.5
6
D
Q
MAX
LE
Q
MAX
OE
Q
MAX
OE
Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
487
2414
MEMORY DECODER WITH ON-CHIP VCC MONITOR
● Built-In Supply-Voltage Monitor for VCC
● Separate Enable Inputs for Easy Cascading
Logic Diagram
VCC
20
VCOMP
Vbat
SD
1A
1
19
2
18
1G
2G
G
17
5
15
2B
1Y2
1Y3
8
9
4
6
13
12
11
488
1Y1
7
14
2A
1Y0
3
16
1B
VS
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2Y0
2Y1
2Y2
2Y3
FUNCTION TABLE
INPUTS
OUTPUTS
SELECT
CONTROL
G 1G SD 1B 1A 1Y0 1Y1 1Y2 1Y3
H
H
H
H
X
X
H
X
X
X
X
X
X
H
H
H
H
H
X
H
X
L
X
X
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
H
L
L
H
L
H
H
H
L
H
L
L
L
H
H
H
H
H
L
L
H
L
H
INPUTS
OUTPUTS
CONTROL
SELECT
G 2G SD 2B 2A 2Y0 2Y1 2Y2 2Y3
H
H
H
H
H
X
X
X
X
H
H
X
X
H
X
X
H
H
H
X
H
X
L
H
H
X
X
L
L
L
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
L
H
H
H
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
Ibat (Output low)
IOL
MAX or MIN
SN74
BCT
UNIT
MAX
MAX
MAX
MAX
3
-0.4
3
8
mA
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A or B
Any Y
MAX
Any G
Any Y
MAX
SD
Any Y
MAX
VCC
Any Y
MAX
VCC
VS
MAX
SN74
BCT
12
12
10
11
12
12
250
250
250
250
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
489
Logic Diagram
2541
OCTAL LINE DRIVERS/MOS DRIVERS
WITH 3-STATE OUTPUTS
1
OE1
19
OE2
● Outputs Have 25-Ω Series Resistor So No External
Resistors Are Required
A1
A2
RECOMMENDED OPERATING CONDITIONS
A3
PARAMETER
MAX or MIN
ALS
UNIT
ICCZ
ICCL
MAX
MAX
22
25
mA
mA
IOH
IOL
MAX
MAX
-0.4
12
mA
mA
A4
A5
A6
SWITCHING CHARACTERISTICS
PARAMETER
A7
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
ALS
A8
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
15
12
15
20
10
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
Y3
Y4
Y5
Y6
Y7
Y8
12
Logic Diagram
OE1
10-BIT BUS/MOS MEMORY DRIVERS
WITH 3-STATE OUTPUTS
OE2
● Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are Required
(SN74ABT2827)
● Output Ports Have Equivalent 25-Ω Resistors; No
External Resistors Are Required (SN74BCT2827C)
PARAMETER
MAX or MIN
SN74
BCT
MAX
MAX
MAX
MAX
6
40
-1
12
A1
1
13
2
23
Y1
To Nine Other Channels
SWITCHING CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
490
Y2
All output resistors are 25 Ω.
2827
ICCZ
ICCL
IOH
IOL
Y1
ABT
UNIT
0.25
40
-12
12
mA
mA
mA
mA
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
SN74
BCT
ABT
6
7.8
10.7
12.9
13
10
5.5
5.1
6.7
7.8
7.2
7.5
Logic Diagram
2828
10-BIT BUS/MOS MEMORY DRIVERS
WITH 3-STATE INVERTING OUTPUTS
OE1
OE2
● Output Ports Have Equivalent 33-Ω Series
Resistors, So No External Resistors Are Required
(SN74BCT2828)
A1
1
13
2
23
Y1
To Nine Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICCZ
ICCL
IOH
IOL
MAX or MIN
SN74
BCT
UNIT
MAX
MAX
MAX
MAX
6
40
-1
12
mA
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
SN74
BCT
6.6
5
9
11.5
10.8
8.7
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
491
2952
OCTAL BUS TRANSCEIVERS AND REGISTERS
● Two 8-Bit Back-to-Back Registers Store Data Flowing in Both Directions
● Noninverting Outputs
● 3-State Outputs
Logic Diagram
CLKENAB
CLKAB
OEAB
CLKENBA
CLKBA
OEBA
11
10
9
13
14
15
C1
A1
16
8
1D
C1
1D
To Seven Other Channels
492
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
FUNCTION TABLE†
INPUTS
OUTPUT
B
A
X
L
H
X
OEAB
L
L
L
H
CLKENAB CLKAB
X
H
L
↑
L
↑
X
X
B0
L
H
Z
† A-to-B data flow is shown; B-to-A data flow is similar but uses
CLKENBA, CLKBA, and OEBA.
‡ Level of B before the indicated steady-state input conditions were
established
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
PARAMETER
ICC
IOH
IOL
MAX
A
MAX
B
A
MAX
B
SN74
BCT
ABT
LVC
3V
55
LVT
3V
UNIT
mA
35
0.01
5
-3
-32
-24
-32
mA
-15
24
-32
64
-24
24
-32
64
mA
mA
64
64
24
64
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
fmax
tw
CLK "H"
tPLH
tPHL
tPZH
SN74
BCT
ABT
LVC
3V
LVT
3V
MIN
125
4
4
150
3.3
3.3
150
3.3
3.3
150
3.3
3.3
2.5
2.5
2
2
1.5
2.5
2.5
3
3
1.5
1.3
1.3
1.1
1.1
1.1
1.5
1.5
1.5
1.9
1
2.5
9
10.5
8.2
12.9
2
5.9
6.3
5.6
6.6
1.1
8.2
8.2
7.8
7.8
1.2
4.6
4.6
4.6
4.6
8.4
7
6.4
6.2
7.8
7.8
5.4
5.1
MIN
CLKENAB or CLKENBA High
CLKENAB or CLKENBA Low
A or B
CLKENAB or CLKENBA
CLKBA
A,B
CLKAB
OEBA
A,B
OEAB
tPZL
tPHZ
OEBA
tPLZ
OEAB
UNIT fmax : MHz other : ns
MAX or MIN
MIN
CLK "L"
A or B High
A or B Low
tsu
th
OUTPUT
A,B
MIN
MAX
MAX
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
493
2953
OCTAL BUS TRANSCEIVERS AND REGISTERS
● Two 8-Bit, Back-to-Back Registers Store Data Flowing in Both Directions
● Inverting Outputs
● 3-State Outputs
Logic Diagram
CLKENAB
CLKAB
OEAB
CLKENBA
CLKBA
OEBA
11
10
9
13
14
15
C1
A1
16
8
1D
C1
1D
To Seven Other Channels
494
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
FUNCTION TABLE†
INPUTS
OEAB
H
L
L
X
CLKAB
↑
↑
↑
X
OEAB
L
L
L
H
OUTPUT
B
A
X
L
H
X
A0
H
L
Z
† A-to-B data flow is shown; B-to-A data flow is similar but uses
CEBA, CLKBA, and OEBA.
‡ Level of B before the indicated steady-state input conditions were
established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
SN74
BCT
UNIT
MAX
55
mA
-3
mA
-15
24
mA
mA
64
mA
ICC
IOH
IOL
A
MAX
B
A
MAX
B
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
tsu
th
CLK "H"
CLK "L"
A or B High
A or B Low
CLKENAB or CLKENBA High
CLKENAB or CLKENBA Low
A or B
CLKENAB or CLKENBA
CLKBA
A,B
CLKAB
tPZH
OEBA
A,B
tPZL
OEAB
tPHZ
OEBA
A,B
tPLZ
OEAB
UNIT fmax : MHz other : ns
tPLH
tPHL
MAX or MIN
SN74
BCT
MIN
110
MIN
MIN
MIN
MAX
MAX
MAX
4.5
4.5
2.5
2.5
2
2
1.5
2
9.5
10.2
8.8
14
9.1
7.6
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
495
Logic Diagram
3245
OCTAL BUS TRANSCEIVER WITH
ADJUSTABLE OUTPUT VOLTAGE
AND 3-STATE OUTPUTS
2
DIR
22
3
A1
21
To Seven Other Channels
FUNCTION TABLE
INPUTS
OE
DIR
L
L
L
H
X
H
OPERATION
B data to A bus
A data to B bus
Isolation
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
VCCA(V)
VCCB(V)
LVCC
UNIT
ICCA
B to A
MAX
3.6
OPEN
3.6
5.5
0.05
0.05
0.05
mA
mA
mA
ICCB
A to B
MAX
3.6
3.6
5.5
0.05
0.08
-12
-24
-12
mA
mA
mA
mA
mA
-24
12
24
12
mA
mA
mA
mA
24
mA
IOHA
MAX
IOHB
MAX
IOLA
MAX
IOLB
MAX
2.7
3.3
2.7
3.3
2.7
3.3
2.7
3.3
3
3.3
3
3
3.3
3
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZL
tPZH
tPZL
tPZH
tPLZ
tPHZ
tPLZ
tPHZ
UNIT: ns
496
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OE
A
MAX
OE
B
MAX
OE
A
MAX
OE
B
MAX
LVCC
VCCA = 2.5V
VCCB = 3.3V
LVCC
VCCA = 3.6V
VCCB = 5V
9.4
9.1
11.2
9.9
14.5
12.9
13
12.8
7.1
6.9
8.8
8.9
6
5.3
5.8
7
9.2
9.5
8.1
8.4
7
7.8
7.3
7
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OE
B1
Logic Diagram
4002
DUAL 4-INPUT POSITIVE-NOR GATES
nA
nB
● Y=A+B+C+D
nY
nC
nD
FUNCTION TABLE
A
L
H
X
X
X
INPUTS
B
C
L
L
X
X
H
X
X
H
X
X
D
L
X
X
X
H
OUTPUT
Y
H
L
L
L
L
NOTES:
H = High Voltage Level
L = Low Voltage Level
X = Irrelevant
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN SN74 CD74 UNIT
HC
HC
MAX
MAX
MAX
0.02
-4
4
0.04
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
A, B, C, D
Y
MAX or MIN SN74 CD74
HC
HC
MAX
28
30
MAX
28
30
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
497
4015
DUAL 4-STAGE STATIC SHIFT REGISTER
Logic Diagram
Q0
Q1
5(13)
Q2
4(12)
Q3
3(11)
2(10)
7(15)
D
DATA
Q
D
CP Q
R
9(1)
CP
Q
D
CP Q
R
Q
Q
D
CP Q
R
CP Q
R
6(14)
MR
RECOMMENDED OPERATING CONDITIONS
FUNCTION TABLE
INPUTS
CP
D
l
↑
h
↑
X
↓
X
X
R
L
L
L
H
Q0
L
H
q’0
L
OUTPUT
Q2
Q1
q’1
q’0
q’1
q’0
q’2
q’1
L
L
Q3
q’2
q’2
q’3
L
NOTES:
H = High Voltage Level
h = High Voltage Level One Set-up Time Prior to the Low to High
Clock Transition
L = Low Voltage Level
l = Low Voltage Level One Set-up Time Prior to the Low to High
Clock Transition
X = Don’t Care.
↑ = Low to High Clock Transition
↓ = High to Low Clock Transition
q’n = Lower case letters indicate the state of the referenced output
one set-up time prior to the Low to High clock transition.
PARAMETER
ICC
IOH
IOL
CD74
HC
UNIT
MAX
MAX
MAX
0.16
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
fmax
tW
UNIT
OUTPUT
Clock
MR
tSUL
tSUH
tH
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
498
MAX or MIN
MIN
45
24
45
18
18
0
54
54
83
83
98
98
MIN
MIN
MIN
Data-In to CP
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CD74
HC
MIN
Data-In to CP
fmax : MHz
MAX or MIN
Clock
Qn
MAX
MR
Qn
(Clock High)
MAX
MR
Qn
(Clock Low)
MAX
other : ns
4016
QUAD BILATERAL SWITCH
Logic Diagram
nY
VCC
nZ
nE
GND
FUNCTION TABLE
INPUT
nE
L
H
SWITCH
OFF
ON
NOTES:
H = High Level Voltage
L = Low Level Voltage
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
MAX or MIN
CD74
HC
UNIT
MAX
0.32
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
INPUT
OUTPUT
MAX or MIN
Switch In
Switch Out
MAX
En
Z
MAX
En
Z
MAX
CD74
HC
18
18
57
57
44
44
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
499
4017
DECADE COUNTERS/DRIVERS
Logic Diagram
CLKEN
CLK
CLR
(13)
(14)
1D
C1
R
(15)
(3)
(2)
(4)
1D
C1
R
(7)
(10)
1D
C1
R
(1)
(5)
1D
C1
R
(6)
(9)
(11)
1D
C1
R
500
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(12)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
CO
FUNCTION TABLE
INPUTS
CLK
L
X
X
↑
↓
X
H
CLKEN
X
H
X
L
X
↑
↓
OUTPUT
STATE†
No Change
No Change
“0” = H, “1”-“9” = L
Increments Counter
No Change
No Change
Increments Counter
CLR
L
L
H
L
L
L
L
NOTES:
H = High Level
L = Low Level
↑ = High to Low Transition
↓ = Low to High Transition
X = Don’t Care
† If n < 5 TC = H, Otherwise = L
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN SN74 CD74 UNIT
HC
HC
MAX
MAX
MAX
0.08
-4
4
0.16
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
MAX or MIN SN74 CD74
HC
HC
MIN
tw
CLK (CP)
CLR (MR) H
MIN
tsu
CLKEN to CLK (CE to CP )
CLK Inactive
MIN
CLKEN to CLK (CE to CP )
MIN
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
CLK
(CP)
Y, C0
(0 to 9, TC)
MAX
CLKEN
(CE)
Y, C0
(0 to 9, TC)
MAX
CLR
(MR)
Y
(0 to 9)
MAX
CLR
(MR)
C0
(TC)
MAX
tPHL
UNIT fmax : MHz, other : ns
25
20
20
20
24
24
13
13
5
58
58
22
0
69
69
63
63
58
58
-
75
75
69
69
69
58
69
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
501
4020
14-STAGE BINARY COUNTERS
● Same Pinouts as CMOS4020
● VCC: 2V to 6V
Logic Diagram
11
CLR
R
10
CLK
R
T
R
T
R
T
R
T
9
7
QA
R
R
T
R
T
6
13
QG
QD
R
T
R
T
12
QH
R
T
14
QI
15
QJ
QK
→
→
X
CLR
L
L
H
OUTPUT
No Change
Advance to Next State
All Outputs Are Low
NOTE: H = High Voltage Level, L = Low Voltage Level,
X = Don’t Care, =↑ Transition from Low to High Level,
↓= Transition from High to Low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
SN74
HC
CD74
HC
CD74
HCT
UNIT
MAX
MAX
MAX
0.08
-4
4
0.16
-4
4
0.16
-4
4
mA
mA
mA
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
CLK
CLR high
CLK
tsu
tPLH
tPHL
tPHL
UNIT fmax : MHz other : ns
502
MAX or MIN
SN74
HC
CD74
HC
CD74
HCT
MIN
22
23
18
15
38
38
35
20
24
24
42
42
51
16
30
30
60
60
60
MIN
CLR inactive before CLK
MIN
CLK
QA
MAX
CLR
Any
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
T
5
4
QE
QF
R
T
FUNCTION TABLE
CLK
R
T
R
T
T
1
2
3
QL
QM
QN
4024
7-STAGE BINARY COUNTERS
Logic Diagram
1
CP Q
CP
CP Q
CP Q
CP Q
CP Q
CP Q
2
3
4
5
6
7
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
R
R
R
R
R
R
R
1 Q1
CP Q
2
MR
7
GND
14
12
VCC
Q1’
11
Q2
9
Q3
6
Q4
5
Q5
4
Q6
3
Q7
FUNCTION TABLE
CLK
↓
↑
X
CLR
L
OUTPUT STATE
No Change
L
Advance to Next State
H
All outputs Are Low
NOTES:
H = High Voltage Level, L = Low Voltage Level, X = Don’t
Care, ↑ = Transition form Low to High Level, ↓ = Transition
High to Low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN SN74 CD74 CD74 UNIT
HC
HC HCT
MAX
MAX
MAX
0.08
-4
4
0.16
-4
4
0.16
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
INPUT
OUTPUT
MAX or MIN SN74 CD74 CD74
HC
HC HCT
MIN
CLK (CP)
CLR (MR) H
CLR iow before CLK
tsu
tPLH
CLK
(CP)
tPHL
tPLH
CLR (MR)
tPHL
UNIT fmax : MHz, other : ns
MIN
MIN
QA
(Q1)
MAX
any Q
MAX
22
23
20
20
30
30
33
20
24
24
42
42
51
51
16
30
30
60
60
60
60
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
503
4040
12-STAGE BINARY COUNTERS
● Same Pinouts as CMOS4040
● VCC: 2V to 6V
Logic Diagram
CLR
11
R
CLK
10
R
T
R
R
T
7
QA
QB
R
T
2
4
QF
QG
R
T
12
↑
↓
X
CLR
L
Advance to Next State
H
All Outputs Are Low
QK
NOTE: H = High Voltage Level, L = Low Voltage Level,
X = Don’t Care, ↑ = Transition from Low to High Level,
↓ = Transition from High to Low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
SN74
HC
CD74
HC
CD74
HCT
LV
3V
LV
5V
UNIT
MAX
MAX
MAX
0.08
-4
4
0.16
-4
4
0.16
-4
4
-6
6
0.02
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw
CLK
CLR high
CLK
tsu
CLR inactive before CLK
tPLH
CLK
QA
tPHL
tPHL
CLR
Any
UNIT fmax : MHz other : ns
504
MAX or MIN
SN74
HC
CD74
HC
CD74
HCT
LV
3V
LV
5V
MIN
22
23
18
15
38
38
35
20
24
24
42
42
51
16
30
30
60
60
60
50
5
5
5
17.5
17.5
18.5
80
5
5
5
10.5
10.5
12
MIN
MIN
MAX
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
T
15
QJ
OUTPUT
No Change
L
QE
R
T
14
QI
3
QD
FUNCTION TABLE
CLK
T
6
QC
R
QH
R
T
5
T
13
R
T
9
R
T
R
T
1
QL
4046
PHASE-LOCKED-LOOP WITH VCO
Logic Diagram
C1
6
7 4
3
14
SIGIN
COMPIN
+
VREF
C1B
VCOOUT
C1A
12 R2
SD
-
R2
PC1OUT
2
PC3OUT
15
Q
VCO
Q
RD
11 R1
-
+
VCC
R1
10
DEMOUT
R5
-
VCC
D
Q
UP
p
CP Q
RD
+
13
PC2OUT
R3
C2
n
VCC
D
Q
GND
DOWN
CP
Q
RD
INH
VCOIN
5
9
Pin Descriptions
PIN NUMBER
SYMBOL
1
PCPOUT
Phase Comparator Pulse Output
2
PC1OUT
Phase Comparator 1 Output
3
COMPIN
Comparator Input
4
VCOOUT
VCO Output
5
INH
Inhibit Input
6
C1A
Capacitor C1 Connection A
C1B
Capacitor C1 Connection B
8
GND
Ground (0V)
9
VCOIN
10
DEMOUT
11
R1
Resistor R1 Connection
12
R2
Resistor R2 Connection
13
PC2OUT
SIGIN
15
PC3OUT
16
VCC
PCPOUT
RECOMMENDED OPERATING CONDITIONS
NAME AND FUNCTION
7
14
1
VCO Input
PARAMETER
MAX or MIN
CD74 CD74
UNIT
HC HCT
ICC
IOH
MAX
MAX
0.16
-4
0.16
-4
mA
mA
IOL
MAX
4
4
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
CD74 CD74
HC HCT
Demodulator Output
Phase Comparator 2 Output
Signal Input
Phase Comparator 3 Output
Positive Supply Voltage
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tTLH
tTHL
tPZH
tPZL
tPLZ
tPHZ
UNIT:ns
SIGIN
COMPIN
SIGIN
COMPIN
SIGIN
COMPIN
PCIOUT
MAX
PCPOUT
MAX
PC3 OUT
MAX
A
Y
MAX
PC2 OUT
MAX
PC2 OUT
MAX
SIGIN
COMPIN
SIGIN
COMPIN
60
60
90
90
74
74
22
22
80
80
95
95
68
68
102
102
87
87
22
22
90
90
102
102
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
505
Logic Diagram
4049
HEX INVERTING BUFFERS
A
Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
CD74
UNIT
HC
ICC
IOH
MAX
MAX
0.04
-4
mA
mA
IOL
MAX
4
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
nA
nY
MAX or MIN CD74
HC
MAX
26
26
4050
Logic Diagram
HEX NON-INVERTING BUFFERS
A
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
MAX
MAX
MAX
CD74
UNIT
HC
0.04
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
506
INPUT
OUTPUT
nA
nY
MAX or MIN CD74
HC
MAX
26
26
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Y
4051
8-CHANNEL ANALOG MULTIPLEXERS / DEMULTIPLEXERS
Logic Diagram
3
13
A
14
11
15
B
12
10
1
C
5
9
2
INH
4
6
COM
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
FUNCTION TABLE
INH
L
L
L
L
L
L
L
L
H
INPUTS
C
B
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
X
X
A
L
H
L
H
L
H
L
H
X
ON
CHANNEL
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
None
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
MAX or MIN
MAX
CD74
HC
0.16
CD74
HCT
LV
3V
LV
5V
UNIT
0.16
-
0.02
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
COM or Yn
Yn or COM
MAX
INH
COM or Yn
MAX
INH
COM or Yn
MAX
CD74
HC
CD74
HCT
LV
3V
LV
5V
18
18
68
68
68
68
18
18
83
83
68
68
12
12
25
25
25
25
8
8
18
18
18
18
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
507
4052
DUAL 4-CHANNEL ANALOG MULTIPLEXERS / DEMULTIPLEXERS
Logic Diagram
13
12
A
14
9
11
1
5
2
INH
6
4
3
FUNCTION TABLE
INH
L
L
L
L
H
INPUTS
B
A
L
L
L
H
H
L
H
H
X
X
ON
CHANNEL
1Y0, 2Y0
1Y1, 2Y1
1Y2, 2Y2
1Y3, 2Y3
None
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
MAX or MIN
CD74
HC
CD74
HCT
LV
3V
LV
5V
UNIT
MAX
0.16
0.16
-
0.02
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
508
1Y0
10
15
B
1-COM
INPUT
OUTPUT
MAX or MIN
CD74
HC
CD74
HCT
LV
3V
LV
5V
COM or Yn
Yn or COM
MAX
18
18
18
18
INH
COM or Yn
MAX
INH
COM or Yn
MAX
98
98
75
75
105
105
75
75
12
12
25
25
25
25
8
8
18
18
18
18
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
2-COM
4053
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
Logic Diagram
15
14
A
12
2
1Y1
2Y0
2Y1
9
5
3
INH
1Y0
10
1
C
1-COM
11
13
B
2-COM
6
4
3Y0
3Y1
3-COM
FUNCTION TABLE
INH
L
L
L
L
L
L
L
L
H
INPUTS
C
B
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
X
X
A
L
H
L
H
L
H
L
H
X
ON CHANNEL
1Y0, 2Y0, 3Y0
1Y1, 2Y0, 3Y0
1Y0, 2Y1, 3Y0
1Y1, 2Y1, 3Y0
1Y0, 2Y0, 3Y1
1Y1, 2Y0, 3Y1
1Y0, 2Y1, 3Y1
1Y1, 2Y1, 3Y1
None
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
MAX or MIN
CD74
HC
CD74
HCT
LV
3V
LV
5V
UNIT
MAX
0.16
0.16
-
0.02
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
CD74
HC
CD74
HCT
LV
3V
LV
5V
COM or Yn
Yn or COM
MAX
18
18
18
18
INH
COM or Yn
MAX
INH
COM or Yn
MAX
66
66
63
63
72
72
66
66
12
12
25
25
25
25
8
8
18
18
18
18
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
509
4059
CMOS PROGRAMMABLE DIVIDE-BY-N COUNTER
Function Diagram
PROGRAM JAM INPUTS (BCD)
J1
3
12
J2
J3
4
J4
5
J5
6
J6
22
J7
21
GND
J8
20
J9 J10 J11 J12
19
18
17
16
15
J13 J14 J15 J16
10
9
8
7
PRESETTABLE LOGIC
24
VCC
CLOCK
INPUT
FIRST
COUNTING
SECTION
+10, 8, 5, 4, 2
1
LAST
COUNTING
SECTION
+1, 2, 2, 4, 8
INTERMEDIATE COUNTING SECTION
+10
+10
+10
RECOGNITION
GATING
14
Ka
MODE
SELECT
INPUTS
13
Kb
11
MODE
CONTROL
PRESET
ENABLE
Kc
23
4059
Function
2
OUTPUT
STAGE
LATCH
ENABLE
FUNCTION TABLE
MODE
SELECT
INPUT
Ka
H
L
H
L
H
X
Kb
H
H
L
L
H
L
Kc
H
H
H
H
L
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
CD74
UNIT
HC
ICC
MAX
0.16
mA
IOH
IOL
MAX
MAX
-4
4
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
tsu
tPLH
tPHL
tPLH
tPHL
UNIT
510
INPUT
OUTPUT
CP
CP
Kb, Kc to CP
fmax : MHz
MAX or MIN CD74
HC
MIN
MIN
MIN
CP
Q
MAX
LE
Q
MAX
other : ns
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
18
27
22
60
60
53
53
DIVIDE-BY-N
OUTPUT
4060
ASYNCHRONOUS 14-STAGE BINARY COUNTERS AND OSCILLATORS
● Same Pinouts as CMOS4060
● Allow Design of Either RC or Crystal Oscillator Circuits
● VCC: 2V to 6V
Logic Diagram
R
R
T
CLR
R
T
R
T
4
6
QF
QG
R
T
14
R
T
13
QH
R
T
15
QI
QJ
R
T
T
1
2
3
QL
QM
QN
12
R
R
T
CLKI
R
T
9
11
10
R
T
R
T
R
T
T
CLKO
CLKO
7
5
QD
QE
FUNCTION TABLE
INPUTS
CLKI
CLR
L
↑
L
↓
X
H
OUTPUTS
CLKO
QD to QN
No Change
Advance to Next State
All Outputs are Low
↑
↓
L
CLKO
↓
↑
H
OPERATING CONDITIONS
MAX or MIN
SN74
HC
CD74
HC
CD74
HCT
UNIT
MAX
MAX
MAX
0.08
-4
4
0.16
-4
4
0.16
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw
INPUT
OUTPUT
CLKI
CLR high
tsu
CLR inactive before CLK
tPLH
CLKI
QD
tPHL
tPHL
CLR
Any
UNIT fmax : MHz other : ns
MAX or MIN
SN74
HC
CD74
HC
CD74
HCT
MIN
22
23
23
40
123
123
35
20
24
24
90
90
53
20
24
38
100
100
66
MIN
MIN
MAX
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
511
4066
QUADRUPLE BILATERAL SWITCHES
●
●
●
●
●
●
Same Pinouts as CMOS4016, 4066
Low On-State Impedance: 50-Ω TYP at VCC = 6V
Individual Switch Controls
Extremely Low Input Current
High On-Off Output Voltage Ratio
Low Crosstalk Between Switches
Logic Diagram
A
VCC
VCC
B
C
One of Four Switches
FUNCTION TABLE
INPUT
(C)
L
H
SWITCH
OFF
ON
NOTE:
H = High Level
L = Low Level
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
MAX or MIN
SN74
HC
CD74
HC
CD74
HCT
LV
3V
LV
5V
UNIT
MAX
0.02
0.04
0.04
-
0.02
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
512
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
C
A or B
MAX
C
A or B
MAX
SN74
HC
CD74
HC
CD74
HCT
LV
3V
LV
5V
15
15
45
45
50
50
18
18
30
30
45
45
18
18
36
36
53
53
12
12
22
22
22
22
8
8
16
16
16
16
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4067
16-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER
Function Diagram
I0
S0
S1
S2
S3
9
10
11
P
14
N
13
BINARY
1 OF 16
DECODER
SN = 5 STAGES
E = 4 STAGES
14 - OUTPUT CIRCUITS
SAME AS ABO VE
(WITH ANALOG INPUTS)
I1 TO I14
1
P
N
16
15
I15
E
FUNCTION TABLE
S0
X
S1
X
S2
X
S3
X
E
X
0
RECOMMENDED OPERATING CONDITIONS
SELECTED
CHANNEL
PARAMETER
None
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
2
1
1
0
0
0
3
0
0
1
0
0
4
1
0
1
0
0
5
0
1
1
0
0
6
1
1
1
0
0
7
0
0
0
1
0
8
1
0
0
1
0
9
0
1
0
1
0
10
1
1
0
1
0
11
0
0
1
1
0
12
1
0
1
1
0
13
0
1
1
1
0
14
1
1
1
1
0
15
NOTES:
H = High Level
L = Low Level
COMMON
INPUT/
OUTPUT
ICC
MAX or MIN CD74 CD74 UNIT
HC HCT
MAX
0.16
0.16
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
UNIT:ns
MAX or MIN CD74 CD74
HC HCT
INPUT
OUTPUT
Switch In
COMON I/O
MAX
E
COMON I/O
MAX
Sn
COMON I/O
MAX
E
COMON I/O
MAX
Sn
COMON I/O
MAX
22
22
83
83
90
90
83
83
87
87
22
22
90
90
90
90
83
83
87
87
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
513
Logic Diagram
4075
TRIPLE 3-INPUT OR GATES
nA
● Y=A+B+C
nB
nC
514
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
nY
FUNCTION TABLE
INPUTS
C
A
B
L
L
L
H
X
X
H
X
X
X
X
H
NOTES:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
OUTPUT
Y
L
H
H
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN SN74 CD74 CD74 UNIT
HC
HC HCT
ICC
MAX
0.02
0.04
0.04
mA
IOH
MAX
-4
-4
-4
mA
IOL
MAX
4
4
4
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
A, B or C
A, B or C
Y
Y
MAX or MIN SN74 CD74 CD74
HC
HC HCT
MAX
MAX
25
25
30
30
36
36
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
515
4094
8-STAGE SHIFT AND STORE BUS REGISTER, THREE-STATE
Logic Diagram
D
Q
2
DATA
FFO
CP
FF1
FF2
FF3
FF4
FF5
FF6
FF7
CP
9
3
QS1
CP
CP
CP
D
L8
Q
1
STR
10
STR STR
LO
L1
L2
L3
L4
L5
L6
QS2
L7
Q
15
OE
OE OE
4
Q0
516
5
Q1
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
6
Q2
7
Q3
14
Q4
13
Q5
12
Q6
11
Q7
FUNCTION TABLE
PALALLEL
OUTPUT
INPUTS
CP
↑
↓
↑
↑
↑
↓
OE
L
L
H
H
H
H
STR
X
X
L
H
H
H
D
X
X
X
L
H
H
Q0
Z
Z
NC
L
H
NC
Qn
Z
Z
NC
Qn-1
Qn-1
NC
SERIAL
OUTPUT
QS1‡
Q’6
NC
Q’6
Q’6
Q’6
NC
QS2
NC
Q’7
NC
NC
NC
Q’7
NOTES:
†. H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
NC = No charge, Z = High Impedance Off-state,
↑ = Transition from Low to High Level, ↓ = Transition from High Low.
‡. At the positive clock edge the information in the seventh resister stage is
transferred to the 8th register stage and QS1 output.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN CD74 CD74 UNIT
HC HCT
ICC
IOL
MAX
MAX
0.16
4
0.16
4
mA
mA
IOH
MAX
-4
-4
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
tW
tWH
CP
STR
tSU
Data
STR
Data
STR
tH
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPLZ
tPHZ
UNIT:ns
MAX or MIN
MIN
MIN
MIN
MIN
CP
QS1
MAX
CP
QS2
MAX
CP
Qn
MAX
STR
Qn
MAX
OE
Qn
MAX
OE
Qn
MAX
CD74 CD74
HC HCT
24
24
24
24
15
30
3
0
45
15
30
4
0
-
45
41
41
59
59
-
54
54
53
53
38
-
38
-
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
517
4245
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS
Logic Diagram
DIR
2
22
A1
21
To Seven Other Channels
FUNCTION TABLE
INPUTS
OE
DIR
L
L
L
H
X
H
OPERATION
B data to A bus
A data to B bus
Isolation
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LVC
LVCC
UNIT
ICCA
ICCB
MAX
MAX
0.08
0.05
0.08
0.08
mA
mA
IOH
IOL
MAX
MAX
-24
24
-24
24
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZL
tPZH
tPZL
tPZH
tPLZ
tPHZ
tPLZ
tPHZ
UNIT: ns
518
OE
3
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OE
A
MAX
OE
B
MAX
OE
A
MAX
OE
B
MAX
LVC
LVCC
VCCB
3.3V
6.3
6.7
6.1
5
9
8.1
8.8
9.8
7
5.8
7.7
7.8
7
7
6.2
5.3
9
8
10
10.2
5.2
5.2
5.4
7.4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
4316
QUAD ANALOG SWITCH WITH LEVEL TRANSLATION
Logic Diagram
nY
TO 3 OTHER
SWITCHES
VCC
VCC
LOGIC
LEVEL
CONV.
E
nZ
VEE
VEE
nS
FUNCTION TABLE
INPUTS
E
S
L
L
H
L
H
X
SWITCH
OFF
ON
OFF
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
MAX or MIN
MAX
CD74 CD74
UNIT
HC HCT
0.16
0.16
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPLZ
tPHZ
tPLZ
tPHZ
UNIT:ns
MAX or MIN CD74 CD74
HC HCT
INPUT
OUTPUT
Switch in
Switch out
MAX
E
Z
MAX
nS
Z
MAX
E
Z
MAX
nS
Z
MAX
18
18
62
62
53
53
62
62
53
53
18
18
66
85
60
75
75
66
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
519
4351
ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH
Logic Diagram
A0
A1
A2
A3
A4
A5
A6
A7
S0
S1
S2
LE
E1
E2
13
12
L
H
A1
L
H
L
A2
H
L
H
H
A3
H
H
L
L
A4
H
H
L
H
A5
L
H
H
H
L
A6
L
H
H
H
H
H
L
X
X
X
A7
None
H
L
H
L
L
L
A COMMON
6
2
5
CHANNEL
ADDRESS
LATCH
NOTES:
† When LE is low S0-S2 data are latched and switches cannot change state.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
520
4
RECOMMENDED OPERATING CONDITIONS
L
L
MULTIPLEXER/
DEMULTIPLEXER
1
8
S0
L
S2
L
16
7
S1
L
E2
H
19
11
“ON”†
SWITCCHES
LE = H
A0
E1
L
18
15
FUNCTION TABLE
INPUTS
17
PARAMETER
MAX or MIN
ICC
MAX
CD74 CD74
UNIT
HC HCT
0.16
0.16
mA
SWITCHING CHARACTERISTICS
PARAMETER
tW
tsu
tH
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPLZ
tPHZ
tPLZ
tPHZ
tPLZ
tPHZ
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
MAX or MIN
MIN
MIN
MIN
LE
Sn to LE
Sn to LE
Switch In
Switch Out
MAX
E1, E2, LE
VOS
MAX
Sn
VOS
MAX
E1
VOS
MAX
E2
VOS
MAX
LE
VOS
MAX
Sn
VOS
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CD74 CD74
HC HCT
30
5
11
11
90
90
90
90
75
75
75
75
83
83
83
83
28
5
11
11
113
113
113
113
83
83
90
90
90
90
98
98
4352
ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH
Function Diagram
A CHANNELS IN/OUT
VCC
A3
A2
A1
A0
15
19
18
16
20
TG
S0
S0
13
S0
LATCHES
S1
LE
12
TG
S1
TG
S1
BINARY
TO
1 OF 4
DECODER
WITH
ENABLE
LOGIC
LEVEL
CONVERSION
11
TG
17
A COMMON
OUT/IN
TG
4
B COMMON
OUT/IN
TG
E1
7
E2
8
TG
TG
10
9
GND
VEE
FUNCTION TABLE
INPUTS
E1
L
L
L
L
H
E2
H
H
H
H
L
S1
L
L
H
H
X
S0
L
H
L
H
X
“ON”†
SWITCCHES
LE = H
A0, B0
A1, B1
A2, B2
A3, B3
None
NOTES:
† When LE is low S0-S2 data are latched and switches
cannot change state.
H = High Voltage Level, L = Low Voltage Level, X =
Don’t Care
5
2
6
1
B0
B1
B2
B3
B CHANNELS IN/OUT
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
MAX or MIN CD74 UNIT
HC
MAX
0.16
mA
SWITCHING CHARACTERISTICS
PARAMETER
tW
tsu
tH
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPLZ
tPHZ
UNIT:ns
INPUT
OUTPUT
MAX or MIN
MIN
MIN
MIN
LE
Sn to LE
Sn to LE
Switch In
Switch Out
MAX
E1, E2, LE
VOS
MAX
Sn
VOS
MAX
E1, E2, LE
VOS
MAX
CD74
HC
30
5
11
11
105
105
113
113
83
83
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
521
Logic Diagram
4374
OCTAL EDGE-TRIGGERED D-TYPE
DUAL-RANK FLIP-FLOP WITH
3-STAE OUTPUTS
OE
CLK
10
11
C1
● 3-State Outputs Drive Bus Lines Directly
1D
20
1D
C1
1D
To Seven Other Channels
FUNCTION TABLE
OE
L
L
L
H
INPUTS
CLK
↑
↑
L
X
D
H
L
X
X
OUTPUT
Q
H
L
QO
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
AS
UNIT
ICC
MAX
150
mA
IOH
IOL
MAX
MAX
-15
48
mA
mA
SWITCHING CHARACTERISTICS
MAX or MIN
AS
fmax
PARAMETER
INPUT
MIN
125
tw
tsu
th
tPLH
tPHL
MIN
MIN
MIN
4
4
1
8
8
CLK
tPZH
OE
tPZL
tPHZ
OE
tPLZ
UNIT fmax : MHz other : ns
522
OUTPUT
Q
MAX
Q
MAX
Q
MAX
6
8
6.5
7
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1
1Q
4511
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS
Logic Diagram
4
13
BI
a
6
D3
D
12
Q
b
LATCH
LE
LE
LE
LE
Q
11
c
2
D2
D
Q
LATCH
LE
LE
LE
LE
10
d
Q
1
D1
D
Q
LATCH
LE
LE
LE
LE
Q
D
Q
9
e
7
D0
15
f
LE
LE
LE
LE
Q
5
LE
LE
14
LE
g
3
LT
FUNCTION TABLE
LE
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
Bt
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
LT
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
D3
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
D2
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
D1
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
D0
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
a
H
L
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
b
H
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
L
c
H
L
H
H
L
H
H
H
H
H
H
H
L
L
L
L
L
L
NOTES:
X = Don’t Care
Depends on BCD code previously appied when LE = L
Display is blank for all illegal input codes (BCD > HLLH).
RECOMMENDED OPERATING CONDITIONS
d
H
L
H
L
H
H
L
H
H
L
H
L
L
L
L
L
L
L
e
H
L
H
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
f
H
L
H
L
H
L
H
H
H
L
H
H
L
L
L
L
L
L
g
H
L
L
L
L
H
H
H
H
L
H
H
L
L
L
L
L
L
Display
8
Blank
0
1
2
3
4
5
6
7
8
9
Blank
Blank
Blank
Blank
Blank
Blank
PARAMETER
MAX or MIN
CD74 CD74
UNIT
HC HCT
ICC
MAX
0.16
0.16
mA
IOH
IOL
MAX
MAX
-7.4
4
-7.4
4
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tW
tsu
tH
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
Latch Enable
Dn to LE
Dn to LE
MAX or MIN
MIN
MIN
MIN
Dn
a to g
MAX
LE
a to g
MAX
BI
a to g
MAX
LT
a to g
MAX
CD74 CD74
HC HCT
20
20
3
75
75
68
68
55
55
40
40
20
20
5
75
75
68
68
55
55
41
41
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
523
4514
4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES
Logic Diagram
11
Y0
9
Y1
10
Y2
2
A0
S
8
Q
Y3
7
Y4
3
A1
R
S
Q
Q
6
Y5
5
Y6
4
21
A2
R
S
Q
Y7
18
Q
Y8
17
Y9
22
A3
R
S
Q
20
Q
19
Y10
Y11
14
1
LE
R
Q
Y12
13
Y13
23
16
E
Y14
15
Y15
524
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLE
(LE = H)
DECODER INPUTS
E
ADDRESSED OUTPUT H
A3
A2
A1
A0
L
L
L
L
L
L
L
L
L
H
Y1
L
L
L
H
L
Y2
L
L
L
H
H
Y3
L
L
H
L
L
Y4
L
L
H
L
H
Y5
L
L
H
H
L
Y6
L
L
H
H
H
Y7
L
H
L
L
L
Y8
L
H
L
L
H
Y9
L
H
L
H
L
Y10
L
H
L
H
H
Y11
L
H
H
L
L
Y12
L
H
H
L
H
Y13
L
H
H
H
L
Y14
L
H
H
H
H
Y15
H
X
X
X
X
All outputs = L
Y0
H = high, L = low, X = don’t care
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN SN74 CD74 CD74 UNIT
HC
HC HCT
MAX
MAX
MAX
0.08
-4
4
0.16
-4
4
0.08
-6
6
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
LE (LE)
LE (LE)
LE (LE)
A, B, C, D
(A1, 2, 3, 4)
Y
LE
(LE)
Y
G
(E)
Y
MAX or MIN SN74 CD74 CD74
HC
HC HCT
MIN
MIN
MIN
MAX
20
25
5
58
58
22
30
0
83
83
38
25
5
69
69
MAX
58
58
44
44
68
68
53
53
63
63
50
50
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
525
4515
4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES
Logic Diagram
11
Y0
9
Y1
10
Y2
2
A0
S
8
Q
Y3
7
Y4
3
A1
R
S
Q
Q
6
Y5
5
Y6
4
21
A2
R
S
Q
Y7
18
Q
Y8
17
Y9
22
A3
R
S
Q
20
Q
19
Y10
Y11
14
1
LE
R
Q
Y12
13
Y13
23
16
E
Y14
15
Y15
526
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLE
(LE = H)
DECODER INPUTS
E
ADDRESSED OUTPUT L
A3
A2
A1
A0
L
L
L
L
L
L
L
L
L
H
Y1
L
L
L
H
L
Y2
L
L
L
H
H
Y3
L
L
H
L
L
Y4
L
L
H
L
H
Y5
L
L
H
H
L
Y6
L
L
H
H
H
Y7
L
H
L
L
L
Y8
L
H
L
L
H
Y9
L
H
L
H
L
Y10
L
H
L
H
H
Y11
L
H
H
L
L
Y12
L
H
H
L
H
Y13
L
H
H
H
L
Y14
L
H
H
H
H
Y15
H
X
X
X
X
All outputs = H
Y0
H = high, L = low, X = don’t care
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN SN74 CD74 CD74 UNIT
HC
HC HCT
MAX
MAX
MAX
0.08
-4
4
0.16
-4
4
0.08
-6
6
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
tw
tsu
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT:ns
OUTPUT
LE (LE)
LE (LE)
LE (LE)
MAX or MIN SN74 CD74 CD74
HC
HC HCT
MIN
MIN
20
25
22
30
38
25
MIN
5
58
58
58
58
0
83
83
68
68
5
69
69
63
63
44
44
53
53
50
50
A, B, C, D
(A1, 2, 3, 4)
Y
(CD74HCT:Y)
MAX
LE
(LE)
Y
(CD74HCT:Y)
MAX
G
(E)
Y
(CD74HCT:Y)
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
527
4518
DUAL SYNCHRONOUS COUNTERS
Logic Diagram
Q0
Q1
3(11)
Q
FF
CL Q
R
D
Q
FF
CL Q
R
Q2
4(12)
Q3
5(13)
Q
FF
CL Q
R
D
Q
FF
CL Q
R
D
D
7(15)
MR
1(9)
CP
2(10)
E
16
VCC
8
GND
FUNCTION TABLE
INPUTS
E
CP
MR
H
L
L
L
X
L
H
L
L
L
H
L
L
X
H
OUTPUT STATE
Increment Counter
Increment Counter
No Change
No Change
No Change
No Change
Q0 thru Q3 = L
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN CD74 UNIT
HC
ICC
IOH
IOL
MAX
MAX
MAX
0.16
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
fmax
tw
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
528
MAX or MIN CD74
HC
MIN
CP
MR
Enable to CP
CP to Enable
tsu
UNIT
OUTPUT
MIN
MIN
CP
Qn
MAX
Enable
Qn
MAX
MR
Qn
MAX
fmax : MHz
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
other : ns
20
24
30
24
24
72
72
72
72
45
45
6(14)
4520
DUAL SYNCHRONOUS COUNTERS
Logic Diagram
Q0
Q1
3(11)
D
Q
FF
CL Q
R
Q2
4(12)
D
Q
FF
CL Q
R
Q3
5(13)
D
Q
FF
CL Q
R
6(14)
D
Q
FF
CL Q
R
7(15)
MR
VCC
1(9)
CP
2(10)
E
16
VCC
8
GND
FUNCTION TABLE
INPUTS
E
MR
H
L
L
L
X
L
L
X
L
L
H
L
X
X
H
CP
OUTPUT STATE
Increment Counter
Increment Counter
No Change
No Change
No Change
No Change
Q0 thru Q3 = L
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN CD74 CD74 UNIT
HC HCT
ICC
IOH
IOL
MAX
MAX
MAX
0.16
-4
4
0.16
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
fmax
tw
MAX or MIN
MIN
CP
MR
Enable to CP
CP to Enable
tsu
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT
OUTPUT
fmax : MHz
MIN
MIN
CP
Qn
MAX
Enable
Qn
MAX
MR
Qn
MAX
CD74 CD74
HC HCT
20
24
30
24
24
72
72
72
72
45
45
17
30
30
24
80
80
83
83
53
53
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
529
4538
DUAL RETRIGGERABLE PRECISION MONO STABLE MULTIVIBRATOR
Logic Diagram
16
VCC
VCC
VCC
VCC
RX
2(14)
CX
R1
+
COMP II
6(10)
Q
-
1(15)
R2
VCC
VCC
8
3(13)
R
VCC
4(12)
D R1
A
5(11)
CL
R2
FF
CL
Q
Q
B
530
7(9)
Q
HIGH Z
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLE
R
L
X
X
H
H
INPUTS
A
B
X
X
X
H
X
L
L
H
OUTPUTS
Q
E
H
L
H
L
H
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN CD74 CD74 UNIT
HC HCT
ICC
MAX
0.16
0.16
mA
IOH
IOL
MAX
MAX
-4
4
-4
4
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tW
tWL
tWL
tPLH
tPHL
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
A, B
A, B
R
A, B
R
MAX or MIN
MIN
Q
Q
Q
Q
MAX
MAX
CD74 CD74
HC HCT
24
24
24
75
24
24
30
83
75
75
83
75
60
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
531
4543
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS
Logic Diagram
7
9
B1
5
a
10
b
D0 Q0
D0
LATCH
LD
LD Q0
LD
LD
11
c
3
D1 Q1
D1
LATCH
LD
LD Q1
LD
LD
12
d
LD
Qn
Dn Qn
Dn
2
D2
D2
LD
LATCH
LD
LD
n
LD Q n
Q2
p
LD
LD
LD Q2
13
e
Qn
LD
p
n
LD
4
D3
D3 Q3
15
f
LATCH
LD
1
LD
LD
LD
LD Q3
LD
14
g
LD
PH
532
6
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLE
B1
LD
H
X
H
L
H
L
L
H
H
L
H
L
H
L
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
as above
PH
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
N
D3 D2 D1
X X X
L L L
L L L
L L H
L L H
L H L
L H L
L H H
L H H
H L L
H L L
H L H
H L H
H H L
H H L
H H H
H H H
X X X
as above
D0
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
a
L
H
L
H
H
L
H
H
H
H
H
L
L
L
L
L
L
b
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
L
c
L
H
H
L
H
H
H
H
H
H
H
L
L
L
L
L
L
d
L
H
L
H
H
L
H
H
L
H
H
L
L
L
L
L
L
e
L
H
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
f
L
H
L
L
L
H
H
H
L
H
H
L
L
L
L
L
L
inverse above
Display
g
L
L
L
H
H
H
H
H
L
H
H
L
L
L
L
L
L
Blank
0
1
2
3
4
5
6
7
8
9
Blank
Blank
Blank
Blank
Blank
Blank
as above
NOTES:
Depends open the BCD code previously appied when LE = High
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
CD74 CD74
UNIT
HC HCT
ICC
MAX
0.16
0.16
mA
IOH
IOL
MAX
MAX
-1
1
-1
1
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tW
tsu
tH
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
Latch Disable
Dn to LD
Dn to LD
MAX or MIN
CD74 CD74
HC HCT
MIN
MIN
13
15
13
15
MIN
8
85
85
93
93
10
100
100
96
96
66
66
50
50
83
83
83
83
Dn
a to g
MAX
LD
a to g
MAX
B1
a to g
MAX
PH
a to g
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
533
Logic Diagram
5400
11-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
OE1
OE2
● Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are Required
(SN74ABT5400A)
D1
14
15
28
1
Y1
To Ten Other Channels
FUNCTION TABLE
OE1
L
L
H
X
INPUTS
OE2
D
L
L
H
L
X
X
H
X
INPUT
Y
L
H
Z
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
MAX or MIN
ABT
UNIT
MAX
MAX
MAX
45
-12
12
mA
mA
mA
PARAMETER
INPUT
OUTPUT
MAX or MIN
D
Y
MAX
OE
Y
MAX
OE
Y
MAX
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
5401
ABT
6.2
5.6
8.7
7.5
5.2
6.9
Logic Diagram
OE1
11-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
OE2
● Output Ports Have Equivalent 25-Ω Series Resistors,
So No External Resistors Are Required
(SN74ABT5401)
D1
14
15
28
1
Y1
To Ten Other Channels
FUNCTION TABLE
OE1
L
L
H
X
INPUTS
OE2
D
L
L
L
H
X
X
H
X
OUTPUT
Y
H
L
Z
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
MAX or MIN
ABT
UNIT
MAX
MAX
MAX
45
-12
12
mA
mA
mA
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
534
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
INPUT
OUTPUT
MAX or MIN
D
Y
MAX
OE
Y
MAX
OE
Y
MAX
ABT
6.9
5.7
8.5
6.8
5.2
6.9
Logic Diagram
5402
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
OE1
OE2
● Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are Required
(SN74ABT5402A)
D1
14
15
28
1
Y1
To Eleven Other Channels
FUNCTION TABLE
OE1
L
L
H
X
INPUTS
OE2
D
L
L
L
H
X
X
H
X
OUTPUT
Y
L
H
Z
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
MAX or MIN
ABT
UNIT
MAX
MAX
MAX
48
-12
12
mA
mA
mA
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
D
Y
MAX
OE
Y
MAX
OE
Y
MAX
5403
ABT
6.2
5.6
8.7
7.5
5.2
6.9
Logic Diagram
OE1
11-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
OE2
● Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are Required
(SN74ABT5403)
D1
14
15
28
1
Y1
To 11 Other Channels
FUNCTION TABLE
OE1
L
L
H
X
INPUTS
OE2
D
L
L
L
H
X
X
H
X
OUTPUT
Y
H
L
Z
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
MAX or MIN
ABT
UNIT
MAX
MAX
MAX
45
-12
12
mA
mA
mA
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
D
Y
MAX
OE
Y
MAX
OE
Y
MAX
ABT
6.9
5.7
8.5
6.8
5.2
6.9
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
535
Logic Diagram
7001
QUADRUPLE POSITIVE-AND GATES
WITH SCHMITT-TRIGGER INPUTS
●
●
●
●
A
Y
B
Same Pinouts as SN74HC08
VCC: 2V to 6V
Schmitt-Triggered Inputs
Y = A•B
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
HC
UNIT
ICC
MAX
0.02
mA
IOH
IOL
MAX
MAX
-4
4
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
INPUT
OUTPUT
MAX or MIN
HC
A or B
Y
MAX
33
33
7002
Logic Diagram
QUADRUPLE POSITIVE-NOR GATES
WITH SCHMITT-TRIGGER INPUTS
●
●
●
●
A
Y
B
Same Pinouts as SN74HC36
VCC: 2V to 6V
Schmitt-Triggered Inputs
Y=A+B
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
HC
UNIT
MAX
MAX
MAX
0.02
-4
4
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
536
INPUT
OUTPUT
MAX or MIN
HC
A or B
Y
MAX
33
33
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
7032
QUADRUPLE 2-INPUT POSITIVE-OR GATES
WITH SCHMITT-TRIGGER INPUTS
●
●
●
●
A
Y
B
Same Pinouts as SN74HC32
VCC: 2V to 6V
Schmitt-Triggered Inputs
Y=A+B
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
HC
UNIT
ICC
IOH
MAX
MAX
0.02
-4
mA
mA
IOL
MAX
4
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
INPUT
OUTPUT
MAX or MIN
HC
A or B
Y
MAX
33
33
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
537
7046
PHASE-LOCKED LOOP WITH VCO AND LOCK DETECTOR
Logic Diagram
C1
6
7 4
3
14
SIGIN
COMPIN
PC1OUT
+
VREF
C1B
VCOOUT
C1A
12 R2
150Ω
-
R2
2
1.5K
VCO
LOCK DETECTOR
1
11 R1
LOCK
DETECTOR
OUTPUT
15
CLD
LOCK
DETECTOR
CAPACITOR
R1
-
R5
+
VCC
DEMOUT
10
-
VCC
D
Q
UP
p
CP Q
RD
+
13
PC2OUT
C2
n
VCC
D
Q
GND
DOWN
CP
Q
RD
INH
VCOIN
5
9
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
538
SWITCHING CHARACTERISTICS
MAX or MIN CD74 CD74 UNIT
HC HCT
MAX
MAX
MAX
R3
0.16
-4
4
0.16
-4
4
mA
mA
mA
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
MAX or MIN CD74 CD74
HC HCT
INPUT
OUTPUT
SIGIN,
COMPIN
PC1 OUT
MAX
SIGIN,
COMPIN
PC2 OUT
MAX
SIGIN,
COMPIN
PC2 OUT
MAX
60
60
84
84
98
98
68
68
90
90
105
105
Logic Diagram
7266
QUAD 2-INPUT EXCLUSIVE-NOR GATES
nA
● Y=A⊕B
nB
nY
FUNCTION TABLE
INPUTS
A
B
L
L
L
H
H
L
H
H
OUTPUT
Y
H
L
L
H
NOTES:
H = High Voltage Level
L = Low Voltage Level
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
MAX or MIN SN74 CD74 UNIT
HC
HC
MAX
MAX
MAX
0.02
-4
4
0.04
-4
4
PARAMETER
mA
V
V
tPLH
tPHL
UNIT:ns
INPUT
OUTPUT
A or B
Y
Y
8003
MAX or MIN SN74 CD74
HC
HC
MAX
MAX
25
25
35
35
Logic Diagram
DUAL 2-INPUT POSITIVE-NAND GATES
1A
1B
2A
2B
1
2
6
7
3
5
1Y
2Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
AS
UNIT
MAX
MAX
MAX
1.5
-0.4
8
8.7
-2
20
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
UNIT: ns
INPUT
A or B
OUTPUT
Y
MAX or MIN
ALS
AS
MAX
11
8
4.5
4
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
539
16240
16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
540
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OE
A
H
L
L
L
X
H
OUTPUT
Y
L
H
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
LVT
3V
LVTH
3V
ALVT
3V
AC
ACT
AHC
AHCT
LVCH
3V
LVCZ
3V
ALVCH
3V
UNIT
MAX
MAX
MAX
34
-32
64
5
-32
64
5
-32
64
5
-32
64
0.08
-24
24
0.08
-24
24
0.04
-8
8
0.04
-8
8
0.02
-24
24
0.1
-24
24
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
ABT
LVT
3V
LVTH
3V
ALVT
3V
AC
ACT
AHC
AHCT
4.7
4.8
5.3
7.1
6.1
5.6
3.5
3.5
4
4.4
4.5
4.2
3.5
3.5
4
4.4
4.5
4.2
3.3
3.2
3.7
3.1
5
4.1
5.8
7.1
6.6
8.1
8.1
7.3
8.5
10.2
9.4
11.4
12
10.7
8.5
8.5
10.5
10.5
10.5
10.5
10.5
10.5
13
13
13
13
LVCH
3V
LVCZ
3V
ALVCH
3V
4.2
4.2
4.7
4.7
5.9
5.9
4.2
4.2
4.7
4.7
5.9
5.9
3.9
3.9
5
5
4.4
4.4
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
541
16241
16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
542
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
FUNCTION TABLE
INPUTS
1OE, 4OE 1A, 4A
H
L
L
L
H
X
OUTPUTS
1Y, 4Y
L
H
Z
INPUTS
2OE, 3OE 2A, 3A
H
H
H
L
L
X
OUTPUTS
2Y, 3Y
H
L
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
LVTH
3V
ACT
UNIT
MAX
MAX
MAX
34
-32
64
5
-32
64
0.08
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE or OE
Y
MAX
OE or OE
Y
MAX
ABT
LVTH
3V
ACT
3.7
4.5
5
6.9
6.2
5.6
3.5
3.5
4.5
4.5
5.3
4.9
9.5
9.1
9.4
10.5
11.6
10.7
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
543
16244
16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
544
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
FUNCTION TABLE
(each buffer)
INPUTS
A
OE
H
L
L
L
X
H
OUTPUT
Y
H
L
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
ABTH
LVT
3V
LVTH
3V
ALVTH
3V
AC
ACT
AHC
AHCT
LVC
3V
LVCH
3V
UNIT
MAX
MAX
MAX
32
-32
64
32
-32
64
5
-32
64
5
-32
64
5
-32
64
0.08
-24
24
0.08
-24
24
0.04
-8
8
0.04
-8
8
0.02
-24
24
0.02
-24
24
mA
mA
mA
MAX or MIN
LVCZ
3V
ALVC
3V
ALVCH
3V
AVC
3V
UNIT
MAX
MAX
MAX
0.1
-24
24
0.04
-24
24
0.04
-24
24
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
ABT
ABTH
LVT
3V
LVTH
3V
ALVTH
3V
AC
ACT
AHC
3.5
4.1
4.8
4.8
4.8
4.1
3.5
4.1
4.8
4.8
4.8
4.1
3.2
3.2
4
4
4.5
4.2
3.2
3.2
4
4
4.5
4.2
2.4
2.5
3.8
2.9
4.2
3.6
7.1
7.9
7.5
9
8.4
7.6
9.4
9.5
8.9
10.3
11.3
10.3
8.5
8.5
10.5
10.5
10.5
10.5
AHCT
LVC
3V
LVCH
3V
LVCZ
3V
ALVC
3V
ALVCH
3V
AVC
3V
10.5
10.5
13
13
13
13
4.1
4.1
4.6
4.6
5.8
5.8
4.1
4.1
4.6
4.6
5.8
5.8
4.1
4.1
4.6
4.6
5.8
5.8
3
3
4.4
4.4
4.1
4.1
3
3
4.4
4.4
4.1
4.1
1.7
1.7
3.5
3.5
3.5
3.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
545
16245
16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Logic Diagram
1DIR
1
2DIR
48
1A1
2A1
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2OE
36
13
1B1
To Seven Other Channels
546
25
1OE
47
2
24
To Seven Other Channels
2B1
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE
DIR
L
L
L
H
X
H
OPERATION
B data to A bus
A data to B bus
Isolation
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
ABTH
LVT
3V
LVTH
3V
ALVTH
3V
AC
ACT
AHCT
UNIT
MAX
MAX
MAX
32
-32
64
32
-32
64
5
-32
64
5
-32
64
5
-32
64
0.08
-24
24
0.08
-24
24
0.04
-8
8
mA
mA
mA
MAX or MIN
LVC
3V
LVCH
3V
LVCHR
3V
LVCZ
3V
ALVCH
3V
ALVC
HR
3V
AVC
3V
UNIT
MAX
MAX
MAX
0.02
-24
24
0.02
-24
24
0.02
-12
12
0.06
-24
24
0.04
-24
24
0.04
-12
12
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
OE
B or A
MAX
OE
B or A
MAX
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
OE
B or A
MAX
OE
B or A
MAX
ABT
ABTH
LVT
3V
LVTH
3V
ALVTH
3V
AC
ACT
AHCT
3.9
4.2
6.3
6.4
6.3
5.2
3.9
4.2
6.3
6.4
6.3
5.2
3.3
3.3
4.5
4.6
5.1
5.1
3.3
3.3
4.5
4.6
5.1
5.1
3.1
2.9
4.2
3.5
5.3
5
7.9
8.9
8.6
10.7
9.8
8.7
10.5
10.2
10
11.6
12.6
11.8
10.5
10.5
15
15
15
15
LVC
3V
LVCH
3V
LVCHR
3V
LVCZ
3V
ALVCH
3V
ALVC
HR
3V
AVC
3V
4
4
5.5
5.5
6.6
6.6
4
4
5.5
5.5
6.6
6.6
4.8
4.8
6.3
6.3
7.4
7.4
4
4
5.6
5.6
6.6
6.6
3
3
4.4
4.4
4.1
4.1
4.2
4.2
5.6
5.6
5.5
5.5
1.7
1.7
3.7
3.7
3.9
3.9
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
547
16260
12-BIT TO 24-BIT MULTIPLEXES D-TYPE LATCH WITH 3-STATE OUTPUTS
Logic Diagram
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
A1
2
27
30
55
56
29
1
28
8
G1
C1
1
1D
23
1B1
1
C1
1D
C1
1D
C1
1D
To 11 Other Channels
548
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
6
2B1
FUNCTION TABLE
B TO A (OEB = H)
1B
H
L
X
X
X
X
X
2B
X
X
X
H
L
X
X
INPUTS
SEL LE1B LE2B OEA
X
L
H
H
X
L
H
H
H
X
L
L
L
X
L
H
L
X
L
H
X
L
L
L
X
X
X
H
OUTPUT
A
H
L
A0
H
L
A0
Z
A TO B (OEA = H)
INPUTS
1B LEA1B LEA2B OE1B OE2B
L
L
H
H
H
L
L
H
L
H
L
L
H
H
L
L
L
L
L
H
L
L
L
H
H
L
L
L
L
H
L
L
L
L
X
X
X
H
X
H
X
X
L
H
X
X
L
X
X
H
X
X
X
L
L
OUTPUTS
1B
2B
H
H
L
L
2B0
H
2B0
L
1B0
H
1B0
L
1B0
2B0
Z
Z
Z
Active
Z
Active
Active Active
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABTH
ALVCH
3V
UNIT
MAX
MAX
MAX
63
-32
64
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
tw Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high
tsu Setup time, data before LE1B, LE2B, LEA1B, or LEA2B
th Hold time, data after LE1B, LE2B, LEA1B, or LEA2B
tPLH
A or B
B or A
tPHL
tPLH
LE
A or B
t
MAX or MIN
ABTH
ALVCH
3V
MIN
MIN
MIN
3.3
1.5
1
5.6
5.9
5.8
5.3
5.3
6
4.4
5.9
5.7
5.8
6.4
4.8
3.3
1.1
1.5
4.3
4.3
4.4
4.4
5.6
5.6
5.6
5.6
5.4
5.4
4.6
4.6
MAX
MAX
PHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
SEL
SEL
SEL
SEL
(B1)
(B2)
(B1)
(B2)
MAX
A
MAX
OE
A or B
MAX
OE
A or B
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
549
16269
12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Logic Diagram
CLK
OEB1
29
C1
2
1D
C1
OEB2
CLKENA1
CLKENA2
56
1D
30
55
C1
SEL
OEA
28
1D
1
1D
1 of 12 Channels
C1
G1
A1
8
C1
1
1D
23
1B1
1
CE
C1
1D
CE
C1
1D
550
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
6
2B1
FUNCTION TABLE
OUTPUT ENABLE
→→→→
INPUTS
CLK OEA OEB
H
H
L
H
L
H
L
L
OUTPUTS
A 1B,2B
Z
Z
Z
Active
Active
Z
Active Active
A-TO-B STORAGE (OEB = L)
→→→→
INPUTS
CLKENA1 CLKENA2 CLK
H
H
X
X
L
X
L
X
L
X
L
A
X
L
H
L
H
OUTPUTS
1B
2B
1B0† 2B0†
X
L
X
H
X
L
X
H
† Output level before the indicated steady-state input conditions
were established
B-TO-A STORAGE (OEA = L)
→→→→
CLK
X
X
INPUTS
SEL
1B
H
X
L
X
H
H
H
L
L
X
L
X
2B
X
X
X
X
L
H
OUTPUT
A
A0†
A0†
L
H
L
H
† Output level before the indicated steady-state
input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
MAX
MAX
MAX
ICC
IOH
IOL
ALVCH ALVCHR
3V
3V
0.04
-24
24
0.04
-12
12
AVC
3V
UNIT
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration, CLK high or low
A data before CLK
B data before CLK
tsu Setup time
SEL before CLK
CLKENA1 or CLKENA2 before CLK
OE before CLK
A data after CLK
B data after CLK
th Hold time
SEL after CLK
CLKENA1 or CLKENA2 after CLK
OE after CLK
B
tpd
CLK
A
B
ten
CLK
A
B
tdis
CLK
A
UNIT fmax : MHz other : ns
MAX or MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MAX
MAX
MAX
ALVCH ALVCHR
3V
3V
135
3.3
1.7
1.8
1.3
0.9
1.3
0.6
0.6
0.7
1.1
0.8
6.2
5
6.1
5.9
6.1
5.6
135
3.3
1
1.1
1.3
0.8
1.2
1.2
1
1.7
1.6
1.2
5.8
5.2
5.8
5.3
6
6
AVC
3V
175
3.5
1.9
1.9
1.3
1.1
1.1
1
0.7
0.4
1
0.3
3
2.7
3.8
3.4
3.7
3.4
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
551
16270
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
Logic Diagram
29
CLK
2
CLKEN1B
CLKEN2B
CLKENA1
CLKENA2
OEB
SEL
OEA
27
30
55
C1
56
1D
28
1
CE
1D
C1
1D
C1
G1
A1
1
CE
C1
1D
1D
CE
C1
1D
C1
1D
CE
C1
1D
1 of 12 Channels
552
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1B1
CE
1
8
23
6
2B1
FUNCTION TABLE
OUTPUT ENABLE
→→→→
INPUTS
CLK OEA OEB
H
H
L
H
L
H
L
L
OUTPUTS
A 1B,2B
Z
Z
Z
Active
Active
Z
Active Active
A-TO-B STORAGE (OEB = L)
INPUTS
CLKENA1 CLKENA2 CLK
L
H
H
L
L
L
L
L
L
H
H
L
H
X
H
→→→→→→
A
L
H
L
H
L
H
X
OUTPUTS
1B
2B
L† 2B0‡
H† 2B0‡
L†
L
H†
H
L
1B0‡
H
1B0‡
1B0‡ 2B0‡
† Two CLK edges are needed to propagate data.
‡ Output level before the indicated steady-state input conditions
were established
B-TO-A STORAGE (OEA = L)
→→→→
INPUTS
CLKEN1B CLKEN2B CLK SEL
X
X
H
H
X
H
X
L
L
X
H
L
X
H
X
L
L
X
L
L
1B
X
X
H
L
X
X
OUTPUT
A
A0‡
A0‡
L
H
L
H
2B
X
X
X
X
L
H
‡ Output level before the indicated steady-state input conditions were
established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
fmax
tw Pulse duration, CLK high or low
A data before CLK
B data before CLK
tsu Setup time
CLKENA1 or CLKENA2
CLKEN1B or CLKEN2B
OE before CLK
A data after CLK
B data after CLK
th Hold time
CLKENA1 or CLKENA2
CLKEN1B or CLKEN2B
OE after CLK
tpd
ten
tdis
UNIT
fmax : MHz
OUTPUT
before CLK
before CLK
after CLK
after CLK
MAX or MIN
ALVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
150
3.3
3.1
0.9
2.7
2.6
3.2
0.2
1.7
0.3
0.6
0.1
5.1
4.7
5.5
6
6
5.8
5.8
CLK
A or B
MAX
SEL
A
MAX
CLK
A or B
MAX
CLK
A or B
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
553
16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS
Logic Diagram
CLK
29
2
LE1B
27
LE2B
CLKENA1
CLKENA2
30
55
56
OEB
28
SEL
LE
23
1
1D
OEA
1B1
G1
1
8
A1
LE
6
1
1D
CE
C1
1D
CE
C1
1D
1 of 12 Channels
554
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2B1
FUNCTION TABLE
OUTPUT ENABLE
INPUTS
OEA OEB
X
H
L
L
L
H
L
L
OUTPUTS
A
1B, 2B
Z
Z
Z
Active
Active
Z
Active Active
A-TO-B STORAGE (OEB = L)
→→→→
INPUTS
CLKENA1 CLKENA2 CLK
H
X
H
L
X
X
L
L
X
X
L
A
X
L
H
L
H
OUTPUTS
1B
2B
1B0† 2B0†
L
X
X
H
L
X
A0
H
B-TO-A STORAGE (OEA = L)
LE
H
H
L
L
L
L
INPUTS
SEL
1B
X
X
X
X
H
L
H
H
X
L
L
X
OUTPUTA
2B
X
X
X
X
L
H
A0†
A0†
L
H
L
H
† Output level before the indicated steady-state
input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
MAX or MIN
ALVCH
3V
B
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MAX
130
3.3
1.7
1.3
1
0.7
1.1
0.9
4.3
4
4.8
5.2
5.1
4.2
fmax
tw Pulse duration, CLK high or low
tsu Setup time
th Hold time
tpd
ten
tdis
UNIT
fmax : MHz
A before CLK
B before LE
CLKEN before CLK
A after CLK
B after LE
CLKEN after CLK
CLK
B
LE
SEL
OEB or OEA
OEB or OEA
other : ns
A
MAX
B or A
B or A
MAX
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
555
16282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
Logic Diagram
CLK
SEL
OE
39
40
42
CE
C1
DIR
41
1D
25
1 of 18 Channels
1B1
G1
CE
C1
A1
27
1
1D
C1
1D
1
CE
C1
1D
C1
1D
CE
C1
1D
556
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
24
2B1
FUNCTION TABLE
A-TO-B STORAGE (OE = L, DIR = H)
INPUTS
CLK
A
X
X
L
H
→→
SEL
H
L
L
OUTPUTS
1B
2B
1B0† 2B0†
L‡
X
H‡
X
† Output level before the indicated steady-state
input conditions were established
‡ Two CLK edges are needed to propagate the
data.
B-TO-A STORAGE (OE = L, DIR = L)
→→→→
CLK
INPUTS
SEL
1B
H
X
H
X
L
L
L
H
OUTPUT
A
L§
H§
L
H
2B
L
H
X
X
§ Two CLK edges are needed to propagate the
data. The data is loaded in the first register when
SEL is low and propagates to the second register
when SEL is high.
OUTPUT ENABLE
→→→
CLK
INPUTS
OE
DIR
H
X
L
L
L
H
OUTPUTS
A 1Ｂ, 2Ｂ
Z
Z
Active
Z
Active
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration, CLK high or low
A data before CLK
B data before CLK
tsu Setup time
DIR before CLK
SEL before CLK
A data after CLK
B data after CLK
th Hold time
DIR after CLK
SEL after CLK
tpd
CLK
ten
OE
tdis
OE
UNIT
fmax : MHz
A
B
A
B
A
B
MAX or MIN
ALVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
150
3.3
2
1.8
1.7
1.8
0.7
0.6
0.5
0.8
5
5.3
5.7
7.4
5.7
6.4
MAX
MAX
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
557
16334
16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
Logic Diagram
OE
CLK
LE
A1
1
48
25
47
1D
C1
CLK
To 15 Other Channels
558
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2
Y1
FUNCTION TABLE
INPUTS
OE
H
L
L
L
L
L
LE
X
L
L
H
H
H
CLK
X
X
X
↑
↑
L or H
A
X
L
H
L
H
X
OUTPUT
Y
Z
L
H
L
H
Y0†
† Output level before the indicated steady-state
input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVC
3V
ALVCH
3V
AVC
3V
UNIT
MAX
MAX
MAX
0.04
-24
24
0.04
-24
24
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tpd
ten
tdis
UNIT
fmax : MHz
LE low
CLK high or low
Data before CLK
Data before LE
CLK high
Data before LE
CLK low
Data after CLK
Data after LE
CLK high
Data after LE
CLK low
A
LE
CLK
OE
OE
other : ns
MAX or MIN
ALVC
3V
ALVCH
3V
AVC
3V
MIN
150
3.3
3.3
1.5
1.3
1.2
0.9
1.1
1.1
3.3
4.4
4.1
4.6
4.4
150
3.3
3.3
1.5
1.3
1.2
0.9
1.1
1.1
3.3
4.4
4.1
4.6
4.4
150
3.3
3.3
0.7
0.9
1
0.7
1.5
1.3
2.5
4
3.1
6.2
5.3
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MAX
Y
MAX
Y
Y
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
559
16344
1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
Logic Diagram
OE4
OE3
OE2
OE1
56
29
28
1
2
3
1A
8
6
9
10
14
13
16
17
15
20
23
24
4A
21
26
27
560
31
30
1B4
41
2B1
40
2B2
42
38
2B3
37
2B4
48
3B1
47
3B2
7A
19
36
1B3
6A
12
3A
33
1B2
5A
5
2A
34
1B1
43
45
3B3
44
3B4
55
4B1
54
4B2
8A
4B3
4B4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
49
52
51
5B1
5B2
5B3
5B4
6B1
6B2
6B3
6B4
7B1
7B2
7B3
7B4
8B1
8B2
8B3
8B4
FUNCTION TABLE
INPUTS
OE
L
L
H
A
H
L
H
OUTPUT
Bn
H
L
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
B
MAX
OE
B
MAX
OE
B
MAX
ALVCH
3V
4
4
5.1
5.1
4
4
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
561
16373
16-BIT TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
Logic Diagram
1OE
1LE
1D1
1
2OE
48
47
2LE
C1
1D
2
1Q1
To Seven Other Channels
562
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2D1
24
25
36
C1
1D
To Seven Other Channels
13
2Q1
FUNCTION TABLE
(each latch)
INPUTS
LE
D
OE
H
H
L
H
L
L
X
L
L
H
X
X
OUTPUT
Q
H
L
QO
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
LVTH
3V
ALVTH
3V
AC
ACT
AHC
AHCT
LVC
3V
LVCH
3V
ALVCH
3V
AVC
3V
UNIT
MAX
MAX
MAX
85
-32
64
5
-32
64
5
-32
64
0.08
-24
24
0.08
-24
24
0.04
-8
8
0.04
-8
8
0.02
-24
24
0.02
-24
24
0.04
-24
24
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
tw Pulse duration, LE high or low
Data before LE , data high
tsu Setup time
Data before LE , data low
Data after LE , data high
th Hold time
Data after LE , data low
tPLH
D
tPHL
tPLH
LE
tPHL
tPZH
OE
tPZL
tPHZ
OE
tPLZ
PARAMETER
INPUT
th Hold time
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
ABT
LVTH
3V
ALVTH
3V
AC
ACT
AHC
AHCT
MIN
MIN
MIN
MIN
MIN
3.3
1.5
1.5
1
1
6.3
6.2
6.7
6.1
6.1
5.6
8.1
6.5
3
1
1
1
1
3.8
3.6
4.3
4
4.3
4.3
5
4.7
1.5
1.4
0.9
0.9
1.4
3.1
3.3
3.3
3.5
4
3.4
4.9
4.5
4
1.5
1.5
2.4
2.4
9.7
10.1
11.9
10.9
10.8
12.8
8.8
8.1
1
1
1
5
5
11.1
12.3
12.8
12.2
12.1
14.2
10.7
9.4
5
4
4
1
1
10.5
10.5
10.5
10.5
11.5
11.5
11.5
11.5
6.5
1.5
1.5
3.5
3.5
10.5
10.5
10.5
10.5
11.5
11.5
12
12
Q
MAX
Q
MAX
Q
MAX
Q
MAX
OUTPUT
MAX or MIN
LVC
3V
LVCH
3V
ALVCH
3V
AVC
3V
MIN
3.3
3.3
3.3
1.8
MIN
MIN
MIN
MIN
1.7
1.7
1.2
1.2
4.2
4.2
4.6
1.7
1.7
1.2
1.2
4.2
4.2
4.6
1.1
1.1
1.4
1.4
3.6
3.6
3.9
0.8
0.8
1
1
2.8
2.8
3.2
4.6
4.7
4.7
5.9
5.9
4.6
4.7
4.7
5.9
5.9
3.9
4.7
4.7
4.1
4.1
3.2
3.4
3.4
3.9
3.9
tw Pulse duration, LE high or low
tsu Setup time
MAX or MIN
Data before LE , data high
Data before LE , data low
Data after LE , data high
Data after LE , data low
D
Q
MAX
LE
Q
MAX
OE
Q
MAX
OE
Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
563
16374
16-BIT EDGE-TRIGGERD D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
Logic Diagram
1OE
1CLK
1D1
1
2OE
48
47
2CLK
C1
1D
2
1Q1
To Seven Other Channels
564
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2D1
24
25
36
C1
1D
To Seven Other Channels
13
2Q1
FUNCTION TABLE
(each fllp-flop)
→→
INPUTS
D
OE CLK
H
L
L
L
L
H or L X
H
X
X
OUTPUT
Q
H
L
QO
Z
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ABT
LVTH
3V
ALVTH
3V
AC
ACT
AHC
AHCT
LVC
3V
LVCH
3V
ALVCH
3V
AVC
3V
UNIT
ICC
IOH
MAX
MAX
72
-32
5
-32
5
-32
0.08
-24
0.08
-24
0.04
-8
0.04
-8
0.02
-24
0.02
-24
0.04
-24
0.04
-12
mA
mA
IOL
MAX
64
64
64
24
24
8
8
24
24
24
12
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
PARAMETER
CLK high
CLK low
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
ABT
LVTH
3V
ALVTH
3V
AC
ACT
AHC
AHCT
MIN
150
3.3
3.3
160
3
3
250
1.5
1.5
100
5
5
65
7.5
4.5
110
5
5
110
6.5
6.5
1.1
1.1
1.3
1.3
6.2
5.9
5.6
1.8
1.8
0.8
0.8
4.5
4
4.5
1
1.5
0.5
1
3.2
3.2
3.8
5
5
0
0
10.8
10.6
10.2
4.5
4.5
6.5
6.5
12.4
12.2
11.9
3
3
2
2
11.5
11.5
11.5
2.5
2.5
2.5
2.5
11.5
11.5
11.5
5.3
8.2
6.6
4.4
5
4.6
3.3
4.6
4.2
12.1
8.2
7.9
13.4
10.4
9.8
11.5
11.5
11.5
11.5
12
12
MIN
Data before CLK , data high
Data before CLK , data low
Data after CLK , data high
Data after CLK , data low
MIN
MIN
CLK
Q
MAX
OE
Q
MAX
OE
Q
MAX
INPUT
OUTPUT
MAX or MIN
LVC
3V
LVCH
3V
ALVCH
3V
AVC
3V
MIN
150
150
150
200
MIN
3.3
3.3
3.3
3.3
3.3
3.3
2.5
2.5
1.9
1.9
1.9
1.4
1.9
1.9
1.9
4.5
4.5
4.6
4.6
5.5
5.5
1.9
1.1
1.1
4.5
4.5
4.6
4.6
5.5
5.5
1.9
0.5
0.5
4.2
4.2
4.8
4.8
4.3
4.3
1.4
1.1
1.1
3.3
3.3
3.4
3.4
3.9
3.9
fmax
tw Pulse duration
MAX or MIN
CLK high
CLK low
Data before CLK
, data high
MIN
Data before CLK , data low
Data after CLK , data high
Data after CLK , data low
MIN
CLK
Q
MAX
OE
Q
MAX
OE
Q
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
565
16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS
Logic Diagram
CLK
SELEN
SEL0
SEL1
56
1
55
28
2
29
Flow and Storage Control
27
SEL2
SEL3
30
SEL4
3
1Ax
2A
CLK
D
1Bx 2Ax
2Bx 2Bx
1A
CLK
D
3
2Ax 1Ax
CLK
D
3
1B
3
1Ax
1Ax
1Bx
2Bx
2Ax
1Bx
2Ax
1Bx
CLK
D
2B
2Bx
One of Nine Channels
566
PRE
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
DATA-FLOW CONTROL
FUNCTION TABLE
INPUTS
CLK
SEND PORT
X
X
INPUTS
OUTPUT
RECEIVE PORT
PRE
SELEN
CLK
SEL0
SEL1
SEL2
SEL3
SEL4
H
X
X
X
X
X
X
X
DATA FLOW
X
L
B0†
L
L
H
↑
X
X
X
X
X
No change
X
H
H
L
L
↑
0
0
0
0
0
None, all I/Os off
All outputs disabled
↑
L
L
L
L
↑
0
0
0
0
1
Not used
↑
H
L
↑
0
0
0
1
0
Not used
X
H
B0†
B0†
L
H
L
L
↑
0
0
0
1
1
Not used
0
0
Not used
L
X
† Output level before the indicated steady-state
input conditions were established
L
L
↑
0
L
L
↑
0
0
1
0
1
Not used
L
L
↑
0
0
1
1
0
Not used
L
L
↑
0
0
1
1
1
Not used
0
2A to 1A and 1B to 2B
L
L
0
1
1
↑
0
L
L
↑
0
1
0
0
1
L
L
↑
0
1
0
1
0
2B to 1B
L
L
↑
0
1
0
1
1
2A to 1A and 2B to 1B
0
1A to 2A and 1B to 2B
1
0
0
1
0
2A to 1A
L
L
↑
0
L
L
↑
0
1
1
0
1
1A to 2A
L
L
↑
0
1
1
1
0
1B to 2B
L
L
↑
0
1
1
1
1
1A to 2A and 2B to 1B
L
L
↑
1
0
0
0
0
1A to 1B and 2B to 2A
L
L
↑
1
0
0
0
1
L
L
↑
1
0
0
1
0
2A to 2B
L
L
↑
1
0
0
1
1
1A to 1B and 2A to 2B
1B to 1A and 2A to 2B
1A to 1B
L
L
↑
1
0
1
0
0
L
L
↑
1
0
1
0
1
L
L
↑
1
0
1
1
0
2B to 2A
L
L
↑
1
0
1
1
1
1B to 1A and 2B to 2A
1
0
2B to 1A and 2A to 1B
L
0
0
1B to 1A
L
↑
1
L
L
↑
1
1
0
0
1
L
L
↑
1
1
0
1
0
2B to 1A
L
L
↑
1
1
0
1
1
2B to 1A and 1B to 2A
1
0
1A to 2B and 1B to 2A
1
0
1B to 2A
L
L
↑
1
L
L
↑
1
1
1
0
1
L
L
↑
1
1
1
1
0
2A to 1B
L
L
↑
1
1
1
1
1
1A to 2B and 2A to 1B
1A to 2B
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVCH
3V
ALVC
HR
3V
UNIT
MAX
MAX
MAX
0.04
-24
24
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
OUTPUT
MAX or MIN
ALVCH
3V
ALVC
HR
3V
fmax
tw Pulse duration, CLK high or low
A or B data before CLK
SEL before CLK
tsu Setup time
SELEN before CLK
PRE before CLK
A or B data after CLK
th Hold time
SEL after CLK
SELEN after CLK
CLK
tpd
CLK
ten
A or B
A or B
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MAX
MAX
tdis
A or B
MAX
120
3
1.4
3.5
1.8
0.7
1
0
0.8
5.1
5.7
5.7
6.1
120
3
1.4
3.5
1.8
0.7
1
0
0.8
6.2
6.8
6.1
6.4
PARAMETER
UNIT
INPUT
PRE
fmax : MHz
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
567
16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS WITH 3-STATE OUTPUTS
Logic Diagram
LEB4
LEB3
LEB2
LEB1
24
28
23
27
6
2
5
1
56
55
CLKENB
30
20
29
9
SEL1
SEL0
LEBA
CLKBA
CLKENBA
14
54
15
1A
19
8
LEAB1
OEB1
OEB2
OEB3
OEB4
OEB
CE_SEL0
CE_SEL1
CLKENAB
CLKENAB Selector
21
P
M
U
X
LE
D
CLK
CE
52
LE
D
CLK
CE
51
CLK
CE
D
LE
49
CLK
CE
D
LE
48
10
26
12
LE
CLK
CE
D
LE
CLK
CE
D
LE
CLK
CE
D
LE
CLK
CE
D
568
LEAB2
3
CE
CLK
D
LE
OEA
LEAB3
31
One of Four
Channels
CLKAB
LEAB4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1B1
1B2
1B3
1B4
FUNCTION TABLE
A-TO-B OUTPUT ENABLE
(assuming OEB = L, OEBn = L) ‡
A-TO-B OUTPUT ENABLE
INPUTS
OEB OEBn
H
H
H
L
L
H
L
L
INPUTS
CLKENAB CE_SEL1 CE_SEL0 CLKAB LEAB1 LEAB2 LEAB3 LEAB4
X
H
L
L
L
X
X
H or L
X
H
H
H
L
X
X
H or L
X
L
L
L
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
L
L
H
L
L
L
L
H
L
X
X
L
L
L
H
L
†n = 1, 2, 3, 4
B-TO-A STORAGE
(after point P)
L
→
L
L
L
L
L
L
L
L
L
OUTPUTS
B2
B3
A0
A0
A
A
A0
A0
A0
A0
A0
A
A0
A
A0
A0
A0
A0
B4
A0
A0
A0
A0
A0
A0
A
A0
B-TO-A STORAGE
(after point P)
SEL1 SEL0
L
L
L
H
H
L
H
H
L
L
L
H
H
L
H
H
L
L
L
H
H
L
H
H
INPUTS
CLKENBA CLKBA LEBA OEA
X
X
X
H
X
X
H
L
X
X
H
L
H
L
X
L
L
L
L
L
L
L
L
L
L
L
P
B1
B2
B3
B4
B1
B2
B3
B4
B10†
B20†
B30†
B40†
→→
INPUTS
CLKENB CLKBA LEB1 LEB2 LEB3 LEB4
X
X
L
L
L
H
X
L
L
L
X
H
X
X
L
L
H
L
X
H
X
L
L
L
L
B1
A
A
A0
A
A0
A0
A0
A0
→→→→→
OUTPUT
Bn
Z
Z
Z
Active
OUTPUT
A
Z
L
H
A0†
L
H
A0†
B
X
L
H
X
L
H
X
‡ Output level before the indicated steady-state input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABTH
UNIT
MAX
MAX
MAX
32
-32
64
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw Pulse duration
CLKAB high or low
CLKBA high or low
LEAB1, 2, 3 or 4 high
LEBA high
LEB1, 2, 3 or 4 high
A bus
CE_SEL0/1
Before CLKAB
CLKENAB
Before LEAB1, 2, 3, or 4
A bus
B bus
tsu Setup time
Before CLKBA
CLKENB
CLKENBA
LEB1, 2, 3 or 4
SEL0/1
Before LEB1, 2, 3, or 4
B bus
B bus
LEB1, 2, 3 or 4
Before CLKBA
SEL0/1
A bus
CE_SEL0/1
after CLKAB
CLKENAB
after LEAB1, 2, 3, or 4
A bus
B bus
th Hold time
after CLKBA
CLKENB
CLKENBA
SEL0/1
after LEB1, 2, 3, or 4
B bus
B bus
after CLKBA
SEL0/1
MAX or MIN
ABTH
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
160
3.8
4.5
2.2
2.1
2.4
2.5
3.2
3.2
3.6
3.8
2.3
2.5
4.3
4.5
3.2
4
4.4
4.3
0.5
1.1
0.5
1.2
1.3
1
1
0
1.5
0.4
0.1
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT
INPUT
OUTPUT
MAX or MIN
B
A
MAX
OEA
A
MAX
OEA
A
MAX
A
B
MAX
OEB
B
MAX
OEB
B
MAX
OEB1, 2, 3, 4
B
MAX
OEB1, 2, 3, 4
B
MAX
CLKBA
A
MAX
CLKAB
B
MAX
LEBA
A
MAX
LEAB1, 2, 3, 4
B
MAX
LEBA1, 2, 3, 4
A
MAX
SEL
A
MAX
fmax : MHz
ABTH
6.5
6.5
5.6
5.2
5.9
6.5
5.7
5.7
6.4
6.3
7
6.1
5.8
5.6
6.1
5.3
7.4
7.7
6.2
5.9
5.6
5.3
5.8
5.6
7.2
6.8
7.5
6.9
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
569
16470
16-BIT REGISTERD TRANSCEIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1OEBA
1CLKENBA
1CLKBA
1OEAB
1CLKENAB
1CLKAB
1A1
56
54
55
1
3
2
C1
5
1D
52
1B1
C1
1D
To Seven Other Channels
2OEBA
2CLKENBA
2CLKBA
2OEAB
2CLKENAB
29
31
30
28
26
27
2CLKAB
2A1
C1
15
1D
C1
1D
To Seven Other Channels
570
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
42
2B1
FUNCTION TABLE
INPUTS
CLKENAB CLKAB OEAB
X
X
H
X
H
X
L
L
L
L
L
L
L
→→
A
X
X
X
L
H
OUTPUT
B
Z
Z
B0‡
L
H
† A-to-B data flow is shown: B-to-A flow is similar but
uses CLKENBA, CLKBA, and OEBA.
‡ Output level before the indicated steady-state input
conditions were established.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
ACT
UNIT
MAX
MAX
MAX
35
-32
64
0.08
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration, CLKAB or CLKBA high
tw Pulse duration, CLKAB or CLKBA low
tsu Setup time, data before CLKAB or CLKBA
th Hold time, data after CLKAB or CLKBA
tPLH
CLK
A or B
tPHL
tPZH
OE
A or B
tPZL
tPHZ
OE
A or B
t
MAX or MIN
ABT
ACT
MIN
MIN
150
3.3
3.3
4
1
4.9
4.9
4.9
6.8
5.5
5.3
5.7
7.2
5.8
5.4
55
4
8.5
6
1
11.8
11.7
11.9
13.4
9.9
9.5
12.5
14.3
11.2
10.9
MIN
MIN
MAX
MAX
MAX
PLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
CLKEN
A or B
MAX
CLKEN
A or B
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
571
16500
18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Logic Diagram
1
OEAB
55
CLKAB
2
LEAB
LEBA
28
30
CLKBA
OEBA
A1
27
3
1D
C1
CLK
1D
C1
CLK
To 17 Other Channels
572
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
54
B1
FUNCTION TABLE
INPUTS
CLKAB
LEAB
X
X
X
H
H
X
L
L
H
L
L
L
→→
OEAB
L
H
H
H
H
H
H
A
X
L
H
L
H
X
X
OUTPUT
B
Z
L
H
L
H
B0‡
B0§
† A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, and CLKBA.
‡ Output level befor the indicated steady-state input
conditions were established.
§ Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was low before LEAB went low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
LVTH
3V
ALVCH
3V
UNIT
MAX
MAX
MAX
36
-32
64
5
-32
64
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB
B before CLKBA
A before LEAB or LEBA CLK high
A before LEAB or LEBA CLK low
A after CLKAB or B after CLKBA
A after LEAB or B after LEBA high
A after LEAB or B after LEBA low
MAX or MIN
ABT
LVTH
3V
ALVCH
3V
MIN
150
2.5
3
3
3
1
2.5
0
2
2
4
4.9
5
5
5.3
5.3
5.1
5.4
6.5
5.4
5.1
5.4
6.5
5.4
150
3.3
3.3
2.9
2.9
1.4
2.9
0.4
1.6
1.6
3.7
3.7
5.1
5.1
5
5
4.8
4.8
5.8
5.8
4.8
4.8
5.8
5.8
150
3.3
3.3
1.3
1.3
1
1.4
1.3
1.5
1.2
3.9
3.9
4.7
4.7
5.5
5.5
4.6
4.6
5
5
5.2
5.2
4.3
4.3
MIN
MIN
MIN
A or B
B or A
MAX
LEAB or LEBA
B or A
MAX
CLKAB or CLKBA
B or A
MAX
OEAB
B
MAX
OEAB
B
MAX
OEBA
A
MAX
OEBA
A
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
573
16501
18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Logic Diagram
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
1D
C1
CLK
1D
C1
CLK
To 17 Other Channels
574
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
54
B1
FUNCTION TABLE
INPUTS
CLKAB
LEAB
X
X
H
X
H
X
L
L
H
L
L
L
→→
OEAB
L
H
H
H
H
H
H
A
X
L
H
L
H
X
X
OUTPUT
B
Z
L
H
L
H
B0‡
B0§
† A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was high before LEAB went low.
§ Output level before the indicated steady-state input
conditions were established.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
LVTH
3V
ALVCH
3V
UNIT
MAX
MAX
MAX
76
-32
64
5
-32
64
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB
B before CLKBA
A before LEAB or LEBA CLK high
A before LEAB or LEBA CLK low
A after CLKAB or B after CLKBA
A after LEAB or B after LEBA
MAX or MIN
ABT
LVTH
3V
ALVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
105
3.3
4.7
3.5
3.5
4
1.5
1
2.5
3.7
4
5.1
4.4
5
4.4
4.7
6.5
5.8
4.9
4.7
6.5
5.8
4.9
150
3.3
3.3
2.1
2.1
2.4
1.4
1
1.7
3.7
3.7
5.1
5.1
5.1
5.1
4.8
4.8
5.8
5.8
4.8
4.8
5.8
5.8
150
3.3
3.3
1.7
1.7
1.5
1
0.7
1.4
3.9
3.9
4.6
4.6
4.9
4.9
4.6
4.6
5
5
5
5
4.2
4.2
A or B
B or A
MAX
LEAB or LEBA
B or A
MAX
CLKAB or CLKBA
B or A
MAX
OEAB
B
MAX
OEAB
B
MAX
OEBA
A
MAX
OEBA
A
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
575
16524
18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Logic Diagram
CLK
CLKENBA
OEAB
OEBA
SEL
30
28
2
27
55
1 of 18 Channels
CE
3
A1
576
C1
1D
G1
1
1
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CE
C1
1D
CE
C1
1D
CE
C1
1D
54
B1
FUNCTION TABLE
B-TO-A STORAGE (OEBA = L)
INPUTS
CLK SEL
X
X
H
H
L
L
→→→→
CLKENBA
H
L
L
L
L
B
X
L
H
L
H
OUTPUT
A
A0†
L
H
L‡
H‡
† Output level before the indicated steady-state input
conditions were established
‡ Four positive CLK edges are needed to propagate data
from B to A when SEL is low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
fmax
tw Pulse duration, CLK high or low
B data before CLK
tsu Setup time
SEL before CLK
CLKENBA before CLK
B data after CLK
th Hold time
SEL after CLK
CLKENBA after CLK
A
tpd
CLK
ten
OEAB or OEBA
tdis
OEAB or OEBA
UNIT fmax : MHz other : ns
OUTPUT
B
A
A or B
A or B
MAX or MIN
ALVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
150
3
1.1
2.1
2
1.2
0.8
0.3
3.2
5.2
5.1
4.9
MAX
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
577
16525
18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Logic Diagram
CLKAB
CLK1BA
CLK2BA
CLKENBA
CLKENAB
OEAB
OEBA
SEL
55
30
29
28
1
2
27
56
1 of 18 Channels
G1
CE
A1
3
C1
1D
1
1
CE
C1
1D
CE
C1
1D
578
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CE
C1
1D
CE
C1
1D
54
B1
FUNCTION TABLE
A-TO-B STORAGE (OEAB = L)
→→
INPUTS
CLKENAB CLKAB
X
H
L
L
A
X
L
H
OUTPUT
B
B0†
L
H
† Output level before the indicated steady-state
input conditions were established
B-TO-A STORAGE (OEBA = L)
→→
INPUTS
CLK2BA CLK1BA SEL
X
X
X
X
H
X
H
L
L
→→→→
CLKENA
H
L
L
L
L
OUTPUT
A
A0†
L
H
L‡
H‡
B
X
L
H
L
H
† Output level before the indicated steady-state input conditions were
established
‡ Three CLK1BA edges and one CLK2BA edge are needed to propagate
data from B to A when SEL is low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration, CLK high or low
A data before CLKAB
B data before CLK2BA
B data before CLK1BA
tsu Setup time
SEL before CLK2BA
CLKENAB before CLKAB
CLKENBA before CLK1BA
CLKENBA before CLK2BA
A data after CLKAB
B data after CLK2BA
B data after CLK1BA
th Hold time
SEL after CLK2BA
CLKENAB after CLKAB
CLKENBA after CLK1BA
CLKENBA after CLK2BA
tpd
CLKAB or CLK2BA
A or B
ten
OEAB or OEBA
A or B
tdis
OEAB or OEBA
A or B
UNIT fmax : MHz other : ns
MAX or MIN
ALVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
150
3
1.3
1.7
1.1
3.3
1.6
2.1
2.2
0.9
0.6
1
0.1
0.3
0.1
0
4.2
5.1
4.9
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
579
16540
16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1OE1
1OE2
1A1
1
2OE1
48
2OE2
2
47
1Y1
2A1
24
25
36
13
To Seven Other Channels
To Seven Other Channels
FUNCTION TABLE
(each 8-bit section)
INPUTS
A
OE1 OE2
L
L
L
L
H
L
X
X
H
X
H
X
OUTPUT
Y
H
L
Z
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
ACT
AHC
AHCT
LVCH
3V
UNIT
MAX
MAX
MAX
34
-32
64
0.08
-24
24
0.04
-8
8
0.04
-8
8
0.02
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
580
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2Y1
ABT
ACT
AHC
AHCT
LVCH
3V
4.1
4.3
5.1
5.9
5.7
4.7
7.5
9.5
8.9
10.5
11.9
11.1
8.5
8.5
10.5
10.5
10.5
10.5
10.5
10.5
13
13
13
13
3.7
3.7
4.8
4.8
5.9
5.9
16541
16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1
1OE1
25
2OE2
2
47
1A1
24
2OE1
48
1OE2
1Y1
36
2A1
13
To Seven Other Channels
2Y1
To Seven Other Channels
FUNCTION TABLE
(each 8-bit section)
INPUTS
A
OE1 OE2
L
L
L
L
H
L
X
X
H
X
H
X
OUTPUT
Y
L
H
Z
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
LVTH
3V
ACT
AHC
AHCT
LVCH
3V
UNIT
MAX
MAX
MAX
34
-32
64
5
-32
64
0.08
-24
24
0.04
-8
8
0.04
-8
8
0.02
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
ABT
LVTH
3V
ACT
AHC
AHCT
LVCH
3V
3.4
4.2
5.2
6
5.4
4.3
3.5
3.5
4.6
4.6
5.9
5.4
9
9.2
9.7
11
11.3
10.7
8.5
8.5
10.5
10.5
10.5
10.5
10.5
10.5
13
13
13
13
4.2
4.2
5.6
5.6
6.8
6.8
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
581
16543
16-BIT REGISTERD TRANSCEIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
56
54
55
1
3
2
C1
5
1D
52
1B1
C1
1D
To Seven Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1
29
31
30
28
26
27
C1
15
1D
C1
1D
To Seven Other Channels
582
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
42
2B1
FUNCTION TABLE
(each 8-bit section)
OEAB
H
X
L
L
L
INPUTS
OEAB
LEAB
X
X
H
X
H
L
L
L
L
L
A
X
X
X
L
H
OUTPUT
B
Z
Z
B0‡
L
H
† A-to-B data flow is shown: B-to-A flow control is the
same except that it uses CEBA, LEBA, and OEBA.
‡ Output level before the indicated steady-state input
conditions were established.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
LVTH
3V
AC
ACT
LVC
3V
LVCH
3V
ALVCH
3V
UNIT
MAX
MAX
MAX
35
-32
64
5
-32
64
0.08
-24
24
0.08
-24
24
0.04
-24
24
0.02
-24
24
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
tw Pulse duration, LEAB or LEBA low
Data before LEAB or LEBA , high
Data before LEAB or LEBA , low
tsu Setup time
Data before CEAB or CEBA , high
Data before CEAB or CEBA , low
Data after LEAB or LEBA , high
Data after LEAB or LEBA , low
th Hold time
Data after CEAB or CEBA , high
Data after CEAB or CEBA , low
tPLH
A or B
B or A
tPHL
tPLH
LE
A or B
tPHL
tPZH
OE
A or B
tPZL
tPHZ
OE
A or B
tPLZ
tPZH
CE
A or B
tPZL
tPHZ
CE
A or B
tPLZ
UNIT: ns
MAX or MIN
ABT
LVTH
3V
AC
ACT
LVC
3V
LVCH
3V
ALVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
4
1.5
3.5
1.5
2
3.8
5.1
5.2
5.6
5.2
7
5.7
4.6
6.2
7.8
6.6
5.4
3.3
0.5
0.8
0
0.6
1.5
1.2
1.7
1.6
3.2
3.2
3.9
3.9
4.3
4.3
4.7
4.4
4.5
4.5
4.9
4.7
4
1
1
3
3
8.8
9.2
11.5
10.9
9.6
11.3
8.9
8.4
9.8
11.5
9.3
8.8
7.5
2.5
2.5
4
4
10.5
11.6
13.8
13.5
11.4
13.2
11.1
9.6
11.7
13.5
11.6
10.5
4
2
2
2
2
2
2
2
2
8
8
9
9
8.5
8.5
8.5
8.5
9
9
9
9
3.3
1.1
1.1
1.1
1.1
1.9
1.9
1.9
1.9
5.4
5.4
6.1
6.1
6.3
6.3
6.3
6.3
6.6
6.6
6.6
6.6
3.3
1.2
1.2
1.2
1.2
1.3
1.3
1.3
1.3
4.3
4.3
5
5
5.3
5.3
4.6
4.6
5.6
5.6
5.1
5.1
MAX
MAX
MAX
MAX
MAX
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
583
16600
18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
Logic Diagram
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
CE
3
1D
C1
CLK
CE
1D
C1
CLK
To 17 Other Channels
584
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
54
B1
FUNCTION TABLE
INPUTS
LEAB
X
H
H
L
L
L
L
L
L
CLKAB
X
X
X
X
X
→→
CLKENAB OEAB
X
H
X
L
X
L
L
H
L
H
L
L
L
L
L
L
L
L
H
L
OUTPUT
B
Z
L
H
B0‡
B0‡
L
H
B 0‡
B0§
A
X
L
H
X
X
L
H
X
X
† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, CLKBA and CLKENBA.
‡ Output level before the indicated steady-state input conditions were
established.
§ Output level before the indicated steady-state input conditions were
established, provided that CLKAB was low before LEAB went low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ABT
ALVCH
3V
UNIT
MAX
MAX
MAX
36
-32
64
0.04
-24
24
mA
mA
mA
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB or B before CLKBA
Data before CLK
A before LEAB or B before LEBA , CLK high
A before LEAB or B before LEBA , CLK low
CLKEN after CLK
CLKEN after CLK
th Hold time
A after CLKAB or B after CLKBA
Data after CLK
A after LEAB or B after LEBA , CLK high
A after LEAB or B after LEBA
CLKEN after CLK
CLKEN after CLK
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
, CLK low
MAX or MIN
ABT
ALVCH
3V
MIN
150
150
MIN
MIN
2.5
3
3
2.5
2.5
3.3
3.3
1.2
1.1
1.5
MIN
2.5
2.5
0
2
0.8
1.5
1.6
MIN
2
1.3
MIN
1
4
1.4
4
4.9
5
5
5.3
5
5.1
5.4
6.2
5.4
5.1
5.4
6.2
5.4
4
4.8
4.8
5.7
5.7
5.2
5.2
4.4
4.4
5.2
5.2
4.4
4.4
MIN
MIN
MIN
MIN
MIN
A or B
B or A
MAX
LEAB or LEBA
B or A
MAX
CLKAB or CLKBA
B or A
MAX
OEAB
B
MAX
OEAB
B
MAX
OEBA
A
MAX
OEBA
A
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
585
16601
18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
Logic Diagram
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
CE
3
1D
C1
CLK
CE
1D
C1
CLK
To 17 Other Channels
586
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
54
B1
FUNCTION TABLE
INPUTS
LEAB
X
H
H
L
L
L
L
L
L
CLKAB
X
X
X
X
X
→→
CLKENAB OEAB
X
H
X
L
X
L
H
L
H
L
L
L
L
L
L
L
L
L
L
H
OUTPUT
B
Z
L
H
B0‡
B0‡
L
H
B 0‡
B0§
A
X
L
H
X
X
L
H
X
X
† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, CLKBA and CLKENBA.
‡ Output level before the indicated steady-state input conditions were
established.
§ Output level before the indicated steady-state input conditions were
established, provided that CLKAB was low before LEAB went low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ABT
MAX
MAX
MAX
36
-32
64
ICC
IOH
IOL
ALVTH ALVCH ALVCHR
3V
3V
3V
5
-32
64
0.04
-24
24
0.04
-12
12
UNIT
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
LEAB or LEBA high
CLKEN before high
CLKEN before low
Data after CLK high
Data after CLK low
A after LEAB or B after LEBA
A after LEAB or B after LEBA
CLKEN after high
CLKEN after low
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
ABT
MIN
MIN
150
150
150
150
2.5
3
4
4
2.5
1
1.8
2.3
2.4
3.8
1
0.6
3.3
3.3
2.1
2.1
1.6
1.1
3.3
3.3
2.1
2.1
1.6
1.1
2.5
2.5
0
0
2
1.4
1.9
0.5
0.5
2
1.7
1.7
0.8
0.8
1.4
1.7
1.7
0.8
0.8
1.4
2
0
0
2.3
0.6
0.5
1.7
0.6
0.6
1.7
0.6
0.6
4
3.9
4.1
4.4
4.9
5
5.2
4.7
4.6
5.5
5.8
6.2
5.4
5.5
5.8
6.2
5.4
3.9
4.6
4.6
4.5
4.6
4.2
4.4
5.3
4.6
4.2
4.4
5.3
4.6
4.1
4.7
4.7
5
5
5.2
5.2
4.4
4.4
5.2
5.2
4.4
4.4
4.4
5.1
5.1
5.4
5.4
5.6
5.6
4.7
4.7
5.6
5.6
4.7
4.7
MIN
CLKAB or CLKBA high or low
Data before CLK high
Data before CLK low
A before LEAB or B before LEBA
A before LEAB or B before LEBA
MIN
, CLK high
, CLK low
ALVTH ALVCH ALVCHR
3V
3V
3V
MAX or MIN
MIN
MIN
MIN
MIN
, CLK high
MIN
, CLK low
MIN
MIN
A or B
B or A
MAX
LEAB or LEBA
B or A
MAX
CLKAB or CLKBA
B or A
MAX
OEAB
B
MAX
OEAB
B
MAX
OEBA
A
MAX
OEBA
A
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
587
16620
16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1OEBA
1OEAB
1A1
48
2OEBA
1
2OEAB
47
2A1
2
24
36
13
1B1
To Seven Other Channels
588
25
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
To Seven Other Channels
2B1
FUNCTION TABLE
INPUTS
OEAB
OEBA
L
L
L
H
OPERATION
B data to A bus
B data to A bus,
A data to B bus
H
L
Isolation
H
H
A data to B bus
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
AC
ACT
UNIT
ICC
MAX
0.08
0.08
mA
IOH
IOL
MAX
MAX
-24
24
-24
24
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OEBA
A
MAX
OEBA
A
MAX
OEAB
B
MAX
OEAB
B
MAX
AC
ACT
6.8
8.5
8.2
6.8
8.2
7.9
9.4
10.5
8.5
10.5
9.1
10.9
9.2
8.3
7.3
9.1
9
11.9
10.6
8.9
10.5
10.8
8
9.6
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
589
16623
16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1OEBA
1OEBA
1OEBA
48
2OEBA
1
2OEBA
47
2OEBA
2
25
24
36
13
1B1
To Seven Other Channels
To Seven Other Channels
FUNCTION TABLE
(each 8-bit section)
INPUTS
OEBA OEAB
L
L
L
H
H
H
L
H
OPERATION
B data to A
B data to A
A data to B
Isolation
A data to B
bus
bus,
bus
bus
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ABT
ACT
UNIT
ICC
MAX
35
0.08
mA
IOH
IOL
MAX
MAX
-32
64
-24
24
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
590
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
OEBA
A
MAX
OEBA
A
MAX
OEAB
B
MAX
OEAB
B
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
ABT
ACT
3.6
4.3
4.9
6
6
5.4
4.9
6
6
5.4
7.7
8.6
9.5
11.1
12
10.7
9.3
10.6
10.4
9.5
2B1
16640
16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Logic Diagram
1OE
1DIR
1A1
48
2OE
1
2DIR
47
2
1B1
2A1
25
24
36
13
To Seven Other Channels
2B1
To Seven Other Channels
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE
DIR
L
L
H
L
H
X
OPERATION
B data to A bus
A data to B bus
Isolation
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ABT
AC
ACT
UNIT
ICC
IOH
PARAMETER
MAX
MAX
32
-32
0.08
-24
0.08
-24
mA
mA
IOL
MAX
64
24
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
OE
A or B
MAX
OE
A or B
MAX
ABT
AC
ACT
4.3
3.9
5.5
6.3
6.3
4.2
7.3
8.6
8
9.9
9.9
9
9.1
10.5
9.8
11.5
12.5
11
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
591
16646
16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
Logic Diagram
1OE
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
56
1
55
54
2
3
One of Eight Channels
1D
C1
1A1
5
52
1B1
1D
C1
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
To Seven Other Channels
29
28
30
31
27
26
One of Eight Channels
1D
C1
2A1
15
42
1D
C1
To Seven Other Channels
592
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2B1
FUNCTION TABLE
INPUTS
CLKAB CLKBA SAB
X
X
X
X
X
X
H or L H or L
X
X
X
H or L
X
X
X
L
X
H or L
X
H
→ →
→
DIR
X
X
X
X
L
L
H
H
→
OE
X
X
H
H
L
L
L
L
SBA
X
X
X
X
L
H
X
X
DATA
A1 THRU A8
Input
Unspecified †
Input
Input disabled
Output
Output
Input
Input
I/O
B1 THRU B8
Unspecified †
Input
Input
Input disabled
Input
Input
Output
Output
OPERATION OR FUNCTION
Store A, B unspecitied †
Store B, A unspecitied †
Store A and B data
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
† The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions
are always enabled; i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ABT
LVTH
3V
AC
ACT
LVCH
3V
ALVCH
3V
AVC
UNIT
ICC
MAX
32
5
0.08
0.08
0.02
0.04
0.04
mA
IOH
IOL
MAX
MAX
-32
64
-32
64
-24
24
-24
24
-24
24
-24
24
-12
12
mA
mA
MAX or MIN
ABT
LVTH
3V
AC
ACT
LVCH
3V
ALVCH
3V
AVC
MIN
MIN
MIN
MIN
MIN
125
4.3
3
3
0
150
3.3
1.2
2
0.5
75
6.5
5
5
1
90
5.5
4
6
1.5
150
3.3
2.9
2.9
0.3
150
3.3
1.4
1.4
0.7
350
1.4
0.8
0.8
0.6
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw Pulse duration
tsu Setup time
th Hold time
INPUT
CLKAB or CLKBA high or low
A or B before CLKAB or CLKBA , data high
A or B before CLKAB or CLKBA , data low
A or B after CLKAB or CLKBA , data high
A or B after CLKAB
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
OUTPUT
or CLKBA
, data low
MIN
CLKAB or CLKBA
B or A
MAX
A or B
B or A
MAX
SAB or SBA
B or A
MAX
OE
A or B
MAX
OE
A or B
MAX
DIR
A or B
MAX
DIR
A or B
MAX
0
0.5
1
1.5
0.3
0.7
0.6
4.9
4.7
3.9
4.2
4.2
3.4
12.1
11.9
9.5
12.2
12.3
10.6
6.7
6.7
5.7
4.5
4.5
3.9
3.3
3.3
2.6
4.6
5
5
5.5
5.7
3.4
4.5
4.5
4.3
4.3
9.7
12.5
13.1
10.5
12.2
11.4
15.6
16.7
11.9
13.5
5.7
7.7
7.7
6.9
6.9
3.9
5.3
5.3
5.1
5.1
2.6
4
4
4
4
5.4
4.5
5.4
5.6
6.7
5.6
5.4
4.4
4.4
5.7
8.9
8.6
10.9
12.2
9.4
10.2
9.9
15.2
13.1
10.8
6.9
6.9
7.2
7.2
7
4.7
4.7
5.1
5.1
5.3
4.2
4.2
4.3
4.3
4.3
5.9
5.2
8.8
10.4
7
5.3
4.3
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
593
16651
16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
Logic Diagram
1OEBA
1OEAB
1CLKBA
1SBA
56
1
55
54
1CLKAB 2
3
1SAB
C1
TG
1A1
1D
5
TG
C1
1D
TG
52
TG
1B1
To Seven Other Channels
2OEBA
2OEAB
2CLKBA
2SBA
29
28
30
31
2CLKAB 27
26
2SAB
C1
TG
2A1
1D
15
TG
C1
1D
TG
42
TG
To Seven Other Channels
594
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2B1
FUNCTION TABLE
L
→
→→ →
H
→
→→ →
INPUTS
OEAB OEBA CLKAB CLKBA SAB
L
L
X
H
L
L
X
H
X
X
L
H
H
X‡
H
L
X
L
X
L
X
L
X
L
X
X
L
X
L
L
L
X
X
X
H
L
H
L
X
H
H
H
L
L
SBA
X
X
X
X
X
X‡
L
H
X
X
H
DATA I/O †
A1-A8
B1-B8
Input
Input
Input
Input
Unspecified‡
Input
Input
Output
Unspecified‡
Input
Output
Input
Output
Input
Output
Input
Output
Input
Input
Output
Output
H
OPERATION OR FUNCTION
Output
Isolation
Store A and B data
Store A, hold B
Store A in both registers
Hold A, store B
Store B in both registers
Real-time B data to A bus
Store B data to A bus
Real-time A data to B bus
Store A data to B bus
Store A data to B bus and
Store B data to A bus
† The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are
always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡ Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ACT
UNIT
ICC
IOH
MAX
MAX
0.08
-24
mA
mA
IOL
MAX
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
INPUT
OUTPUT
CLKAB or CLKBA high or low
A before CLKAB or B before CLKBA
A after CLKAB or B after CLKBA
MAX or MIN
ACT
MIN
MIN
MIN
90
5.5
5.3
MIN
1
11.3
11.9
13.7
13.6
A or B
B or A
MAX
CLKAB or CLKBA
A or B
MAX
SAB or SBA
A or B
MAX
OEBA
A
MAX
OEBA
A
MAX
OEAB
B
MAX
OEAB
B
MAX
17.3
17.8
12.3
13.9
10.6
10.8
11.9
13.5
11.4
11.6
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
595
16652
16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
Logic Diagram
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
56
1
55
54
2
3
One of Eight Channels
1A1
1D
C1
5
52
1D
1B1
C1
To Seven Other Channels
2OEBA
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
29
28
30
31
27
26
One of Eight Channels
2A1
15
42
1D
C1
To Seven Other Channels
596
1D
C1
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2B1
FUNCTION TABLE
H
L
→
→→→
→
→→→
INPUTS
OEAB OEBA CLKAB CLKBA SAB
L
H
H or L H or L
X
H
L
X
H
H or L
X
X
H
X‡
H
L
X
X
H or L
L
L
X
L
L
X
X
X
L
L
X
H or L
X
X
X
L
H
H
X
H
H
H or L
H
H or L H or L
H
DATA I/O†
A1 THRU A8 B1 THRU B8
Input
Input
Input
Input
Unspecified ‡
Input
Output
Input
Unspecified ‡
Input
Output
Input
Output
Input
Input
Output
Output
Input
Input
Output
SBA
X
X
X
X
X
X‡
L
H
X
X
H
Output
OPERATION OR FUNCTION
Output
Isolation
Store A and B data
Store A, hold B
Store A in both registers
Hold A, store B
Store B in both registers
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Store A data to B bus
Stored A data to B bus and
stored B data A bus
† The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs.
Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition of the clock
inputs.
‡ Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered in order to load both registers.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ABT
LVTH
3V
AC
ACT
LVCH
3V
UNIT
ICC
MAX
32
5
0.08
0.08
0.02
mA
IOH
IOL
MAX
MAX
-32
64
-32
64
-24
24
-24
24
-24
24
mA
mA
MAX or MIN
ABT
LVTH
3V
AC
ACT
LVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
125
4.3
3
3
0
0
150
3.3
1.2
2
0.5
0.5
95
5
4.5
4.5
0
0
90
5.5
4.5
4.5
1
1
150
3.3
3
3
0.2
0.2
4.9
4.7
3.9
4.6
4.2
4.2
3.4
3.4
12.2
12.3
9.9
10.2
12.3
12.3
10.5
11.6
6.4
6.4
6.3
6.3
5
5
5
5.3
4.9
4
4.2
4.6
5.9
5.2
4.5
4.5
4.3
4.3
5.6
5.4
4.2
4.2
5.5
5.5
13.8
13.8
10.7
13.2
8.8
8.7
10.5
13
8
7.8
16
16.9
11.7
13.4
9.5
9.2
10.8
12.4
10.5
9.9
7.4
7.4
6.3
6.3
6.2
6.2
6.3
6.3
6.2
6.2
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
INPUT
OUTPUT
CLKAB or CLKBA high or low
A before CLKAB or B before CLKBA , high
A before CLKAB or B before CLKBA , low
A after CLKAB or B after CLKBA , high
A after CLKAB or B after CLKBA , low
CLKAB or CLKBA
A or B
MAX
A or B
B or A
MAX
SAB or SBA
A or B
MAX
OEBA
A
MAX
OEBA
A
MAX
OEAB
B
MAX
OEAB
B
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
597
16657
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
Logic Diagram
T/R
OE
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
ODD/EVEN
PARITY
ERR
598
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLE
(each 8-bit section)
NUMBER OF A OR B
INPUTS THAT ARE HIGH
0, 2, 4, 6, 8
1, 3, 5, 7
Don't care
INPUTS
OE T/R ODD/EVEN
H
H
L
H
L
L
H
L
L
H
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
L
L
H
L
L
L
L
L
L
L
L
X
X
H
INPUT/OUTPUT
PARITY
H
L
H
L
H
L
L
H
H
L
H
L
Z
OUTPUTS
ERR OUTPUT MODE
Transmit
Z
Z
Transmit
H
Receive
Receive
L
L
Receive
H
Receive
Z
Transmit
Z
Transmit
L
Receive
H
Receive
H
Receive
L
Receive
Z
Z
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ABT
ACT
UNIT
ICC
IOH
PARAMETER
MAX
MAX
36
-32
0.08
-24
mA
mA
IOL
MAX
64
24
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
A or B
OUTPUT
MAX or MIN
B or A
MAX
A or B
PARITY
MAX
ODD / EVEN
PARITY, ERR
MAX
B
ERR
MAX
PARITY
ERR
MAX
OE
A or B
MAX
OE
A or B
MAX
OE
PARITY, ERR
MAX
OE
PARITY, ERR
MAX
ABT
ACT
4.1
4.3
6.7
6.1
10.7
10.6
14.3
14.3
6.7
6.1
6.7
6.1
6.7
13.7
14.1
14.6
14.7
13.8
6.1
5.6
6
5.4
4.3
14.2
11.3
13
11.2
10.5
5.6
6
5.4
4.3
11.3
13
11.2
10.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
599
Logic Diagram
16721
20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
OE
1
56
CLK
29
CLKEN
CE
C1
D1
55
1D
To 19 Other Channels
FUNCTION TABLE
(each filp-flop)
INPUTS
CLKEN
H
L
L
L
X
CLK
X
→→
OE
L
L
L
L
H
L
X
D
H
H
L
X
X
OUTPUT
Q
QO
H
L
QO
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
600
fmax : MHz
INPUT
OUTPUT
CLK high or low
Data before CLK
CLKEN before CLK
Data after CLK
CLKEN after CLK
MAX or MIN
ALVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
150
3.3
3.1
2.7
0
0
4.3
4.3
4.8
4.8
4.4
4.4
CLK
Q
MAX
OE
Q
MAX
OE
Q
MAX
other : ns
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2
Q1
Logic Diagram
16722
22-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
OE
1
64
CLK
33
CLKEN
D1
63
CE
C1
1D
2
Q1
To 21 Other Channels
FUNCTION TABLE
(each filp-flop)
INPUTS
OE
L
L
L
L
H
CLKEN
H
L
L
L
X
CLK
X
↑
↑
L or H
X
D
X
H
L
X
X
OUTPUT
Q
QO
H
L
QO
Z
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
AVC
3V
UNIT
ICC
MAX
0.04
mA
IOH
IOL
MAX
MAX
-12
12
mA
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
INPUT
OUTPUT
CLK high or low
Data before CLK
CLKEN before CLK
Data after CLK
CLKEN after CLK
MAX or MIN
AVC
3V
MIN
MIN
MIN
MIN
MIN
MIN
150
2.8
2.5
1.4
0
1.2
2.6
2.6
4.3
4.3
3.4
3.4
CLK
Q
MAX
OE
Q
MAX
OE
Q
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
601
Logic Diagram
16820
10-BIT EDGE-TRIGGERD D-TYPE FLIP-FLOPS
WITH DUAL OUTPUTS
1OE
1
28
2OE
CLK
2
56
C1
D1
55
1D
To Nine Other Channels
FUNCTION TABLE
(each fllp-flop)
→→
INPUTS
OEn† CLK
D
H
L
L
L
X
L
L
X
H
X
OUTPUT
Qn†
H
L
Q0
Z
† n = 1, 2
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
602
fmax : MHz
INPUT
OUTPUT
CLK high or low
Data before CLK
Data after CLK
MAX or MIN
ALVCH
3V
MIN
MIN
MIN
MIN
150
3.3
1.4
1
4.8
4.8
5
5
4.5
4.5
CLK
Q
MAX
OE
Q
MAX
OE
Q
MAX
other : ns
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1Q1
3
1Q2
Logic Diagram
16821
1
20-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
1OE
1CLK
56
One of Ten
Channels
C1
55
1D1
2
1D
1Q1
To Nine Other Channels
2OE
2CLK
28
29
One of Ten
Channels
FUNCTION TABLE
C1
(each fllp-flop)
→→
INPUTS
OE CLK
D
H
L
L
L
X
L
L
H
X
X
42
2D1
OUTPUT
Q
H
L
Q0
Z
1D
15
2Q1
To Nine Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
ALVTH
3V
ACT
ALVCH
3V
UNIT
MAX
MAX
MAX
89
-32
64
5
-32
64
0.08
-24
24
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
INPUT
OUTPUT
CLK high or low
Data before CLK , low
Data before CLK , high
Data after CLK , high
Data after CLK , low
MAX or MIN
ABT
ALVTH
3V
MIN
MIN
150
3.3
MIN
MIN
MIN
MIN
CLK
Q
MAX
OE
Q
MAX
OE
Q
MAX
1.8
1.8
1.3
1.3
6.1
5.4
5.7
5.6
6.5
7.1
ACT
ALVCH
3V
150
1.5
70
7
150
3.3
1.5
1.5
1
1
3.5
3.5
4.1
3.6
4.8
4.8
7.5
7.5
0.5
0.5
13.4
14
11.9
14.7
10.7
10
3.4
3.4
0
0
4.5
4.5
5.1
5.1
4.6
4.6
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
603
Logic Diagram
16823
18-BIT EDGE-TRIGGERD
D-TYPE FLIP-FLOPS
WITH DUAL OUTPUTS
1OE
1CLR
1CLKEN
2
1
55
CE
R
1CLK
1D1
56
C1
54
3
1Q1
1D
To Eight Other Channels
2OE
2CLR
2CLKEN
27
28
30
CE
R
FUNCTION TABLE
2CLK
(each 9-bit filp-flop)
CLR
L
H
H
H
H
X
CLK
X
→→
OE
L
L
L
L
L
H
INPUTS
CLKEN
X
L
L
L
H
X
L
X
X
2D1
OUTPUT
Q
L
H
L
Q0
Q0
Z
D
X
H
L
X
X
X
29
C1
42
1D
To Eight Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ABT
ABTH
AC
ACT
ALVCH
3V
UNIT
ICC
MAX
80
80
0.08
0.08
0.04
mA
IOH
IOL
MAX
MAX
-32
64
-32
64
-24
24
-24
24
-24
24
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
CLR low
CLK high or low
CLR inactive
Data high before CLK
Data low before CLK
CLKEN low before CLK
Data high after CLK
Data low after CLK
CLKEN low after CLK
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
604
fmax : MHz
MAX or MIN
ABT
ABTH
AC
ACT
ALVCH
3V
MIN
MIN
MIN
MIN
150
3.3
3.3
1.6
150
3.3
3.3
1.6
115
3.3
4.4
0.6
90
3.3
5.5
0.5
150
3.3
3.3
0.8
MIN
MIN
MIN
MIN
MIN
MIN
1.7
1.7
2.8
1.2
1.2
0.6
6.8
6
6.1
4.9
5.5
6.1
8.7
1.7
1.7
2.8
1.2
1.2
0.6
6.8
6
6.7
4.9
5.5
6.1
8.7
5
5
4.2
1.3
1.3
1.4
12
12.7
11
9.7
11.8
9.3
8.6
7
7
3.5
0.5
0.5
2.5
12.1
12.9
12.5
10.7
12.8
10.3
9.4
1
1.3
1.5
0.8
0.5
0.4
4.5
4.5
4.6
4.6
4.8
4.8
4.5
4.5
CLK
Q
MAX
CLR
Q
MAX
OE
Q
MAX
OE
Q
MAX
other : ns
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
15
2Q1
Logic Diagram
16825
18-BIT BUS BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1OE1
1OE2
1A1
1
56
55
2
1Y1
To Eight Other Channels
2OE1
2OE2
2A1
28
29
16
41
2Y1
To Eight Other Channels
FUNCTION TABLE
(each 9-bit section)
OE1
L
L
H
X
INPUTS
OE2
A
L
L
L
H
X
X
X
H
OUTPUT
Y
L
H
Z
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
ACT
ALVCH
3V
UNIT
MAX
MAX
MAX
32
-32
64
0.08
-24
24
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
ABT
ACT
ALVCH
3V
3.9
4.4
6.1
6
6.9
6.6
10.5
10.3
11
13.2
11.5
10.6
3.4
3.4
4.7
4.7
4.5
4.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
605
Logic Diagram
16827
1
20-BIT BUS BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1OE1
1OE2
1A1
56
55
2
1Y1
To Nine Other Channels
28
2OE1
2OE2
2A1
29
42
15
2Y1
To Nine Other Channels
FUNCTION TABLE
(each 10-bit section)
OE1
L
L
H
X
INPUTS
OE2
A
L
L
L
H
X
X
X
H
OUTPUT
Y
L
H
Z
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
ALVTH
3V
ACT
ALVCH
3V
AVC
UNIT
MAX
MAX
MAX
32
-32
64
6
-32
64
0.08
-24
24
0.04
-24
24
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
606
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
ABT
ALVTH
3V
ACT
ALVCH
3V
AVC
3.4
4.2
5.6
5.5
6.6
6.1
3
2.8
3.9
3.4
5.8
4.6
11
10.8
11.7
14
12.4
11.5
3.4
3.4
4.7
4.7
4.5
4.5
1.7
1.7
5.1
5.1
4.7
4.7
16831
1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
Logic Diagram
OE1
OE2
20
5
4
CLK
19
8
D
3Y1
Q
1
SEL
2Y1
CLK
2
A1
1Y1
21
4Y1
22
To Eight Other Channels
FUNCTION TABLE
INPUTS
SEL CLK
X
X
H
X
H
X
L
L
→→
OE
H
L
L
L
L
A
X
L
H
L
H
OUTPUT
Y
Z
L
H
L
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALVCH
3V
UNIT
ICC
IOH
MAX
MAX
0.04
-24
mA
mA
IOL
MAX
24
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
INPUT
OUTPUT
CLK high or low
A data before CLK
A data after CLK
MAX or MIN
ALVCH
3V
MIN
MIN
MIN
MIN
150
3.3
1.6
1.1
3.6
3.6
3.9
3.9
4.4
4.4
4.3
4.3
4.5
4.5
A
Y
MAX
CLK
Y
MAX
SEL
Y
MAX
OE
Y
MAX
OE
Y
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
607
16832
1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
Logic Diagram
OE1
OE2
16
5
4
CLK
15
7
D
18
To Six Other Channels
608
3Y1
Q
1
SEL
2Y1
CLK
2
A1
1Y1
17
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4Y1
FUNCTION TABLE
INPUTS
SEL CLK
X
X
H
X
H
X
L
L
→→
OE
H
L
L
L
L
A
X
L
H
L
H
OUTPUT
Y
Z
L
H
L
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALVCH
3V
UNIT
ICC
MAX
0.04
mA
IOH
IOL
MAX
MAX
-24
24
mA
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
INPUT
OUTPUT
CLK high or low
A data before CLK
A data after CLK
MAX or MIN
ALVCH
3V
MIN
MIN
MIN
150
3.3
1.6
MIN
1.1
3.6
3.6
3.9
3.9
A
Y
MAX
CLK
Y
MAX
SEL
Y
MAX
OE
Y
MAX
OE
Y
MAX
4.4
4.4
4.3
4.3
4.5
4.5
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
609
16833
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
Logic Diagram
8
1A1–1A8
8x
8
1B1–1B8
EN
8x
8
EN
1OEB
1OEA
1
54
56
8
1PARITY
8
1 MUX
1
2k
9
1
P
1
G1
1CLK
1CLR
1D
C1
R
2
55
8
2A1–2A8
8x
3
8
1ERR
2B1–2B8
EN
8x
8
EN
2OEB
2OEA
28
31
29
8
2PARITY
8
1 MUX
1
1
9
2k
P
1
G1
2CLK
2CLR
610
27
30
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1D
C1
R
26
2ERR
FUNCTION TABLE
INPUTS
OEB
OEA
CLR
CLK
OUTPUT AND I/O
Ai
Σ OF H
Odd
Even
L
H
X
X
H
L
H
↑
NA
X
X
H
H
L
H
L
H
H
X
No ↑
No ↑
↑
↑
X
X
X
Odd
Even
Odd
Even
L
L
X
X
Bi†
Σ OF H
NA
Odd
Even
X
NA
A
L
H
B
NA
NA
X
NA
NA
Z
Z
Z
A
H
L
X
NA
FUNCTION
B PARITY ERR‡
A
NA
NA
H
L
H
NC
H
H
L
NA
A data to B bus and
generate parity
B data to A bus and
check parity
Check error flag register
Isolation§
A data to B bus and
generate inverted parity
NA = not applicable, NC = no change, X = don’t care
‡ Output states shown assume ERR was previousiy high.
† Summation of high-level inputs includes PARITY along with Bi inputs. § In this mode, ERR (when clocked) shows inverted panrity of the A bus.
ERROE-FLAG FUNCTION TABLE
INPUTS
CLR
H
H
H
L
CLK
↑
↑
↑
X
INTERNAL
OUTPUT
TO DEVICE PRE-STATE
POINT P
ERRn-1†
H
H
X
L
L
X
X
X
OUTPUT
ERR
FUNCTION
H
L
L
H
Sample
Clear
† State of ERR before any changes at CLR, CLK, or point P
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
ACT
UNIT
MAX
MAX
MAX
36
-32
64
0.08
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
CLK high or low
CLR low
A data before CLK
, A port
tsu Setup time
A data before CLK
A data before CLK
, CLR
, OEA
th Hold time
tPLH
tPHL
tPLH
A data after CLK
tw Pulse duration
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
MAX or MIN
ABT
ACT
MIN
3
-
4
4
MIN
4..5
1
5
1.5
-
, A port or OEA
MIN
A or B
B or A
MAX
A
PARITY
MAX
OEB or OEA
A or B
MAX
OEB or OEA
A or B
MAX
CLK, CLR
CLK
ERR
MAX
OEB
PARITY
MAX
OEA
PARITY
MAX
OEB
PARITY
MAX
OEB
PARITY
MAX
OEA
PARITY
MAX
OEA
PARITY
MAX
0
0
4.1
4.3
6.7
10.4
10.7
13.5
6.1
5.6
6
5.4
4.3
4.6
3.9
13.8
11.2
13
10.8
10.1
15.8
11.6
6.7
6.1
6.7
6.1
5.7
6.5
4.7
4.1
5.7
6.5
4.7
4.1
13.2
13.6
9.5
10.7
10.2
9.7
-
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
611
Logic Diagram
16834
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
OE
CLK
LE
A1
27
30
28
54
1D
C1
CLK
To 17 Other Channels
FUNCTION TABLE
INPUTS
CLK
LE
X
X
L
X
L
X
H
H
H
H
L
H
→→
OE
H
L
L
L
L
L
L
OUTPUT
Y
Z
L
H
L
H
Y0†
Y0‡
A
X
L
H
L
H
X
X
† Output level before the indicated steady-state
input conditions were established, provided that
CLK is high before LE goes high
‡ Output level before the indicated steady-state
input conditions were established
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALVC
3V
AVC
3V
UNIT
ICC
IOH
MAX
MAX
0.04
-24
0.04
-12
mA
mA
IOL
MAX
24
12
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
612
fmax : MHz
LE low
CLK high or low
Data before CLK
Data before LE , CLK high
Data before LE , CLK low
A data after CLK
Data after LE , CLK high
Data after LE , CLK low
MAX or MIN
ALVC
3V
AVC
3V
MIN
MIN
MIN
150
3.3
3.3
150
3.3
3.3
MIN
1.7
1.9
1.5
0.7
1
1
0.7
0.9
0.9
0.9
1.4
1.3
3.6
3.6
4.9
4.9
4.6
4.6
5
5
4.5
4.5
2.5
2.5
4
4
3.1
3.1
6.2
6.2
5.3
5.3
MIN
MIN
MIN
A
Y
MAX
LE
Y
MAX
CLK
Y
MAX
OE
Y
MAX
OE
Y
MAX
other : ns
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
3
Y1
Logic Diagram
16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
OE
CLK
LE
A1
27
30
28
54
1D
C1
3
Y1
CLK
To 17 Other Channels
FUNCTION TABLE
INPUTS
LE
CLK
X
X
X
H
X
H
L
L
L
H
L
L
→→
OE
H
L
L
L
L
L
L
A
X
L
H
L
H
X
X
OUTPUT
Y
Z
L
H
L
H
Y0†
Y0‡
† Output level before the indicated steady-state
input conditions were established, provided that
CLK was high before LE went low.
‡ Output level before the indicated steady-state
input conditions were established
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LVTH
3V
ALVC
3V
ALVCH
3V
AVC
3V
UNIT
ICC
IOH
MAX
MAX
5
-32
0.04
-24
0.04
-24
0.04
-12
mA
mA
IOL
MAX
64
24
24
12
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
LE low
CLK high or low
Data before CLK
Data before LE , CLK high
Data before LE , CLK low
A data after CLK
Data after LE , CLK high
Data after LE , CLK low
MAX or MIN
LVTH
3V
ALVC
3V
ALVCH
3V
AVC
3V
MIN
MIN
MIN
150
3.3
3.3
150
3.3
3.3
150
3.3
3.3
150
3.3
3.3
MIN
MIN
MIN
2.1
2.3
1.5
1.7
1.5
1
1.7
1.5
1
0.7
0.8
0.5
MIN
MIN
MIN
1
0.8
0.8
0.7
1.4
1.4
0.7
1.4
1.4
1.3
1.6
1.4
3.7
3.7
5.1
5.1
5.1
5.1
4.6
4.6
5.8
5.8
3.6
3.6
4.2
4.2
4.5
4.5
4.6
4.6
3.9
3.9
3.6
3.6
4.2
4.2
4.5
4.5
4.6
4.6
3.9
3.9
2.5
2.5
3.8
3.8
3.1
3.1
6.2
6.2
5.3
5.3
A
Y
MAX
LE
Y
MAX
CLK
Y
MAX
OE
Y
MAX
OE
Y
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
613
16841
20-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
Logic Diagram
1OE
1LE
1
2OE
56
2LE
C1
1D1
55
2
1D
28
29
C1
1Q1
2D1
42
1D
To Nine Other Channels
To Nine Other Channels
FUNCTION TABLE
(each 10-bit latch)
OE
L
L
L
H
INPUTS
LE
D
H
H
L
H
X
L
X
X
OUTPUT
Q
H
L
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
ACT
ALVCH
3V
UNIT
MAX
MAX
MAX
89
-32
64
0.08
-24
24
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
614
INPUT
OUTPUT
LE high or low
Data before LE
Data after LE , high
Data after LE , low
MAX or MIN
ABT
ACT
ALVCH
3V
MIN
MIN
MIN
MIN
4
1
2
2
4
1.5
3
4.5
3.3
1.1
1.1
1.1
5
5.1
5
5
5.7
5.6
6.5
7.1
11.8
12.2
12.7
12.7
11.3
13.7
10.2
9.6
3.9
3.9
4.3
4.3
4.9
4.9
4.1
4.1
D
Q
MAX
LE
Q
MAX
OE
Q
MAX
OE
Q
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
15
2Q1
16843
18-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
Logic Diagram
1OE 2
2OE 27
1PRE 55
2PRE 30
1CLR 1
2CLR 28
1LE 56
2LE 29
S2
C1
1D
R
1D1 54
3
1Q1
To Eight Other Channels
2D1 42
S2
C1
1D
R
15
2Q1
To Eight Other Channels
FUNCTION TABLE
(each 9-bit latch)
INPUTS
PRE
L
H
H
H
H
X
CLR
X
L
H
H
H
X
OE
L
L
L
L
L
H
LE
X
X
H
H
L
X
OUTPUT
Q
D
X
X
L
H
X
X
H
L
L
H
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ABT
UNIT
MAX
MAX
MAX
85
-32
64
mA
mA
mA
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
OUTPUT
ABT
MIN
3.3
3.3
0.9
0.6
1.7
1.8
4.8
4.8
5.9
5.3
6.1
5
5.4
6
5.4
5.8
6.3
5.2
3.3
CLR low
PRE low
LE high
Data before LE
Data before LE
Data after LE
Data after LE
MAX or MIN
, high
, low
, high
, low
MIN
MIN
D
Q
MAX
LE
Q
MAX
PRE
Q
MAX
CLR
Q
MAX
OE
Q
MAX
OE
Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
615
16853
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
Logic Diagram
8
A1–A8
8x
8
B1–B8
EN
8x
8
EN
OEB
OEA
PARITY
8
8
MUX
1
1
2k
9
1
P
1
G1
ERR
LE
CLR
FUNCTION TABLE
INPUTS
OUTPUT AND I/Os
L
H
X
X
Ai
Σ OF H
Odd
Even
H
L
H
L
NA
H
X
L
X
H
H
H
L
H
L
X
X
H
H
H
H
L
L
L
L
X
X
NA
X
X
X
L Odd
H Even
Odd
Even
OEB
OEA
LE
CLR
Bi†
Σ OF H
A
B PARITY ERR‡
NA
A
L
H
B
NA
NA
X
X
NA
NA
NA
NA
X
Z
Z
Z
NA
NA
A
H
L
NA
Odd
Even
X
X
NA
H
L
NC
H
NC
H
H
L
NA
NA = not applicable, NC = no change, X = don’t care
† Summation of high-level inputs includes PARITY along with Bi inputs.
‡ Output states shown assume ERR was previousiy high.
§ In this mode, ERR (when clocked) shows inverted panrity of the A bus.
ERROR-FLAG FUNCTION TABLE
INPUTS
CLR
LE
L
L
INTERNAL
TO DEVICE
POINT P
H
L
L
H
L
H
L
X
H
X
H
H
X
OUTPUT
ERRn-1†
X
X
L
H
X
L
H
OUTPUT
ERR
L
H
L
L
H
H
L
H
FUNCTION
Pass
Sample
Clear
Store
† State of ERR before changes at CLR, LE, or point P
616
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION
A data to B bus and
generate parity
B data to A bus and
check parity
Store error flag
Clear error flag register
Isolation§
(parity check)
A data to B bus and
generate inverted parity
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ABT
UNIT
ICC
MAX
40
mA
IOH
IOL
MAX
MAX
-32
64
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw Pulse duration
tsu Setup time
MAX or MIN
ABT
LE high or low
INPUT
OUTPUT
MIN
8.5
CLR low
A, B and PARITY before LE
MIN
10
MIN
0
0
4
CLR before LE
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
UNIT: ns
A, B and PARITY after LE
CLR after LE
A or B
B or A
MAX
A or OE
PARITY
MAX
CLR
ERR
MAX
OE
A or B
MAX
OE
A or B
MAX
OE
PARITY
MAX
OE
PARITY
MAX
LE
ERR
MAX
A, B or PARITY
ERR
MAX
0
4.1
4.3
7.1
7.2
5.7
5.6
6
5.4
4.3
5.7
6.5
4.7
4.1
4.8
4.9
7.2
7.4
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
617
16861
20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1OEBA
1OEAB
1A1
56
2OEBA
1
2OEAB
55
2
1B1
2A1
To Nine Other Channels
(each 10-bit section)
L
L
L
H
H
H
L
H
OPERATION
Latch A and B
(A = B)
A to B
B to A
Isolation
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ACT
UNIT
MAX
MAX
MAX
0.08
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
618
28
42
15
To Nine Other Channels
FUNCTION TABLE
INPUTS
OEAB OEBA
29
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
OEBA or OEAB
A or B
MAX
OEBA or OEAB
A or B
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
ACT
10.4
11.1
10
12.7
10.7
10
2B1
16863
18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1OEBA
1OEAB
1A1
56
2OEBA
1
2OEAB
55
2
1B1
2A1
29
28
42
To Nine Other Channels
15
2B1
To Nine Other Channels
FUNCTION TABLE
(each 9-bit section)
INPUTS
OEAB OEBA
H
L
H
L
H
H
OPERATION
B data to A bus
A data to B bus
Isolation
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
ACT
ALVCH
3V
UNIT
MAX
MAX
MAX
32
-32
64
0.08
-24
24
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
OEBA or OEAB
A or B
MAX
OEBA or OEAB
A or B
MAX
ABT
ACT
ALVCH
3V
3.5
3.9
5.4
4.8
6
5
11.1
11.8
10.6
13.6
11.6
11
3.4
3.4
4.7
4.7
4.2
4.2
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
619
16901
18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS
Block Diagram
2
LEAB
1, 32
1CLKENAB
2CLKENAB
2
3
CLKAB
30
OEAB
35
1A1–1A8
A-Port
Parity
Generate
and
Check
B Data
61
1ERRB
2A1–2A8
28
2APAR
18
36
2ERRB
18-Bit
Storage
18
5
1APAR
QB
1B1–1B8
18
60
QA
B-Port
Parity
Generate
and
Check
A Data
18
18-Bit
Storage
4
2BPAR
2ERRA
31
62
64, 33
63
FUNCTION TABLE
INPUTS
CLKENAB OEAB LEAB CLKAB
X
X
X
H
L
X
H
X
L
X
H
X
L
L
X
H
L
L
L
↑
L
L
L
↑
L
L
L
L
L
H
L
L
A
X
L
H
X
L
H
X
X
Z
L
H
B0‡
L
H
B0‡
B0§
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
H
1CLKENBA
2CLKENBA
LEBA
OPERATION OR FUNCTION
Parity is checked on port A and is generated on port B.
Parity is checked on port B and is generated on port A.
Parity is checked on port B and port A.
Parity is generated on port A and B if device is in FF mode.
QA data to B, QB data to A
Parity funcions are
disabled; device acts as a
QB data to A
standard 18-bit registered
QA data to B
transceiver.
Isolation
PARITY FUNCTION TABLE
SEL OEBA OEAB ODD/EVEN
CLKBA
PARITY-ENABLE FUNCTION TABLE
INPUTS
SEL OEBA OEAB
L
L
H
H
L
L
H
L
H
L
L
L
L
L
H
L
H
H
L
H
H
H
H
H
OUTPUT
B
‡ Output level before the indicated steady-state input conditions
were established
§ Output level before the indicated steady-state input conditions
were established, provided that CLKAB was low before LEAB
went low
INPUTS
Σ OF INPUTS
A1-A8 = H
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
N/A
N/A
N/A
N/A
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
N/A
N/A
N/A
N/A
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
N/A
N/A
OUTPUTS
Σ OF INPUTS
APAR BPAR
B1-B8 = H
N/A
N/A
L
N/A
N/A
L
N/A
N/A
H
N/A
N/A
H
N/A
0, 2, 4, 6, 8
L
1, 3, 5, 7
N/A
L
0, 2, 4, 6, 8
N/A
H
1, 3, 5, 7
N/A
H
N/A
N/A
L
N/A
N/A
L
N/A
N/A
H
N/A
N/A
H
0, 2, 4, 6, 8
N/A
L
1, 3, 5, 7
N/A
L
0, 2, 4, 6, 8
N/A
H
1, 3, 5, 7
N/A
H
0, 2, 4, 6, 8
L
L
1, 3, 5, 7
L
L
0, 2, 4, 6, 8
H
H
1, 3, 5, 7
H
H
0, 2, 4, 6, 8
L
L
1, 3, 5, 7
L
L
0, 2, 4, 6, 8
H
H
H
1, 3, 5, 7
H
N/A
N/A
N/A
N/A
N/A
N/A
† Parity output is set to the level so that the specific bus side is set to even parity.
‡ Parity output is set to the level so that the specific bus side is set to odd parity.
620
1ERRA
2B1–2B8
37
29
2
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
1BPAR
34
ODD/EVEN
SEL
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
OEBA
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
APAR ERRA BPAR ERRB
N/A
N/A
N/A
N/A
L
H
L
H
N/A
N/A
N/A
N/A
H
L
H
L
Z
Z
Z
Z
Z
Z
Z
Z
PE†
PO‡
H
L
L
H
Z
Z
Z
Z
L
H
H
L
Z
Z
Z
Z
H
L
L
H
L
H
H
L
Z
Z
L
H
L
H
N/A
N/A
N/A
N/A
H
L
H
L
N/A
N/A
N/A
N/A
Z
Z
Z
Z
Z
Z
Z
Z
PE†
PO‡
Z
Z
Z
Z
H
L
L
H
Z
Z
Z
Z
L
H
H
L
H
L
L
H
L
H
H
L
Z
Z
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LVCH
3V
ALVCH
3V
ICC
MAX
0.02
0.04
mA
IOH
IOL
MAX
MAX
-24
24
-24
24
mA
mA
PARAMETER
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
CLK
LE high
A, APAR or B, BPAR before CLK
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
CLKEN before CLK
A, APAR or B, BPAR before LE
A, APAR or B, BPAR after CLK
CLKEN after CLK
A, APAR or B, BPAR after LE
MAX or MIN
LVCH
3V
ALVCH
3V
MIN
MIN
MIN
125
3
3
125
3
3
MIN
MIN
2.5
2.5
1.7
1.7
MIN
MIN
2
1.3
1.2
0.5
MIN
1.5
0.7
MIN
1.7
5.4
0.9
4.4
5.4
7.7
7.7
5.7
5.7
4.4
6.7
6.7
4.7
4.7
8.5
8.5
7.8
7.8
7.5
7.5
7.5
6.8
6.8
6.5
7.5
6.1
6.1
6.1
6.1
6.5
5.1
5.1
5.1
5.1
6.6
6.6
8.7
8.7
8.9
5.6
5.6
7.7
7.7
7.9
8.9
5.8
5.8
6.3
6.3
8.4
8.4
8.5
8.5
6.3
6.3
5.9
5.9
5.9
5.9
6.7
6.7
6.5
6.5
5.9
5.9
7.9
4.8
4.8
5.3
5.3
7.4
7.4
7.5
7.5
5.3
5.3
4.9
4.9
4.9
4.9
5.7
5.7
5.5
5.5
4.9
4.9
A or B
B or A
MAX
A or B
BPAR or APAR
MAX
APAR or BPAR
BPAR or APAR
MAX
APAR or BPAR
ERRA or ERRB
MAX
ODD / EVEN
ERRA or ERRB
MAX
ODD / EVEN
BPAR or APAR
MAX
SEL
BPAR or APAR
MAX
CLKAB or CLKBA
A or B
MAX
CLKAB or CLKBA
BPAR or APAR
parity feedthrough
MAX
CLKAB or CLKBA
BPAR or APAR
parity generated
MAX
CLKAB or CLKBA
ERRA or ERRB
MAX
LEAB or LEBA
A or B
MAX
LEAB or LEBA
BPAR or APAR
parity feedthrough
MAX
LEAB or LEBA
BPAR or APAR
parity generated
MAX
LEAB or LEBA
ERRA or ERRB
MAX
OEAB or OEBA
B, BPAR
or A, APAR
MAX
OEAB or OEBA
B, BPAR
or A, APAR
MAX
OEAB or OEBA
ERRA or ERRB
MAX
OEAB or OEBA
ERRA or ERRB
MAX
SEL
ERRA or ERRB
MAX
SEL
ERRA or ERRB
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
621
16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
Logic Diagram
1
OE
MODE
CLK
33
13
1A–12A,
APAR
(1A–12A)
12
13
1Y2–12Y2
13
CLKEN
1Y1–12Y1
12
56
(1A–8A)
8
29
13
12
(1A–11A/YERREN, APAR)
D
11A/YERREN
Q
Flip-Flop
11
5
(9A–12A, APAR)
APAR
5
APAR
Flip-Flop
D
Q
D
Q
10
(1A–10A)
Parity
Check
D
XOR
36
Q
YERR
30
PARI/O
PAROE
28
FUNCTION TABLE
INPUTS
OE MODE CLKEN CLK
L
L
L
L
L
L
H
L
L
L
H
L
X
X
L
H
X
X
H
L
H
X
X
X
→→→→
A
H
L
H
L
H
L
X
OUTPUTS
1Yn† – 8Yn† 9Yn† – 12Yn†
H
H
L
L
H
Y0
L
Y0
H
H
L
L
Z
Z
†n =1, 2
PARI/O FUNCTION†
PAROE
L
L
L
L
H
INPUTS
Σ OF INPUTS
1A – 10A = H
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
X
APAR
OUTPUT
PARI/O
L
L
H
H
X
L
H
H
L
Z
PARITY FUNCTION
INPUTS
OE PAROE‡ 11A/YERREN§ PARI/O
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
X
H
L
L
L
L
H
H
H
H
X
X
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
0, 2, 4, 6, 8, 10
1, 3, 5, 7, 9
X
X
‡ When used as a single device, PAROE must be tied high.
§ Valid after appropriate number of clock pulses have set internal register.
† This table applies to the first device of a cascaded pair
of ALVCH16903 devices.
622
H
H
H
H
H
H
H
H
X
X
Σ OF INPUTS
APAR
1A – 10A = H
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
L
L
H
H
L
L
H
H
X
X
OUTPUT
YERR
H
L
L
H
L
H
H
L
H
H
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALVCH
3V
ICC
MAX
0.04
mA
IOH
IOL
MAX
MAX
-24
24
mA
mA
PARAMETER
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
MAX or MIN
MIN
125
MIN
MIN
3
1.45
1A-10A before CLK , buffer mode
APAR before CLK , resister mode
MIN
MIN
4.4
1.3
APAR before CLK , buffer mode
PARI/O before CLK , both mode
MIN
MIN
3.1
1.7
11A/YERREN before CLK
MIN
1.6
CLKEN before CLK , resister mode
1A-12A after CLK , resister mode
MIN
MIN
2.2
0.55
1A-10A after CLK , buffer mode
APAR after CLK , resister mode
APAR after CLK , buffer mode
PARI/O before CLK , resister mode
PARI/O before CLK , buffer mode
MIN
MIN
MIN
MIN
MIN
0.25
0.7
0.25
0.4
0.5
11A/YERREN after CLK , buffer mode
CLKEN after CLK , resister mode
MIN
MIN
0.4
0.4
3.8
3.8
CLK
1A-12A before CLK
tPLH
Buffer mode
tPHL
, resister mode
, buffer mode
A
Y
MAX
CLK
YERR
MAX
CLK
PARI / O
MAX
MODE
Y
MAX
CLK
Y
MAX
OE
Y
MAX
Both mode
PAROE
PARI / O
MAX
Both mode
OE
Y
MAX
Both mode
PAROE
PARI / O
MAX
OE
YERR
MAX
tPLH
Both mode
tPHL
tPLH
Both mode
tPHL
tPLH
Both mode
tPHL
tPLH
Resister mode
t
PHL
tPZH
Both mode
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
tPLH
tPHL
UNIT
Both mode
fmax : MHz
ALVCH
3V
4.4
4.4
6.6
6.6
4.9
4.9
4.8
4.6
5.4
5.4
4.8
4.8
5
5
3.8
3.8
4
4.2
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
623
16952
16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1CLKENAB
1CLKAB
1OEBA
1A1
3
54
2
55
56
1
5
One of Eight
Channels
C1
CE
1D
52
1CLKENBA
1CLKBA
1OEAB
1B1
C1
CE
1D
To Seven Other Channels
2CLKENAB
2CLKAB
2OEBA
2A1
26
31
27
30
29
28
15
One of Eight
Channels
C1
CE
1D
C1
CE
1D
To Seven Other Channels
624
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
42
2CLKENBA
2CLKBA
2OEAB
2B1
FUNCTION TABLE
INPUTS
→→
CLKENAB CLKAB
H
X
X
L
L
L
H
X
OEAB
L
L
L
L
H
A
X
X
L
H
X
OUTPUT
B
B0‡
B0‡
L
H
Z
† A-to-B data flow is shown; B-to-A data flow is similar
but uses CLKENBA, CLKBA, and OEBA.
‡ Level of B before the indicated steady-state input
conditions were established.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
AC
LVTH
3V
LVCH
3V
ALVCH
3V
UNIT
MAX
MAX
MAX
35
-32
64
0.08
-24
24
5
-32
64
0.02
-24
24
0.04
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
CLKEN high
CLK high or low
Data before CLK
CLKEN before CLK
Data after CLK
CLKEN after CLK
MAX or MIN
ABT
AC
LVTH
3V
LVCH
3V
ALVCH
3V
MIN
150
3.3
3.5
3
1
1
4.3
4.5
4.6
6
5.5
4.2
75
6.7
5
6.5
1
0
11.8
11.7
11.2
13
9.4
8.7
150
3.3
1.7
2
0.8
0.4
4.4
4.4
4.9
4.9
6.2
5.3
150
3.3
2.8
1.4
0.5
1.9
6.6
6.6
6.6
6.6
6.7
6.7
150
3.3
3.3
1.5
1
0.8
1.1
3.9
3.9
4.4
4.4
4
4
MIN
MIN
MIN
CLK
A or B
MAX
OEBA or OEAB
A or B
MAX
OEBA or OEAB
A or B
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
625
Logic Diagram
25244
25-Ω OCTAL BUS BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1OE
1A1
● High Output Drive Current
● Distributed VCC and GND Pins Minimize Noise
Generated by the Simultaneous Switching of
Outputs
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
24
23
1
22
3
20
4
1Y3
19
6
1Y4
18
7
17
9
15
10
14
12
(each buffer/driver)
OUTPUT
Y
H
L
Z
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
SN74
BCT
SN64
BCT
UNIT
ICC
MAX
119
119
mA
IOH
IOL
MAX
MAX
-80
-80
mA
188
188
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
626
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1Y2
13
FUNCTION TABLE
INPUTS
OE
A
H
L
L
L
X
H
1Y1
SN74
BCT
SN64
BCT
5.5
6
9.3
10.2
6.3
8.4
5.5
6.3
9.7
10.4
6.5
9.5
2Y1
2Y2
2Y3
2Y4
Logic Diagram
25245
25-Ω OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
DIR
24
13
● High Output Drive Current
● Distributed VCC and GND Pins Minimize Noise
Generated by the Simultaneous Switching of
Outputs
A1
OE
1
23
B1
To Seven Other Channels
FUNCTION TABLE
INPUTS
OE
DIR
L
L
L
H
H
X
OPERATION
B data to A bus
A data to B bus
Isolation
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOH
IOL
IOL
(A port)
(B port)
(A port)
(B port)
MAX or MIN
SN74
BCT
ABTH
UNIT
MAX
125
20
mA
MAX
MAX
MAX
MAX
-80
-3
188
24
-80
-32
188
64
mA
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OE
A
MAX
OE
A
MAX
OE
B
MAX
OE
B
MAX
SN74
BCT
ABTH
5.7
7.2
5.5
6.2
9.6
10.3
6.2
8.3
8.9
9.7
6.9
7.5
3.9
4.3
3.9
4.3
6.5
6.8
7.2
6.4
6.5
6.8
7.2
6.4
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
627
Logic Diagram
25642
OE
25-Ω OCTAL BUS TRANSCEIVER
● High Output Drive Current
● Distributed VCC and GND Pins Minimize Noise
Generated by the Simultaneous Switching of
Outputs
DIR
A1
13
24
23
1
To Seven Other Channels
FUNCTION TABLE
INPUTS
DIR
OE
L
L
H
L
H
X
OPERATION
B data to A bus
A data to B bus
Isolation
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
SN74
BCT
UNIT
ICC
IOH (B port)
IOL (A port)
IOL (B port)
MAX
MAX
MAX
MAX
125
-3
188
24
mA
mA
mA
mA
VOH (A port)
MAX
5.5
V
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
628
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OE
A
MAX
OE
B
MAX
OE
B
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
SN74
BCT
6.2
4
6.3
5.9
11.6
11.3
9.1
9.8
7.3
7.3
B1
Logic Diagram
29821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
OE
CLK
● 3-State Outputs
● Data Flow-Through Pinout
1
13
C1
1D
2
23
1Q
1D
To Nine Other Channels
FUNCTION TABLE
(each fllp-flop)
INPUTS
CLK
D
H
L
H or L X
X
X
→→
OE
L
L
L
H
OUTPUT
Q
H
L
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
SN74
BCT
UNIT
MAX
MAX
MAX
115
-24
48
35
-24
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
INPUT
OUTPUT
MAX or MIN
CLK high or low
MIN
Data before CLK
Data after CLK
MIN
MIN
CLK
Q
MAX
OE
Q
MAX
OE
Q
MAX
ALS
SN74
BCT
7
125
7
4
2
10
10
14
14
14
12
7
1
12
10
12
13
8
8
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
629
29825
8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
● 3-State Outputs
● Data Flow-Through Pinout
Logic Diagram
OE1
OE2
OE3
CLR
CLKEN
CLK
1D
1
2
23
11
14
22
R
13
1Q
C1
3
1D
To Seven Other Channels
FUNCTION TABLE
CLR
L
H
H
H
X
INPUTS
CLKEN CLK
X
X
L
L
H or L
H
X
X
→→
OE†
L
L
L
L
H
D
X
H
L
X
X
RECOMMENDED OPERATING CONDITIONS
OUTPUT
Q
L
H
L
Q0
Z
PARAMETER
ICC
IOH
IOL
MAX or MIN
SN74
BCT
UNIT
MAX
MAX
MAX
40
-24
48
mA
mA
mA
† OE = H if any of the output-enable inputs is high.
OE = L if all of the output-enable inputs are low.
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
CLK low
CLK high or low
Before CLK
Before CLK
, data high
, data low
CLR
CLKEN before CLK
After CLK , data high
After CLK , data low
CLKEN after CLK
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
630
fmax : MHz
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
MAX or MIN
SN74
BCT
MIN
MIN
MIN
125
4
4
MIN
MIN
MIN
6
3.5
1
MIN
8
MIN
MIN
MIN
1.5
0
0.5
9
8.4
9.5
CLK
Q
CLR
Q
MAX
OE
Q
MAX
OE
Q
MAX
other : ns
MAX
10.3
10.2
9
8.2
Logic Diagram
29827
OE1
10-BIT BUFFERS AND BUS DRIVERS
WITH 3-STATE OUTPUTS
OE2
● pnp Inputs Reduce dc Loading
● 3-State Outputs
● Data Flow-Through Pinout
A1
1
13
2
23
Y1
To Nine Other Channels
FUNCTION TABLE
OE1
L
L
L
H
INPUT
OE2
L
L
X
H
A
L
H
X
X
OUTPUT
Y
L
H
Z
Z
†n = 1,2
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALS
SN74
BCT
UNIT
ICC
IOH
MAX
MAX
40
-24
40
-24
mA
mA
IOL
MAX
48
48
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
ALS
SN74
BCT
7
7.5
15
5.5
7.5
9.1
15
17
12
12.8
8.8
8.4
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
631
Logic Diagram
29828
OE1
10-BIT BUFFERS AND BUS DRIVERS
WITH 3-STATE OUTPUTS
OE2
● pnp Inputs Reduce dc Loading
● 3-State Outputs
● Data Flow-Through Pinout
A1
1
13
2
23
To Nine Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
UNIT
MAX
MAX
MAX
40
-24
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
NOTICE : ALS IS NOT RECOMMENDED FOR NEW DESIGNS
632
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
ALS
7
7.5
15
15
17
12
Y1
Logic Diagram
29841
10-BIT BUS INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
OE
● 3-State Outputs
● Data Flow-Through Pinout
LE
1
13
C1
2
1D
1D
23
1Q
To Nine Other Channels
FUNCTION TABLE
OE
L
L
L
H
INPUTS
LE
D
H
H
H
L
L
X
X
X
OUTPUT
Q
H
L
Q0
Z
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALS
SN74
BCT
UNIT
ICC
IOH
MAX
MAX
85
-24
35
-24
mA
mA
IOL
MAX
48
48
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
LE high or low
Data beforeLE
Data after LE , high
Data after LE , low
MAX or MIN
ALS
SN74
BCT
MIN
MIN
MIN
MIN
6
2.5
4.5
4.5
4
2
1.5
3.5
9.5
9.5
12
12
14
14
15
12
7.5
8.6
8.6
8.1
9.2
12.8
6.9
6.9
D
Q
MAX
LE
Q
MAX
OE
Q
MAX
OE
Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
633
29843
9-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
● 3-State Outputs
● Data Flow-Through Pinout
Logic Diagram
OE
PRE
CLR
LE
1
14
11
13
S
1D
C1
2
1D
R
To Eight Other Channels
634
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
23
1Q
FUNCTION TABLE
PRE
L
H
H
H
H
X
CLR
X
L
H
H
H
X
INPUTS
OE
L
L
L
L
L
H
LE
X
X
H
H
L
X
OUTPUT
Q
H
L
L
H
Q0
Z
D
X
X
L
H
X
X
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
SN74
BCT
UNIT
ICC
IOH
MAX
MAX
35
-24
mA
mA
IOL
MAX
48
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
INPUT
PRE low
CLR low
LE high
Data before LE
OUTPUT
MIN
, high or low
MIN
PRE or CLR inactive
Data after LE , high or low
D
MAX or MIN
MIN
Q
MAX
LE
Q
MAX
PRE
Q
MAX
CLR
Q
MAX
OE
Q
MAX
OE
Q
MAX
SN74
BCT
7
5
4
1.5
2
3.5
8
9
10
10
12
12
12
12
15
15
8
8
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
635
29854
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
Logic Diagram
A1–A8
8x
8
8
B1–B8
EN
8x
8
EN
OEB
8
OEA
PARITY
8
MUX
1
1
9
2k
P
1
1
G1
ERR
LE
CLR
636
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLE
INPUTS
OEB
OEA
CLR
L
H
X
H
L
X
H
X
L
X
H
H
H
L
H
L
X
X
L
L
X
OUTPUT AND I/O
Ai
Bi†
LE
Σ of Hs Σ of Ls
Odd
NA
X
Even
Odd
L
NA
Even
H
X
NA
X
H
X
H
X
H
X
X
L
L Odd
L H Even
Odd
NA
X
Even
A
OPERATION
B PARITY ERR‡
NA
A
H
L
B
NA
NA
X
X
NA
NA
NA
NA
Z
Z
Z
NA
A
L
H
NA
A data to B bus and generate parity
H
L
N-1
H
NC
H
L
H
NA
B data to A bus and check parity
Store error flag
Clear error-flag register
Isolation§
A data to B bus and generate inverted
parity
NA = not applicable, NC = no change, X = don’t care
† Summation of high-level inputs includes PARITY along with Bi inputs.
‡ Output states Shown assume ERR was previously high.
§ In this mode, ERR, when enabled, shows inverted parity of the A bus.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ALS
SN74
BCT
UNIT
ICC
IOH
MAX
MAX
100
-24
80
-24
mA
mA
IOL
MAX
48
48
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
tw Pulse duration
LE high
LE low
CLR low
tsu Setup time
Before LE
Before LE
th Hold time
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPHL
tPLH
tPLH
tPHL
tPLH
tPHL
UNIT: ns
OUTPUT
, Bi and PARITY
, CLR high
Bi and PARITY after LE
MAX or MIN
ALS
SN74
BCT
MIN
MIN
MIN
10
10
10
10
10
MIN
MIN
10
15
18
-
MIN
3
8
8
15
18
8
8
8
15
15
17
17
15
8
12
12
17
19
15
17
9
15
17
19
20
20
15
16
20
15
A or B
B or A
MAX
A
PARITY
MAX
OEA or OEB
A or B
MAX
OEA or OEB
A or B
MAX
LE
CLR
ERR
ERR
MAX
MAX
OEA
PARITY
MAX
Bi / PARITY
ERR
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
637
Logic Diagram
29863
OEAB1
9-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
OEAB2
A1
13
1
14
11
2
23
● True Outputs
FUNCTION TABLE
INPUTS
OPERATION
OEAB1 OEAB2 OEBA1 OEBA2
L
L
Latch A and B
L
L
L
H
X
L
A to B
H
L
L
X
X
H
L
L
B to A
H
L
X
L
H
H
X
X
H
X
H
X
Isolation
X
X
H
H
X
H
X
H
To Eight Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALS
SN74
BCT
UNIT
MAX
MAX
MAX
65
-24
48
45
-24
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
638
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
OEAB or OEBA
A or B
MAX
OEAB or OEBA
A or B
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
ALS
SN74
BCT
8
8
15
5
7.5
8.4
15
17
12
12.6
8.8
8.1
OEBA1
OEBA2
B1
Logic Diagram
29864
OEAB1
9-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
OEAB2
A1
13
1
14
11
2
23
OEBA1
OEBA2
B1
● Inverted Outputs
FUNCTION TABLE
INPUTS
OPERATION
OEAB1 OEAB2 OEBA1 OEBA2
L
L
L
Latch A and B
L
L
L
H
X
A to B
L
L
X
H
H
X
L
L
B to A
X
L
H
L
H
H
X
X
H
X
H
X
Isolation
X
X
H
H
X
H
X
H
To Eight Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
SN74
BCT
UNIT
MAX
MAX
MAX
45
-24
48
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
OEAB or OEBA
A or B
MAX
OEAB or OEBA
A or B
MAX
SN74
BCT
6.1
4.8
8.4
12.5
8.4
8.2
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
639
32240
32-BIT BUFFER/DRIVER
Logic Diagram
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
5OE
5A1
5A2
5A3
5A4
6OE
6A1
6A2
6A3
6A4
640
A3
3OE
A5
A2
A6
A1
B5
B2
B6
B1
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
A4
3A4
4OE
C5
C2
C6
C1
D5
D2
D6
D1
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
J3
7OE
J5
J2
J6
J1
K5
K2
K6
K1
5Y1
7A1
5Y2
7A2
5Y3
7A3
5Y4
7A4
J4
8OE
L5
L2
L6
L1
M5
M2
M6
M1
6Y1
8A1
6Y2
8A2
6Y3
8A3
6Y4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
8A4
H4
E5
E2
E6
E1
F5
F2
F6
F1
3Y1
3Y2
3Y3
3Y4
H3
G5
G2
G6
G1
H6
H1
H5
H2
4Y1
4Y2
4Y3
4Y4
T4
N5
N2
N6
N1
P5
P2
P6
P1
7Y1
7Y2
7Y3
7Y4
T3
R5
R2
R6
R1
T6
T1
T5
T2
8Y1
8Y2
8Y3
8Y4
FUNCTION TABLE
(each 4bit buffer/drirer)
INPUTS
A
H
L
X
OE
L
L
H
OUTPUT
Y
L
H
Z
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LVT
ICC
PARAMETER
MAX
10
UNIT
mA
IOH
MAX
-32
mA
IOL
MAX
64
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT:ns
INPUT
OUTPUT
A
Y
OE
Y
OE
Y
MAX or MIN
LVT
MAX
MAX
MAX
MAX
MAX
3.5
3.5
4
4.4
4.5
MAX
4.2
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
641
32244
36-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
Logic Diagram
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
5OE
5A1
5A2
5A3
5A4
6OE
6A1
6A2
6A3
6A4
642
A3
3OE
A5
A2
A6
A1
B5
B2
B6
B1
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
A4
3A4
4OE
C5
C2
C6
C1
D5
D2
D6
D1
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
J3
4A4
7OE
J5
J2
J6
J1
K5
K2
K6
K1
5Y1
7A1
5Y2
7A2
5Y3
7A3
5Y4
7A4
J4
8OE
L5
L2
L6
L1
M5
M2
M6
M1
6Y1
8A1
6Y2
8A2
6Y3
8A3
6Y4
8A4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
H4
E5
E2
E6
E1
F5
F2
F6
F1
3Y1
3Y2
3Y3
3Y4
H3
G5
G2
G6
G1
H6
H1
H5
H2
4Y1
4Y2
4Y3
4Y4
T4
N5
N2
N6
N1
P5
P2
P6
P1
7Y1
7Y2
7Y3
7Y4
T3
R5
R2
R6
R1
T6
T1
T5
T2
8Y1
8Y2
8Y3
8Y4
FUNCTION TABLE
INPUTS
A
OE
L
H
L
L
H
X
OUTPUT
Y
H
L
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
LVT
3V
LVTH
3V
ALVTH
3V
LVC
3V
LVCH
3V
ALVCH
3V
UNIT
ICC
MAX
10
10
5
0.02
0.02
0.04
mA
IOH
IOL
MAX
MAX
-32
64
-32
64
-32
64
-24
24
-24
24
-24
24
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
LVT
3V
LVTH
3V
ALVTH
3V
LVC
3V
LVCH
3V
ALVCH
3V
3.2
3.2
2.4
4.1
4.1
3
3.2
4
4
4.5
4.2
3.2
4
4
4.5
4.2
2.5
3.8
2.9
4.2
3.6
4.1
4.6
4.6
5.8
5.8
4.1
4.6
4.6
5.8
5.8
3
4.4
4.4
4.1
4.1
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
643
32245
36-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Logic Diagram
1DIR
A3
2DIR
A4
1A1
H4
1OE
A5
2A1
A2
H3
E2
1B1
To Seven Other Channels
3DIR
J3
4DIR
T3
T4
3OE
J5
4A1
J2
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4OE
N5
N2
3B1
To Seven Other Channels
644
2B1
To Seven Other Channels
J4
3A1
2OE
E5
To Seven Other Channels
4B1
FUNCTION TABLE
(each 9-bit section)
INPUTS
OE
DIR
L
L
L
H
H
X
OPERATION
B data to A bus
A data to B bus
Isolation
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ABTH
LVTH
3V
LVC
3V
LVCH
3V
ALVCH
3V
UNIT
ICC
MAX
20
10
0.04
0.02
0.04
mA
IOH
IOL
MAX
MAX
-32
64
-32
64
-24
24
-24
24
-24
24
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
INPUT
OUTPUT
MAX or MIN
A or B
B or A
MAX
OE
B or A
MAX
OE
B or A
MAX
ABTH
LVTH
3V
LVC
3V
LVCH
3V
ALVCH
3V
5
3.3
4
4
3
5.2
7.3
8.1
6.5
6.9
3.3
4.5
4.6
5.1
5.1
4
5.5
5.5
6.6
6.6
4
5.5
5.5
6.6
6.6
3
4.4
4.4
4.1
4.1
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
645
32316
16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
Logic Diagram
OEC
SELC
CLKC
CLKENC
LEC
C1
OEB
SELB
CLKB
CLKENB
LEB
B1
OEA
SELA
CLKA
CLKENA
LEA
A1
646
77
76
74
73
75
CLK
C
CE
52
24
25
27
28
26
CLK
C
CE
32
78
79
22
21
23
CLK
C
CE
80
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1 of 16 Channels
FUNCTION TABLE
STORAGE†
RECOMMENDED OPERATING CONDITIONS
INPUTS
CLKA
X
→→
CLKENA
H
L
L
X
X
X
X
H
L
X
X
LEA
L
L
L
L
L
H
H
A
X
L
H
X
X
L
H
OUTPUT
Q0‡
L
H
Q0‡
Q0‡
L
H
† A-port register shown, B and C ports are similar but use
CLKENB, CLKENC, CLKB, CLKC, LEB, and LEC.
‡ Output level before the indicated steady-state input
conditions were established.
A-PORT OUTPUT
INPUTS
OEA
SELA
X
H
H
L
L
L
OUTPUT A
Z
Output of C register
Output of B register
MAX or MIN
ABTH
UNIT
ICC
MAX
40
mA
IOH
IOL
MAX
MAX
-32
64
mA
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
tw Pulse duration
tsu Setup time
B-PORT OUTPUT
INPUTS
OEB
SELB
X
H
H
L
L
L
OUTPUT B
Z
Output of A register
Output of C register
C-PORT OUTPUT
INPUTS
OEC
SELC
X
H
H
L
L
L
OUTPUT C
Z
Output of B register
Output of A register
INPUT
OUTPUT
MAX or MIN
ABTH
MIN
150
LE high
CLK high or low
MIN
MIN
3.3
3.3
A, B, or C before CLK
MIN
MIN
2.4
2.1
MIN
3.2
MIN
MIN
1.4
2.1
MIN
1.1
6.1
6.6
6.5
6.5
fmax
th Hold time
A or B before LE
CLKEN before CLK
A, B, or C after CLK
A or B after LE
CLKEN after CLK
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
A, B, or C
C, B, or A
MAX
SEL
A, B, or C
MAX
LE
A, B, or C
MAX
CLK
A, B, or C
MAX
OE
A, B, or C
MAX
OE
A, B, or C
MAX
7.5
6.9
7.5
6.7
6.4
6.8
6
6.1
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
647
32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
Logic Diagram
OEC
SELC
CLKC
LEC
C1
OEB
SELB
CLKB
LEB
B1
OEA
SELA
CLKA
LEA
A1
648
77
76
74
75
Q
CLK
LE
D
52
24
25
27
26
Q
CLK
LE
D
28
78
79
22
23
Q
CLK
LE
D
80
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1 of 18 Channels
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
STORAGE†
→→
CLKA
H
L
X
X
INPUTS
LEA
L
L
L
L
H
H
A
L
H
X
X
L
H
OUTPUT
L
H
Q0‡
Q0‡
L
H
† A-port register shown, B and C ports are
similar but use CLKB, CLKC, LEB, and LEC.
‡ Outpu level befor the indicated steady-state
input conditions were established.
A-PORT OUTPUT
INPUTS
OEA
H
L
L
SELA
X
H
L
OUTPUT A
Z
Output of C register
Output of B register
PARAMETER
OEB
H
L
L
SELB
X
H
L
C-PORT OUTPUT
INPUTS
OEC
H
L
L
SELC
X
H
L
OUTPUT C
Z
Output of B register
Output of A register
UNIT
MAX
45
mA
IOH
IOL
MAX
MAX
-32
64
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
LE high
CLK high or low
tsu Setup time
A, B, or C before CLK
A, B, or C before LE
th Hold time
A, B, or C after CLK
A, B, or C after LE
OUTPUT B
Z
Output of A register
Output of C register
ABTH
ICC
B-PORT OUTPUT
INPUTS
MAX or MIN
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
MAX or MIN
ABTH
MIN
MIN
150
3.3
MIN
MIN
3.3
2.4
MIN
2.1
MIN
MIN
1.4
2.1
A, B, or C
C, B, or A
MAX
SEL
A, B, or C
MAX
LE
A, B, or C
MAX
CLK
A, B, or C
MAX
OE
A, B, or C
MAX
OE
A, B, or C
MAX
6.1
6.6
6.5
6.5
7.5
6.9
7.4
6.7
6.8
7.1
6.2
6
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
649
32373
32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
Logic Diagram
1OE
1LE
A3
2OE
A4
2LE
C1
1D1
A5
A2
1D
H3
H4
C1
1Q1
2D1
E5
To Seven Other Channels
3OE
3LE
3D1
4OE
J4
J5
4LE
1D
J2
T3
T4
C1
3Q1
To Seven Other Channels
650
2Q1
To Seven Other Channels
J3
C1
E2
1D
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4D1
N5
1D
To Seven Other Channels
N2
4Q1
FUNCTION TABLE
OE
L
L
L
H
INPUTS
LE
D
H
H
H
L
L
X
X
X
OUTPUT
Q
H
L
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LVTH
3V
ALVTH
3V
LVCH
3V
UNIT
MAX
MAX
MAX
10
-32
64
5
-32
64
0.02
-24
24
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
tw Pulse duration, LE high or low
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
MAX or MIN
LVTH
3V
ALVTH
3V
LVCH
3V
MIN
3
1.5
3.3
, data high
MIN
1
1.4
1.7
Data before LE , data low
Data after LE , data high
Data after LE , data low
MIN
MIN
MIN
1
1
1
3.8
3.6
4.3
4
0.9
0.9
1.4
3.1
3.3
3.3
3.5
1.7
1.2
1.2
4.2
4.2
4.6
4.6
4.3
4.3
5
4.7
4
3.4
4.9
4.5
4.7
4.7
5.9
5.9
Data before LE
D
Q
MAX
LE
Q
MAX
OE
Q
MAX
OE
Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
651
32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Logic Diagram
A3
H3
1OE
2OE
A4
H4
1CLK
1D1
2CLK
A5
C1
A2
1D
1Q1
2D1
E5
To Seven Other Channels
3OE
J3
4OE
2Q1
T3
T4
3CLK
4CLK
J5
C1
1D
J2
3Q1
To Seven Other Channels
652
E2
1D
To Seven Other Channels
J4
3D1
C1
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4D1
N5
C1
1D
To Seven Other Channels
N2
4Q1
FUNCTION TABLE
(each flip-flop)
INPUTS
CLK
D
H
L
H or L X
X
X
→→
OE
L
L
L
H
OUTPUT
Q
H
L
Q0
Z
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
LVTH
3V
ALVTH
3V
LVCH
3V
ALVCH
3V
UNIT
ICC
MAX
10
5
0.02
0.04
mA
IOH
IOL
MAX
MAX
-32
64
-32
64
-24
24
-24
24
mA
mA
PARAMETER
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration, CLK high or low
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
MAX or MIN
MIN
MIN
MIN
MIN
MIN
Data before CLK , data high
Data before CLK , data low
Data after CLK , data high
Data after CLK , data low
CLK
Q
MAX
OE
Q
MAX
OE
Q
MAX
LVTH
3V
ALVTH
3V
LVCH
3V
ALVCH
3V
160
3
250
1.5
150
3.3
150
3.3
1.8
1.8
0.8
0.8
4.5
4
1
1.5
0.5
1
3.2
3.2
1.9
1.9
1.1
1.1
4.5
4.5
1.9
1.9
0.5
0.5
4.2
4.2
4.5
4.4
5
4.6
3.8
3.3
4.6
4.2
4.6
4.6
5.5
5.5
4.8
4.8
4.3
4.3
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
653
32501
36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1OEAB
1CLKAB
1LEAB
1LEBA
1CLKBA
1OEBA
1A1
B3
A4
A3
K3
J4
J3
A2
1D
A5
C1
CLK
1B1
1D
C1
CLK
To 17 Other Channels
2OEAB
2CLKAB
2LEAB
2LEBA
2CLKBA
2OEBA
2A1
L3
K5
K2
W3
V4
V3
L2
1D
C1
CLK
1D
C1
CLK
To 17 Other Channels
654
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
L5
2B1
FUNCTION TABLE†
→→
INPUTS
OEAB LEAB CLKAB
X
X
L
H
H
X
X
H
H
L
H
H
L
L
H
H
L
H
L
OUTPUT
B
Z
L
H
L
H
B0‡
B0§
A
X
L
H
L
H
X
X
† A-to-B data flow is shown: B-to-A flow is similar
but uses OEBA, LEBA, and CLKBA.
‡ Outoput level before the indicated steady-state
input conditions were established
§ Output level before the indicated steady-state
input conditions were established, provided that
CLKAB was high before LEAB went low
RECOMMENDED OPERATING CONDITIONS
MAX or MIN
ABTH
ALVCH
3V
ICC
MAX
90
0.02
mA
IOH
IOL
MAX
MAX
-32
64
-24
24
mA
mA
PARAMETER
UNIT
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB
B
A
A
A
A
before CLKBA
before LEAB or LEBA CLK high
before LEAB or LEBA CLK low
after CLKAB or B after CLKBA
after LEAB or B after LEBA
MAX or MIN
ABTH
ALVCH
3V
MIN
MIN
MIN
150
3.3
3.3
150
3.3
3.3
MIN
MIN
MIN
MIN
3.5
3.5
1.6
1.6
1.7
1.7
1.5
1
MIN
0
0.7
MIN
1.6
4.8
5.4
5.3
5.5
1.4
3.9
3.9
4.6
4.6
5.3
5.4
5.6
6
5.9
4.9
4.9
4.6
4.6
5
5.6
5.6
6
5.9
5.6
5
5
5
4.2
4.2
A or B
B or A
MAX
LEAB or LEBA
B or A
MAX
CLKAB or CLKBA
B or A
MAX
OEAB
B
MAX
OEAB
B
MAX
OEBA
A
MAX
OEBA
A
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
655
32543
36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
90
91
89
86
85
87
C1
92
1D
84
1B1
C1
1D
To 17 Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1
36
35
37
40
41
39
C1
14
1D
C1
1D
To 17 Other Channels
656
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
62
2B1
FUNCTION TABLE
INPUTS
CEAB LEAB OEAB
X
H
X
H
X
X
L
L
H
L
L
L
L
L
L
A
X
X
X
L
H
OUTPUT
Y
Z
Z
B0‡
L
H
† A-to-B data flow is shown: B-to-A flow conditions
is the same that it uses CEBA, LEBA, and OEBA.
‡ Outoput level before the indicated steady-state
input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ABTH
UNIT
ICC
IOH
MAX
MAX
20
-32
mA
mA
IOL
MAX
64
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
tw Pulse duration, LEAB or LEBA low
Data before LEAB or LEBA
tsu Setup time
Data before CEAB or CEBA
th Hold time
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
Data after LEAB or LEBA
Data after CEAB or CEBA
MAX or MIN
ABTH
MIN
3.3
MIN
2.1
MIN
MIN
MIN
1.7
0.6
0.9
5.9
5.7
A or B
B or A
MAX
LE
A or B
MAX
CE
A or B
MAX
CE
A or B
MAX
OE
A or B
MAX
OE
A or B
MAX
7.5
6.6
8
8.8
7.1
7.5
7.3
8.1
6.5
6.9
UNIT: ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
657
Logic Diagram
40103
TC
8-STAGE SYNCHRONOUS DOWN COUNTERS
7
6
5
P4
P3
P2
P1
P0
PE
4
P5
15 9 3 1 2
FUNCTION TABLE
CONTROL INPUTS
TE
MR
PL
PE
L
X
X
L
X
H
X
L
L
X
X
L
H
L
L
L
H
L
H
L
PRESET MODE
Synchronous
Asynchronously
ACTION
Inhibit Counter
Cownt Down
Preset On Next Positive Clock Transition
Preset Asychronously
Clear to Maximum Count
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
CD74 CD74
UNIT
HC HCT
ICC
MAX
0.16
0.16
mA
IOH
IOL
MAX
MAX
-4
4
-4
4
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
OUTPUT
MAX or MIN
tw
CP
MIN
tsu
PL
MR
P to CP
PE to CP
TE to CP
P to CP
MIN
th
TE to CP
PE to CP
MIN
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT:ns
658
INPUT
CP
CP
TC
(Async Preset)
TC
(Sync Preset)
MAX
MAX
TE
TC
MAX
PL
TC
MAX
MR
TC
MAX
CD74 CD74
HC HCT
50
38
38
30
22
45
5
0
2
90
90
90
90
60
60
83
83
83
83
53
63
53
36
30
60
5
0
2
90
90
95
95
75
75
102
102
83
83
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
GND
10
P6
VCC
11
P7
MR
12
PL
TE
CP
13
16 8
162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
● SN74LVT162240, SN74LVTH162240: Output Ports Have Equivalent 22-Ω Series Resistors
Logic Diagram
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
FUNCTION TABLE
INPUTS
OE
A
H
L
L
L
X
H
OUTPUT
Y
L
H
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LVT
3V
LVTH
3V
UNIT
MAX
MAX
MAX
5
-12
12
5
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
LVT
3V
LVTH
3V
4
4
4.8
4.7
4.7
4.5
4
4
4.8
4.7
4.7
4.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
659
162241
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Logic Diagram
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
FUNCTION TABLE
INPUTS
1OE, 4OE 1A, 4A
H
L
L
L
X
H
OUTPUT
1Y, 4Y
H
L
Z
INPUTS
2OE, 3OE 2A, 3A
H
H
H
L
X
L
OUTPUT
2Y, 3Y
H
L
Z
1
47
2
46
3
44
5
43
6
3A1
1Y1
1Y2
3A2
1Y3
3A3
3A4
1Y4
48
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
4OE
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LVTH
3V
UNIT
MAX
MAX
MAX
5
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
660
25
3OE
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE or OE
Y
MAX
OE or OE
Y
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
LVTH
3V
4.1
4.1
4.9
4.8
5.3
4.9
162244
16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
●
●
●
●
●
●
SN74ABT162244: Output Ports Have Equivalent 25-Ω Series Resistors
SN74LVT162244A, LVTH162244: Output Ports Have Equivalent 22-Ω Series Resistors
SN74ALVTH162244: Output Ports Have Equivalent 30-Ω Series Resistors
SN74LVC162244A: Output Ports Have Equivalent 26-Ω Series Resistors
SN74LVCH162244A: Output Ports Have Equivalent 26-Ω Series Resistors
SN74ALVCH162244: Output Ports Have Equivalent 26-Ω Series Resistors
Logic Diagram
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OE
A
OUTPUT
Y
L
L
H
H
L
X
H
L
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
LVT
3V
LVTH
3V
ALVTH
3V
LVC
3V
LVCH
3V
ALVCH
3V
UNIT
MAX
MAX
MAX
30
-12
12
5
-12
12
5
-12
12
5
-12
12
0.02
-12
12
0.02
-12
12
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
ABT
LVT
3V
LVTH
3V
ALVTH
3V
LVC
3V
LVCH
3V
ALVCH
3V
3.9
4.8
5.4
5.1
4.6
4.5
4
3.6
5.1
4.5
5
5
4
3.6
5.1
4.5
5
5
3.3
3.3
4.9
3.3
4.9
4.3
4.4
4.4
5.5
5.5
6.3
6.3
4.4
4.4
5.5
5.5
6.3
6.3
4.2
4.2
5.6
5.6
5.5
5.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
661
162245
16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS
●
●
●
●
SN74ABT162245, SN74ABTH162245: A-Port Outputs Have Equivalent 25-Ω Series Resistors
SN74LVT162245A, SN74LVTH162245: A-Port Outputs Have Equivalent 22-Ω Series Resistors
SN74ALVTH162245: A-Port Outputs Have Equivalent 30-Ω Series Resistors
SN74LVCR162245: All Outputs Have Equivalent 26-Ω Series Resistors
Logic Diagram
1DIR
1
48
1A1
47
2
To Seven Other Channels
662
1OE
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1B1
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE
L
L
H
DIR
L
H
X
OPERATION
B data to A bus
A data to B bus
Isolation
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH (A port)
IOH (B port)
IOL (A port)
IOL (B port)
MAX or MIN
ABT
ABTH
LVT
3V
LVTH
3V
ALVTH
3V
LVCR
3V
UNIT
MAX
MAX
MAX
MAX
MAX
32
-12
-32
12
64
32
-12
-32
12
64
5
-12
-32
12
64
5
-12
-32
12
64
5
-12
-32
12
64
0.02
-12
-12
12
12
mA
mA
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OE
B
MAX
OE
B
MAX
OE
A
MAX
OE
A
MAX
ABT
ABTH
LVT
3V
LVTH
3V
ALVTH
3V
LVC
3V
3.9
4.2
4.6
5.1
6.3
6.4
6.3
5.2
7.1
7
6.6
5.7
3.9
4.2
4.6
5.1
6.3
6.4
6.3
5.2
7.1
7
6.6
5.7
3.3
3.3
4
3.4
4.6
4.6
5.2
5.1
5.3
5.1
5.6
5.5
3.3
3.3
4
3.4
4.6
4.6
5.2
5.1
5.3
5.1
5.6
5.5
3.1
3
3.7
3.4
3.8
3.4
4.7
4.8
4.7
3.9
5
4.9
7.5
7.5
7.5
7.5
9
9
7.5
7.5
9
9
7.5
7.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
663
162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS
● SN74ABTH162260: B-Port Outputs Have Equivalent 25-Ω Series Resistors
● SN74ALVCH162260: B-Port Outputs Have Equivalent 26-Ω Series Resistors
Logic Diagram
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
A1
2
27
30
55
56
29
1
28
8
G1
C1
1
1D
23
1B1
1
C1
1D
C1
1D
C1
1D
To 11 Other Channels
664
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
6
2B1
FUNCTION TABLE
B TO A (OEB = H)
1B
H
L
X
X
X
X
X
2B
X
X
X
H
L
X
X
INPUTS
SEL LE1B LE2B OEA
L
H
X
H
X
L
H
H
H
X
L
L
H
L
L
X
X
H
L
L
L
L
X
L
X
X
X
H
OUTPUT
A
H
L
A0
H
L
A0
Z
A TO B (OEA = H)
A
H
L
H
L
H
L
X
X
X
X
X
INPUTS
LEA1B LEA2B OE1B OE2B
L
H
L
H
L
L
H
H
L
L
H
L
L
L
H
L
L
L
L
H
L
L
L
H
L
L
L
L
H
X
X
H
L
H
X
X
H
L
X
X
L
L
X
X
OUTPUTS
1B
2B
H
H
L
L
H
2B0
2B0
L
1B0
H
1B0
L
1B0 2B0
Z
Z
Z
Active
Z
Active
Active Active
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH (A port)
IOH (B port)
IOL (A port)
IOL (B port)
MAX or MIN
ABTH
ALVCH
3V
UNIT
MAX
MAX
MAX
MAX
MAX
63
-32
-32
64
12
0.04
-24
-12
24
12
mA
mA
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high
tsu Setup time, data before LE1B, LE2B, LEA1B, or LEA2B
th Hold time, data after LE1B, LE2B, LEA1B, or LEA2B
tPLH
A
B
tPHL
tPLH
B
A
tPHL
tPLH
LE
A
tPHL
tPLH
LE
B
tPHL
SEL (1B)
tPLH
SEL (2B)
A
SEL (1B)
tPHL
SEL (2B)
tPZH
OE
A
tPZL
tPZH
OE
B
tPZL
tPHZ
OE
A
tPLZ
tPHZ
OE
B
tPLZ
UNIT fmax : MHz other : ns
MAX or MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
ABTH
ALVCH
3V
3.3
1.5
1
6.1
7.1
6
6.2
6.3
5.8
6.1
7.1
5.6
6.3
5
6.2
6.3
6.5
6.3
8.2
6.7
5.2
7.5
6.2
150
3.3
1.1
1.5
4.9
4.9
4.3
4.3
4.4
4.4
5
5
5.6
5.6
5.6
5.6
5.4
5.4
6
6
4.6
4.6
5.1
5.1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
665
162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
● SN74ALVCH162268: B-Port Outputs Have Equivalent 26-Ω Series Resistors
Logic Diagram
29
CLK
2
CLKEN1B
CLKEN2B
CLKENA1
CLKENA2
OEB
27
30
55
C1
56
1D
C1
SEL
OEA
28
1D
1
CE
1D
C1
1D
C1
G1
A1
1
CE
C1
1D
1D
CE
C1
1D
C1
1D
CE
C1
1D
1 of 12 Channels
666
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1B1
CE
1
8
23
6
2B1
FUNCTION TABLE
OUTPUT ENABLE
→→→→
INPUTS
CLK OEA OEB
H
H
L
H
L
H
L
L
OUTPUTS
A 1B, 2B
Z
Z
Z
Active
Active
Z
Active Active
A-TO-B STORAGE (OEB = L)
INPUTS
CLKENA1 CLKENA2 CLK
H
X
H
X
L
X
L
X
L
L
X
→→→→
A
X
L
H
L
H
OUTPUTS
1B
2B
1B0‡ 2B0‡
X
L†
X
H†
L
X
X
H
† Two CLK edges are needed to propagate data.
‡ Output level before the indicated steady-state input conditions
were established
B-TO-A STORAGE (OEA = L)
→→→→
INPUTS
CLKEN1B CLKEN2B CLK SEL
X
H
X
H
X
H
X
L
X
L
H
X
L
H
X
L
L
L
X
L
1B
X
X
H
L
X
X
2B
X
X
X
X
L
H
OUTPUT
A
A0‡
A0‡
L
H
L
H
‡ Output level before the indicated steady-state input conditions were
established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH (A port)
IOH (B port)
IOL (A port)
IOL (B port)
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
MAX
MAX
0.04
-24
-12
24
12
mA
mA
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
fmax
tw Pulse duration, CLK high or low
A data before CLK
B data before CLK
SEL before CLK
tsu Setup time
CLKENA1 or CLKENA2
CLKENB1 or CLKENB2
OE before CLK
th Hold time
A data after CLK
B data after CLK
SEL after CLK
CLKENA1 or CLKENA2
CLKENB1 or CLKENB2
OE after CLK
tpd
CLK
ten
CLK
tdis
UNIT
CLK
fmax : MHz
OUTPUT
before CLK
before CLK
after CLK
after CLK
B
A (1B)
A (2B)
A (SEL)
B
A
B
A
MAX or MIN
ALVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
150
3.3
3.4
1
1.3
2.8
2.5
3.2
0.2
1.3
1
0.4
0.5
0.2
5.4
4.8
4.8
5.8
6.1
5.1
5.9
5
MAX
MAX
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
667
162280
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS
● SN74ALVCHG162280: A-Port Outputs Have Equivalent 50-Ω Series Resistors
● B-Port Outputs Have Equivalent 20-Ω Series Resistors
Logic Diagram
CLK
SEL
OE
39
40
42
CE
C1
DIR
41
1D
19
1 of 16 Channels
1B1
G1
CE
C1
A1
29
1
1D
C1
1D
1
CE
C1
1D
C1
1D
CE
C1
1D
668
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
18
2B1
RECOMMENDED OPERATING CONDITIONS
FUNCTION TABLE
A-TO-B STORAGE (OE = L, DIR = H)
SEL
H
L
L
INPUTS
CLK
A
X
X
L
H
OUTPUTS
1B
2B
1B0† 2B0†
L‡
X
H‡
X
† Output level before indicated steady-state
input conditions were established
‡ Two CLK edges are needed to propagate the
data.
PARAMETER
ICC
IOH (A to B)
IOH (B to A)
IOL (A to B)
IOL (B to A)
MAX or MIN
ALVCHG
3V
UNIT
MAX
MAX
MAX
MAX
MAX
0.04
8
6
8
6
mA
mA
mA
mA
mA
B-TO-A STORAGE (OE = L, DIR = L)
CLK
↑
↑
↑
↑
INPUTS
SEL
1B
H
X
H
X
L
L
L
H
2B
L
H
X
X
OUTPUT
A
L§
H§
L
H
§ Two CLK edges are needed to propagate the
data. The data is loaded in the first register when
SEL is low and propagates to the second register
when SEL is high.
SWITCHING CHARACTERISTICS
PARAMETER
C-TO-D STORAGE (OE = L)
INPUTS
CLK
C
X
X
L
↑
H
↑
OUTPUT
1D
2D
1B0† 2B0†
L‡
L
H‡
H
† Output level before indicated steady-state
input conditions were established
‡ Two CLK edges are needed to propagate the
data.
OUTPUT ENABLE
CLK
↑
↑
↑
INPUTS
OE
DIR
H
X
L
H
L
L
OUTPUT
A
1B, 2B 1D, 2D
Z
Z
Z
Z
Active Active
Z
Active
Active
OUTPUT
fmax
tw Pulse duration, CLK high or low
A data before CLK , high or low
B data before CLK , high or low
C data before CLK , high or low
DIR before CLK , high or low
SEL before CLK , high or low
A data after CLK , high or low
B data after CLK , high or low
th Hold time
C data after CLK , high or low
DIR after CLK , high or low
SEL after CLK , high or low
A
CLK
B
tpd
D
A
CLK
B
A
ten
OE
B
D
A
CLK
B
A
tdis
OE
B
D
UNIT fmax : MHz other : ns
tsu Setup time
SEL
H
L
L
INPUT
MAX or MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
MAX
ALVCHG
3V
160
2.3
1.4
2
1.3
2
2
0.3
0.3
0.3
0.3
0.3
5
7.4
7.2
6.2
9.4
6
9.5
7.9
6.4
7.8
5
7.6
6.7
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
669
162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
● SN74ALVCHG162282: A-Port Outputs Have Equivalent 50-Ω Series Resistors
● B-Port Outputs Have Equivalent 20-Ω Series Resistors
Logic Diagram
CLK
SEL
OE
39
40
42
CE
C1
DIR
41
1D
25
1 of 18 Channels
1B1
G1
CE
C1
A1
27
1
1D
C1
1D
1
CE
C1
C1
1D
1D
CE
C1
1D
670
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
24
2B1
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
A-TO-B STORAGE
(OE = L, DIR = H)
INPUTS
SEL
H
L
L
CLK
X
↑
↑
A
X
L
H
PARAMETER
OUTPUTS
1B
2B
1B0† 2B0†
L‡
L
H‡
H
† Output level before indicated steady-state
input conditions were established
‡ Two CLK edges are needed to propagate
the data.
B-TO-A STORAGE
(OE = L, DIR = L)
INPUTS
CLK
↑
↑
↑
↑
SEL
H
H
L
L
1B
X
X
L
H
2B
L
H
X
X
OUTPUT
A
L§
H§
L
H
§ Two CLK edges are needed to propagate the data.
The data is loaded in the first register when SEL is
low and proparates to the second register when
SEL is high.
ICC
IOH (A to B)
IOH (B to A)
IOL (A to B)
IOL (B to A)
OE
H
L
L
DIR
X
H
L
OUTPUTS
A
1B, 2B
Z
Z
Z
Active
Active
Z
ALVCHG
3V
UNIT
MAX
MAX
MAX
MAX
MAX
0.04
8
6
8
6
mA
mA
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration, CLK high or low
tsu Setup time
OUTPUT ENABLE
INPUTS
CLK
↑
↑
↑
MAX or MIN
th Hold time
tpd
A data before CLK
B data before CLK
DIR before CLK
SEL before CLK
A data after CLK
B data after CLK
DIR after CLK
SEL after CLK
CLK
CLK
ten
OE
CLK
tdis
OE
UNIT
fmax : MHz
A
B
A
B
A
B
A
B
A
B
MAX or MIN
ALVCHG
3V
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
160
2.3
1.5
2
2
2
0.3
0.3
0.3
0.3
5
7.4
6.3
9.4
6
9.5
6.4
7.8
5
7.6
MAX
MAX
MAX
MAX
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
671
162334
16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
● SN74ALVC162334: Output Ports Have Equivalent 26-Ω Series Resistors
● SN74ALVCH162334: Output Port Has Equivalent 26-Ω Series Resistors
Logic Diagram
OE
CLK
LE
A1
1
48
25
47
1D
C1
CLK
To 15 Other Channels
672
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2
Y1
FUNCTION TABLE
INPUTS
CLK
LE
X
X
L
X
L
X
H
H
H
L or H
→→
OE
H
L
L
L
L
L
A
X
L
H
L
H
X
OUTPUT
Y
Z
L
H
L
H
Y0†
† Output level before the indicated steady-state
input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVC
3V
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-12
12
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tpd
ten
tdis
UNIT
fmax : MHz
LE low
CLK high or low
Data before CLK
Data before LE
CLK high
Data before LE
CLK low
Data after CLK
Data after LE
CLK high
Data after LE
CLK low
A
LE
CLK
OE
OE
other : ns
MAX or MIN
ALVC
3V
ALVCH
3V
MIN
150
3.3
3.3
1.5
1.3
1.2
0.9
1.1
1.1
3.9
5
4.9
5.4
5
150
3.3
3.3
1.5
1.3
1.2
0.9
1.1
1.1
3.9
5
4.9
5.4
5
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MAX
Y
MAX
Y
Y
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
673
162344
1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
● SN74ALVCH162344: Output Ports Have Equivalent 26-Ω Series Resistors
Logic Diagram
OE4
OE3
OE2
OE1
56
29
28
1
2
3
1A
5A
6
9
10
13
16
17
41
2B1
40
2B2
23
38
37
2B4
48
3B1
47
3B2
24
45
44
3B4
55
4B1
54
4B2
8A
26
27
4B3
4B4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
5B3
5B4
6B1
6B2
6B3
6B4
7B1
7B2
43
3B3
21
5B2
42
2B3
7A
20
674
30
1B4
15
19
4A
31
6A
5B1
36
1B3
14
12
3A
33
1B2
8
5
2A
34
1B1
7B3
7B4
8B1
8B2
49
52
51
8B3
8B4
FUNCTION TABLE
INPUTS
OE
A
H
L
L
L
X
H
OUTPUT
Bn
H
L
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
B
MAX
OE
B
MAX
OE
B
MAX
ALVCH
3V
4.4
4.4
5.7
5.7
4.5
4.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
675
Logic Diagram
162373
3.3-V ABT 16-BIT TRANSPARENT
D-TYPE LATCHES
WITH 3-STATE OUTPUTS
1OE
● SN74LVTH162373: Output Ports Have
Equivalent 22-Ω Series Resistors
1D1
1LE
1
48
47
C1
2
1D
1Q1
To Seven Other Channels
2OE
2LE
2D1
24
25
36
C1
1D
FUNCTION TABLE
To Seven Other Channels
(each 8-bit section)
INPUTS
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LVTH
3V
UNIT
MAX
MAX
MAX
5
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
tw Pulse duration, LE high or low
Data before LE , data high
tsu Setup time
Data before LE , data low
Data after LE , data high
th Hold time
Data after LE , data low
tPLH
D
tPHL
tPLH
LE
tPHL
tPZH
OE
tPZL
tPHZ
OE
tPLZ
UNIT: ns
676
MAX or MIN
LVTH
3V
MIN
MIN
MIN
MIN
MIN
3
1
1
1
1
4.6
4
5.1
4.6
5.4
4.9
5.4
5.1
Q
MAX
Q
MAX
Q
MAX
Q
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
13
2Q1
Logic Diagram
162374
3.3-V ABT 16-BIT EDGE-TRIGGERED
D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
1OE
1CLK
● SN74LVTH162374: Output Ports Have
Equivalent 22-Ω Series Resistors
● SN74ALVCH162374: Output Ports Have
Equivalent 26-Ω Series Resistors
1D1
1
48
C1
47
2
1D
1Q1
To Seven Other Channels
2OE
2CLK
2D1
24
25
C1
36
1D
FUNCTION TABLE
13
2Q1
To Seven Other Channels
(each fllp-flop)
CLK
D
OUTPUT
Q
L
L
L
H
→→
INPUTS
OE
H
L
X
X
H
L
Q0
Z
L
X
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LVTH
3V
ALVCH
3V
UNIT
MAX
MAX
MAX
5
-12
12
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration, CLK high or low
Data before CLK , data high
tsu Setup time
Data before CLK , data low
Data after CLK , data high
th Hold time
Data after CLK , data low
tPLH
CLK
Q
tPHL
tPZH
OE
Q
tPZL
tPHZ
OE
Q
tPLZ
UNIT fmax : MHz other : ns
MAX or MIN
MIN
MIN
MIN
MIN
MIN
MAX
MAX
MAX
LVTH
3V
ALVCH
3V
160
3
1.8
1.8
0.8
0.8
5.3
4.9
5.6
4.9
5.4
5
150
3.3
1.9
1.9
0.5
0.5
4.6
4.6
5.2
5.2
4.5
4.5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
677
162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
● SN74ABTH162460: B-Port Outputs Have Equivalent 25-Ω Series Resistors
Logic Diagram
LEB4
LEB3
LEB2
LEB1
24
28
23
27
6
2
5
1
56
55
CLKENB
30
20
29
9
SEL1
SEL0
LEBA
CLKBA
CLKENBA
14
54
15
19
8
OEB1
OEB2
OEB3
OEB4
OEB
CE_SEL0
CE_SEL1
CLKENAB
21
P
M
U
X
LE
D
CLK
CE
52
LE
D
CLK
CE
51
CLK
CE
D
LE
49
10
26
12
48
LE
CLK
CE
D
LE
CLK
CE
D
LE
CLK
CE
D
LE
CLK
CE
D
678
LEAB1
CLKENAB Selector
CLK
CE
D
LE
1A
LEAB2
3
CE
CLK
D
LE
OEA
LEAB3
31
One of Four
Channels
CLKAB
LEAB4
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1B1
1B2
1B3
1B4
FUNCTION TABLE
A-TO-B STORAGE
(assuming OEB = L, OEBn = L)
A-TO-B OUTPUT ENABLE
INPUTS
OEB OEBn
H
H
H
L
L
H
L
L
INPUTS
CLKENAB CE_SEL1 CE_SEL0 CLKAB LEAB1 LEAB2 LEAB3 LEAB4
X
H
L
L
L
X
X
H or L
X
H
H
H
L
X
X
H or L
X
L
L
L
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
L
L
H
L
L
L
L
H
L
X
X
L
L
L
H
L
†n = 1, 2, 3, 4
B-TO-A STORAGE
(after point P)
L
→
L
L
L
L
L
L
L
L
L
OUTPUTS
B2
B3
A0
A0
A
A
A0
A0
A0
A0
A0
A
A0
A
A0
A0
A0
A0
B4
A0
A0
A0
A0
A0
A0
A
A0
B-TO-A STORAGE
(after point P)
SEL1 SEL0
L
L
L
H
H
L
H
H
L
L
L
H
H
L
H
H
L
L
L
H
H
L
H
H
INPUTS
CLKENBA CLKBA LEBA OEA
X
X
X
H
X
X
H
L
X
X
H
L
H
L
X
L
L
L
L
L
L
L
L
L
L
L
P
B1
B2
B3
B4
B1
B2
B3
B4
B10†
B20†
B30†
B40†
→→
INPUTS
CLKENB CLKBA LEB1 LEB2 LEB3 LEB4
X
X
L
L
L
H
X
L
L
L
X
H
X
X
L
L
H
L
X
H
X
L
L
L
L
B1
A
A
A0
A
A0
A0
A0
A0
→→→→→
OUTPUT
Bn
Z
Z
Z
Active
OUTPUT
A
X
L
H
A0†
L
H
A0†
B
X
L
H
X
L
H
X
† Output level before the indicated steady-state input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH (A port)
IOH (B port)
IOL (A port)
IOL (B port)
MAX or MIN
ABTH
UNIT
MAX
MAX
MAX
MAX
MAX
32
-32
-12
64
12
mA
mA
mA
mA
mA
INPUT
OUTPUT
MAX or MIN
B
A
MAX
OEA
A
MAX
OEA
A
MAX
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw Pulse duration
CLKAB high or low
CLKBA high or low
LEAB1, 2, 3 or 4 high
LEBA high
LEB1, 2, 3 or 4 high
A bus
CE_SEL0/1
Before CLKAB
CLKENAB
Before LEAB1, 2, 3, or 4
A bus
B bus
tsu Setup time
Before CLKBA
CLKENB
CLKENBA
LEB1, 2, 3 or 4
SEL0/1
Before LEB1, 2, 3, or 4
B bus
B bus
LEB1, 2, 3 or 4
Before CLKBA
SEL0/1
A bus
CE_SEL0/1
after CLKAB
CLKENAB
after LEAB1, 2, 3, or 4
A bus
B bus
th Hold time
after CLKBA
CLKENB
CLKENBA
SEL0/1
after LEB1, 2, 3, or 4
B bus
B bus
after CLKBA
SEL0/1
MAX or MIN
ABTH
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
160
3.8
4.5
2.8
2.8
3
2.5
3.2
3.2
3.6
3.8
2.3
2.5
4.3
4.5
3.2
4
4.4
4.3
0.5
1.1
0.5
1.2
1.3
1
1
0
1.5
0.4
0.1
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
UNIT: ns
A
B
MAX
OEB
B
MAX
OEB
B
MAX
OEB1, 2, 3, 4
B
MAX
OEB1, 2, 3, 4
B
MAX
CLKBA
A
MAX
CLKAB
B
MAX
LEBA
A
MAX
LEAB1, 2, 3, 4
B
MAX
LEBA1, 2, 3, 4
A
MAX
SEL
A
MAX
ABTH
6.5
6.5
5.6
5.5
5.9
6.5
6.2
6.5
6.8
6.3
6.2
5.8
6.6
6.2
5.3
4.9
7.4
7.7
6.5
6.5
5.8
5.8
6.2
6.2
7.2
6.8
7.5
6.9
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
679
162500
18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
● SN74ABT162500: B-Port Outputs Have Equivalent 25-Ω Series Resistors
Logic Diagram
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
1D
C1
CLK
1D
C1
CLK
To 17 Other Channels
680
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
54
B1
FUNCTION TABLE
INPUTS
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
→→
OEAB
L
H
H
H
H
H
H
H
L
A
X
L
H
L
H
X
X
OUTPUT
B
Z
L
H
L
H
B0‡
B0§
‡ Output level before the indicated steady-state input
conditions were established.
§ Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was low before LEAB went low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH (A port)
IOH (B port)
IOL (A port)
IOL (B port)
MAX or MIN
ABT
UNIT
MAX
MAX
MAX
MAX
MAX
36
-32
-12
64
12
mA
mA
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB
B before CLKBA
A before LEAB or LEBA CLK high
A before LEAB or LEBA CLK low
A after CLKAB or B after CLKBA
A after LEAB or B after LEBA
MAX or MIN
ABT
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
150
2.5
3
3.3
3.3
1
2.5
0
2
4.8
5.7
5.6
5.9
5.9
6
5.3
5.4
6.5
5.8
5.3
5.4
6.5
5.8
A or B
B or A
MAX
LEAB or LEBA
B or A
MAX
CLKAB or CLKBA
B or A
MAX
OEAB
B
MAX
OEAB
B
MAX
OEBA
A
MAX
OEBA
A
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
681
162501
18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
● SN74ABT162501: B-Port Outputs Have Equivalent 25-Ω Series Resistors
Logic Diagram
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
1D
C1
CLK
1D
C1
CLK
To 17 Other Channels
682
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
54
B1
FUNCTION TABLE†
→→
INPUTS
OEAB LEAB CLKAB
X
L
X
H
H
X
X
H
H
H
L
H
L
H
H
L
L
L
H
OUTPUT
Y
Z
L
H
L
H
B0‡
B0§
A
X
L
H
L
H
X
X
† A-to-B data flow is shown: B-to-A flow is similar
but uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state
input conditions were established, provided that
CLKAB was high before LEAB went low
§ Outoput level before the indicated steady-state
input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH (A port)
IOH (B port)
IOL (A port)
IOL (B port)
MAX or MIN
ABT
UNIT
MAX
MAX
MAX
MAX
MAX
36
-32
-12
64
12
mA
mA
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB
B before CLKBA
A before LEAB or LEBA CLK high
A before LEAB or LEBA CLK low
A after CLKAB or B after CLKBA
A after LEAB or B after LEBA
MAX or MIN
ABT
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
150
3
3.3
4.3
4.3
2.5
1
0
2
4.8
5.7
5.6
5.9
5.5
5.3
5.3
5.4
6.5
5.8
5.3
5.4
6.5
5.8
A or B
B or A
MAX
LEAB or LEBA
B or A
MAX
CLKAB or CLKBA
B or A
MAX
OEAB
B
MAX
OEAB
B
MAX
OEBA
A
MAX
OEBA
A
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
683
162525
18-BIT REGSTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
● SN74ALVCH162525: B-Port Outputs Have Equivalent 26-Ω Series Resistors
Logic Diagram
CLKAB
CLK1BA
CLK2BA
CLKENBA
CLKENAB
OEAB
OEBA
SEL
55
30
29
28
1
2
27
56
1 of 18 Channels
G1
CE
A1
3
C1
1D
1
1
CE
C1
1D
CE
C1
1D
684
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CE
C1
1D
CE
C1
1D
54
B1
FUNCTION TABLE
A-TO-B STORAGE(OEAB=L)
→→
INPUTS
CLKNAB OLKAB
H
X
L
L
A
X
L
H
OUTPUT
B
B0†
L
H
† Output level before the indicated steady-state
input conditions were established
B-TO-A STORAGE (OEBA = L)
→ →
→ → → →
INPUTS
CLKENBA CLK2BA CLK1BA SEL
H
X
X
X
L
H
X
L
H
X
L
L
L
L
B
X
L
H
L
H
OUTPUT
A
A0†
L
H
L‡
H‡
† Output level before the indicated steady-state input conditions
were established
‡ Three CLK1BA edges and one CLK2BA edge are needed to
propagate data from B to A when SEL is low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH (A port)
IOH (B port)
IOL (A port)
IOL (B port)
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
MAX
MAX
0.04
-24
-12
24
12
mA
mA
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration, CLK high or low
A data before CLKAB
B data before CLK2BA
B data before CLK1BA
tsu Setup time
SEL before CLK2BA
CLKENAB before CLKAB
CLKENBA before CLK1BA
CLKENBA before CLK2BA
A data after CLKAB
B data after CLK2BA
B data after CLK1BA
th Hold time
SEL after CLK2BA
CLKENAB after CLKAB
CLKENBA after CLK1BA
CLKENBA after CLK2BA
CLKAB
tpd
CLK2BA
OEBA
ten
OEAB
OEBA
tdis
OEAB
UNIT fmax : MHz other : ns
B
A
A
B
A
B
MAX or MIN
ALVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
150
3
1.3
1.7
1.1
3.3
1.6
2.1
2.2
0.9
0.6
1
0.1
0.3
0.1
0
4.7
4.2
5.1
5.7
4.9
4.9
MAX
MAX
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
685
162541
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
● SN74LVTH162541: Output Ports Have Equivalent 22-Ω Series Resistors
Logic Diagram
1OE1
1OE2
1A1
1
48
47
2
1Y1
To Seven Other Channels
2OE1
2OE2
2A1
24
25
36
13
2Y1
To Seven Other Channels
686
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FUNCTION TABLE
(each 8-bit section)
OE1
L
L
H
X
INPUTS
OE2
A
L
L
L
H
X
X
H
X
OUTPUT
Y
L
H
Z
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LVTH
3V
UNIT
MAX
MAX
MAX
5
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
LVTH
3V
4.1
4.1
5
4.8
5.9
5.4
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
687
162601
18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
● SN74ABT162601: B-Port Outputs Have Equivalent 25-Ω Series Resistors
● SN74ALVCH162601: B-Port Outputs Have Equivalent 26-Ω Series Resistors
Logic Diagram
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
CE
3
1D
C1
CLK
CE
1D
C1
CLK
To 17 Other Channels
688
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
54
B1
FUNCTION TABLE
INPUTS
LEAB
X
H
H
L
L
L
L
L
L
CLKAB
X
X
X
X
X
→→
CLKENAB OEAB
H
X
X
L
X
L
H
L
H
L
L
L
L
L
L
L
L
L
L
H
OUTPUT
B
A
X
L
H
X
X
L
H
X
X
Z
L
H
B0‡
B 0‡
L
H
B 0‡
B 0§
† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, CLKBA, and CLKENBA.
‡ Output level before the indicated steady-state input conditions
were established.
§ Output level before the indicated steady-state input conditions
were established, provided that CLKAB was low before LEAB went
low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ABT
ALVCH
3V
UNIT
MAX
MAX
MAX
MAX
MAX
36
-32
-12
64
12
0.04
-24
-12
24
12
mA
mA
mA
mA
mA
ICC
IOH (A port)
IOH (B port)
IOL (A port)
IOL (B port)
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
UNIT
fmax : MHz
LEAB or LEBA high
CLKAB or CLKBA high or low
Data before CLK
A before LEAB or B before LEBA , CLK high
A before LEAB or B before LEBA , CLK low
CLKEN before
Data after CLK
A after LEAB or B after LEBA , CLK high
A after LEAB or B after LEBA , CLK low
CLKEN after
MAX or MIN
ABT
ALVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
150
2.5
3
4.3
2.5
1
2.7
0
0.5
0.5
0
4.8
5.7
4
4.9
5
5
5.6
5.9
5.3
5
5.5
5.3
5.1
5.4
6.1
5.7
6.2
5.4
5.4
5.2
150
3.3
3.3
2.1
1.6
1.1
1.7
0.8
1.4
1.7
0.6
4.5
4.5
4.1
4.1
4.7
4.7
5.1
5.1
5
5
5.5
5.5
5.2
5.2
5.7
5.7
4.4
4.4
4.8
4.8
A
B
MAX
B
A
MAX
LEBA
A
MAX
LEAB
B
MAX
CLKBA
A
MAX
CLKAB
B
MAX
OEBA
A
MAX
OEAB
B
MAX
OEBA
A
MAX
OEAB
B
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
689
Logic Diagram
162721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
OE
1
56
● SN74ALVCH162721: Output Ports Have Equivalent
26-Ω Series Resistors
CLK
CLKEN
29
CE
C1
D1
55
1D
To 19 Other Channels
FUNCTION TABLE
(each flip-flop)
INPUTS
CLKEN CLK
X
H
L
L
L or H
L
X
X
→→
OE
L
L
L
L
H
D
X
H
L
X
X
OUTPUT
Q
Q0
H
L
Q0
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
690
fmax : MHz
INPUT
OUTPUT
CLK high or low
Data before CLK
CLKEN before CLK
Data after CLK
CLKEN after CLK
MAX or MIN
ALVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
150
3.3
3.1
2.7
0
0
5.3
5.3
5.8
5.8
5
5
CLK
Q
MAX
OE
Q
MAX
OE
Q
MAX
other : ns
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2
Q1
Logic Diagram
162820
3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS
AND 3-STATE OUTPUTS
● SN74ALVCH162820: Output Ports Have Equivalent
26-Ω Series Resistors
1OE
2OE
CLK
1
28
56
2
1Q1
C1
D1
55
1D
3
1Q2
To Nine Other Channels
FUNCTION TABLE
(each flip flop)
INPUT
OEn† CLK
L
↑
L
↑
L
L
X
H
D
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
†n = 1,2
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
fmax
tw Pulse duration CLK high or low
tsu Setup time
Data before CLK
th Hold time
Data after CLK
tPLH
CLK
tPHL
tPZH
OE
tPZL
tPHZ
OE
tPLZ
UNIT fmax : MHz other : ns
OUTPUT
MAX or MIN
ALVCH
3V
MIN
MIN
MIN
MIN
150
3.3
1.4
1
5.4
5.4
5.6
5.6
5
5
Q
MAX
Q
MAX
Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
691
162823
18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
● SN74ABT162823A: Output Ports Have Equivalent 25-Ω Series Resistors
Logic Diagram
OE1
OE2
16
5
4
CLK
15
7
D
3Y1
Q
1
SEL
2Y1
CLK
2
A1
1Y1
17
4Y1
18
To Six Other Channels
FUNCTION TABLE
INPUTS
CLR CLENK CLK
X
X
L
L
H
L
H
L
L
H
X
H
H
X
X
X
→→
OE
L
L
L
L
L
H
D
X
H
L
X
X
X
RECOMMENDED OPERATING CONDITIONS
OUTPUT
Q
L
H
L
Q0
Q0
Z
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
UNIT
MAX
MAX
MAX
80
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
692
fmax : MHz
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLR low
CLK high or low
CLR inactive
Data before CLK
CLKEN low before CLK
Data after CLK
CLKEN low after CLK
MAX or MIN
ABT
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
150
3.3
3.3
1.6
2
2.8
1.2
0.6
7.5
6.7
7
5.9
7
6.6
9
CLK
Q
CLR
Q
MAX
OE
Q
MAX
OE
Q
MAX
other : ns
MAX
Logic Diagram
162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
1OE1
1OE2
● SN74ABT162825: Output Ports Have Equivalent
25-Ω Series Resistors
1A1
1
56
55
2
1Y1
To Eight Other Channels
2OE1
2OE2
2A1
28
29
41
16
2Y1
To Eight Other Channels
FUNCTION TABLE
INPUTS
OE1
L
L
H
X
OE2
L
L
X
H
A
L
H
X
X
OUTPUT
Y
L
H
Z
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
UNIT
MAX
MAX
MAX
32
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
ABT
3.9
4.7
6.9
6.3
6.6
6.3
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
693
Logic Diagram
162827
1
20-BIT BUS BUFERS/DRIVERS
WITH 3-STATE OUTPUTS
1OE1
1OE2
● SN74ABT162827A: Output Ports Have Equivalent
25-Ω Series Resistors
● SN74ALVTH162827: Output Ports Have Equivalent
30-Ω Series Resistors
● SN74ALVCH162827: Output Ports Have Equivalent
26-Ω Series Resistors
1A1
56
55
2
1Y1
To Nine Other Channels
28
2OE1
2OE2
2A1
29
42
15
2Y1
To Nine Other Channels
FUNCTION TABLE
(each flip flop)
INPUTS
OE1 OE2
A
L
L
L
H
L
L
H
X
X
H
X
X
OUTPUT
Y
L
H
Z
Z
†n = 1,2
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
MAX
MAX
MAX
32
-12
12
ALVTH ALVCH
3V
3V
5.5
-12
12
0.04
-12
12
UNIT
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
694
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
ABT
3.9
4.7
6.9
6.3
6.6
6.3
ALVTH ALVCH
3V
3V
3.9
3.7
5.6
4.1
6.3
5.1
3.8
3.8
5.1
5.1
4.7
4.7
Logic Diagram
162830
1-BIT TO 2-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
OE2
OE1
● SN74ALVCH162830, SN74ALVCHS162830: Output
Ports Have Equivalent 26-Ω Series Resistors
21
20
5
A1
1Y1
7
4
2Y1
To 17 Other Channels
FUNCTION TABLE
OE1
L
L
H
H
L
L
H
INPUTS
OE2
H
H
L
L
L
L
H
A
H
L
H
L
H
L
X
OUTPUTS
1Yn 2Yn
H
Z
L
Z
Z
H
L
Z
H
H
L
L
Z
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
MAX
MAX
MAX
ICC
IOH
IOL
ALVCH ALVCHS
3V
3V
0.04
-12
12
0.04
-12
12
UNIT
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
MAX or MIN
A
Y
MAX
OE
Y
MAX
OE
Y
MAX
ALVCH ALVCHS
3V
3V
3.5
3.5
4.8
4.8
5.2
5.2
3.5
3.5
4.8
4.8
5.2
5.2
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
695
162831
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
● SN74ALVC162831, SN74ALVCH162831: Output Ports Have Equivalent 26-Ω Series Resistors
Logic Diagram
OE1
OE2
20
5
4
CLK
19
8
D
3Y1
Q
1
SEL
2Y1
CLK
2
A1
1Y1
21
4Y1
22
To Eight Other Channels
FUNCTION TABLE
→→
OE
H
L
L
L
L
INPUTS
SEL CLK
X
X
H
X
H
X
L
L
A
X
L
H
L
H
OUTPUT
Y
Z
L
H
L
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALVC
3V
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-12
12
0.04
-12
12
mA
mA
mA
ICC
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
fmax
tw Pulse duration CLK high or low
tsu Setup time
A data before CLK
th Hold time
A data after CLK
tPLH
A
tPHL
tPLH
CLK
tPHL
tPLH
SEL
tPHL
tPZH
OE
tPZL
tPHZ
OE
tPLZ
UNIT fmax : MHz other : ns
696
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OUTPUT
MAX or MIN
ALVC
3V
ALVCH
3V
MIN
MIN
MIN
MIN
150
3.3
1.6
1.1
4.3
4.3
4.7
4.7
4.8
4.8
5.1
5.1
5.1
5.1
150
3.3
1.6
1.1
4.3
4.3
4.7
4.7
4.8
4.8
5.1
5.1
5.1
5.1
Y
MAX
Y
MAX
Y
MAX
Y
MAX
Y
MAX
162832
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
● SN74ALVCH162832: Output Ports Have Equivalent 26-Ω Series Resistors
Logic Diagram
OE1
OE2
16
5
4
CLK
15
7
D
3Y1
Q
1
SEL
2Y1
CLK
2
A1
1Y1
17
4Y1
18
To Six Other Channels
FUNCTION TABLE
INPUTS
SEL CLK
X
X
H
X
H
X
L
L
→→
OE
H
L
L
L
L
A
X
L
H
L
H
OUTPUT
Y
Z
L
H
L
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
fmax
tw Pulse duration CLK high or low
tsu Setup time
A data before CLK
th Hold time
A data after CLK
tPLH
A
tPHL
tPLH
CLK
tPHL
tPLH
SEL
tPHL
tPZH
OE
tPZL
tPHZ
OE
tPLZ
UNIT fmax : MHz other : ns
OUTPUT
MAX or MIN
ALVCH
3V
MIN
MIN
MIN
MIN
150
3.3
1.6
1.1
4.3
4.3
4.7
4.7
4.8
4.8
5.1
5.1
5.1
5.1
Y
MAX
Y
MAX
Y
MAX
Y
MAX
Y
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
697
Logic Diagram
162834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
OE
CLK
● SN74ALVC162834: Outputs Have Equivalent
26-Ω Series Resistors
LE
A1
27
30
28
54
1D
C1
CLK
To 17 Other Channels
FUNCTION TABLE
INPUTS
LE
CLK
X
X
L
X
L
X
H
H
H
H
H
L
→→
OE
H
L
L
L
L
L
L
OUTPUT
Y
Z
L
H
L
H
Y0†
Y 0‡
A
X
L
H
L
H
X
X
† Output level before the indicated steady-state
input conditions were established, provided that
CLK is high before LE goes high
‡ Output level before the indicated steady-state
input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVC
3V
UNIT
MAX
MAX
MAX
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
698
fmax : MHz
LE low
CLK high or low
Data before CLK
Data before LE , CLK high
Data before LE , CLK low
A data after CLK
Data after LE , CLK high
Data after LE , CLK low
MAX or MIN
ALVC
3V
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
150
3.3
3.3
1.7
1.9
1.5
0.7
0.9
0.9
4.2
4.2
5.8
5.8
5.4
5.4
5.9
5.9
5
5
A
Y
MAX
LE
Y
MAX
CLK
Y
MAX
OE
Y
MAX
OE
Y
MAX
other : ns
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
3
Y1
Logic Diagram
162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
OE
● SN74ALVC162835, SN74ALVCH162835: Output Port
Has Equivalent 26-Ω Series Resistors
CLK
LE
A1
27
30
28
54
1D
C1
3
Y1
CLK
To 17 Other Channels
FUNCTION TABLE
INPUTS
CLK
LE
X
X
H
X
H
X
L
L
L
L or H
→→
OE
H
L
L
L
L
L
OUTPUT
Y
Z
L
H
L
H
Y0†
A
X
L
H
L
H
X
† Output level before the indicated steady-state
input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVC
3V
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-12
12
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
fmax : MHz
LE low
CLK high or low
Data before CLK
Data before LE , CLK high
Data before LE , CLK low
A data after CLK
Data after LE , CLK high
Data after LE , CLK low
MAX or MIN
ALVC
3V
ALVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
150
3.3
3.3
1.7
1.5
1
0.7
1.4
1.4
4.2
4.2
5.1
5.1
5.4
5.4
5.5
5.5
4.5
4.5
150
3.3
3.3
1.7
1.5
1
0.7
1.4
1.4
4.2
4.2
5.1
5.1
5.4
5.4
5.5
5.5
4.5
4.5
A
Y
MAX
LE
Y
MAX
CLK
Y
MAX
OE
Y
MAX
OE
Y
MAX
other : ns
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
699
Logic Diagram
162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
OE
CLK
● SN74ALVC162836, SN74ALVCH162836: Output Port
Has Equivalent 26-Ω Series Resistors
LE
A1
1
56
29
55
1D
C1
CLK
To 19 Other Channels
FUNCTION TABLE
INPUTS
CLK
LE
X
X
L
X
X
L
H
H
L or H
H
→→
OE
H
L
L
L
L
L
OUTPUT
Y
Z
L
H
L
H
Y0†
A
X
L
H
L
H
X
† Output level before the indicated steady-state
input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ALVC
3V
ALVCH
3V
UNIT
MAX
MAX
MAX
0.04
-12
12
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT
700
fmax : MHz
LE low
CLK high or low
Data before CLK
Data before LE , CLK high
Data before LE , CLK low
A data after CLK
Data after LE , CLK high
Data after LE , CLK low
MAX or MIN
ALVC
3V
ALVCH
3V
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
150
3.3
3.3
1.5
1.3
1.2
0.9
1.1
1.1
4
4
5.1
5.1
5
5
5.5
5.5
5.1
5.1
150
3.3
3.3
1.5
1.3
1.2
0.9
1.1
1.1
4
4
5.1
5.1
5
5
5.5
5.5
5.1
5.1
A
Y
MAX
LE
Y
MAX
CLK
Y
MAX
OE
Y
MAX
OE
Y
MAX
other : ns
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2
Y1
Logic Diagram
162841
20-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
1OE
1LE
● SN74ABT162841: Output Ports Have Equivalent
25-Ω Series Resistors
● SN74ALVCH162841: Output Ports Have
Equivalent 26-Ω Series Resistors
1
56
C1
1D1
55
2
1D
1Q1
To Nine Other Channels
2OE
2LE
FUNCTION TABLE
28
29
(each 10-bit latch)
OE
L
L
L
H
INPUTS
LE
H
H
L
X
D
H
L
X
X
C1
OUTPUT
Q
H
L
Q0
Z
2D1
42
1D
15
2Q1
To Nine Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
ABT
ALVCH
3V
UNIT
MAX
MAX
MAX
89
-12
12
0.04
-12
12
mA
mA
mA
SWITCHING CHARACTERISTICS
PARAMETER
tw Pulse duration
tsu Setup time
th Hold time
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
UNIT: ns
INPUT
OUTPUT
LE high or low
Data before LE
Data after LE
MAX or MIN
ABT
ALVCH
3V
MIN
MIN
MIN
4
0.8
1.8
5.2
6
5.4
5.8
5.7
6.5
6.5
7.1
3.3
1.1
1.1
4.3
4.3
4.7
4.7
5.3
5.3
4.4
4.4
D
Q
MAX
LE
Q
MAX
OE
Q
MAX
OE
Q
MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
701
Logic Diagram
164245
16-BIT TRANSCEIVER AND 3.3-V TO 5-V
SHIFTER
WITH 3-STATE OUTPUTS
1
1DIR
48
● SN74ALVC164245:
A port has VCCA, which is set to operate at 2.5 V
and 3.3 V
B port has VCCB, which is set to operate at 3.3 V
and 5 V
● SN74AVCB164245, SN74AVCBH164245:
The A-port is designed to track VCCA, VCCA accepts
any supply voltage from 1.4 V to 3.6 V
The B-port is designed to track VCCB, VCCB accepts
any supply voltage from 1.4 V to 3.6 V
47
1A1
2
24
25
2A1
13
(each 8-bit section)
DIR
L
L
H
L
H
X
OPERATION
B data to A bus
A data to B bus
Isolation
To Seven Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX or MIN
ALVC
AVCB
AVCBH
UNIT
MAX
MAX
MAX
MAX
MAX
MAX
0.04
0.02
-24
24
-12
12
0.04
-8
8
0.04
-8
8
mA
mA
mA
mA
mA
mA
ICC (5V)
ICC (3V)
IOH (5V)
IOL (5V)
IOH (2.3V)
IOL (2.3V)
SWITCHING CHARACTERISTICS
ALVC
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZL
tPZH
tPZL
tPZH
tPLZ
tPHZ
tPLZ
tPHZ
UNIT: ns
702
INPUT
OUTPUT
MAX or MIN
A
B
MAX
B
A
MAX
OE
B
MAX
OE
A
MAX
OE
B
MAX
OE
A
MAX
VCCB : 3V
VCCA : 2.3V
7.6
7.6
7.6
7.6
11.5
11.5
12.3
12.3
10.5
10.5
9.3
9.3
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
VCCB : 5V
VCCA : 3V
5.8
5.8
5.8
5.8
8.9
8.9
9.1
9.1
9.5
9.5
8.6
8.6
2OE
36
FUNCTION TABLE
OE
1B1
To Seven Other Channels
2DIR
INPUTS
1OE
AVCB
AVCBH
VCCB : 3V
VCCB : 3V
VCCA : 2.3V VCCA : 2.3V
3.4
3.4
3.4
3.4
3.7
3.7
3.7
3.7
5.1
5.1
5.1
5.1
4.2
4.2
4.2
4.2
3.3
3.3
3.3
3.3
3
3
3
3
2B1
322374
3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
● Output Ports Have Equivalent 22-Ω Series Resistors
Logic Diagram
1OE
1CLK
1D1
A3
2OE
A4
2CLK
C1
A5
A2
1D
1Q1
2D1
H3
H4
C1
E5
3CLK
3D1
J3
4OE
J4
4CLK
C1
J5
J2
1D
2Q1
To Seven Other Channels
To Seven Other Channels
3OE
E2
1D
3Q1
4D1
T3
T4
N2
C1
N5
4Q1
1D
To Seven Other Channels
To Seven Other Channels
FUNCTION TABLE
(each 8bit flip-flop)
INPUTS
OE
L
L
L
H
CLK
↑
↑
H or L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
SWITCHING CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
PARAMETER
ICC
IOH
IOL
MAX or MIN
LVTH
3V
UNIT
MAX
MAX
MAX
10
-12
12
mA
mA
mA
PARAMETER
INPUT
OUTPUT
fmax
tw Pulse duration, CLK high or low
Data before CLK , data high
tsu Setup time
Data before CLK , data low
Data after CLK , data high
th Hold time
Data after CLK , data low
tPLH
CLK
Q
tPHL
tPZH
OE
Q
tPZL
tPHZ
OE
Q
tPLZ
UNIT fmax : MHz other : ns
MAX or MIN
MIN
MIN
MIN
MIN
MIN
MAX
MAX
MAX
LVTH
3V
160
3
1.8
1.8
0.8
0.8
5.3
4.9
5.6
4.9
5.4
5
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
703
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A070802
Printed in Japan
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