CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
A METHOD TO INCREASE TESTABILITY OF
LSI/VLSI CIRCUITS
A thesis submitted in partial satisfaction
of the requirements for the degree of
Master of Science in
Engineering
by
Babak Nikoomanesh
January 1986
The Thesis of Babak Nikoomanesh is approved:
Dr.
v.
Metz1er
/'
Dr. Mohammad R. Roosta
Committee Chair
California State University, Northridge
ii
To my parents for their continuous support, and
to my wife for all her efforts to help me with
this thesis.
Also my thanks to Dr. Roosta who
served as my committee chairman and helped me a
great deal.
iii
TABLE OF CONTENT.S
Page
DEDICATION .
iii
• .
. vi
LIST OF FIGURES
ABSTRACT .
.
.
. viii
.
CHAPTER
I.
II.
III.
IV.
INTRODUCTION
1
1.
Introduction
1
2.
Research Objectives
2
FAULT INTRODUCTION
3
1.
Fault Definition
3
2.
Masking a Fault
3
3.
Fault Types . .
5
4.
Fault Equivalencies
6
AN OVERVIEW OF METHODS FOR FAULT DETECTION
7
1.
One-Dimensional Path Sensitizing
7
2.
Boolean Difference
9
3.·
D Algorithm . . . . . .
LSI/VLSI TECHNOLOGY; RELIABILITY AND
FAULT PATHOLOGY .
. . . . . .
10
14
14
1.
Introduction
2.
Gate-Oxide
3.
Contact Metallurgy Problem
17
4.
Bridging Faults and Opens . .
18
5.
Radiation Effects .
19
Br~akdown
iv
14
CHAPTER
V.
VI.
VII.
VIII.
Page
LSI/VLSI TESTING; THE PROBLEM AREAS
. . . . 21
1.
Introduction . . . .
. .
. 21
2.
Timing and Synchronization
. 22
3.
Verification . .
4•
Accessibility
5.
Automated Test Equipment .
~
•
•
•
• 23
•
• 24
•
• 24
DESIGN FOR TESTABILITY; THE PREVIOUS WORK
. 29
1.
Level Sensistive Scan Design (LSSD)
. 29
2.
Signature Analysis .
•
• 32
3.
Syndrome Testing .
.
. 35
INCREASED CONTROLLABILITY AND OBSERVABILITY
BY UTILIZING SPECIAL FEATURE GATES . . . . 39
1.
Introduction . .
2.
The Bi-Functional Gate .
3.
FET Structure of the Bi-Functional
Gate . . . . . . . . . . . . . .
. 40
4.
Partitioning .
•
5.
Examples . .
• 46
6.
The Generalized Algorithm
CONCLUSION . . . .
1.
Conclusion .
2.
Directions for Future Research
•
•
• 39
•
• 39
•
44
• 59
•
• • 67
•
•
• 67
•
• 68
REFERENCES
69
APPENDIX - DATA SHEETS
•
v
• 73
LIST OF FIGURES
Figure
2-1.
Page
Example of a Redundant Circuit With
Undetectable Fault . .
. •.
4
3-1.
Example of One Dimensional Path Sensitizing
8
3-2.
D Algorithm Flowchart
11
3-3.
Line Justification Flowchart .
12
4-1.
Maximum Time in Breakdown Versus Thickness
of Sio with Al and Si Electrodes in MOS
2
Capacitor Structures . . . . . .
16
5-l.
Block Diagram of a VLSI Tester .
26
5-2.
Block Diagram of Pattern Generator .
28
6-1.
Shift Register Latch .
30
6-2.
An LSSD LSI Chip .
30
6-3.
Block Diagram oj: Signature Analysis
34
6-4.
Example of Combinational Circuit With "OR"
Gate Termination . . . . . . . . . . . .
38
7-1.
Bi-functional "NAND" .
41
7-2.
Bi-functional "NOR"
42
7-3.
FET Structure for Bi-functional "NAND" .
43
7-4.
FET Structure for Bi-functional "NOR"
45
7-5.
ALU Input Partition
48
7-6.
ALU Output Partition (Part 1)
49
7-7.
ALU Output Partition (Part 2)
50
7-8.
ALU Carry Bit Partition
51
7-9.
Modified ALU Input Partition
53
vi
Figure
Page
7-10.
Partition Test Generation Table .
. . 55
7-11.
Input Partition . .
.
7-12.
Output Partition
• • 58
7-13.
Modified Output Partition
7-14.
Modified Input Partition
7-15.
Procedure 1 Flowchart .
7-16.
Procedure 2 Flowchart .
.•.
vii
•
. 57
• 59
6Q
.
•
•
•
•
• 65
•
• 66
ABSTRACT
A METHOD TO INCREASE TESTABILITY AND FAULT
DETECTION OF LSI/VLSI CIRCUITS
by
Babak Nikoomanesh
Master of Science in Engineering
The objective of this tnesis is to develop an
algorithm for testing of LSI/VLSI circuits, which will
result in increased controllability and observability of
the inaccessible nodes.
This algorithm utilizes a new type of gates
introduced as bi-functional gates that work in two modes
namely 1) functional 2) testing.
The algorithm determines wherein a given
combinational circuit, logic gates should be replaced
with these bi-functional gates to obtain maximum testability of that circuit.
The applicability of the algorithm is evaluated by
considering two realistic examples.
viii
Th~s
thesis also includes a comparative study of
the existing techniques in the field of design for testability, as well as a review of some of the basic fault
detection methods.
ix
Chapter I
INTRODUCTION
I.
Introduction
Recent advances in LSI/VLSI technology have led to
packages of increasing complexity.
Besides the consider-
able problem of testing the packages by themselves, the
incorporation of these into larger designs has caused the
cost of test generation to grow exponentially.
In many
cases the testing cost has reached beyond the practical
limits for the device manufacturers.
The field of design for testability although in its
infancy, is receiving much attention presently, because of
the possible solutions it could offer to the expensive
testing problems.
There have been some successful methods implemented
in design for testability such as LSSD (Level Sensitive
Scan Design), signature analysis and syndrome testing.
Here, we discuss the advantages and disadvantages of these
methods.
We also present a new algorithm which results in
increased controllability and observability.
In Chapter 2, the concept of fault, its nature and
behavior is introduced.
Chapter 3 covers some of the
developed methods for fault detection.
1
Chapter 4
2
concentrates on the VLSI technology as far as its
reliability and fault pathology.
In Chapter 5 the prob-
lem areas in testing of LSI/VLSI circuits are discussed.
Chapter 6 reviews three of the methods that have been
developed in design for testability.
In Chapter 7, a new
algorithm is introduced to increase testability of LSI/
VLSI circuits.
rithm.
Examples are given to justify the algo-
In the last chapter the summarized results and
conclusions are discussed.
2.
Research Objectives
The main theme of this research is to evaluate LSI
and VLSI circuits for their testability problems.
The concentration areas are the following:
1) Utilizing the partition approach to increase
controllability and observability.
2) Improving fault coverage using special gates.
3) Development of an algorithm to obtain the optimal
points where in a given design the gates should be replaced with these special feature gates.
4) Evaluation of existing methods in design for
testability.
Chapter II
FAULT INTRODUCTION
1.
Fault Definition
In any circuit composed of logic gates there is a
possibility of the occurrence of a fault.
A fault is defined to have occurred when any circuit
variable assumes a value (1, 0, or X) which differs from
the expected value, i.e., violates the original circuit
equations.
2.
Masking a Fault
The presence of an internal or input fault may not
be observable at the circuit outputs in which case the
fault is considered to be masked.
A single fault may be masked as a result of 1) reconvergent fanout where unequal parity changes have occurred;
2) circuit redundancy deliberately inserted for fault tolerance; 3) the previous occurrence of undetectable faults.
Masked faults are undetectable by definition since the
observed circuit behavior is correct.
Figure 2-6 shows
a redundant circuit with undetectable fault.
In Figure
2-1, if the output of gate 1 is stuck at zero
(S-A-~)
3
the
4
y
Fig. 2-l.
=
Example of a redundant circuit
with undetectable fault.
5
fault is undetectable, because forcing a 1 on the output
of gate 1 will result a 1 on the output of gates
Therefore, the output of gate
!
~or
3.
will never see the fault
and the fault is said to be masked.
3.
Fault Types
Faults may be indeterminate in value (suspended
between logical 1 and logical
(exhibiting a 0 and a 1) .
Q)
or determinate in value
Faults may be transient (inter-
mittent, time varying) in which case they are difficult to
detect.
Faults may be permanent, in which case they are
easy to detect if they are not masked and if a proper test
is used.
Faults may be multiple in occurrence which is usually
considered a rare event.
(In LSI and VLSI the probability
of occurrence of multiple faults is increased.)
Faults may occur singly which is the most likely
event.
Further, multiple faults may occur in such a man-
ner that each fault represents a single fault by itself
named as its equivalent fault.
discussed in the next·section.)
(Fault equivalencies are
A test which detects the
presence of this equivalent single fault is sufficient to
detect the existence of the fault.
6
4.
Fault Equivalencies
Fault ct is said to be equivalent to fault B if there
is no test which distinguishes a and B.
There are several
fault equivalencies that exist which are useful in fault
detection and which make fault location considerably more
difficult.
Some of these equivalencies are:
1) One or more inputs to an
~oR"
gate is stuck at 1
(S-a-1) is equivalent to the output of that gate S-a-1.
2) One or more inputs to an "AND" gate is S-a-o is
equivalent to the output.off that gate S-A-o.
3) All inputs to an "OR" gate S-A-o is equivalent to
the output of that gate S-A-o.
4) All inputs to an "AND" gate S-A-1 is equivalent
to the output of that gate S-A-1.
5) Failures on both the inputs and the output of a
gate will propagate the gate output failure; making the
input faulting.
And
6) Any gate output fault has, as an equivalent, a
single gate input fault or multiple input faults.
How-
ever, any gate input fault does not necessarily have an
equivalent output fault.
Chapter III
AN OVERVIEW OF METHODS FOR FAULT DETECTION
1.
One-Dimensional Path Sensitizing
Path Sensitizing is a method to generate a test to
detect a fault through sensitizing a particular path in
the circuit.
A fault is chosen and traced forward, toward
the circuit output, setting variables, such that the output will reflect the occurrence of the fault.
for an input Xi to detect a fault a S-a-J, J
In order
=
0,1 the
input Xi must cause the signal A in the normal (fault free)
circuit to take the value J.
An example is given in
Figure 3-1, to detect a Gl:S-a-1, an input Xi must be such
that Gl(Xi)
0.
For this circuit, this implies that X2
to propagate the error signal through G3,
(X
1
x1
= X3 = 0, now
must be high
= 1), and to propagate it through the last stage GS,
G4 must be 0.
Having
x1 =
1 guarantees a zero on G4,
therefore, the test vector required is
x1 x2 x3 .
One dimensional path sensitizing works for an
irredundant fan-out free combinational circuits.
The
tests produced are minimized as a routine coverage problem.
7
8
G3
GS
G4
Fig. 3-1.
Example of one dimensional path
sensitizing
9
2.
Boolean Difference
Boolean difference is notationally defined as a
pseudo calculus representation and has been based on
knowledge of circuit logic configuration.
Consider a combinational circuit c which realizes
. .,
the function f(X , x ,
2
1
X
n
Let
) •
_ f.(o)
.1.
and
· ·' xi-1' 1 • xi+l'
• ,
The set of tests which detect the fault a.
X
n
)
:: f. (1)
.1.
(Xi S-a-o)
corresponds to the 1-points of the function.
T
=
f (X) E9 fa. (X)
Since Fa(X) = f. (0), by Shannon's expansion theorem we
.1.
have that:
T =
(Xi- fi(O)
T = Xi .
or
( f i ( 1)
The factor fi ( 1)
EfJ
+Xi . fi(l))
ffi fi(O)
f i ( 0) )
EfJ
fi ( 0) , \vhich is referred to as the
boolean difference of f with respect to Xi, is denoted by
df
dX . and represents all the conditions under which the
.1.
value of f is sensitive to the value of Xi alone.
Thus Xi .
( 4)
~~i represents theset of all the tests for the
fault X. S-a-o since X. applies the opposite signal value
.1.
.1.
df
on the faulty input and the factor dXi ensures that this
erroneous signal affects the value of f.
10
3.
D Algorithm
D Algorithm is an extension to Path Sensitization
method, which is developed in an algorithmic way to sensitize more than one path if required, and to propagate the
fault to a primary output.
To facilitate the multiple path sensitization
process, a new algebra was introduced.
Symbol D repre-
sents a signal which has the value 1 in the normal circuit
and 0 in the faulty circuit (1/0), and
D represents
a
signal which has a value 0 in the normal circuit and 1 in
the faulty circuit.
The flow chart for the D Algorithm is shown in
Figure 3-2 and Figure 3-3.
It is summarized in the fol-
lowing steps.
(1) Select a primitive D-cube of fault under
consideration.
This produces an error signal D or D at
the site of fault.
(2) Implication; some gate inputs or outputs maybe
specified so as to uniquely imply values on other signals
in the circuit.
The implication procedure traces such
signal determination both forwards and backwards.
(3) D-Drive; the D-frontier consists of the sets of
all elements whose output values are unspecified but whose
input has some signal D or D.
D drive attempts to propa-
gate the D or D of the inputs of an associated element to
the outputs of that associated element.
11
Input Circuit Description;
Construct necessary dolo
structures and number lines*
Select fault; Initialize
index** I=O; Initialize test
cube (tc
to be completely
unspecified
r'
l
none
exists
Select c, o pdcf I
I
* * *
•
No test exists
for fault, circuit
is redundant
inconsistent Intersect c with previous test
cube and perform implication
to generate new test cube tc 1
consistent
Is there oDor Don
any primary output ?
yes
2.20b)
no
Increment
I by 1
I
Construct new D-frontier,
At
I
Decrement
•
Select an element Er from
AI, delete S from AI
!
Line
Justification
Subprogram
(See Figure
<f l
none
exists
I by I to
backtrack
to previous
0-frontier
or to next
pdcf.
none
exists Select o propagation
D-cube of Er OS c***
* **
I
Fig. 3-2.
Source:
D Algorithm Flowchart
Ref. 5
yes
-f_o?
no
12
Begin
'
Set index !',...!
• !
Flag all lines in
fer' which ore
not justified
none
exists
Test /las been
generated
I
!
Select flagged
line ftr· w1tll
largest number.
1
~
~
Select a primitive
cube c, to justify
~·
fl
* *
l
Intersect c wil/1
tci' and perform
inconsistent implication to
generate tcfi'+IJ
l
consistent
Increment I' by/
J
Fig. 3-3.
Source:
Decrement I' and
backtrack to
select another
primitive cube.
none
exists
I
jno
.
J\. Is!'=!?
_fes
Justification
impossible,
backtrack to
cons1der another
propagation
0-cube of Er
cb
Line Justification Flowchart
Ref. 5
13
(4) Implication of the D-drive.
(5) Repeat (3) and (4) until the faulty signal has
reached an output terminal.
Chapter IV
LSI/VLSI TECHNOLOGY; RELIABILITY AND
FAULT PATHOLOGY
1.
Introduction
In this chapter, the LSI/VLSI technology is reviewed.
It is important to understand the specifics of VLSI environment and the differences from our past knowledge and
experience in the fault modeling and test generation.
It
is shown that a variety of the new faults and conditions
exist which is of great concern to test generation and
test strategies applied.
Generally VLSI reliability problems can be divided
into two categories.
In the first category, there are
problems related to VLSI technology and effects that could
be overcome by technological improvements alone.
The
second category is wider and contains problems of different nature such as; design, modeling and testability.
2.
Gate-Oxide Breakdown
Gate-oxide breakdown is one of the major reliability
concerns in devices with reduced dimensions.
Gate-oxide
reliability or wear out phenomena, in terms of time to
14
15
failure t 1 can be expressed as:
t
=
tmax exp [A(EBD- Ei)]
where t max is the wear out time for an intrinsic oxide,
EBD is the experimentally observed breakdown field of the
oxide, E. is the intrinsic oxide breakdown field, and A
l
is a constant. (26).
For given t
max
, it has been determined experimentally
that the mean time to failure t is about 1 decade for each
mv/cm difference between the intrinsic and experimentally
observed breakdown field.
When the thickness of the oxide
is decreased the breakdown field increases.
As a result
the mean time to failure of a thin oxide increases for a
given field.
The wear out phenomena is also electrode dependent.
Figure 4-l shows a comparison of maximum time to failure
of aluminum and silicon electrodes on MOS capacitor
structures.
It is clear from the results, that for a given
applied field on the MOS structures, those with silicon
electrodes resist wear-out about 3 orders of magnitude in
time better than the aluminum electrodes do over a 25 nm
oxide layer.
of
Thus in addition to the well know advantages
self-aligned silicon-gate MOSFET technology for
achieving greater density and superior performance, the
enhanced resistance to wear-out of an oxide layer further
strengthens the case for employing a silicon gate approach in scaled down devices.
16
d
6
ox
(nm)
Poly-Si Electrode
=
Eox
5
/
5 MV/Cm
3QQO C
/
/
Poly-Si
/
/
--------- Al
/
Al Electrode
/
3
/
/
/
2
/
/
Sio
Si
2
0
-
/
/
1.0
1.2 1.4 1.6 1.8 2.0
2.2
Thickness of Sio , d
, in Log(nm)
2
ox
Fig. 4-1.
Maximum time in breakdown versus
thickness of Sio with Al and Si
2
electrodes in MOS Capacitor
structures.
17
Gate-oxide breakdown, can cause stuck-at and
reconfiguration types of faults, depending on where in
the MOS structure the gate-oxide breakdown occurs.
3.
Contact Metallurgy Problem
Contact resistance is fast becoming of considerable
importance, because it may represent a fundamental limit
or at least a major obstacle that must be contended with,
as device dimensions continute to shrink. The resistance
2
of 1 urn contact to silicon could range between 1000 and
100, if contact interfacial resistivity falls in to the
10
-5
and 10
-7
A . 25 um
4000 to 400.
0/crn
2
2
range, respectively (26).
co11tact could exhibit values ranging from
For the 1 urn MOSFET technology the smallest
contact holes gave contact resistances of 10-200 which
are small compared to circuit impedances.
However the
design problems for MOSFETS could be serious if additional problems such as process contamination and interfacial imperfections were to come into the picture.
Thus,
like temperature, contact resistance is a potential limit
to be considered, and work is needed to understand the
limits imposed by surfaces and the manner in which surfaces are processed.
The majority of faults caused by open contacts
results in stuck-at type faults.
Bridging faults due to
18
shorts between two adjacent metal lines are a common type
and some studies show that they account for up to 39% of
the total faults of the Ic, while open metal line account
for 15% of the faults (26).
If a circuit is designed in such a way that the
current density exceeds a certain limiting value, it will
cause metal lines in the circuit to open after a short
period of time.
To prevent this effect, a circuit should
be carefully designed making sure that the current density in any part of the circuit is kept well below the
limit.
4.
Bridging Faults and Opens
Shorts between adjacent lines, or shorts between
adjacent diffusion lines are a very common type of faults
encountered in MOSFET circuit technology.
These faults in
some cases account for up to 49% of all types of faults
encountered (11).
Although this type of fault is very
common, their effect can be quite uncommon and difficult
to model.
In addition to stuck-at faults that are easily
modeled at the gate level, bridging faults may produce
reconfiguration type of faults that results in a logic
circuit with logic behavior that differs from the nonfaulty
circuit.
The commonly used gate level stuck-at model does
not allow the representation of these possible physical
19
failures, making an already difficult problem of fault
modeling and related functional testing even more difficult.
It is likely that this type of problems will result
in additional design rules imposed to a VLSI circuit
designer.
Opens in metal lines, diffusion or Poly silicon, is
another large contributor to the total of all on-chip
faults.
5.
Radiation Effects
As the device features scale down the amount of
electrical charge, required to be introduced in order to
bring the device from one stable state to another stable
state becomes smaller and the device becomes more sensitive to external interferences, one of them being radiation.
This shrinking of geometry is the reason for
appearance of the so called "soft errors,'' which were
completely unknown until recent years.
Today, the design
of large dynamic memories is limited. by the soft errors
rather than by the problems associated with achieving
high density.
The characteristics of soft errors is their random
occurrence and their disappearance in the process of rewriting in to the faulty location within the memory.
20
They are caused by the radiation of the alpha particles
from the housing and their effect is more pronounced as
the quantity of the charge used to store the information
approaches the ionization charge that the alpha particle
of a particular energy is able to produce in the silicon
sub-strate and which amounts to 10
6
electron-hole pairs.
Another important consideration is the effect of
cosmic rays at sea level, on a device with reduced geometry.
There are two general classes of interactions of
cosmic rays.
Energy charged particles can penetrate the
semiconductor and leave an ionization wake of electronhole pairs, or they can directly interact with a single
silicon nucleas and cause a variety of heavy recoiling
charged particles, which also creates a burst of electron
hole-pairs.
Chapter V
LSI/VLSI TESTING; THE PROBLEM AREAS
1.
Introduction
The problems involved in testing LSI and VLSI have
increased considerably in the last few years for both the
manufacturer and the user of the devices.
In 1976, the
complexity of the LSI devices was 100 logic gates per
square milimiter.
over
With the current VLSI devices there are
100,000 gates on the areas approach 1 cm 2 .
This
improvement has given the designer the freedom to increase
the performance of the chip even more.
32 bit micro-
processors and 1 M bit RAM have already been introduced.
The testability of the devices rather than the
technology may become the limiting factor in their development.
Limited access into VLSI circuits is one of the
limitations imposed to testing environment.
The problem is how to apply a suitable set of vectors
to the input pins of the chip and analyze the resulting
data patterns to locate the fault.
Another controversial problem is speed, since
designers and test engineers will always be asked for
higher speeds then are currently available.
The current
VLSI test equipment are designed to run-at 50 MHZ.
21
The-
·--.,---.,
22
difficulties in designing such equipment makes their
price very unaffordable and adds to the testing problems.
therefore, it seems like the only reasonable solution to
design the devices such that their testability is simplified by using same specific methods.
2.
Timing and Synchronization
Meta stable states can cause an anomalous behavior
in synchronizers resulting in the occurrence of random
errors.
This has been pointed out by many researchers
long before the appearance of LSI, but their significance
became more apparent in the analysis of VLSI.
The time
spent in the meta stable state can create a synchronization failure thus causing the system to exhibit the faulty
behavior.
It is very difficult to test the VLSI chip for
a synchronization failure because of the inability to detect and localize the fault_ (16).
The other source of trouble on the VLSI chip is
the propagation delay on the line used for clock distribution or propagation of other types of signals.
When the
devices are designed to a scaled down size, the propagation delay for different types of wire varies by considerable amount.
This factor usually gets neglected and
presents some serious timing problems.
23
3.
Verification
Experience with the LSI has shown that a design
error can penetrate into the production stage and be discovered only in the field.
This unpleasant event usually
turned out to be very expensive in terms of redesign and
production changes required by the manufacture.
The more complex the VLSI chip, the higher the chance
that it contains a design error.
The design error can be
caused by the violation of the design rules which may or
may not result in one of the physical faults after the
prodessing step.
In any case the presence of the fault
will effect the yield.
The specific type of fault and
the location of the fault will determine how seriously
the yield will be affected.
The violation of design rules could be effectively
suppressed by developing the computer aided design tools
and even using the human pattern recognition ability.
However, there is very little or nothing that could be
done against the design errors which do not exhibit themselves as a violation of design rules.
Logic errors,
improper timing could present fatal errors.
To exhaustively test a device and verify an errorfree design is not an easy task, and is impossible with
existing advanced devices.
If the growth of VLSI
24
continues without reviewing the existing designs, more
frequent occurrence of such errors will be expected.
4.
Accessibility
With the increase in complexity of LSI and VLSI, the
accessibility to the internal states of the devices becomes very difficult.
Having limited access during testing results in
inefficient testing and very expensive test equipment.
There have been many discussions in the literature
on proper testing of a device.
One approach to gain in-
sight and knowledge of electrical properties of the circuit has been the application of Scanning Electron Microscopes (SEM) in the voltage contrast mode.
This technique
allows us not only to trace the circuit voltages, but the
propagation of the signals as well.
Another way to have a look inside the circuit is
through the shift registers connected together in the
test mode (LSSD).
The problem in this approach, inspite
of a gain in accessibility is the loss of speed during the
test and an increase in hardware redundancy.
5.
Automated Test Equipment
With the current VLSI devices which are mostly
designed without the considerations for testability, the
25
only way to test them is to utilize automatic test
equipment.
7
A VLSI tester is a system designed to test
parametic and functional parameters on VLSI devices at
speeds of up to 50 MHZ.
Design of such systems are very
involved and therefore the systems are very expensive.
A typical VLSI test system consists of the following
sections.
1.
Pattern Generator
2.
Formatting System
3.
Timing Generators
4.
Measurement System
5.
Data Bus
Figure 5-l shows a general block diagram of a typical
test system.
The user communicates with the test system via the
computer.
All the test vectors are loaded in to the pat-
tern generator.
The pattern generator starts executing
the patterns and sends the data into the formatters.
The
formatters buffer the data in to the test head where the
device under test is mounted.
The device will then react
to the original data and the return data goes back to the
formatters where it is compared with the original data
and if there is any errors, _an interrupt will be generated
which will stop the pattern generator and fail data will
be stored in the fail memory where it can be examined and
determine the reason for the failure.
26
c
..
0
m
p
~
~
'
u
Pattern
/
generator
'
t
e
r
I
'
Timing
D.C.
-
~
,____
..
_
,.
.
L_
Formatters
I("
'
J~
Test
,..
~
Station
Fig. 5-l.
'
Block Diagram of a VLSI Tester
;
27
A detailed pattern generator block diagram is shown
in Figure 5-2.
The timing generators generate the timing strobes for
the drive and compare formats.
They can be multiplexed
in to each channel that is required to send any data.
The measurement system is where all the parametric
measurements are done.
It determines how much current
the device is sinking or sourcing.
It can examine the
dynamic current loading of the device and it can be used
for very accurate voltage measurements.
The need for this complicated automatic test
equipment is mostly due to the fact that the design
engineers are not obeying testability rules and therefore,
manually testing these devices has become an impossible
task.
-
,--------·f;t~<.TtOt-I.M,. kRRot{
p~oc.i.) Sop.,
fARlT\
t---------------.::;;:.!:::::~.!..-----·--.,-..,
eR.~o~
fA~L
P~oc.rs.so~
r
1
.•
1_.-
-
~ M.E..t"''R' E.
-
( f>\l'ol
SL,
c.e:.
ao~tos
H•
-,
~s~-t----~--------~
-
'vee-rop,. /
t"\EMoA'(
2.5b X.~&~
-
s
)
I
I Do VI~'~ ItO ~
I
, ,__________......;•==:~....,-....~I~ " PN~/~r-'(----t---Ji)
r-~-:
__
~....;;;B_,TS
_ _-t~--14 ~Ct>~ i.. <;.!) t---.''-~__,,_~__..
. .,;;u·u.-)
C.tWNi~
_::rr f
'
··nr-tlu6
~DG-~
"fH·la..
TP'
\
9<.?
~
~RAt'\
C.iu·~~
~
CONrtOL
or.c..v,T~~
'I'
J
---i-t-+---·..-.-·--i.--
PC.P
'INSTl. vt.. T\ o ~
\t.
1
M£MOR..'(
(. "t P'\~t\,
.......,...._.,
c~~ x. \\ z.. ~\'\S)
~}+~
.SOV~C:E. SiLCf;l" MtJ)(..
.,.__,fr---+-'
~c~.
f
I
L_
'i: 1
"f'ilo\l:v(iM(i"'.
Jt)'f1"4-SovAc.E
.Sou4c~
(256:
'JC.
~6.l.ic.'T' iJIN
I
)'1EMo~~
f
SELQ:.T
'il(.fZ.'t 81\S)
,
...... ~
I
I
7.-S'-
Q~Ep
Tl~\NC,.
I
ME.""'oA.'(
_ ,.
------,----_j
· S$ M'EMo•.Y. ~Ol.~S S 1_
I~
.:;:.. ~\f,.l1o~
At.t?oC.~S
.
_X _r··H?~~._b;r..f\.o.
L 0(;-IC.
F1..nvc:.:no N
6-ENI::t.,M~
Ro""
)l. MrM.o~~~
C>PrTF\
Gf.t-.~t!tf.\ Tt{\
.~
,\'t
,~
~M"'T~.
I~
,
1\iX)e_. -~
,
11Mtf.!Ct MEM. ~04.·
r--~~~~~~J~~
I"
r
AuTO ':tW.elEM&.J\
c.o meo \,.
(DA-TA- il~ W/~}
-l
Fig. 5-2.
Block Diagram of
Pattern Generator
28
Chapter VI
DESIGN FOR TESTABILITY; THE PREVIOUS WORK
In this chapter the previous work done in the field
of design for testability is reviewed.
Some of the suc-
cessful methods are discussed for their advantages and
disadvantages and compared to the others.
1.
Level Sensitive Scan Design (LSSD)
One of the principal methods in design for
testability has been Level Sensitive Scan Design which
attacks the problem of having inaccessible nodes in the
device.
This method utilizes shift registers in a scan
mode to send the data in and out of the chip and access
all nodes.
LSSD offers potential for high stuck-fault coverage,
reduced development time and expense through computer
generated data, consistent testing and maintenance techniques and improved diagnosis.
With LSSD the only type of storage element permitted
is the SRL-(Shift Register Latch).
Figure 6-1 shows a
pair of polarity hold latches with the output of the
first latch (Ll) permanently tied to the data input of
the-second latch (LZ).
The Ll can be set by either
29
---------
-
--·~-~·-
---~
·--
~~~~
30
L1
r--------~------,
I
I
1
I
I
-SDI----------~~-r
:I
p...._----L 1
I
I
I
I
L2
r---------------,
I
I
I
I
I
I
I
I
I
n-+L1
Il
-ACLK
,..Lv
I
I
I
I
I
I
r:!NL......J
-- 'U
_r
I
I
I
i
+9CLK-rr
I
... L2
I
I
I
I
I
I
I
I
L---------------~
Fig. 6-1.
Shift Register Latch
t - - - - - - + - o PRIMARY
,:.. C:.OCK
OUTPUT
I
·------------------~
I
I
I
I
I
I
F' R I,,~.:.Rv ~·~PUT o--+------------.L:L:l
PRIMARY
OUTPUT
-o5CAN DATA OUT
Fig. 6-2.
Source:
An LSSD LSI Chip
Ref. 23
31
system data/clock or by scan data/A clock, because it
functions as a storage element during system operation
and as a component of LSSD shift register during testing.
All the SRLs on a chip are connected into a shift register
with the input of the first latch designated as scan data
in and the out of last SRL L2 designated as scan data out.
The dashed line represents the shift path.
Two chip in-
puts for non-overlapping.
Scan A and B clocks are connected to each SRL Ll and
L2.
The designer has lost the use of four chip pins and
the circuits required to implement L2 latch and associated
clock drivers.
But the connection of the SRLs in to a
shift register does not interfere with the normal operation of the chip.
The only requirement during the shift-
ing is that functional system clocks remain inactive so
as not to interfere with the shift operation.
The design rules for the LSSD are the following.
1.
The only type of storage element allowed in the
device is SRL.
2.
All the storage elements should be designed in
such a way that they can also operate as SRL.
3.
The correct operation is not dependent on use
time, fall time or minimum delay of the individual circuits.
The only dependence is that total delay through
the number of levels should be less than some known value.
32
The LSSD has been successfully implement in the IBM
system/38.
The chip is tested for 98-100% of all the
stuck faults with program generated test data.
Oyer head
due to the use of LSSD concept accounts for 20% additional
hardware.
More than 85% of L2 latches are used during
the normal operation.
The LSSD has some disadvantages as well.
The depth
of the patterns to be shifted varies from device to device.
During functional testing it can be necessary to shift a
pattern in for every parallel vector.
For a given part
100,000 shift patterns may be required.
This signifi-
cantly slows down the test process and the test may be
intolerably long.
2.
Signature Analysis
Signature Analysis is based on the concept of data
compression, which is an economical way to deal with
large amount of data by using simple compression
algorithms.
There are only a few methods for data compressions.
One method is transition count technique.
In this method
the validity of the circuit is based on the correct number of transitions from one to zero or vice versa.
The
method based on transition counting, but which uses a
probabilistic count of one is another method in use.
33
Although these techniques succeed in logarithmic
compression of the response data, they require, in the
worst case, twice the number of tests required for conventional testing, and thus the total length of the test
data is not compressed in general.
Another method which is more efficient is called the
Cyclic Redundancy Code (CRC), a sort of check sum produced
by a Pseudo Random Binary Sequence (PRBS) generator which
utilizes Linear Feedback Shift Registers (LFSR) .
This
CRC value is stored in the CRC register and is called the
Signature.
If the signature matches the expected value
which would be produced by a fault free circuit we assume
the device is nonfaulty.
Moreover, a similar feedback
register can be used to produce a PRBS to serve as an
excitation to the device under test.
A device under test
might be a combinational network, or, in addition contain
some amount of storage and exhibit a sequential behavior.
Initially, the signature register is set to some
value So= S(to) and test pattern generator to the value
Xo = X(to).
(Figure 6-3)
After applying the test pat-
tern X(t) generated by test pattern generator, at sometime t the signature register will contain some value
S(t) which will be a function of the previous value
S(t-1) and the input Y(t).
s (t) = s (t-1) y (t)
At the end of the testing period, the signature register
34
PARALELL INPUT
TEST PATTERN
GENERATOR
SHIFT IN
SHIFT OUT
X(t)
LOGIC UNDER
TEST
REGISTERS
n
Y(t)
f
= Y(t)
SIGNATURE
REGISTER
SHIFT IN
SHJcT OUT
n
f
S(t)
S(t)
=
PARALELL OUTPUT
Fig. 6-3.
Source:
Block Diagram of Signature
Analysis
Ref. 13
35
sn
S will contain some value
which will be a function of
the initial state So and all the inputs Y.
sn =
f[So, Y]
If the inputs
y
were coming from an error free device,
the signature Sn, after applying the test would be
S~
=
f[So, Yc]
If the device contained errors,
the signature would be.
The feedback of the signature register, and the test
pattern generator should be chosen in such a way that the
probability P that:
f[So, Yc]
=
f[So, Yf]
is the lowest possible.
This could be achieved by
clearer selection of the input test patterns and/or, if
the fault distribution is known to us, by designing the
signature register with the most appropriate feedback.
3.
Syndrome Testing
Another method that has been implemented in the
design for testability is syndrome testing.
This method
dictates designing combinational circuits so, that the
storage requirement for implementing the test procedure
-
will be restricted to only one number called the syndrome
of the circuit, which is based on the number of minters
realized by the switching function.
36
A cricuit is called syndrome testable if the syndrome
of any faulty version of the circuit, induced by a single
stuck-at fault, does not equal the syndrome of the fault
free cricuit.
The test procedure consists of applying
all the input combinations to the device under test and
recording its syndrome.
In order to reduce the test length for circuits with
large number of inputs the combinational circuit is partitioned in to sub circuits, each designed to be syndrome
testable.
For example a circuit with 20 inputs can be
tested separately from the rest of the circuit, in approximately 1 sec (assuming a 1 MHZ testing clock) .
The penalty for producing a syndrome testable design
is a slight increase in the number of input pins.
The syndrome S of an n variable boolean function is
defined as the ratio of the actual number of min terms
of the function to the maximum possible number of min
terms.
s =
k
0 <
s
<1
2n
Following this the syndrome for several n input logic
gates can be developed.
"AND" gate
s =
1
2n
"OR" gate
s =
2n-l
2n
=
1-2-n
"NAND" gate
s =
2n-l
2n
=
1-2-n
=
2-n
37
1
"NOR" gate
s
=
"XOR" gate
s
= 21
2n
=
2
-n
Using the above equations the syndrome for combinational
logic circuits can be determined.
An example of a corn-
binational circuit with "OR" gate termination is shown in
Figure 6-4.
The cricuits Sl and S2 have syndrome Kl and
2n
K2
respectively.
2m
The syndrome So can easily be calculated to be:
So
=
Kl . 2m + K2 . 2n - Kl . K2
rn+n
2
With the same manner,
=
S
+ S
1
2 - sls2
the syndromes for the combinational
logic circuits with other terminator gates such as "AND,"
"XOR," etc. can be calculated.
To show that a function is syndrome testable it is
sufficient to show that any single stuck-at fault will
change its syndrome.
It has been determined that every
fanout free irredundant combinational circuit composed of
"AND," "OR," "NAND," "NOR," and "NOT" gates is syndrome
testable, however the problem arises when using the "XOR,"
gates because it could imply reconvergent fanouts.
The extra hardware required for this method has been
estimated to be 5% which is less than LSSD and the
penalties are not as bad as the LSSD.
at fault coverage is not as good.
t~rne
However, the stuck-
38
Sl
Fl
Xn-----t
yl
y2
F2
f
y
•'•
n
S2
~
Fig. 6-4.
Example of Combinational Circuit
with "OR" Gate Termination
Chapter VII
INCREASED CONTROLLABILITY AND OBSERVABILITY
BY UTILIZING SPECIAL FEATURE GATES
l.
Introduction
In this chapter we present a method for testability
which utilizes special gates that function in two modes
l) functional,
2) testing.
It will be shown that these gates will increase
controllability and observability of the LSI-VLSI devices.
An algorithm is presented which is based on the Dalgorithm (4), which finds the optimum points where the
existing gates should be replaced with these bi-functional
gates.
By doing so, we achieve maximum accessibility to the
device and therefore the testability is maximized.
Examples will be given to compare this method with
existing methods and finally the advantages and disadvantages of this method will be discussed.
2.
The Bi-Functional Gate
The problem of inaccessibility is merely due to the
lack of control on some nodes within the device.
There-
fore, by increasing controllability of the circuit we can
achieve better testability.
39
40
One solution is to utilize gates that have the
following properties.
1.
They can act like any other logic gates during
the functional mode.
2.
During testing mode, they should be able to
propagate the signal only from one of the inputs, which
is designated as the high priority input.
Figure 7-1 and
Figure 7-2 showthe bi-functional "NAND" and "NOR' gates
and their truth tables.
The idea is to be able to force the propagation Dcubes i.n to the gate.
Hence if the other inputs to the
gate are not controlled, the fault can be forced out of
the gate via the high priority input.
3.
FET Structure of the Bi-Functional Gate
The bi-functional gate is easy to design and the
only difference with regular gates is the addition of one
FET transistor for controlling the test function.
The
structure for a "NAND" gate is shown in Figure 7-3b.
If T
=
0, the gate will act like any other "NAND" gate
because QS will not interfere with the gate functionality.
When T goes high then Q3 and Q4 are bypassed and f will be
dependent only on Q2.
Addition of QS is expected to have an effect on
increasing the propagation delay of the gate because of
4:L
A1
A2
A
n
f
'
''
T
T
A1
A2
A
n
=
f
0
0
A1 A2 ---An
1
A1
••
•
T = l
Fig. 7-l.
Bi-functional "NAND"
42
Al
A2
f
An
=
Al
A2
0
f
T
f
0
Al + A2 +
1
Al
A
n
1
Fig. 7-2.
Bi-Functional "NOR"
...
+ An
43
1-----f
a
b
Q3
b
T
c
c
Q4
Q4
(a)
Fig. 7-3.
(b)
FET Structure for Bi-Functional
"NAND"
44
the associated capacitances that will be added to that
node.
The additional delay is expected to be very insig-
nificant compared to total propagation delay and it will
only affect the path that goes through the particular
gate.
Similar modifications can be done on other logic
gates to make them controllable.
Another example is shown on the "NOR" gate.
Figure
7-4b shows the FET structure of the bi-functional "NOR"
gate.
=
In this case if T
normally and when T
=
1 the gate is functioning
0 it goes to the test mode.
Also,
in this case the propagation delay is more than the bifunctional "NAND" gate because Q5 is in series with Q4
and Q3 and Q5 has to be "ON" during the functionality of
the gates.
Utilizing the bi-functional gates in conjunction
with partitioning can result in improved test generation.
Before, an example is given,partitioning characteristics
is reviewed.
4.
Partitioning
The larger and the more complex the circuit, the
more difficult it will be to test.
Therefore it seems
reasonable to try to partition a large circuit into
smaller segments and test each smaller segment separately.
45
vdd
=
5 v
a
c
(a)
Ql
f
Q5
a
Q2
T
Q3
b
Q4
c
(b)
Fig. 7-4.
FET Structure for
Bi-Functional "NOR"
46
In general, a circuit can be partitioned into two or
more
subcircuits~
If partitioning can be carried out
such that the number of the input lines of each subcircuit
is singificantly fewer than that in the original circuit,
it will be possible to test each subcircuit exhaustively.
The time required to test all subcircuits exhaustively
will be less than the time to test the whole circuit.
In
fact, it is just necessary to have each partition output
function depend on a sufficiently small number of input
variables.
In order to exhaustively test each subcircuit, all
the subcircuit inputs must be controllable at the input
of the circuit and all the subcircuit outputs must be
'
observable at the circuit output.
Any algorithm given
for partition testing must meet these two limitations.
5.
Examples
In order to illustrate the use of bi-functional
gates along with partitioning, we have chosen the 74181
ALU chip.
McCluskey (15), uses the same example, in which the
partition approach together with hardware multiplexers
are used for testability.
It is shown that in one case
the exhaustive testing of the device results in a total
of 1056 randomly generated vectors with approximately
33% hardware redundancy.
47
The partition approach is used along with the bifunctional gates in the following manner.
First the device is partitioned into three sub
partitions.
The first one is the input partition shown
in Figure 7-5.
The input partition is broken in two sub
partitions with outputs Li and Hi.
The next partition is the output partition which has
also been broken into 4 sub partitions shown in Figure 7-6
and Figure 7-7.
The last partition is the ALU carry bit
partition shown in Figure 7-8.
The inputs to the input partition are the primary
inputs of the device.
The outputs of the input partition
are the inputs to the output partition and the outputs of
the output partition are the primary outputs of the
device itself.
For the carry bit partition, the inputs
are the outputs from the input partition and the outputs
are primary outputs.
To exhaustively test each partition we must obey the
partition rules that require a) All the partition inputs
must be controllable at primary input and b) all the partition outputs must be observable at a primary output.
In order to test the input partition we will test
the sub partitions separately.
To exhaustively test the
Li, Hi must be set at a known level say 0 to set Hi
we should have 82
=
83 = 0.
=
0,
To make Li pass through the
last gate M should be set to l therefore the other input
48
H.
l
L.
l
Fig.
7-5.
ALU Input Partition
49
M L1
I
-l
Fig. 7-6.
ALU Output Partition (Part 1)
50
M Lo
cn
Lo
Ho
C
n
M Ho
l
Fo
Fl
Fig. 7-7.
ALU Output Partition (Part 2)
51
H
H 3
H 2
H 1
0
1
L
c
,
H
1
,
p
Fig. 7-8.
ALU Carry Bit Partition
52
to that gate would be 1 and Li will be propagated to F.
l
which is a primary output.
So, Ai, Bi and
s1
Now, we can cycle the inputs
through all possible combinations.
Thus, to have Li tested exhaustively there is a need for
2
4
=
16 vectors.
To test Hi, Li should be set to a known level.
set Li
=
0 we should have So
= s1 =
1.
Then M is set to
L and Hi is observed at a primary output.
exhaustively test hi, inputs Ai, Bi,
To
s2 , s3
Therefore, to
should be
cycled through all possible combinations which yields
24
=
16 vectors.
Thus, a total of 32 vectors is required
to test the input partitions.
To test the output partition, Li and Hi which are
In order to
inputs should be related to primary inputs.
relate Li to a primary input we can set So
Li would be dependent on Ai only.
= s1 =
0 and
To relate Hi to a
primary input is not possible with the given design, but
if we modify one of the gates to a bi-functional gate it
can be done.
partition.
Figure 7-9 shows the modified h
1
sub
In this case by setting B to be the high
priority input Hi
=
Bi in the test mode.
Now, in'order to exhaustively test the out
partition we can cycle through all the 2
tions of inputs, but L
3
10
=
L024 combina-
and H3 have already been part of
the path to test the input partition and therefore, fully
53
Ai
s
A.
B.
l
3
l
Control
Fig. 7-9.
Modified ALU Input Partition
54
tested.
Thus all we need to do is to cycle through the
remaining inputs which is 2 8
=
256 combinations.
The last partition to be tested is the carry bit
partition.
Testing this partition is similar to the out-
put partition.
The carry bit partition is divided into
two sub partitions.
The first one has 5 inputs which are
directly related to primary inputs, and the second one
has seven inputs.
Hence a total of 2 5 + 2 7
=
=
32 + 128
160 vectors are required to test the carry bit partition.
The required number of test vectors for each
partition is summarized in Figure 7-10.
A total of 448 vectors are required to exhaustively
test the 74181 ALU.
If the partitioning and bi-
functional gate approach had not been used, a·total of
2
14
~ 16K vectors would be required.
Therefore, there
has been a drastic improvement on the test generation.
As far as hardware redundancy, the device needs an
additional pin for controlling the bi-functional gate
and 4 gates have to be modified to be bi-functional.
The
total redundancy in this case can be approximated to be
about 5% which is tolerable.
Another example of the partition approach along with
the bi-functional gates is shown on the 74280 even/odd
parity generator device.
two sections.
a) Input partition
The device is partitioned into
55
Partition
Number of vectors required
32
Input
256
Output
160
Carry bit
Total
Fig. 7-10.
=
448
Partition Test Generation Table
56
b) Out partition
Figure
7~11
shows the input partition which is divided
into three sub partitions Ll, L2 and L3.
The inputs of
the input partition are primary inputs and the outputs
are the inputs for the output partition.
To test each
one of these sub partitions exhaustively we have to create a path from the output of that partition to an observable device output
(~E,
~0).
In order to propagate Ll to
an output L 2 and L must be set to 1 (L = L = 1).
3
2
3
order to achieve this I
I 5 = I 6 = I 7 =IS= 1).
3
through Is must be 1 (I
Now, to pass L
1
3
In
= I4 =
through the last
stage the "NOR" gate should be modified to a bi-functional
"NOR" gate with the high priority input set to be input A
which is carrying Ll.
Now, we can cycle through the 3
inputs to that sub partition (IO, Il, I2) and exhaustively
test it with a total of 2 3 = S vectors.
Similarly L
IO = Il = I2
=
2
I6
can go through the same path, by setting
I7
=
IS = 1.
By cycling I3, I4, IS
all the vectors are generated to test that sub partition.
For L3 we should have IO = Il
=
I2
=
I4
=
IS
=
1 and by
cycling I6, I7 and IS the last sub partition is fully
tested.
So, a total of S + 8 + S
=
24 vectors are
required to test the input partitions.
In order to test the output partition, Figure 7-12,
a path from a primary input to the partition input should
be created.
This can be done by modifying the 3 "NOR"
57
Fig. 7-11.
Input Partition
58
""'-'-- L:
A
L2
Ll-~
L3--~
'-----'
Fig. 7-12.
Output Partition
E
59
A
T
A
Fig. 7-13.
Modified Output Partition
60
L:
~r/
~,,
.
(JS
Fig. 7-14.
MOdified
I~t
Partition
E
61
gates that generate L , L 2 and L to bi-functional "NOR"
3
1
gates.
I1
=
I2
The priority is set on input A and by setting
=
1, L
by setting I
4
1
would be only dependent on I 0 .
=
I
5
=
Similarly
1, L2 would be dependent on I and
3
L 3 can be dependent on
r 6 by setting I 7 = I 8 = 1.
Now a
total of 8 vectors are required to cycle L , L 2 and L 3 .
1
Therefore, a sum of 24 + 8 = 32 vectors will exhaustively
test the device.
If this method was not used, 2 9 ~ 512
vectors would be needed to do the same job.
Because,
this was a smaller device than the 74181, the added redundancy will have a greater impact on the design cost.
In
this case the redundancy amounts to approximately 10%, and
there will be time penalties because of using the bifunctional "NOR" gate.
6.
The Generalized Algorithm
In the last section the use of partitioning method
along with the bi-functional gates were demonstrated.
In
order to find the locations within the given circuit in
which these bi-functional gates should be placed, the
following algorithm is proposed.
The algorithm should determine:
a) Can an output of a partition be propagated to an
observable point or a primary output of the circuit?
62
b) Can an input to a partition be controlled by a
primary input to the circuit?
c)
If an output of a partition can not progress
through a gate, can that gate be modified to be a bifunctional gate?
d) If an input to a partition can not be directly
controlled by a primary circuit input, can the circuit
be modified by using bi-functional gates to solve this
problem?
To satisfy the foregoing conditions, an algorithm
is given below.
The Algorithm
a) Procedure 1
Step 1.
Determine whether the inputs to the partition
under test (X. 's)are primary inputs to the
l
circuit (I .. ' s).
J
If they are, go to step 2,
otherwise go to Procedure 2.
Step 2.
Force the propagation D-cubes for the outputs
of the partition (Yk's).
If a Yk can not
reach an observable output, go to step 3.
Otherwise go to step 5.
Step 3.
Back track the other inputs to the gate where
Y.'. is blocked.
~
If these inputs can be set to
desired values by controlling the primary inputs that are not part of partition under the
63
test, do so and go back to step 2.
Otherwise go to step 4.
Step 4.
Replace that gate with a bi-functional gate.
Set the priority input on the line containing the Yk.
Step 5.
Repeat steps 2, 3 and 4 until you reach an
observable output.
As it can be seen, procedure 1 carries the partition
output to an observable output and makes whatever modifications needed to do so.
b) Procedure 2:
(Note that this procedure is used only
if the inputs to the partition are not
primary inputs (X.
l
Step 1.
~I.)
J
Back track each partition input X.l to a
primary input Ij.
Step 2.
If a primary input I. alone can control the
J
partition input go to step 4.
Otherwise go
to step 3.
Step 3.
Replace the gate which prevents the primary
input Ij to control the partition input Xi'
with the bi-functional gate.
Set the prior-
ity input on the line containing I ..
J
Step 4.
Repeat steps 1 through 3 for the remaining
inputs.
64
Step 5.
If the output of the partition is not a
primary output go to step 2 of procedure 1.
The flowcharts for these two procedures are shown in
Figure 7-15 and Figure 7-16.
65
I.'?
J
y
y
N
Replace the gate
with bi-functional gate and
propagate
D
Partition input i
Primary input
J
Partition output K
Number of levels for Yk to reach a primary output
Primary inputs that are not part of the partition under
test
y
n
The last partition output
Fig. 7-15.
Procedure 1
Flowchart
66
Can an Ij alone
control the X.?
~
Yes
Replace the gate
that prevents the r.
to control Xi with J
a bi-functional gate
Xi
Ij
Xn
Zm
Partition input
Primary input
Last partition input
Primary output
Fig. 7-16.
Procedure 2 Flowchart.
Chapter VIII
CONCLUSION
1.
Conclusion
In this thesis some-of the important problems in
testing of the LSI/VLSI devices are reviewed.
The main
problem addressed was "how to improve testability in the
design stage."
An investigation was done on faults and their nature
and the possible problems they could cause, and some of
the basic fault detection methods were reviewed.
The
basic study was concentrated on the LSI and VLSI circuits
and the field of design for testability.
Some of the
existing methods were discussed, their advantages and
disadvantages were compared.
A new algorithm was introduced for combinational
circuits to replace the logic gates with bi-functional
logic gates which operate in two modes 1) testing,
2) normal.
The algorithm determines the optimal points
in the circuit to utilize these gates.
This new method offers improved controllability and
observability and improved test generation.
It also
causes some tolerable added hardware redundancy and some
timing penalties.
67
68
Overall for combinational circuits it could be a
very practical method.
Examples were shown where this
method was applied to some existing circuits and resulted
in a great improvement on test generation.
It is expected
the given method may be applied to asynchronous sequential
circuits with some modifications.
2.
Directions for Future Research
Further developments may be done on the proposed
algorithm in the following areas.
a) Development of a similar algorithm that utilizes
the bi-functional gates for asynchronous sequential circuits.
b) Research in improvement of multiple fault coverage.
c) Further research in utilizing the bi-functional
gates for elimination of undetectable faults in reconvergent fanouts.
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;:;_·.
APPENDIX
73
74
LOGIC DIAGRAM
.
.,.m..,
..
..
~..
••
••
Vcc•Pilll24
,, .............
GHO • .._ t2'
NOTE
b
FC4' l•"'oly de ct'l•r•et•nlttC•. · - tnltd• lfont CO'Ier tor 54' 7 4 •NJ ll4H17 4H. aMI -ICMI He& C.OHf tor 5"5174$ 4..cl $4lS• 7"l.S NMCtftc:M-.
Source:
Signetics Logic - TTL Data Book, 1985
75
LOGIC DIAGRAM
Vee •
Pin,,.
GNO • Pin 7
74 LS 280 Logic Diagram
Source:
Signetics Logic - TTL Data Book, 1985.