CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
AN IMAGE CORRELATOR LSI
FOR USE IN A SYSTOLIC ARRAY
A graduate project submitted in partial satisfaction of
the requirements for the degree of Master of Science in
Electrical Engineering
by
Elaine Susan Abramson
May 1987
·
The Graduate Project of Elaine Susan Abramson is approved:
California State University,
ii
Northri~ge
TABLE OF CONTENTS
List of Figures.
. .. . . . .. .. .. .. .. . . . . . . .. .. . . . . . .. .. .. .iv
List of Tables •••••••
1\ bstrac t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
1. Intra due tion .•••••••••••••.•••.••••
.. ... ... . .. ... .1
2. Design Req·uiremen t s ••••
• • • • • • • • • • • • • • • I
3. Functional Description ••••••
.. . .. . . . . . . . . . . . . . . . . . •• 9
3.1. The Image Correlator LSI ••.•••••••••••••••••• 9
3.2. Three Processing Elements ••••••••••••.•••••• 20
3.3. An 8
X
8 Systolic Array.
• 25
4. Simulation Results for Modules .••••••••••..••.•.••. 34
4 .1. Registers •••••
.34
4.2. Registers with Parallel Load ••.••••••••..••• 38
4.3. Adder (1-bit)
41
4.4. Adder (4-bit).
. . . . . . . . . . . . . . . . . 43
..................... ......... 57
Multiplier •.••••••.• . . . . . . . .. . . . . . . . . . . . . . . . 59
4.5. Adder ( 20- bit)
4.6.
5. Conclusions and Discussion •.••••••••••••••••••••••• 64
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Bibliography ••••.•••.•.•
Appendix A.
• 68
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
iii
,,
LIST OF FIGURES
Figure
1
Correlation Equation
2
2
Image Correlator LSI
Block Diagram
10
3
Timing Diagram
Image Correlator LSI
12
4A
Timing Diagram
Image Correlator
Test of the Multiplier
16
4B
Timing Diagram
Image Correlator
Test of Adder and Clear Functions
17
SA
Image Correlator
Multiplication Test Results
18
5B
Image Correlator
Adder and Clear Test Results
19
6
Three Processing Elements
Block Diagram
21
7
Timing Diagram
Three Processing Elements
23
8
Timing Diagram
Loading Template Data
24
9A
Three Processing Elements
Test Results, Part A
28
9B
Three Processing Elements
Test Results, Part B
29
9C
Three Processing Elements
Test Results, Part C
30
9D
Three Processing Elements
Test Results, Part D
31
10
8 x 8 Systolic Array Configuration
32
iv
'
LIST OF TABLES
Table
I
Functional Test Data,
Three PE Example
26
II
Simulation Results,
Registers
36
III
Simulation Results,
Registers with Parallel Load
39
IV
Simulation Results,
Adder (1-bit)
42
v
Simulation Results,
Adder (4-bit)
44
VI
Simulation Results,
Adder (20-bit)
58
VII
Simulation Results,
Multiplier
60
v
ABSTRACT
AN IMAGE CORRELATOR LSI
FOR USE IN A SYSTOLIC ARRAY
by
Elaine Susan Abramson
Master of Science in Electrical Engineering
This report describes the design and development of an
integrated
circuit
correlation,
uniqueness
capable
specifically
lies
in
its
of
performing
template
use
as
the
image
matching.
building
Its
block
in
a
systolic array.
The number of LSI's used to form the array
is
the size of the
The
determined by
systolic
architecture
template used in a
allows
a
constant
flow
match.
of
data
through the array so that multiple correlation computations
can proceed simultaneously.
The
I rna g e
performances were
image
several
correlator
image
Simulation
Cor r e 1 a tor
was
obtained through
was
then
correlator
tests
LSI
on
the
designed
simulation testing.
designed
by
LSI's
to
array
indicated
performed as designed.
vi
and
form
a
its
An
interconnecting
systolic
that
the
array.
system
CHAPTER
ONE
INTRODUCTION
With
advent
the
circuits),
a
multitude of
computations have
correlation,
used in
systolic
a
integrated
scale
template
circuit
integrated
requiring
possible • . One of
specifically
an
(large
applications
become
describes
LSI
of
these
rna tching.
which
was
array architecture
to
intensive
is image
This
report
designed
perform
to
be
template
matching.
Image
correlation
is
a
mathematical
compare the similarity of two images.
method
used
to
Template matching is
a type of correlation used to locate a specific object in a
larger
image.
to
matched.
be
region.
a
The
larger
image
is
defines the
object
called
search
the
position
value is
calculated at
each
at
which
considered
the
be
to
correlation
correlation
best
the
equation
pattern are
and
a
value
diagram
given in Figure 1.
region
2
position of
=
of
size
62 '00 1
the
256
X
possible
template
over
1
there
search
th~
the
maximum
normalized
showing
Assuming
256,
is
search
the search
The
match.
bean array of 8 x 8 pixels (picture
(256-8+1)
possible
After the computations are completed,
position.
search
The
or window,
The template is moved across the search region and
correlation
is to
template,
the
that the
search
template
elements), and a
are
(M-I+1)
At
positions.
search area,
a
2
or
each
total
of
2
il -~Flm,n)
~!~
I
~·_iu
,.__ SE~1RCH REGION S
11'-----+--·--J
2.:
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'r
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V..:
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r
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COORDINATE
PEGIOr~
c n 'u'! A' T ...LVI~
T (I ~"I
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3
64
calculations
the
must
correlation
positions
very
value.
over
computations
be
the
and
This
is
search
needed is
consuming
time
made
then
summed,
repeated
area.
for
Therefore,
=
62,001 x 64
operation
to
each of
the
the number
3,968,064.
and
compute
makes
it
of
This is
a
a
perfect
candidate for array processing.
With
array
of which
an
the
processing
usually contain a microprocessor,
The
array.
dependent
image
processing,
upon
form
the
processing,
and
dimensions
application
each
for
processing
elements,
are arranged in
of
the
which it
element
each
is
array
are
used.
(PE) is
For
designed
to process data associated with one pixel of the image.
an
example,
for
an
8
x
8
image,
64
processing
As
elements
would be required.
In
simultaneously
with
instruction,
It
is
is a
the
been
on
data.
multiple
CLIP4
the
This
data
all
the
same set
is
called
array.
(Cellular
Logic
image
processing
developed
chips.
The
approach
is
[ 1]
obvious
the
to
reduction
SIMD,
One
Image
a
example
Processor)
[ 1].
has been
used for
control
the
in
the
computing
single
this
A programming
of
but
of
tasks.
advantage
would
processors
of instructions
LSI-based processing chip that
variety of
has
operate
different
array
array,
processor
a
operations
array
time.
a
language
of
the
processing
Instead
of
having to calculate the correlation component of each pixel
sequentially,
the array allows all these calculations to be
4
done
simultaneously.
template,
the
processing
array
~
~
k
was
CLIP4
temp 1 ate
computational
0. 5
64k, where
Using
and
a
more
matching,
can
to
perform a
But,
processing element
the
region,
8
x
a factor
8
of
to
optimized
in
many
for
different
reduced,
such
as
that
used
than
with
store
image
multitude of operations.
the
template
in
the
time
of
still necessary
to
processing
it is
correlation value at each
search
an
purpose
not
arranged
method
even
each
are
application,
efficient
is
the
be
specific
needed.
reduced by
general
It
CLIP4
compute
for
performances
configurations
a
of
1. 0 depending on the design.
its
for
assumption
time is
designed
rna t chin g •
However,
the
search position over
these
values,
and
then
to
compare them to find the best match.
This
allows
the
a
is
where
further
processing
value
for
the
use
reduction
array
a
systolic
in total
did
for
search
each
of
computing
computing
position,
the
more
data
array in
done
a
streams
various
architecture
be
by
in
regular
flow
speeds
allows
is
data
through
and
systolic
of
[ 2].
correlation
Instead
What
correlation
Typically,
cells
directions
multiple
parallel.
flow.
the
the
time.
array
A systolic array is
accomplishes for all search positions.
characterized
architecture
of
the
This
two
or
systolic
type
of
operations
to
calculating
the
correlation for each position before moving on to the next,
data
is
continuously sent
into one
side of
the array while
5
the results are being retrieved from the other side.
There
are
architecture.
the
other
One
array.
is
Others
advantages
the
to
using
multiple use
are
modularity
a
systolic
of data throughout
of
using
uniform cells and local interconnections.
simple
and
These contribute
to the design of a highly pipelined and highly synchronized
system
[2,4].
These
properties
lend
themselves
to
LSI
implementation.
Systolic arrays can
and
The
synchronously.
whereas
a
for
asynchronous
synchronous
control and
called a
be made to operate asynchronously
global
requires
Array
Processor
It
processing.
recursive
algorithms.
language
called
For
Matrix
is
this
is data
some
driven,
centralized
An asynchronous array
clocking scheme.
Wavefront
image
array
type
(WAP)
[3]
was
particularly
processor,
Data-Flow
designed
useful
a
for
programming
Language
(MDFL)
was
developed which enables the WAP to be used for a variety of
tasks
including
matrix
multiplication,
based computations [3].
and
other
matrix-
This approach has been extended to
do correlation by S.Y. Kung and J.T. Johl [4].
For
the
a
array
frequency.
and
R.L.
approach
this
synchronous
at
a
taken
project.
the
constant_ speed
Basic
Picard
system
to
in
design
has
perform
the
What is
data
been
of
pumped
controlled
described
convolution
design
is
the
proposed here
[4].
system
is a
by
through
the
by
clock
H. T.
Kung
This is
described
the
in
combination of a
,,
6
two-dimensional array processor in a systolic architecture.
The
integrated
element used
circuit
was
designed
as
the
processing
in an array that can be adjusted to any size
window for template matching.
CHAPTER TWO
DESIGN REQUIREMENTS
order
In
requirements
array
of
parts
of
analyze
by
a
the
numerator
be
of
from
designed
by
the
a
not
similar
are
could
can
a
specific
are
timing
to
be
and
to
only
the
denominator,
considered.
it
circuits
given in Figure 1 is
The
design
the
Second,
array.
array.
was
that
for
the
certain
is
elements
coordinate
the
Alternately,
value.
is
The
to
one
integrated
matching.
factor,
that
as
design,
first
correlation equation
computed
shown
The
It
computer
the
this
made.
system.
output
normalization
this
be
designed
l·arger
controlled
be
to
template
purpose,
to
had
elements
a
implement
to
However,
be
be
used
to
the
it can
compute
computed
by
the
controlling computer.
Third,
word.
This
black
as
to
one
Fifth,
pixel
allo1vs
white.
chip,
the
elements.
a
is
When
clock
input
to
an
8
LSI
is
LSI's
pins
and
are
all
x
data
be
8
8-bit
from
assumed
array
of
clear
in
an
input
from
designed
each
to
pixel.
be
8
x
8
processing
but
be used
binary
levels
element
synchronous,
arranged
7
an
intensity
that can
the
by
processing
will
reset signal
the
256
process
window
the
of
each
requiring
asynchronous
represented
range
used
Finally,
chip.
is
Fourth,
template
thus
pixels,
an
each
will
have
to clear
array,
pins
all
are
the
the
wired
8
together.
CHAPTER THREE
FUNCTIONAL DESCRIPTION
Since
format,
it
chip
alone.
the
array
consists
the
integrated
is
insufficient
to
processing
three
parts.
Part two
was designed.
used
in
functionally
an
array
describe
describes a system
This
elements
work.
Part
describes
one
the
section
how the
LSI
provides a detailed explanation of
the operation of one row in an array.
3.1
is
It is necessary to include information on how
of
of
circuit
Then, the third part
with the full 8 x 8 array.
The Image Correlator LSI
The
Image
Correlator
LSI
consists
of
the
following
modules:
0
2
8-bit Registers with parallel load and clear
•
1
8-bit by 8-bit Multiplier
@
1
20- bit Adder
(j,)
1
16-bit Register with clear
0
2
20- bit Registers with clear
The architecture of
the chip is shown as a
block diagram in Figure 2.
signal
( CLEAR-L)
the registers
is
on the
To initialize the chip, a reset
provided.
chip are
When CLEAR-L
set to 0.
goes
Either
template data can enter the chip via the DB bus
where
data.
two
separate
input
functional
registers
are
low,
all
pixel or
(DB7-DBO),
provided
for
the
Register W stores the template data, while Register
9
-------
------~-
tl> DB
!DELAY EO!
CLil-L
L8
DC
DA>--~,
CLOCK.
CU.AR-L.
-§
=:;1 C~l~~~JC
.
r-:Riil
LOAD - - ,
8
08 ---/--·
I)_ I<
--·
I
LD.~-L
PE
D~1
----;. IJ.· R-l.
CLOCK--~
UJ--.1-·l
-,--
L _____ J
t. o.~,o
FJL~! ~;·~,_·
E~L. UC:~: [i
INPUTS = 31
OUTPUTS "' 28
!.'!'
rtv·i(iC[ COF\H[J r:YfOF:;;
CLE0R·-L
TOTAL = 59
L~:;
I
li'iLJ-=I(Y"'l
1-'
0
11
X is
temporary
storage
for
signal
information
positive
low,
is
will
edge
be
of
the
data
stored
the
data.
The
LOAD
X or W, stores the data.
determines which register,
LOAD
pixel
in to
clock
containing
Register
signal.
If
~s
data containing the pixel information
If the
template
W on
LOAD
signal
the
is
next
high,
the
latched into the X
register on the positive clock edge.
Once
the
computations
basic
the chip
data
is
All
registers
start.
synchronized
The
template
by
utilizing
timing
on the
is
the
loaded
same
the
in
the
clock
shown in Figure
DB bus and is
into
3.
signal
Pixel
latched into
chip,
the
chip
are
(CLOCK).
data enters
the X register.
It then also appears on the DBD bus (DBD delayed) as output
data
DBD7-DBDO.
The
Register
lv.
soon
contents
of
next
their
data
latched
into
Register
A is an
arranged
in
coming
and
in
from
as
Registers
clock,
Meanwhile,
is
As
template
an
the
X and
data
is
A on
it
the previous
is
stored
on the
every
provides
processor.
stored
latched,
in
and
storage
the
the
Register
Y.
DA bus
When
in
on
positive
accumulator register.
array,
already
W are multiplied,
the chip
Register
is
pixel
product
entering
data
(DA19-DAO)
clock
edge.
the LSI's are
for
The contents
the
data
of the
Y
A registers are added together and their sum is stored
Register
correlation
C on
the
output
of
next clock.
the
chip
Register
on
the
DC
C provides
bus
The array of LSI's represents the template.
the
(DC19-DCO).
It can be
' .
CLOCK
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LSI
1-'
N
13
considered
it.
stationary
Because of
local
memory
while
this,
for
the
the
the search
X register
multiplier,
region moves
is not
but
also
only used
must
was
necessary
(Register
possible
A)
sum
to
insure
that
was
wide
enough
over
8
or DB delayed.
the
8
contain
For
x 2
8
the
Also,
accumulation
to
processors.
the maximum product would be 2
feed
register
the
maximum
z16 .
=
If there are 8
16
x 8 -- 2
16
x 2
By allowing the accumulator to be 20 bits wide,
2
16
as
large as
it
an 8-bit multiplier,
·
processors,t h en t h e maxlmum
sum would be 2
array could be
as
This is why
pixel data to the next processor in the array.
there is an output bus called DBD,
under
z20 =
16 x 16 since
2
16
3
the
x 2
4
=
16.
X
The chip is designed to have 31 input pins,
( 8),
the
output
DA
bus
pins,
the
( 20),
DBD
CLOCK,
bus
(8)
CLEAR-L
and
and
the
DC
used
to
the DB bus
LOAD,
bus
and
(20)
28
for
a
total of 59 pins.
The
total
number
number
of
utilizing
design,
when
using
transistors
a
many
gate
the
CMOS
required
transistors
Image
construct
may
is
using CMOS technology.
be
this
would
for
the
total
However,
6092.
wasted
Therefore,
Correlator
So,
technology.
array configuration
routing considerations.
that
gates
One gate is considered the equivalent of 4
design is 1523.
transistors
of
when
implementing
due
to
layout
the
and
it would be safe to say
fit
At this time,
on
an
8K
gate
array
CMOS is the preferred
14
technology
due
to
its
low
power
consumption,
reliability
and comparatively low cost (5].
In order
to
design
the
modules (registers, adders,
and
tested.
Computer
design prior
Image
Correlator,
each of
the
multiplier), had to be designed
simulation
to fabrication.
was
Test
used
to
verify
vectors were
the
generated
for each module to simulate its function.
After
fabrication
testing is made
are two types of tests required.
In
this
case,
test
time operation.
chip when
testing
are
One is a functional test.
designed
an
internal
element
of the
circuitry.
Its
the proper operations of each module.
to
determine if
There
to
simulate
real
The test determines the performance of the
used as
the
vectors
on the chip.
there are
array.
goal
The other
is to
is
determine
These tests are made
defects in the chip
before it is
incorporated in the array.
The
and
timing
multiplier
alternately
for
the
into
diagram used
to
is
Figure
shown
in
Register
test
the
4A.
image
Data
correlator
is
loaded
X and Register W to provide data
multiplication.
Since
the
multiplying
functions
had already been thoroughly simulated when it was designed,
it
is
exercise
not
all
necessary
the
bits.
to
In
try
combinations
other
wards,
which
would
data were
chosen
that would demonstrate that each bit would toggle from 0 to
1 and from 1 to 0.
That is why the numbers AA (10101010),
15
55
(01010101),
the
DA
bus
to
FF
0
(11111111)
(refer
to
and 0 were
the
used.
By setting
block diagram in
Figure
2),
the multiplier output would appear on the DC bus two clocks
after the multiplication occurred.
Results of these tests,
as
that
shown
in
Figure
SA,
indicated
each
of
the
bits
toggled properly.
The
that
for
of
other
the
functions
adder
testing
the
and
the
adder
the
that
Figure
4B.
Once
loaded
into
Register A.
to
clear.
and
chip
have
The
clear
is
be
tested
timing
functions
cleared,
This causes
the
information
is
given
FFFFF (all
the adder
are
1' s)
in
are
to see FFFFF
+ 0 and the sum FFFFF to appear at the output (DC bus).
Then,
that
1
is
their
to
product
is
both Register
also
1.
If
X and
the
0.
This
tested
similar
A
adder.
one
approach
is
all
1's and Register
extra
1.
However,
the
largest
could
have
the
registers
would
be
Therefore,
DA
bus
except
FF
in
x
order
input must be
to
so
all
signal
to
x
is
working
set
to
the
( CLEAR-L)
registers
is
given
through
such
the
A contributes
the
255)
which
the
multiplier
FFFFF
F01FE.
all
the
that
that
obtain
function.
the clear
clear
( 255
A contain
to test
that
value
Register
good way
FFFFF
FF
path
taken
provides
adder
adder
possible
multiplier
(65025).
Register W so
summing FFFFF + 1 causes the adder output to roll
properly,
over
loaded into
is
out
FE01
of
the
Now all
the
1 1 s.
This
is
a
The DA bus is forced
contain
(the
1' s.
signal
Then
goes
the
low).
CLOCK
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ADDER AND CLEAR TEST RESUL. TS
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20
This sets all the registers to 0.
Figure SB shows that the
simulation results matched what was expected.
3.2
Three Processing Elements
Once
it
correctly,
has
the
next
This -was
test.
as
they
array.
the
a
functional
an array.
The array was
with
each
row
the rows
chips
performing
being combined
simulating
entire
the
do
operate
several
Therefore,
that
indication
to
chips
connecting
row of
output from
the
was
by
rectangular
the
good
of a
that
step
accomplished
independently,
leave
proven
logical
form part
together to
conceived
been
array
as
one
row is a
would
perform
properly.
The
be
smallest number
connected
concept
would
of
processing
together
and
work
three.
is
still
elements that
prove
The
that
use
of
two
demonstrate the accumulation and flow effect,
redundant.
form a
Figure
6
shows
how
3
partial row of an array.
LSI's onto this
configuration,
be constructed.
The
chips
the
could
array
does
not
while four is
were
connected
to
Similarly connecting more
a
row of
row is limited to
up to
16 LSI's can
16 due
to
the size
of the accumulator.
One
row
of
one-dimensional
let the
the
processors
correlation.
search region
template,
is
and
S
be only
=
the
equivalent
To
simplify
to
the
4 pixels wide.·
search
region,
performing
the
a
equations,
Thus,
if W =
correlation
21
..
I
I
~~
I
l
!4 .T
I I
1
~'
!--~X~
'
1
J
i-
1-11
I
J
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0
u
~:1:
,.-,
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c:-
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w_,
22
operations can be described as follows:
C(1)
the
and
two
C(2)
=
wl w2 w3
(1)
s
=
s1 s2 s3 s4
(2)
C(1)
=
s1w1 + s2w2 + s3w3
(3)
C(2)
=
S2W1 + S3W2 + s4w3
(4)
are
possible
Figure
area.
w
the
two
correlation values
positions of
representing
the template over the search
7 shows how the computations are achieved by
the system.
The
first
requirement of
the
functional
this
The
right.
enter
is
the
followed
row
first
the
to shift to the
pulses,
(this
by ·the rest of
n processors
data
flow is
from left
to
template data of the right-most processor must
Keeping
left.
The
accomplished.
this
Figure 8 shows
configuration is loading the template data.
how
test of
is
W
3
in
the data,
load signal
the
timing
in order,
from right
to
(LOAD) high allows the data
right with each clock pulse.
( 3 for this
diagram),
example),
the load signal goes low,
If there are
then after n-1=2 clock
storing the template data
in its corresponding processor.
The functional
test is
four different templates.
loaded according
to the
divided into
For each part,
four
parts
template data was
timing described in Figure 8.
template and
search region
output would
have an
data were
selected so
easily recognizable
using
The
that the
pattern and
also
23
tj)
z
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(~
r--.
C
r-
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L
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r-
-.• .
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(_)
occ
c_
-,-l-
,-
·
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CLOCK
r···------·------· ---
CLEAR-L
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DATA
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7J>V0------·--··-·······
1
OBDI
W1
oa 02
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----·-----·----------[ ___ -----·-----··-----J--
LOAD
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FIGUHE 8
-~-
I
I !'v1 TNGl ;·)
(') rvj
l....d.H J F'
\n!
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T /', ("'
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L_.I-.... . .l /\• I.____.J T_._ I\.1 ~ l(--,~J. -r Ef-1
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+:-
25
exercise as many
bits as
possible.
Table I
lists the data
used for each part of the test and the expected output.
The
search
loading of
region
the
data
template
are
loaded
data.
For
directly after
this
the
three PE example,
it takes seven clocks from the time the first search region
word
placed
is
on
the
input
data
bus
until
correlation data appears at the output of the row.
valid
This is
because it takes three clocks for the correlation operation
in
the
first
processor
and
two
clocks for
each succeeding
In other words, with n processors it takes 2n +
processor.
1 clocks for valid data to come out of the row.
thereafter
produces
valid
data
until
the
search region data has passed through the
flag
the
entered
end
as
of
data.
the
search
Figures
9A,
Each clock
entire
row of
region,
trailing
9B,
and
9C,
row
PE's.
01s
of
To
were
9D contain
the
simulation outputs for each part of the functional test, as
given
in
Table
I.
This
shows
that
indeed
the
Image
Correlator LSI's perform correctly as a systolic array.
3.3
An 8 x 8 Systolic Array
If
the
desired template
is 8 x 8 pixels,
the systolic
array will be an 8 x 8 configuration as shown in Figure 10.
The
the
basic
array timing
three
First,
PE
is
example
template
data
the
in
same as
the
the
timing used for
previous
is loaded into the
subsection.
array.
Valid
data appear at the other side of the array after 17 clocks.
26
TABLE I: FUNCTIONAL TEST DATA, THREE PE EXAMPLE
Part A
w=
s
1 1 1 ]
[
C(1) = 1'
C(2) = 2
C(3) = 4
C(4) = 8
C(5) = 16
C(6) = 32
+
+
+
+
+
+
2
4
8
16
32
64
+
+
+
+
+
+
4
8
16
32
64
128
=
=
=
=
=
1 2 4 8 16 32 64 128 ]
DEC
7
14
28
56
112
224
HEX
7
E
1C
38
70
EO
Part B
w=
[ 64 64 64 ]
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
64(7)
64 ( 14)
64(28)
64 (56)
64(112)
64 ( 224)
=
=
=
=
=
s
=
=
=
=
=
=
1 2 4 8 16 32 64 128 ]
DEC
448
896
1792
3584
7168
14336
HEX
1CO
380
700
EOO
1COO
3800
27
TABLE I: FUNCTIONAL TEST DATA, THREE PE EXAMPLE (cant)
Part
c
w=
s
[ 1 2 4
=
1 2 4 8 16 32 64 128 ]
[
DEC
C(1) = 1
2
C(2)
C(3) = 4
C(4) = 8
C(S) = 16
C(6) = 32
+
+
+
+
+
+
2(2)
2(4)
2(8)
2(16)
2(32)
2(64)
+
+
+
+
+
+
4(4)
4(8)
4(16)
4(32)
4(64)
4(128)
=
=
=
=
=
=
HEX
2T
15
42
84
168
336
672
2A
54
A8
150
2AO
Part D
w=
[ 32 64 128 ]
C(1) = 32
C(2) = 32(2)
C(3) = 32(4)
C(4) = 32(8)
C(S) = 32(16)
C(6) = 32(32)
+
+
+
+
+
+
s
64(2)
64 ( 4)
64(8)
64 ( 16)
64(32)
64 ( 64)
=
[
+
+
+
+
+
+
1 2 4 8 16 32 64 128 ]
128(4)
128(8)
128(16)
128(32)
128(64)
128(128)
=
=
=
=
=
=
DEC
672
1344
2688
5376
10752
21504
HEX
2AO
540
A80
1500
2AOO
5400
TIME CLOCK CLEAR-L LOAD DATA DBD1 DBD2 ODATA
0. (j
100.0
200.0
300.0
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700.0
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900. 0
1000.0
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1200. 0
1300.0
1400. 0
1500. 0
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1800.0
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2000.0
2100.0
2200. 0
2300. 0
2400.0
2500.0
2600. 0
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2800.0
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FIGURE 9A
THREE PROCESS l NG ELEMEi~TS
TEST RESUL YS, PART A
I,
N
CXl
;-"'
.·~·
TIME CLOCK CLEAR-L LOAD DATA DBD1 DBD2 ODATA
0. 0
100. 0
200. 0
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FIGURE 98
THREE PROCESSING ELEMENTS
TEST RESULTS, PART B
N
1.0
TIME CLOCK CLEAR-L LOAD DATA 0801 0802 ODATA
0. 0
100.0
200. 0
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FIGURE 9C
THREE PROC ES.:O I NG ELEMENTS
TEST RESULTS, PART C
UJ
0
TIME CLOCK CLEAR-L LOAD DATA DBDl 0802 ODATA
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FIGURE 'ID
THREE PROCESSING ELEMEt-HS
TEST RESULTS, PART D
w
f-'
32
.,
"'
,
'A
..
~
33
In
order
to
obtain
the
final
row outputs must be totaled.
an adder tree,
best
match.
provides a
greater
correlation
result,
all
the
This can be achieved by using
the output of which is used to determine the
Once
the
template
continuous flow
speed then had
data
is
loaded,
this
array
of correlation information at a
been previously
possible with other
types of approaches.
Besides
speed,
flexibility.
this
array
has
the
advantage
As the LSI design stands now,
any width and up to 16 processors deep.
However,
the depth can also be increased if desired.
8K
gates.
soon
be
But,
inviting.
increase.
improvement
can
technology
possible
single LSI.
CMOS
to
place
be
increasing
by slight
accumulator,
time
of
an array can be
to
this
design
size
modification
At
the
of
the width
of
the
fabricated with an array
is
always
more
than
improving.
one
It
processor
of
may
onto
a
This would make this systolic design even more
Size and cost would be reduced while speed would
LSI
will
technology
provide
design problems of today.
is
the
here
now
means
to
and
solve
its
continued
many
of
the
CHAPTER FOUR
MODULE PERFORMANCE SIMULATION AND RESULTS
This
section
simulated.
describes
Schematics
following
section.
of
how
each
the
various
module
S imula ti ons
are
were
modules
were
included in
on
modules
the
grouped
together where appropriate.
4.1
Registers
There
LSI,
a
are
two registers
16-bit
register
(REG20).
Both
were
register
(REG4).
used on
(REG16)
and
constructed
Thus,
the
the
Image
a
Correlator
20-bit
from
a
register
smaller
4-bit
same testing approach was
used
for all three modules.
First,
using
the
set to
1,
outputs
switch to
input
(CD)
Q outputs are 0).
initialized (all the
are all
clear
so
on the
all 1's.
tests
the
ability
next positive clock edge
The
possible types of data
Next,
the
guarantee
1's
stored
register,
held
that
low
again.
in
and
clear
the
This
one
insures
the Q
D inputs are then switched
the
Q outputs become 0.
register
function
works,
Therefore,
then the
are
to
accept
both
(0 or 1).
clear
it.
through
of
registers
The data inputs (D)
to 0 so that on the following clock the
This
the
must
the
1' s
clear input
clock edge
that
the
34
be
register
are
before
should
clocked
(CD) is
clear
checked.
into
To
have
the
brought low and
being
signal
brought high
will
override
35
the
clocking
of data
into
summarized in Table II.
the
register.
Test results are
36
TABLE.
II.
SIMULATION RE3ULTS,
4-BIT REGISTER WITH CLE""R
REG4
TIME CU". CD
1 C~O. 0
2()(). ~'::·
1
1
1
'-
500. ()
60C: c~
~
1
0
0
1
0
1
D
oooc~
1
,~.
..)
000()
1111
i 1 .ll.
300
~._}
400. 0
500. 0
600. C•
700. ()
eo~J.
0
9CqJ. 0
10{) (), ~J
1100. 0
-1200. 0
11 i 1
l 1-1
0000
OGC~()
1.COO. C
1; ";
1111
11 ~ 1
REGi6:
" ' •,.J
11 1 1
0000
0000
8()t.J. C·
1200.0
C. :J
0000
1 i 11
ocoo
0
0
1
1 ,-, ("\ 0
200. 0
- xxxx
1111
4
c:_·;;~_
G
1 i i... i
()
TIME
REGISTEFS
0
i6-BIT
.;. ......
1111
1111
i
1111
RE(~ISTER
WITH CLEAR
CD
0
i
"
1
OOOOOGCOOOSCOOGC
111111111::1:11:
1
1111111111111111
0000000000000000
0000000000000000
1
1 1 11111111111111
ooooo::~=.:>:::<:
11111ll11l11111!
000000000C0COOC0
r~.
··J
1
0
11111l~:l~1lill?
:y:x·occ·
1
0
0
1111111111111111
<
0
111:111111111111
0
1
1
1
1
1111111111111111
ooooooooocoooooc
-:.111111111111111
oooooc:::·coc.::,coooo
111111111~11111.1
1111111'2.1:.11:::.111.
1
1
1111111111111111
1111111111111111
111111111:111112
1111111111111111
"
0
1
l)
@
'
37
REG2~).
-
11111~111111:::1::11
0
1
::.
.L
4C(O. 1,}
0
1
500
"
G
...'
1
OOOOQOOOOOOOOCOOCQOO
OOOOOOJOOOOOO:OCOGQO
111111:111111111 :L:.::.
11:111111111111111::
11111111. i 1111: ~ 1 :i:.: - 11111111111111111111
0-
-· C;()
f_,
,;::.
.3C!(j
·-
·-.
i--i~
t:.J '-'' -·
7Ctf) '
·~
E:C~i)
~
....
'.>'
-='00 ,_
~
~~(;!S~ER
0
C·(]0
i
-;
20-EIT
(tiJ(j
-~.
-~
-- i_,··""' -1 ~.}
1 2C"C-. ;
"l
-
~-·
·~·
'~L~AF.:
WITH
~
C:
.l.
0
1
1
r;
....
•l
~
0
1
1
illi.:~.::1111:11111
1111:~1~1111111~1111
.
c~oc:o· ~·<·_,:=~.:··_:,c~oct.Oo<);:,oc,<J<J
0000~CJOGOC000000000
i 111
~ :~
·;,_ :.1111111111 i 1
OOOO~J00000000000000
11111111111111:1:~1:
oooo
:~ooooooooooooc
111t111111!.1i1l1::..1:
il11·.
= :~~11111111111
ll111li111111111l:ll
1111~:~1:!1111111111
111111111111illll~l:
1111~~llll11111111ll
38
4.2
Registers with Parallel Load
An
on
the
8-bit
Image
registers
must
register with
Correlator
LSI.
parallel
load
with
be
parallel load
tested
for
the
It
is
built
(REGLD4).
same
(REGLD8) is used
from
two
REGLD4 and
properties
as
the
4-bit
REGLD8
previous
registers along with their parallel load function.
First the registers are initialized (all
0).
Data
(LOAD)
the
on
is
the
active
data stored
brought low for
1 1 s)
to
be
data
to
all
D inputs
low,
in the
that
all
as
1' s.
The load
long as
register remains
outputs are
signal
LOAD stays high,
the same.
LOAD is
one clock cycle causing the input data (all
loaded
O's,
demonstrates
so
are
Q
into
the
that
the
register.
register
both
0' s
is
and
Then,
changing
the
loaded once
again.
1' s
successfully
can
be
This
loaded into the register.
To
show
that
the
are
loaded
necessary,
1' s
the
signal
clear
resetting
functions
the
of
in Table II I.
(CD)
register
these
is
to
register
can
into
register
the
brought
0.
registers.
low
This
Test
be
for
cleared
a
checks
when
again.
Then,
clock
cycle,
out
results are
all
the
summarized
39
TABLE
I
r I.
.S
IM:_::_ATIQt~
REG!STE~S
REGLD4
RESi..)LTS~
WITH PARALLEL LOA:
4-BIT REGIETER WITH CLEAR AND
T It1E
!]_
-
'~
1 0(.'
,.,_
20C·
{J
300
~J
4()(~
f_j
.soc
6\]()
-
0
J
70\:· c
80C· '""':
900. . '
...1 ooc
;
.L
0
5{)(}. IJ
i 600. ()
1 700. (=J
l 8Q·.J. l -'
·-
9<)C· :-.
2000. C·
1
~
CI:· LOAi:<
c~
:
1
~
J
·,
~
;...,
•..:
1 ' <.i. 1
1 1 <.l 1...
< i
L ... 1 •
J..
11 1 1
•.i. 1 i .l•
0
~
L
.
.
'L
·-·r.
1
0000
1
1
1
o,-,,~
......
".~~·...!
f'i
0000
1
c'!
OC~iJC!
'...
l
1
1
.L
... 1 ' 1
11 11
l ...i 1 1
'.i. l 1 1
1 i... 1 i
1
1i 1
:!.
< .;.
.I..
·~
(;
i
--. c,
1
':..
i
(i
i
-
1
...
1
l
~.)
. . 1 '.
1
1
0
·-:.
Q
-;
~
.;.
I
D
i
1
~.}
.J
1 1 co ;J
i 20<::)
._;
...
<
l 3C~(} _ C·
1 4:)0.
,:u•:.
..t.
<
...
.
i
~
.:.
..
..
.
1;
1 1l
..
FAR~L~~L
L
1l 1i
1l
.i.
11 11
XX\
oocc
00\X
OOG0
OOC<:
1 1 i ...
1 -'-1 ' ··11
11'
j.
~
or.;-- .-V;...
OOOC'
ooo:-::·
OOC<:
1 1 -· '
1i
1 i.l
.- i...
OOC<·
00:-JC:
OC"~:C
C\f"lt~,.-,
..
v~-
00<:.<~
L~AC
40
TABLE
r
J.
T
S It"HJLATION RESULTS,
T
~.:.
.
REGISTERS WITH PARALLEL LOAD
REGLD8:
8-9IT REGISTER WITH CLEAR AND
TIME CU<. CD L!JAD
10().~)
0
?OC:. ~:;
400. '--'
5 \){) C·
0
1
1
1
1
1
0
~-_,~
600. 0
1
1
00. ··~'
800. -~
1
,-
900 0
1
7
1000 ()
11 CO. u
1
1
·~·
.
0
1
l
1
1
i
130C G
1400. G
0
1500. ·~
0
1cOO.
o
1
1
170C C
l
18()0_ ()
1
1900 G
""
1
1
·.-·.
PARh~LEL
D
111-il'!.ii
X xx:::::
1111t11!
111:1111
11111111
OOOOOOOJ
11~11111
111111ii
00000000
ooooooc;o
OOOOOQOO
oooooooo
11111111
11111111
11111111
11111-11
11111'11
11111111
11111111
111"1!11
tcon~. 1
/
:~'<'
oooccoo:
oooccooo
OOOOCOOG
illiii __
111 1 11::
1111. ·r 1 -; ..
1111 ' i . ~
oooococ~
ooooooo:
00000008
OOOOOCJJ
111L1l_.
111::.' '1111111·OOOOGCDC
ooocooc~
11111111
ooooooc:
11111-11
11111111
00000002
0000000(
LO~C
41
4.3
Adder (1-bit)
A 1-bit full adder
for the
8~bit
2 outputs
(F,
(ADDER) was designed as a component
multiplier.
It has 3 inputs (A,
Because
CO).
this
is a
circuit designed with only 3 inputs,
is
straightforward.
combinations
these
for
A,
combinations
outputs
(F,
for
There
B and
were
the
are
the
used
sum,
as
CO,
B, CIN)
combinational
and
logic
the test for the adder
only
8
carry
in
the
test
for
the
possible
( CIN).
vectors
carry
input
So,
all
and
the
out)
monitored for the correct results as shown in Table IV.
were
42
TABLE
IV.
SIMGLATII]!-i RESULTS,
ADDER:
1-8 IT
AD:ER (1-BIT)
t,C>DE;;;:
FUL~
----------------------TIME
G.
A
r:;
....,
CHJ F
Xr v'"'
X
co
X
0
0
()
100. 0
\]
r.
•.J
-
r,
2~Jc~.
Q
l
:]
1
c{
3C C;.
4C(i.
500.
600.
700.
0
0
0
c!
0
·,
._,
l
I)
1
8()0.
-'
.
.
"-'
'.J
0
i
\...·
'•
.i.
...i
0
~J
-
i
c
0
'
0
.;.
0
'...
'4
·-
1
1
r.
\J
'L
<
;,.
..,
,,.·~
l.
1
43
4.4
Adder (4-bit)
A
2 0- b i t
Correlator
make
a
ADDER4
any
two
15,
along
them.
than
256
input
4-bit
8
most
a
a
nee d e d
with
combinational
numbers,
carry
in,
fast
Just
and
in
low
unlike the 1-bit adder,
value
possible.
Actually,
possible
combinations
of
for
connect
1-bit
takes
from 0
and
to
vectors
it
512.
to
is
This
use
to
may
seem like a
test
relatively quick
a
to
adds
2
there
4-bit
single
(on the
large
number
circuit,
order of
are
binary
When the carry in bit (CIN) is added to this,
comes
to
there are many more
combinations
reality,
was
It
active,
input
inputs
I rna g e
like the
circuit.
ranging
is
the
method
carry,
logic
which
f or
design
20-bit version.
binary
with
was
efficient
(ADDER4)
get a
is
However,
numbers.
total
adder
them to
adder,
( ADDER 2 0 )
The
LSI.
4-bit
five of
a dd er
but
the
of
in
minutes).
By using all possible input combinations for this adder,
it
insures that any larger circuits made using this adder will
be
correct.
The
only
possible
interconnecting the adders.
Table V.
design
errors
would
be
in
Test results are summarized in
Q
'
44
TABLE
t.).
S I M'._,ll_A T I ON RESVL TS,
~-~-EITi
ADDE~
4-B IT. ADDER i.JITH FAS: C A;:; F' -,{
ACDER.:l:
----------------------------------TIME
A
B
c IN
0.
()
)(XXXr
X X X Xr
100.
ci
c·
300. i'\.....
0000
0001
0010
400. r.
·~
0011
i
i
1
1
1
5(r(r_
2\JtJ.
7QC.
c!
0100
0101
01 10
8iJ(),
C=
01 :!.1
9~:fc!_
r,
1 c~c·i).
c~
1000
1001
11CO.
c~
6()0.
i.)
,~,
·~
...
.~.
12C'0. ·~
i3<)Cf. ()
140t). ·-'
1500. 0
1600. ()
17{)0. (J
1800. {J
1900. ("'.
2(JCfCI _ 0
.-.
·~·
21<]().
,-,,
\.,'
22CrtJ. :J
2:300. .._,
2400. 0
.-.
25~J'J'
C/
2.6C1C!. c
27()C'. c;
280C:. ()
2900. 0
30C'C'. C:
310C'. 0
3200. G,
3300. 0
34C·C•. 0
3500. ("\
·~·
360<). c!
3700. C·
38C·(). C·
390C~
.~.
·~·
4000. G
1010
101 i
1100
1101
0000
00()0
0000
0000
0000
'
i
1
1
1
1C'C'0
000!)
1
0000
1
1001
1 01(o
'-
1
1012.
1 lOCI
1 101
_.;
1
1 11C
00()()
0000
0000
C00C
OOOCi
OOC·O
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
1001
OOC~l
1010
1011
0001
0001
1100
1101
11 10
0001
... 1
'f ~ 1
.:...<.
0000
0001
0010
0011
0100
0101
0110
01 11
i
OOL
OlOG
010::.
01hi
OiL
0000
1
0100
\) i ~J 1
01 10
01 11
1000
o.ooc-
,,.
"
:;,
11 10
11 11
oc i
x· xn:
::o
000::.
0010
0000
0000
0000
0010
F
0001
OCOl
0001
0010
1
1
1
1
1
i
1
1
;
...
i
1.
J.
1
'i
1
i
"
"
..
1
1 1L
'J..
0001
0010
0011.
1
1
010C·
'
010~
01 iG
01 i i
1
i
1000
1 ·- 100i
1010
1
1
i 011
i
i 100
"...
.
~
'...
1
1
1
"
1
1 101
1 11C•
1 1L
.'
1
OOOG
()
1
001C·
0011
1
1
OOOC•
C' 1C•1
'J..
0 ll!:;
0111
<
1
i
1
0010
1
0010
COlO
0010
1
0010
1
1
•.I.
0010
0010
1
1
1 lOG
1001
1
1
L
i..
;.
1
~
1
45
TABLE V. SIMULATION
FE~JL~S.
TIME
B
A
t_;
4100. ''J
IN
101()
l
1011
iOC·1
(};J 1 c~
4.300. G
4400. 0
101:)
;_
101~
1
4500. 0
11 (.()
110:
111 ')
11 .l. l
1
46C·O. 0
470C•. C
4800. 0
4900. 0
5000 .. 0
5100. 0
,_.._
11
OOi.l
1GC·C!
58()()_
C·
6000. iJ
6100 0
6200. 0
1C•()1
1Q1Cr
101i
1100
1101
630(). t}
.l
.L.
1
i.......
i '.c.
67C~C·.
Q
6800. C·
6'-7'00. C·
7000. 0
L
('t~)
c~
0
6600. 0
11
.,
OlC<
57f)O.
"' 1
ol
l
1
vc~
.~.i-1
o
650~~.
1
OC·: l
00 1tj
t_.}
59C<O. 0
_.. ../
0000
ooo:
001.;,
5400. 0
5500. C·
...'
~.r·,-<
t~t .... ·
4
1
1
1
.....
<
l.
....
i
i
1
4
;--.,-.. ..,. 1
••• ..;
....
..:.
.£,
0000
0001
0010
7100. 0
7200.0
7300. 1)
7400. 0
7500. 0
7600. 0
0110
0111
770,:-. 0
7800. 0
1100
1101
7900. 0
8000. u
111C'
111 i
8100.0
0000
1000
1001
1010
100C
110::..
111C.
1111
010C:
000::.
0011
0 10~:
0102.
0 11·.~;
OiL
10QC:
100l.
10Er
1011.
11 OC.•
1 iO~.
111·-·
111 '
0000
C,,.,
·....J
i
1
<
J,
1
.
1
J,
0
0
1
1
1
i
1
i
i
1
1
0
ooo·~
.-.
l ;_i
0011
0100
01C1
F
i
4200. 0
56c~v.
<4-BIT>
4-BIT ADDER WITH FAST CARFY
ADDER4:
5300.
ADD~~
l.
1
1
ll '}
.~. .-·..
'...t""'
"-''.J
o:oo
c:co
01 C·O
010()
C 1 C:•.J
1011
o1c-o
1
1
1
1
1
1
1
1
1
i
1
1
0010
G
o1vJ
1
1
1
1
1
1
0101
0110
0111
1000
1001
101C
1 Oll
1100
1101
1110
1111
OOOG
0001
0010
001 i
010:.
1
1
1
1
1
0
0
0
0
1
46
TABLE
V.
SIMULATION RESILTS,
ADDEF
<4- !3
(cont. )
4-BIT
ADDEF:4 ·
ADDER L..JI TH
FAS~-
CARR~.-
----------------------------------TIME
•)
8200. ,_,.
8300
tj
840C>.
()
85<::•0.
86(;0.
t..J
!
..
·~·
87C!C!_ 0
8800. l.j
8900. 0
90tJO.
91GO. (J
9200. \_;
',_,}
~
930G.
q,
~1r-.r,
....,.\.1\.:
c
0
9500. 0
960(>. 0
t;?OO. Ct
9800. 0
9900. cl
1 OOCn:~. 0
10100. 0
10200. c~
1 030().
(}
1 Ct4()()
c~
10500. !--
'.../
1 {]6'JCJ. 0
10700. 0
10800. 0
.__.
1 09C:O_ ,.-I
1
... 1000.
'J
1 1100.
c~
1 1200. 0
1
... 1300. Cr
.
1400. 0
11500. 0
.!.
11600. 0
11700. 0
1180~).
0
1900.
f"'.
i
~
·-·
12000. 0
12100. 0
12200. r.
'..J
A
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
111C
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
c IN
I3
F
co
0101
1
1
1
.100-~
0101
1
100::.
..
1
lOE
1
1011
~
01 rt ~
0101
0101
0101
1
1
1
1
11 o-::1
1 10:.
111()
0101.
1
n•
...l.L.
0101
Q1:J1
0101
0101
·i'l
\_, ...
Oi iC
01 L.
i
...
1
;
~
...
1
1
.L.
1
111:..
1
0
1
oooc
ooo:
1
0
01 <J1
1
...
001C
0
0101
•...
1
1
0011.
OlOC
011(
0
101
0110
{]1 iCt
01 iC·
'f
...
0 11::.
1 10C
1
1
1
1
1001
1 OlC·
1
~)
01
'i ,....,
'-'-
0110
1
.
0
.!.
1
0110
01 10
011.0
01 10
1
101}.
i
-;
4
100C
1
110~
1
1
1
0110
1
1010
1011
01 10
1
01 10
1
1100
1101
1110
1111
0000
0001
0010
00.11
0100
0101
0110
0111
1000
1001
01
i~)
1
01 10
01 10
01 10
0111
1
1
1
0111
1
0111
0111
0111
0111
J.
..
L
1
1
1
1
1
• <
l. ~
1
01 11
01 11
1
01
01
i
..
... .l.
....
...!.
1 110
1 111
010()
0001
0010
0011
0000
0102
0 11:!.
100C1001
1010
1011.
1 100
1101.
11 F:'
1111
0000
1
0
0
0
0
0
0
1
1
1
1
1
1
!
1
1
<'J
IT :•
47
TABLE
V.
SIMULATION RE:::v:_TS, ADDEP {4-BITi
(cant. ;
ADDER4: 4-BIT ADDER WITH FAST CARRY
TIME
::IN
A
1 ....
01 L
12300.0
1010
1240tJ. 0
1011
12500. 0
1100
Oi __
12600. 0
1101
1110
<Ji l
0' '
12700.0
12800. ()
1.2900.0
(j
L
..
1~
1
OOOi
1
1
1
1
0010
idl
1
1300C·. :.)
0000
0001
13100. '.,.}
13200. 0
13300. 0
0010
0011
0100
1
1
1
13400. Co
13500.0
13600. 0
0101
0110
01:1
1.3700. !)
13800. 0
'1.000
1001
13900.0
14000.0
14100.0
14200. 0
14300. 0
14400 0
14500. '~'
14600.0
1011
1100
1101
1110
1 11
1
1
:!.OC::
;
L
iCrC·.:
1 O(JC~
1
1
1
1 00:)
1 cJ t)-·')
l<JOC·
1
1
1
10CJC·
10Cl
14700. 0
0001
0010
14800. 0
0011
lOCi
1
l
10Cl
1 5000. I.J
! 5100. 0
0100
01C1
0110
0111
15200. 0
15300. 0
0000
.
J..
1000
1550<) 0
1001
1010
1
l
1
iQ(}l
<
15600.0
1011
15700.0
15800.0
15900. c:·
1'100
c
.l.
1
10C) l.
1101
1110
1
1
1
1
16100. 0
1111
0000
1 (H} 1
iC :.!J
1620~J.
0
0001
!.0 1::·
;
16300. 0
0010
10 1.C
1
16000. C•
001C'
co
0
0
("",
•..;
0
0
1
1
1
1
1
1
1
0
0
0100
0
0
0
0101
OiL)
0111
0
<J
1001.
1 Oli)
1011
110C
1101
.,
i..
1
.
1
1
l
1
lOC'l.
1()01
154()0.
0011
0100
010i
011('
100C
1001
101C
101i
1100
110:
1110
111 i
000(';
0001
001:i.
1
1
1
I
F
1
1..
11L
OOOC:
0001
001C
0011
OiOC·
0101
0110
0111
lOOC•
101C
1011
1000
...
0
0
i
0
0
0
0
0
Q.
1
..
i
1
48
TABLE
IJ.
S It"'ULATION RESULTS,
A DDt:::;
!4-BITl
<cont . .
.::.DDER4: 4-EIT ADDER WITH FAST
C~FR
'{
------------------------------ ----TIME
16 1+0(j. 0
1658C~. 0
i 66()0. 0
16700. 0
l680cJ. 0
16900. 0
1700(). 0
17l.OC•. 0
i 72{JC'. 0
1 73C:). 0
1 74(j{]. 0
1 750C·.
~J
1 76tJCJ.
1 77CiC...
1 78C~·C'.
1 79(i0.
1800•J.
1810().
18200.
0
0
0
Ct
l830C~.
1:3400.
18500.
i 86CtCc.
0
0
0
0
(~•
~·
~J
c
187:)C!. 0
18800. {)
189CO. 0
19000 ~J
19100. c~
19200. 0
193CtQ. 0
19400 0
19500. 0
19600 0
19700. 0
1980(). 0
19900. 0
200<]( c~
20100. 0
1 .
20200. ()
2<)3C~O 0
20400. 0
A
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
11 10
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
01.01
0110
0111
1000
10()1
1010
1011
B
CIN
iOlO
<
1010
1010
1010
10 lC~
1010
1010
1010
1010
101C
1010
1010
1010
1011
1011
1
1
"I
.1 l L
1
1
1
010,::·
000:
L
i
•.. 1! ':.::
,~
•.J
'.
·~
1
1
1
OOlC
(j
001 i
.
0
0
1
0 10'
c~
.i.
c~
1 1::
C;
1
1
1
r.
I...J'
~
i
.·
...
4..
~
1 oo·~
c
1
lOU.
1 iQ;-;.
1 10-..
...
1
1011
1011
1011
<
...
1011
101.1
1C' 11
1011
1011
1011
1011
1011
10 i i
1011
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1:00
(l]
1 10:..
.i.
<
1<) 11
F
!.
1
i
i
L
i
.
.
1
.l.
1
1
1
1
i
1
1
1
1
.....
1
1
ooo~=·
"I
L
;
l<X.'
L
1 i.C·
!..
t 1:
0000
0001
001'::
001 ":.
010G
010!.
0 11;}
011l
100•:::'
100::.
1010
1 1 o~:,
J..
1 101
1 1 l~J
1 1 i <..
.~
·-'
·'
·~·
<
l.
1
1
1
c,
!-)
•.I
0
;_.J
c
c;
c,
0
{)
;j
,......
'
J..
1
1
1
oooc
0
0001
:}
OOiC.
~J
0
.1.
OOli
0 10()
\]
1
0
!_t]-~
'.r
1
Ott::::,
011i
0
<
l.
<
1
.~.
\]
49
TABLE
v. S! r~t.!LAT I C~.J RE::JLTS,
\
con "I:
ADDEF
C4-B IT;.
}
4-BIT A!)!)EF· wiTH FAST CARRY
ADDEh":4:
----------------------------------TIME
. 1 OS-:
205()0. 0
20600. ·~...
."1.100
101
0
0
1 1 10
i 111
0000
.- 1 QO
-j
L
0
0001
0010
001 1
(j
01CO
G
~~
.
01
,~
207()().
206C~{J
20900.
;::tooo.
21 100.
21200.
2 :!.3c·~~:..
214CG.
c0
0
'
1 :!.00
i
.L
{]~J
'-
11 <J 1
:\"i
...1 vJ.
11 ; ' 1
· - - .j,
2160C} . '-..J
21700. (}
218Q;J_ {)
21900 0
01 1 1"'1000
:!.001
11 \] l
i 1 Cl
<
"' ·-·
i 1 {) 1
.-4. iJ.
1. ; '"""'
1 l ~~' 1
-i
... : t] 1
1(110
1
22000.
1( 1
1 100
"'l. 10l.
21.sc.c· ...~·
~.
M
c IN
-;-:.
u
A
·:.J
221C:O. 0
22200. 0
223C~O.
c
224(1().
0
22500.
226CO.
227C<::.
228C<·.
229i)(
230()(].
23100.
c~
1
0
c~
0
0
0
0
232c~~J
·J
23-300. ()
234-00. (J
235tJO.
23600. 0
2370Cs. 0
2380C!. 0
239C:O. 0
24000. 0
c
24100. 0
24200.
2430C•
24400.
24500.
0
0
~
o""'\ o(
·..J~V:..
i , .....
.l 'J
L
<
l.
1
; i
10
'-"' ... ...
L
•
1 1 1
.1.
0000
0001
0010
001
i
J.
01t)Q
0101
C~l 1 ~J
.~
i
~-l J..
'J. 1
1000
10C1
1010
101 1
1 100
L
1101
11 10
11 <.1. .,
0000
0001
.L
0
0010
001 1
0
0100
-
1-... .-
L
~
1 ("\ 1
'"'"
11 C~1
1
i
1
1
1
..
;
1
...<
1
1
"'l
1
1
1
1
1
101
1
1 1 {) 1
1 1 <) 1
1 101
".l.
<
1 l•)
1
'i
-!
1
1
1
L
4
. 10
1 -j... lCf
1110
1 1 10
< ~
.L
10
- 1 10
l. "'... ~l. t}
.
~
1 1I. <4 r.
\.r'
1 1 10
i
1 1C(
,,..
1
1
...<
i
1
1
1
1
1
1
1
.
... 1
1 1 10
i ... 10
11 10
.. .,
...... 10
<
J.. 1 1 1
.;
... l 1. J.
1
1
1
• <
1. .l.
1
1
~
~-
~
11
i "' 1 1
11 ...!. 1
..
.L
1
1
1
1
CD
F
100C•
1001
101:J
101:
1 101.
1 1 !IJ
1 111
.
~
0
0
0
0
...'
1
ooo·:.
1
0
0001
~J
0010
0
0
0
0
0
001 i
0100
0101.
01 10
01 "'J. l
n
·~·
100()
(}
1001
iOE'
0
0
1011
1 100
;J
1 110
1 < 11.
0
1
1
010C
0
0001
001·'J
0
0
0011
0
010:!.
01 10
011:
()
oooc
c,
f)
()
1 10C
1001
101<:)
1011
1000
1 101
0
0
;). 1 11
0000
1
0
..
0001
001C·
001 l
0
r.
'-"
0
r.
v
,,,_..
0
0
50
TABLE V.
SIMULATION RESULTS.
(cont. 1
ACDER4:
ADDER c4-BIT>
4-BIT ADDER WITH FAST
TIME
24600. 0
.;:4700. 0
0101
0110
24800.0
0111
24900. 0
1000
25100. 0
1010
1001
25200. 0
CIN
A
:::. 11
11 ... 1
11 ~ 1
111 .i..
11 i 1
11lt
1011
1100
11
25400:0
1101
i l 11
;_ ::·500. 0
~'5600. G
2'5700. 0
25800. 0
25900. 0
26000. 0
;: ::; 100. 0
1110
11 11
0000
OOC1
0010
001 i
0100
0101
0110
0111
1000
1001
1010
- '- 1.1
26200. 0
26300. 0
26500 0
2660~J.. 0
26700.0
26800. 0
1011
2.:'::,900. 0
2700\J. 0
27100. Q
:;:7200. 0
27300. {]
27400. 0
275()0. 0
27600. 0
27700.0
278tJO. 0
1100
1101
1110
1111
0000
0001
0010
27900.0
28000. 0
28100.0
28200. 0
2830Ct_ t)
0011
0100
0101
0110
i
!
OOtJC>
C;fJ <JC~
oooc
occ::c.
0000
OOC·O
00(}0
0000
0000
0000
ooco
0001
0001
0001
0001
o~J <J 1
0001
OCG1
··~
<
.l.
1
1
1
1
()
0001.
0
0
0
0
0
0
0
(}0 1 C;
001::.
0
0
0
0
0
0
0
0
r.·
0
0
0
0
0
0
0
OOC'l
101C·
0
0
0
28600. 0
1101
OOGl
100C
100::.
1010
1 OL.
i
0001
1100
11C~
,.!..•.i. n·-...;·. __,
1000
.1001
0001
0001
0001
0
1
00()1
1011
F
010~
0111
2840G. <)
285GG. G
CAF~Y
1
010,J
011C
0111
lOC<·
1001.
10L·
1011.
llOC
110:i.
i
l.
...
-.•
1
l
111 c~
1111
0000
oot:.::·
001 i
010G
0101.
0110
0111
lOOC
100:.
1010
1011
110,-::·
110~
0
1
1
1
1
1
1
1
1.
1
0
1
0
1
"
'
51
TABLE v.
S I t1tJL ..; T I 0~~
RE·::;~JL TSI
(cont.
ADDC:R
(4-B!T}
)
4-BIT ADDER WITH FAST CARRY
ADDER4:
----------------------------------TIME
A
g.
CIN
0
0.
0
0
0
0
0
0
0
0
0
28700. 0
28800. 0
iliO
COOl
1111
OOC1
~.)
0000
GOlO
0001
0010
001G
0() i :]
O·:J 1 Ci
28900.
29000.
,...,
'-'
29100. 0
29200. ()
293tJO. ()
29400. 0
29500. c~
29600.
29700.
,-..,
\J
.•
,""""'-.
,...,
C•~'~.,"'
-''-1 ..... .L
0100
0101
iJC:iCl
!)110
OOlC
Ciil
C;{J ltJ
D01Q
CtCj 1 c~
!.)C: 10
tJc;·:{J
1 cic!~J
2980t), ·J
29900. 0
1001
?OOOC. ()
:=::o 1:Jc·.
30200. ·~:-·,
30300. {)
30400.
30500. 0
30600. \..}-.
30700. 0
30800. i'}
1011
i 10(
11 t)l
1110
11 i...
0000
0001
0010
0011
0100
0101
0110
·-·
,~.
,~,
~·
~
3C,9CHJ.
\_,'
:31000.
31100.
.31200.
31300.
31400
31500.
3160()'
31700.
c~
Ct
0l"\
ltJ1~J
1
.
~
,-.. .. of-!
•..../
L.
L
J..
0
1000
1001
1010
1011
1100
1101
1110
11 t1
0000
0001
0010
0011
0100
0101
0
0110
'~
·~
tJ
0
0
31800. C·
31900. 0
32000. 0
32100. 0
32200. 0
32300.
()
32400.
32500.
32600.
32700.
0
0
\)0 1 ~J
OCiO
<)(:
()Cl
1<J
i Ct
00 ::..r::;
0011
0011
0011
0011
']0 11
c,c. 11
Ctf) 11
()0 11
0011
00:!.1
0() 11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
<J
0
0
001 i
0011
0011
0
0011
0011
0100
0100
01 {]·:J
01 (!;J
01 cfcl
010{]
0100
0
0
0
0
0
0
0
0
0
0
0
F
0000
0001
0011
0100
0001
0110
0111
100C
1 10i
1 otc~
101i
1 10•:,
1001
1 110
1 11 i
000'::'
010i
0010
0100
0101
0110
0111
1 00<)
1001
1 Oi<J
101i
1 100
1 101
1 110
1 111
0000
0001
0010
COli
C,i01
0110
0 ill
1000
1001
1010
1011
co
0
0
1
1
1
1
~
"
...
-t
i
1
1
1
...<
1
1
{]
0
0
1
1
1
1
...1.
~
L
1
-;
...
<
1
1
1
,...
0
0
0
0
1
1
1
<
L
...
1
1
.!.
;
J.
52
TABLE V.
SIMULATION RESULTS,
ADDEP
f4-BIT)
{cont. )
ADDER4· 4-SIT ADDER WITH FAST CARRY
Tit1E
:32800. <)
.32900.0
:~3000. 0
33100.0
.33200. C'
:33300. 0
33400.0
33500. 0
3370:J. 0
?3800. 0
34000.0
34100. 0
34200. 0
~34-30tJ. 0·
34400. 0
34500. 0
34600. 0
34700. 0
34800. 0
::34900. 0
:? 5000. 0
A
3:3.300. 0
35400. 0
35500. 0
-··
C ; '"
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0100
0100
0100
0
0100
0
0
0010
010i
0101
0011
0100
0101
0110
0111
1000
1001
1010
0100
0100
01 <')•J
0
0101
01G1
0101
0101
0101
0101
1011
1100
0101
1101
0101
0101
0101.
0110
110L
1110
111 'L
(}
0
0
0101
01.01
0101
1111
0000
0001
F
c~J
110(}
0111
1110
35200. 0
.8
C•
0
0
0
1
'
..l
~
ooo:::
OOOl.
0010
00ll
0100
(j
.~.
\..l
0 11\J
011L
i OOtJ
1
1 00:'_
1010
101 ~
r,-.,
.....·
1 i4\..·
1
0
0
0
0
0
111(
11 L.
0
OO<X
0
0
OOE;
110~
1
1
1
1
1
1
OOOt
t)
G
0
0
0
OlG:..
0111
l
0
100C
1
0 10'::1
0010
0110
0
110~
l
35600.0
0011
0
1010
l
:35700. 0
35800. 0
35900. 0
0100
0110
0110
0110
0
101 -~
1
0
1100
1
1 00~
1 11 ;:,
11 L
1
1
0101
0110
01 i1
0110
011.0
0
0
1000
0110
i)
1001
1010
1011
0110
tJ
1100
0110
3o600. o
36700. 0
36800. 0
1101
0110
1110
1111
C110
0
0
0
0
0
0
0110
0
36000. 0
36100. 0
36200.0
36300. 0
36400. 0
365c~o.
0110
0110
OOOG
c 101
0
0010
c
OCll
0 lOC
0001
01 iG
0
0
0
53
TABLE V.
._ IMiJLATION i=iESIJLTS, ADDER
(4-E :n
ADDER4: 4-BIT ADDER WITH FAST CARRY
A
3.:S90(). 0
:37000. ()
3720(). c
3 7 4C,~:~. r)
3750\J. t)
379<]\J. fJ
3E1<J:J. C·
38200. 0
384()(}. f)
3850C•. C
38600. 0
38700. 0
388(J~J.. c~
389<)~)
(.}
:3900() 0
2910().
39200.
393C.:()
3940().
{)
0
C
<J
0000
OOC1
0010
0011
0100
0101
011.0
0111
B
1000
1001
i
0111
0111
b
1 Ole)
0
r~ 1 1 1
,_. 4 - J.
0
0
0
0
0
1011
1100
1101.
1110
111 ~
C•111
c~11
0111
0111
01~1
1001
(): 11
0111
Cill
1000
1000
1.:::00
:·JOG
10QC
1000
1 ()()(:
1000
c
0111
1001
40'7'00 0
1000
lCOi
40700.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
408·JO. :)
40;;:C·C·. C•
403CO ,::;
4040-:. c
40!YJO. 0
0
i"\
1100
1101
1110
1111
0000
0001
0010
OOil
0100
0101
0110
40 1C.J ._,
.~
lC;C(Ci
1010
1011
398C'). 0
399<: .. C•
400'::.- 0
·.....·
(:1 l l
0001
0010
0011
0100
0101
0110
0111
1000
10C1
F
0
0
0111
1COO
1010
1011
1100
1101
111.0
11 i 1
CIN
1 oo~J
lOOO
1000
10\)l
lOCi
10C1
1C01
\..1
0
0
0
0
0
0
0
0
0
0
0
0
co
1
1
1
1
1
1
1
...
OOQ:_i
000~
0
oou.
0101
0110
011 i
1 OOi
1010
101 i
1100
1101
111{)
1 i 1:
oooc
0001
001C'
001l
0100
0101
0110
0111
1000
.
;•
.)
0
1
1
1
i
1
i
0
0
0
0
()
()
0
0
0
l.
1011
1100
1101
1110
111-:.
0000
0001
00 l:J
1
1
1
1
4
1
0
0
(~.
J
54
TABLE \1.
Sit1ULATION RESvL_TS,
ADDEr>
(4-BIT)
<cont. )
AGDER4:
4-BIT ADDER WITH FAST CARRY
TIME
CIN
A
F
C'J
1001
1010
1011
1001
0
1001
1001
r)
0011
0100
0
C:
010i
()
41300. 0
1100
1001
()
Ci1C
41400. 0
41500. 0
41600. \..}
1101
1110
1001
0
01 L.
100C
,;
,_
1111
f]
100:
0000
0001
0010
1010
1010
0
0
101 i
0
i
0011
101.0
1C• 10
41000. 0
41100. 0
41200. 0
417000
41800. 0
41900.0
42000. 0
42100.0
0100
0101
42300. 0
42400. 0
42500 0
4260·J. 0
427CO. 0
42800.0
0110
42900. 0
1100
1101
11"!.0
1111
0000
0001
0010
0011
43000. 0
43100. 0
4.320<). 0
43300. 0
434C:O. 0
43500. 0
43700. 0
0111
1000
1001
1010
1011
0100
0101
43900.
4400D.
44100.
44200.
44300.
44400
0
0
0
0
0
0
0110
44500. 0
44600. ()
1100
0111
1000
1001
1010
1011
1101
1110
44700. 0
44800. 0
1111
44900. 0
0000
45000. 0
0001
1001
0
1010
0
,..._
1100
1 oo:.
111!J
4 11 :1.
OOOC'
\)
OlOl
\j
001";
•..1
101.C'
v
1010
0
0
0
0
0
0 11 =-
0
011l
0
0
<J.
0
100 1 ~
101G
1010
1010
1010
1010
10:0
lO:.G
1010
1011
1011
10 i 1
1011
101. i
1011
1011
1011
1011
1011
1011
10:.1
1011
1011
lC 11
1011
1100
G
0
,.,
\..
0
0
c
0
0
0
0
0
1
1
010(.~;
000:
110":.
lOEc
1
110;.
1110
<
.!.
1 1 1 i.
GOO•J
0001.
0011:}
0011.
010')
0101
0 J..i,J
0111
:l
'.J
tJ
0
1 OO<:J
0
0
1001.
'-_}
101(;
0
0
0
1011
11 o·~
0
0
1 1 1<")
1
55
TABLE V.
S
I!1ULATIO~J
ADDER4:
RE3:):.... TS,
(cor.t
4-BIT ADDER WITH
TIME
45100. 0
45200. 0
45300.0
45400.-0
45500.0
45oOO.O
45700. 0
45800. 0
45900. 0
46000. G
46100. 0
46200.0
46300 0
46400. 0
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
46700. 0
46800. u
0011
46900. 0
47000. 0
0100
0101
OliO
0111
1000
1001
1010
46600. :)
4 7100 0
47200. 0
47300.0
4 7400. 0
4 7500. ()
47600.0
47700. 0
47800.0
47'7'00. 0
48000. 0
48100. 0
48200.0
48300. 0
48400. 0
48500. 0
48600. 0
~AST
F
A
1100
1101
1110
1111
0000
0001
0010
4650C>. 0
ADDE;;
11 C;O
ll:.X•
11.01]
:1.
1
0
0000
0
0
'0001
0010
0011
O:!.G:J
l Q(j
i :O<J
11 :J(i
11 oc~
0
0
0
0
,-..
'-'
c
0
::. iOO
0
11 Q{}
r•..-~'
0
1101
11 Oi
11 {}1
1101
11 i] i
1101
1101
1101
0
0
-
0011
0100
0101
48700. Q
488CS•. 0
0110
48900. 0
49000. 0
49100. 0
1000
1001
1010
0111
1110
1110
'!.110
111.0
1110
11:0
ill
000<::
...i
ooo::.
0
001<1
0011.
1001
1 01()
1011
110C
1101
i. i 1l
.1.
\-'
1
.i.
{)
1110
1111
0000
0001
0010
1110
11!0
11:0
()
0
0
0
0
0
0
0
0
0
0
0
0
0
0
~~
0
0
0
1000
v
'1 !-t
(
0
;)
,
1
tJ
0
0
1
1
0
0
0
0
0
0110
1: Oi
- "" -
t] 101
0110
OiL
1000
100'!.
1010
1011
110G
.i. 1 i ,-\
0100
0
0
......
.L ...
CO
0101
1101
i.. ~.} l
1 •.
"I
4
CARRY
0
0
0
0
0
1011
1100
1101
~-
i ; .,
0
(4-B IT>
0
0
0
0
1
OOOG
0
0101
0010
•.J
.~
0
0011
0
c
0100
0001
0 11C
0111
:000
0
1101
0
0
0
0
0
0
56
TABLE 'v'.
Sit"l'JLATION RESULIS,
ADDE~:
:.;L-CIT:O
{cont. i
4-BIT ADDER WITH FAST CARRY
ADDEF4
TI
t~E
4.9200. u
A
10i1
1100
1101
1110
1111
B
C IN
0
G
0
F
1101
i110
1110
1110
1110
1110
1111
11::.1
illl
ill-1
1111
1111
1111
1.111
1111
i 111
11 1 l
1111
1111
11U.
51100. 0
1110
1111
0
111n
512<)<]. (\
1111
1111
0
i11i
..t94!JO. ()
4950() cJ
49t00. 0
49800. 0
'50400. Q
506tJt). c~
50700. C'
.50800 '.J
50900. C·
ocoo
0001
0010
0011
0100
0101
0110
0111
1000
1001
101 <)
1011
1100
0
101=·
10L
110::::
100:.
111C
;-.,-.
.• w
()
r
0
0
0
0
0-
0001
001':'
001-:.
0
n
OlOC
c
0
0
0
0
0
0
010:
011C0111.
1 00(J
1 oo::..
1 0 1.:;.
1011
C:
110C:
(j
0
oooc
0
0
1101
·-'
57
4.5
Adder (20-bit)
This
20-bit
Because
modules.
tested as
adder
a
basic
interconnections
input
with
since
ADDER4,
combination
it
between
it
the
on
ADDER4
unit,
combinations
function,
the
(ADDER20)
A
used were
is
the
carry
and
module
was
the
B was
made
had
on
the
outputs
(F
and
been
ADDER4 modules.
chosen to
5
ADDER4
thoroughly
test
The
exercise
the
various
the
carry
interconnected signal.
is
active
used
with
active and inactive to allow the effect
seen
of
only necessary to
only
in
was
The
CO).
low.
the
Each
carry
of the
A
B
CIN
00000
00000
AAAAA
AAAAA
55555
55555
FFFFF
FFFFF
00000
00000
55555
55555
AAAAA
AAAAA
00000
00000
00000
00000
FFFFF
FFFFF
1
0
1
0
1
0
1
0
1
0
The results are summarized in Table VI.
input
in
both
carry to
fallowing
input combinations used (in HEX):
As
are
be
the
il
.
Tt=tBLE VI.
!3 U1ULATION
FIE~·:;uL.T.S,
ADCEF~
<.20-·BIT)
ADDER20: 20-BIT ADDER WITH FAST CARRY
T I ME
0. 0
200. 0
400. 0
GOO. C
800. 0
1000. 0
1200. 0
A
B
00000000000000000000
00000000000000000000
00000000000000000000
101010101010101010t0
10101010101010101010
01 0101 0101 c 1\:-1 C) 1 0101
1400 0
0101010101010L010101
11 11 11 11 i 1 1 111. 11 1 1 1 1
1600 0
1 1 1 1 l J 1 1 l. 1. l
1.
l I. l 1 1 l l l
1800 0
0 I) 0 000 <XK! \)I)({) C 0 0 00 00
c
00000000000000000000
2000.
CI N
F
8000000000!000000000
00000000000000000000
1
1
00000000000000000000
X
1
0000 0000 OOC<: OCOO 0000
!) 1 :) 1 0 1 () l 0 l ::. i ;J 1 !) 1 0 l 0 i
<) 1.:) '1 0 1 0 1. 0 1 (\ ' 0 1 ~~· :L 0 1. () 1
1. (· l G 1 0 1 •) 1 0 .: ' : l C 1. C l <: 1 0
1 0 1 C l 0 1 0 1 0 :; U j t} l I' 1 (': 1 0
0
:l
. 000 OOOQ 000(j 000 0 0000 1
1
00000000000CQ0000000
occo
1
0
11.1ltl1t11.! I LLi.tl.lll
i l 1 .l ' 1 1 1 1. 1 ; :. i ;, : l 1 l 1 1
1
0
l::j()(•(/00000:~·:: <··-~··:: .·.~
<)
1
0
XXX~~jXXXX~XXXX~X~XX
ll:ll11l1l1:i11llL1111
t: c:: C) (> {J,_) () !J () oc~ c·~ ()() () (J c(c· (~.~ r.J
11.LiJ\.il111Jl1.Jlill1
·:JOC ~YJC·U 00()(r 0\J(iU 1)(•000
1 1 i. 'i. t 1 J. 1 t 1 1. '! 1 1. I l l ··, 1 1
•)(!,~;. ,y:,t.rU l)i)C•C• !:·().Ji.' •)0C•(i0
:.!.:l1.l'lill!.:L.Illl.lll1
0 iO•::·I)\}1.)0\JOOi)O!.::•i. ~..::.o,:UO
C0
()
l
0
1
0
1.
0
lJl
())
59
4.6
Multiplier
The
adder
was
tree
used
this
for
8-bit
structure.
was
that
it
will
which
would
least
one
is
each
during
into
two
designed
using
(ADDER) module
to
incorporating
an
that
it
in
possible input combinations
far
too many
input
vectors
to
this with a reasonable assurance
correctly,
toggle
was
prior
65,536
To test
work
time
divided
tested
This
test.
(MULT)
The 1-bit adder
There are
circuit.
use in the
was
already
design.
this
multiplier
of
the
input
the
vectors
input
and
For Part
w
the
A,
selected
output
Actually,
test.
parts.
were
bits
the
input
as
test
bus
was held at 01 while the X bus counted up from 00 to OF and
then
from
10
to
This
switched.
FO.
tested
multiplier output bus
FF while
then
Y.
the
the
X
lower
For Part B,
and
w
eight
the
10
to
This
FO.
Then
exercised all
the
X and
16 bits
w bus
of
were
the
was held at
00 to OF and
W bus
of the
Test results are summarized in Table VII.
inputs
bits
the X bus once again counted up from
from
switched.
Then,
inputs
were
output bus Y.
60
!ABLE './I I
SI MULATIDN RESULTS,
MULT:
r':· __ 7' IPL IEF
8-BIT r"it.IL T'ZPL IE:::
PART
r..
TittlfE
0. (_
20G 0
400 0
600 c
'{
00
00
00
01
<)0
()C~ ~J()
{] 1
Q(l()()
'Jl
0001
01
0002
i
c· 1.
C;C:<J~.3
0000001~
c· ==· ::. 4
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
0001C:)G00
~ 40(- ··-'
l.O:..OG. ·~
l.SOO. _
l.JC:
2CdJ0.
<~
03
2.2f)i]
...(
~.
2400 0
OA
2:StJ<) ,_.:
c:c
~3c~{)(i
c, 1
c;c: ()·-?
c·
1
CCOE
01
OG ... G
1)
:36(:·.}. ·..
42tJC~.
C;
.::.400
'~'
50
c·
oc.:.;.o
0050
46QC:.
~!
C!l
01
4800.
c
c
01
C' •.
0060
0\)~70
5000.
5200. 0
90
c~1
5400. 0
AO
EO
Ol
01
co
()1
ooco
(.) 1
!JC)E{)
0080
(J09C)
OOA(';
c~~:JEC;
DC·
,2,;20c,
c~
EO
6400
'.J
-FO
00000000
00000000
00000000
00000001
00000010
00000000
ooooocoo
00000001
00000001
00000001
OOOCGC01
OC0Q0001
00000001
00000001
00000001
00000001
0000CG0l
00000001
00000001
00000001
GQOOOCOl
00000001
00000001
CC•COU:::Ol
JCt01
0000000000000000
. oc:c;oci()c(JOc}rJ. 1
;:~:,::c
00CCCOOOOOOOOC10
GQCC00COCC0001Gl
0GOG000000000110
0000000000000111
sooooooooooo~coo
(:·::;;~.J
{J(:t)O(J·;J{)tJ:.. C;() 1
~0000000000010:0
0000000000001100
Q000000000001101
OC00000000001110
0QQQQQQQQQQL0QQQ
001 OC·C\<JC\
\JC·C~C
CGCJ000000i00000
00110000
01000000
01010000
01100000
01110000
10000000
10010000
10100000
10110000
11000000
1101b000
11100000
11110000
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
OGOOOOOl
00000001
COOOOOOOOOliOOCO
~QCGOOOOOiGOOOOO
00CCCJ0001010QOQ
CC~Q000001100000
JOCC000001110000
OCCOOC0010000000
!){;;000000 1001 ooco
0000000010100000
0000000010110000
0000000011000000
00000000"1010000
COC00000~1100000
0000000011110000
61
T~BLE
VII.
SIMULATION
REE~LTS,
MULTIPLIER
(con~
'
r-;·_..._ T: S-S:T t1UL TIPL IEF
PART ,.!J,
TH1E
'·
X
("' 1
01
01
01
01
,_. ...
01
, . , •j
'f
;:o•JOGOOOC
00
01
C?.3
C5
C]{)O l
()() c~ ,: _.
oooooo:J1
'JC'000001
OOOOC0C1
0'j00C<• 10
(){]07
000~
s;;:oo.o
OA
c~ooE
OB
(jQ<]F
00000100
CJ.>JOOl 01
c~ooo-:::.<::::·1
::oooo110
..-:;-;:.001 GOO
C;;)00i0 10
oc
i]000C·C~~.:
l
88CrQ {)
or:·
OOOC!C!(JC~
1
c~
OE
9600 0
i):
: (}()Q.<).
0
1 C)2 Ct<).
c~
. , C'4CqJ. C·
01
01
01
~ o.~oc·. ~""'
.
Oi
.· 0800. {J
11<]<)0. ·.J
_ 12C!<J <J
01
~
O<JOC~1101
()G-001110
00::.3
0::.
\ ..i
•X·0011 i 1
OOC·lOOOO
C•C 100000
00110000
::;·. .}
c~o2<J
OC'ODC<::"._:. i
30
003(;
0040
0000()()01
01000000
.. 1010000
(1000C"Y::· i
G1100000
\)111000tJ
lOCiOOOOO
4C::
OOOuC<CC~
()t)5C:
0()6()
Q()!JOOC~c~
i
oooooc,::·l
80
01
OCSG
01
AO
OOACt
01
E"
Q()BC:
00000{:!'::·.
0000000001000000
CG~D00000101~00C
10010000
1C100000
0000000010110000
co
OODO
C:QlJtJoc~c·t
()C,EC
OOFO
c~oao\J.Ct<J
\Jc~oo ococ~
1.1010000
1.1 100000
11110000
0000000011010000
DO
EO
1.2200.0
1.2.!!.00. 0
01
FO
'1110000
t)
01
FCt
OOFO
OOFO
00000001
12.-::-oo.
OOOC0001
11110000
12800. 0
01
F\J
OOFC·
000000<)1
11110000
1
0000000J.
1 l c: c~ <JC·CtC)
11000000
01
01
01
1.2000. Q
C)l)Ci(J tJ·.)OO ~J~:,::) :::: c:·1 oiJ
C•<JOC·Ct(tQCtOC<:.-·:·.:J lC~ l
OOOOC:O<Y::..
8::,oo o
-=<400 0
OOC00000CJOOOOO'
00000011
GOOOOCCl
OCOOOGC1
0~
St)O{)_
c.:, n t. )
f)(yJ~::.oooc1
l. 11. C:···J<Jc·c:
0000 0000 1 .:. _ 1 C>CCC•
0000 0000 l 11 ·-coco
ococ 0000 1 • ~ 0000
0000000011 ' : .J(:C'G
4
62
TABLE VII.
SiMVL~TION
MULT:
FE50LTS,
MULT~PLIER
Ceo~~
S-BI' MULTIPLIER
P.4FT 3
TIME
X
'y
X
00
cr:,
I
01Ft:::
C:OOQ()GC't:·
OOOOOOC•C
OOOOC(:<,: i
00000010
FF
02Fr::
OOOOOCl~
00
~00.
FF
0
:;oo. o
.soo 0
Col
02
04
08
FF
O~F5
oc
FF
FF
FF
OEF4
08
220G.O
240C. C·
2800 <J
:3000 =::·
OD
OE
OF
3600 . . . ,
.1000. ·::·
4200. (/
4600 0
500G.O
520C•. 0
1<)
2{]
FF
CrfJOC: OClC1 C· "' 1 ... 1
i1i112~1
C1t)0Cq}(;tQ 1 ..
~
j.
!.
"
_
i
-_;
~-
_
... ·"
l
C,
1111.1!11
:J5FA
GC,JO•:· ... ~ '-'
:JOOOOl .. l
Ct7F2
00001CC::i
00001 ·.:•C L
1.1111,11
11111111
111111.11
c~oo{)011C· i 1.:
00000111- _l.
OG001C:i0
~~111111
00001001~11~01_0
OOOO:LGil
00001100
ill1.L11
111.11:'1
11111111
1]~)0()
1~111_ tl
1.11 ... 1111
ii111111
OCrQ() 1 iC111 :.11
02F7
OCF.::
00001.i.)l
000011-; ~::.
OEF1
OFFC·
000011.·~
1FEO
1~11
1
:i1
(JtJOC' i00C1 .~ \.1
1 () 1 r)
QOt)C• 1 01 1
.. "1. _
~
tJOl
~ _!](:,J
i -; ~ "\:
1 (} l C: 1
: 1 1 Cr 1 c~c~
oooo 111 o ~ l
~:q:-~0
• ~ ··=
·:::•o ~
00001"11 .• :1JOOO
00011111 i '!-< l)t)C~Jc~
001~) i 1 i l 'i. ~, C l ()Crt)(!
001111 i 1 _ :-:.C tJt.)\JC;C'
:3FCG
0011COCC·
ClOOOOC . :·
50
FF
4FGO
0101000C'
60
FF
FF
011 OCOt::C
.11.(11~1
6F-:;o
0111 c~c~c,c:
11111111
ili1L1.1
C110111110010G00
11111111
i111L.i1
111111.11
11111111
"1111'1i
11)0(} i 1 i 1 C1 : l l QC·t)C'
1 !)() 1 1 11 1 C/11 c~ ~:~ OC: (J
1 01 0 i l 11 1.:: 1 (}i c !-:,".)0
iOi 11111 OiCOGt:)0()
3()
40
80
90
AO
56()iJ.
ll
EO
ssocl.
c~
ri'"\
_._..
6C~0(). ~)
DO
620(}, 0
6400. 0
oococ:..c::.
OA
\...)·~
11111.1..11
i 1 t 11- 1 1.
OOO(JC~: ('!)
FF
FF
FF
FF
FF
FF
FF
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ilili'.t.i
11.11.1111
11111111
l l l l i ... l l
1
010011111uL10C00
_1101111000_0000
63
7ASLE VII.
SIMULATIO~
Mt..!LT:
FES0LTS, MULT:PLIER
:3-GIT MULTIPLIEF
(cont.)
PART B
TIME
7C·<JO.
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".
CHAPTER FIVE
CONCLUSIONS AND DISCUSSION
Before
developing
requirements
to
take
and
had
into
to
Initially,
would
per form
normalization.
to
clear
As
However,
a
to
this
chip
due
intended
to
LSI
is
had
design
the
chip
chip
that
including
the
design
a
as the block diagram developed,
would
lower
require
the
too many
larger
yield
package.
implement
of
these
matching
b ec ames
to
to
the
requirements
aspects
important of
template
the
difficult
required
was
These
various
most
it
that
manufacture
more
spec if ie d.
The
size.
practical.
be
integrated circuit design,
consideration
fabrication.
became
this
array,
it is rna re
per
Since
it
gates
chips
64
was
to
decided
be
expensive
It is
wafer.
it
also
would
to
be
limit
the logic to the correlation function only.
By
Could
more
single
speed
of
doing
than
one
If
so,
chip?
between
the
idea is
array.
not
this,
another
possiblity
processing
this
processing
would
element
improve
elements while
Because each chip requires
practical at
this
time,
but
became
be
the
apparent.
placed
on
a
communication
reducing
the
size
8000 gates,
this
may
be
so
in
the
future.
Another consideration was whether to use a synchronous
or asynchronous design.
S.Y.
Kung
and
J.T.
The correlation design proposed by
Johl
[4]
64
was
intriguing.
Its
data
65
driven
approach
drivers
and
would
other
eliminate
signal
the
need
buffering.
It
for
large
would,
clock
however,
require handshaking
logic on the chip.
There was room for
this
but
been
on
the
implement
unless
transistors
would
specific
used
lengths
connecting
can
used
be
order
it
have
processing
difficult
parameters
An asynchronous circuit is dependent
known.
of
LSI,
to
the
design
it
along
transistors.
preliminary
verify the
the chip,
timing
for
to
timing
design, it
were
upon the
with
to
the
type
wire
Default wire
lengths
simulations.
But
would be necessary to
in
route
extract the actual wire lengths, and then run the
simulations.
Since
this
was
not
feasible,
the
synchronous approach was taken.
When
simulating
information was also
the
chip
produced.
for
functionality,
timing
The gate delays were
based
on conservative estimates from a typical 2 micron CMOS gate
array
process.
They demonstrated
at a 5 MHz clock frequency.
to
have
designed
an
that this
chip could run
It would have been interesting
asynchronous
version
of
the
Image
Correlator and compared simulation results.
New
constantly
advances
in
occuring.
from 2 microns to
integrated
Gate
array
1.5 microns.
circuit
technology
technology
is
are
changing
New channelless arrays are
being developed that have a greater transistor density than
standard
available.
gate
arrays.
These
have
And,
silicon
the
advantage
compilers
of
being
are
now
process
66
independent.
process,
the
Once
a
has
been
designed
using
one
it can be modified for anoth~r process by changing
process
parameters and
is an exciting area of
be
chip
fabricated
In five years,
at this
re-compiling
technology.
time,
the
design.
This
If this design were
to
gate array is the best method.
it is unpredictable.
67
REFERENCES
[1]
M.J.B. Duff, "CLIP4", Special Computer Architectures
for Pattern Processing, K.S. Fu and T. Ichikawa,
Eds., Boca Raton, Florida: CRC Press, 1982.
[2]
H.T. Kung and R.L. Picard, "One-Dimensional Systolic
Arrays for Multidimensional Convolution and
Resampling", VLSI for Pattern Recognition and
Image Processing, K.S. Fu, Ed., New York:
Springer-Verlag, 1984.
[3]
S.Y. Kung, K.S. Anin, R.J. Gal-Ezer, and D.V. Bhaskar
Rao, "Wavefront Array Processor: Language,
Architecture, and Applications", Special Issue
on Parallel and Distributed Computers, IEEE
Transactions in Computers, val. C-31, pp.10541066, 1982.
[4]
S.Y. Kung and J.T. Johl, "VLSI Wavefront Arrays for
Image Processing", VLSI for Pattern Recognition
and Image Processing, K.S. Fu, Ed., New York:
Springer-Verlag, 1984.
[5]
S. Muroga, VLSI System Design, New York: John Wiley
and Sons, 1982.
68
BIBLIOGRAPHY
Duff, M.J., "CLIP4", Special Computer Architectures for
Pattern Processing, K.S. Fu and T. Ichikawa, Eds.,
Boca Raton, Florida: CRC Press, 1982.
Fountain, T.J., "A Survey of Bit-Serial Array Processor
Circuits", Computing Structures for Image Processing,
M.J.B. Duff, Ed., London: Academic Press, 1983.
Kung, H.T. and R.L. Picard, "One-Dimensional Systolic
Arrays for Multidimensional Convolution and Resampling", VLSI for Pattern Recognition and Image
Processing, K.S. Fu, Ed., New York~ Springer-Verlag,
1984.
Kung, S.Y., K.S. Anin, R.J. Gal-Ezer, and D.V. Bhaskar Rao,
"Wavefront Array Processor: Language, Architecture,
and Applications", Special Issue on Parallel and
Distributed Computers, IEEE Transactions on Computers,
vol. C-31, no.11, pp. 1054-1066, 1982.
Kung, S.Y. and J.T. Johl, "VLSI Wavefront Arrays for Image
Processing, VLSI for Pattern Recognition and Image
Processing, K.S. Fu, Ed., New York: Springer-Verlag,
1984.
Liu, H.H. and K.S. Fu, "VLSI Arrays for Minimum-Distance
Classifications", VLSI for Pattern Recognition and
Image Processing, K.S. Fu, Ed., New York: SpringerVerlag, 1984.
Liu, P.S. and T.Y. Young, "VLSI Array Architecture for
Picture Processing", Picture Engineering, K.S. Fu and
T.L. Kunii, Eds., New York: Springer-Verlay, 1982.
Mead, C. and L. Conway, Introduction to VLSI Systems,
Reading, Massachusetts: Addison-Wesley, 1980.
Mukhopadhyay, A., "VLSI Hardware Algorithms", Hardware and
Software Concepts in VLSI, G. Rabbat, Ed., New York:
Van Nostrand Reinhold Company, 1983.
Muroga, S., VLSI System Design, New York: John Wiley and
Sons, Inc., 1982.
Ramamoorthy, C.V. and Y.W. Ma, "Large Scale Computer
Systems", Hardware and Software Concepts in VLSI,
G. Rabbat, Ed., New York: Van Nostrand Reinhold
Company, 1983.
69
Siegel, L.J., H.J. Siegel, and A.E. Feather, "Parallel
Processing Approaches to Image Correlation", IEEE
Transactions on Computers, val. C-31, no. 3, ~208218, 1982.
Sutherland, I. and C. Mead, "Microelectronics and Computer
Science'', Microelectronics, A Scientific American
Book, San Francisco: W.H. Freeman and Company, 1977.
Uhr, L., Algorithm-Structured Computer Arrays and Networks,
Orlando: Academic Press, 1984.
Wong, R.W., Computer Pattern Classification and Scene
Matching, Dept. of Electrical and Computer
Engineering, California State University, Northridge,
1981.
70
APPENDIX A
SCHEMATICS
71
INST
I
ICORR
~DB
(7
~OJ
DBD
.J 0 R ( 19 : Q.J
CLOCK
(7~
8l
0[(19:0)
FUNCTION
LORD
CLERR-L
ICORR
IMRGE CORRELRTOR
72
IJ80(7dlJ
IJll
015
15
OLU
U6
013
ADOEA2e
A19
012
DLL
AlB
DID
A17
D9
DB
07
D6
D5
Oij
U7
D3
D2
Dl
DO
CLA-L
DC 119: l!ll
PA (IS:Iill
W!7dll
CLR-L
us
DA! (]9: l'll
REG2B
D19
DIB
DL 7
Dl6
Dl5
DU
DL3
Dl2
DLL
DID
D9
DB
D7
DB
D5
Dij
D3
D2
DL
e
CLK
Ul3
z
DB
CLK
CLR-L
z
2R
Ulll
CLA-L
______J!2
Ill
OATRI7:6lC
ACCII9:81D
CL OC KD----'--·
OBI"IoBl
JOAIL9:0l
CLOCK
oson,ed
OBOll?• 01
OCII9o0ll
OCI!Ig,g 1
J
,-------U3
loal7o~;-·~~eoo,ml
060217 ' 81
loel7oBl
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loAtl9o01
OC 2119 ' 81
loAII9o61
DCII9:01
OC!I9,811
~~CLOCK
J
DODfHRI7d:ll
--£>COAAil9:0l
----__Lr--"'"""'
LOF1De>----;~~~"[ ~ ~ -~-!±-'
f'CLOCK
CLERA-LC>--
ICORR3
THREE PE EXAMPLE
---.1
w
74
INST
03
]
02
JJDl
DO
FUNCTION
~CLK
I'
CD
REG4
W-BIT REGISTER WITH CLERR
75
u1
p Ql
03
DQ3
IF02j
Jrr:Lun~o..... ,....r;UI·
vI
~
U2
I
C2.
:o
0!
-.-. ~
!
C>Q2
t
I!U::::i
Ijro l
I
I
I
01
I
I
I
,'-"ro
l
I
Q~'
·•'tf
~
I
U3
,.---------,
:o
Q~
Ql
jFD2j
I
DO
CLK~
co
i i
I I
•
I
I
!
![~nQNo-
l
LJ
.0
i
QO
....,i
I r oc: ;
I
!
!_
.
REf'U
t
u
I
co
~
.!.
I
y
l
Ll-BIT
REGISTER WITH CLERR
76
INST
REG16
Q15
015
~~:~
Ql~~
013
Q12
012
1011
...... o
Q 11
QlO
Q9
1G
I
log
os[
-jos
Q7~
~07
Qt
---106
--j OS
QS
~Ol±
Q4
-jo3
Q3
Q2
l02
Ql
101
---j 0 8
goj
I
I
FUNCTIO~
+-iCLK
I
I
I
!Q
'-
r
I
REG16
16-BIT REGISTER WITH CLEAR
77
I
O!SD>------~!o3
Ul
Rm
!oz
014D
n:
t
013
1
012
I
o;l
c•'-'--'----DO!S
DOI!l
o1j
C>!ll3
Q81
DC12
I~D
I '
'I
!
I
I
u~
a3!-:- - - - - - D Q i
02 1
0 18D>-----+-r---ijD<
~:~
i ~~~
!
I~
Ii
07D----+'-+!_,!03
I
D6D
DSD
OI!D
r
!o2
j
Ii
1
CD
REG~
i
io•
'I
j
i
.
!
Q~f-1- - - - - i C > Q 7
I
L..>06
at;~-----,~os
----~C>Q4
oajf-'
4-JCLY.
!
us
Q2
io1
c;
I
.
:
DSC>----+-+·~:os
1'.
REG'l
oze>---~-+~!J2
Q;;
i"o
CLKD-----4·~-icLK
1
o31~----~C>03
o2.~----~e>oz
!Dl
OlD
08D
oe
1
co
COD---·--+-__;y
REGiS
16-Bll
A~Gi5TEF.
l
DQ 18
~~~;...______g~:
~
w:L.
I l
I
ft[Gq
Oll D----f--+-:-;1u3
WJTH CLEAR
Ql
C>w0
78
lNST
REG28
Q19
019
jo1a
Q18
1017
Q17
016
Q16
015
Q15
Dlll
Q1Ll
013
Q13
012
~~~~
~
011
010
Ql
tJ
09
Q9
los
Q8
--jD 7
Q7
-io5
Q6
l
--<05
1
~
Q5
I
-lOL!
Ql±L
Jo3
Jo2
61~
r·':i
Jo1
~DO
ICLK
Q2
Ql
t
L
QO
FUNCTION
co
REG20
28-BIT REGISTER WITH CLEAR
79
Ul
uo
REGij
---i~H---i,D2
j
1------DQ ll
-- !
~;~
rl
CH,
DBC>---~~-t.---ioo
~ oot
II .
C>QHl ·
C>Q9
C>O'
UY
07~03 'iEGU C3t--1----~C>Q7
06C>
DSC>
D!!C>
I,
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i
;
ID2
0211-1- - - - C > 0 6
!ol
ID~
fll,
Qd
4-icLK I
I
1
I
I
i
03C>---+-+~o3
1
0"D
I
02
cy
COD
ctl
!CLK CD
e
I
c31~---~C>Q3
c2i
C>02
QSI
OG
.
I
us
AEGY
o;5f!
I lul
DEl
I
CLK
C>QS
C>Q4
I
y
1
REG20
2G-BJT REGISTER HITH CLEAR
DCll
C>Q8
80
REGLDL1
LORD
I .
I
jD3
03t
~~~
.
~DO
.I
~~~
08
FUNCTION
1CLK CO
y
n''
R L~CI~_ULf
4-BIT REGISTER
WITH CLERR RND PRRRLLEL LORD
81
REGLOL±
ij-aiT REGISTER •ITH CLEAR AND
P~RALLEL
LOAD
82
INST
REG LOB
LOAD
Q7
07
~06
Q51
~OS
~~~
~~
Q3~
Q2
+t02
101
01
._.DO
QO
>UNCT!ON
CLK
CD
'i
RF~I
._uL
DR
_J
8-BIT REGISTER
WITH CLEAR AND PRRRLLEL LORD
83
I
LORDD
•
Ul
AE:GLDIJ:
1LORD
I
7D---+I'I----ii 0 3
D
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·
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1
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I
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0
L
C>Ql
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r
CDC>-----~•----~
RcCLOB
5-BIT REGISTER WITH CLEAR AND FRRRLLEL LORD
84
TINST
I
J.R RooER Fr
C I f\j
1B
1
FUNCTION
co
RODER
1-BIT FULL RODER
p '
85
cc
w
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INST
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F0 <~"1------{~Q
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