:p
CALIFOill~IA
STATE UNIVERSITY, NORTHRIDGE
AN APPARATUS FOR PROCESSING
II
OF ELECTROPHYSIOLOGICAL SIGNALS
A thesis submitted in partial satisfaction of the
requirements for the degree of I'1aster of .Arts in
Psychology
by
Jaromir Cyrill Belie
-
June, 1977
'
The Thesis of Jaromir Cyrill Belie is approved:
Dr:"' ))a::Li d?1ark"er
{)_
Dr. ioyJrif'Hths, Chairman
California State University, Northridge
ii
ACKNO\IJLEDGEI:1ENTS
I would like to express my sincere appreciation to
Dr. Jack Gaston and Dr. David :Parlcer for the cooperation
and assistance they provided during the preparation of
this thesis.
I include a special note of appreciation
to Dr. Roy Griffiths for his patient assistance, support,
and encouragement.
iii
TABLE OF CONTENTS
ACKNOWLEDGEMENTS • • • • • • • • • • • • • • • • •
LIST OF FIGURES
iii
• • • • • • • • • • • • • • • • •
vi
LIST OF TABLES • • • • • • • • • • • • • • • • • •
vii
ABSTRACT •
..
• • • • • • • • • • • • • • • • • •
CHAPTER 1•
INTRODUCTION AND BACKGROUND
CHAPTER 2.
HETHODS AND roiA.TERIALS
viii
• • • • •
• • • • • • • •
17
.A..
PRINCIPLE OF OPERATION • • • • • • • •
17
B.
DESCRIPTION OF THE BUILDING BLOCKS
AND THEIR FUNCTIONS • • • • • • • • •
18
a)
Voltage 'Window comparator
• • • • • •
18
b)
Pulse height analyzer
• •
•
27
c)
l-1ul tiplexer
• • • • • • • • • • • • •
32
d)
Clocl\:
• • • • • • • • • • • • • • • •
36
e)
Steering logic • • • • • • • • • • • •
38
f)
41
g)
Counter and memory • • • • • • • • • •
Display • • • • • • • • • • • • • • •
h)
Digital magnitude discriminator
• • •
47
i)
Digital to analog converter
• • • • •
50
j)
Po1mr supply • • • • • • • • • • • • •
54
iv
~
'"
0
e
e
45
TABLE OF CONTENTS--Continued
Page
CHllTER 3.
RESULTS
• • • • • • • •
• • • • • • •
58
A.
SPECIFICATIONS OF THE APPARATUS
• • •
58
B.
USE IN CARDIAC DATA Al.'JAL YSIS • • • • •
DISCUSSION AND CONCLUSION • • • • • •
63
REFERENCES • • • • • • • • • • • • • • • • • • • •
73
CHAPTER 4.
v
69
LIST OF FIGURES
FIGURE
2
Block diagram of the apparatus • • • •
19
Voltage comparator • • • • • • • • • •
21
3 Voltage vdndow comparator
• • • • • •
21
4
Hodified voltage I·Jindow comparator • •
26
5
Pulse height analyzer
• • • • • • • •
29
6
Wave forms of the
pulse height analyzer
• • • • • • • •
31
• • • • • • • • • • • • •
35
7
~lul tiplexer
8
Clock
• • • • • • • • • • • • • • • •
37
9
Steering logic • • •• • • • • • • • •
4o
10
Counter and memory • • • • • • • • • •
44
11
:Display
46
12
Digital magnitude comparator • • •
13
Digital to analog converter
14
Dual tracking voltage regulator
• • •
55
15
Povrer. supply for logic circuitry • • •
57
•
• • • • • • • • •
• • • • •
•
49
• • • • •
53
•
~-------------------------------------
vi
LIST OF TABLEs·
TABLE 1
Test results of the voltage window
comparator • • • • • • • • • • • • • • •
60
2
Accuracy test of the digital to analog
converter • • • • • • • • • • • • • • • •
62
Performance of the apparatus in
detecting the threshold heart rate
during and after exercise • • • • • • • •
64
Performance of the apparatus in
detecting the upper limit of the
pacem~~er spike interval
•••• • • • •
66
3
4
vii
ABSTRACT
~~
APPARATUS FOR PROCESSING
OF ELECTROPHYSIOLOGICAL SIGNALS
by
Jaromir Cyrill Belie
Master of Arts in Psychology
An apparatus for processing of electrophysiological
signals has been designed and built.
It has advantages
over similar existing devices in that it is frequency independent over the range of electrophysiological signals,
is simple to use, and inexpensive.
The instrument is ver-
satile, since it is capable of threshold detection, amplitude discrimination, frequency
~~d
interval analysis,
and also determination if the frequency or interval of
the examined signal falls within, above, or below a predetermined band.
The design is based on the method of threshold detection of analog signals.
Incoming signals are detected
in a voltage window comparator with two adjustable thresh-
viii
old levels and converted into digital pulses.
Further
signal processing is then performed digitally by 01vlOS
logic circuitry.
The outputs of the apparatus are availa-
ble in a form of an analog voltage for interfacing with
analog devices and pen writing instruments and also in
the form of a 12 bit digital word for interfacing with
digital equipment and computers for further data processing.
A digital readout display is also provided.
The design is modular and each of the building blocks
can be used separately to perform a specific task.
As a demonstration of the feasibility of the instrument for actual physiological data processing, preliminary data on heart rates during and after exercise and
on pacemaker firing rates in .cardiac patients are compiled here, and examples for further use in electrophysiology and medicine are suggested.
ix
CHAPTER 1
INTRODUCTION AND BACKGROUND
"Great demands are made on a modern electrophysiologist.
In addition to being acquainted with the physiolo-
gy of the system
studi~d,
he must know the principles on
which his instruments and apparatus work and the latter's
capabilities and limitations.
This is all the more im-
portant if fundamental problems are being studied.
In
such cases the scientist must seek new approaches and must
thus be acquainted with electronics."
(Bures, et al.,
1967).
This thesis is an attempt to tackle an important
technical aspect of electrophysiology, namely the detection and processing of real time electrophysiological signals.
The art of real time detection is experiencing
rapid development as techniques for the treatment of problems otherNise rendered impossible by their complexity
are being devised.
Two principal methods of real time
detection can be distinguished:
1.
Configuration detection, whereby only those sig-
nals whose configurations meet certain rigidly defined
criteria are detected.
1
2
2.
Thres~old
detection, whereby only those signals
whose amplitudes exceed a given threshold are detected.
In many instances where the wave morphology of the
signal, such as a neural spike, is not relevant to the
variable being analyzed, such as the repetition rate, the
threshold method of detection is preferable for its relative simplicity (as well as for economic reasons) and
will be considered in this work.
Searching through the available literature, the reader will find many published designs of circuits dealing
with the technique of threshold detection and subsequent
processing of real time (or on-line) signals as well as
some commercially available units.
backs, be it the complexity
~~d
All have some draw-
cost of the instrument,
or the lack of precision in the more simple designs.
Also, published designs (Macrides, 1972; Olds, 1973; Buchwald, et al., 1973; Woods, Dafny, 1974; Richardson, et al.,
1977) and commercial units (Haer and Co., 1975) use technology which is usually already obsolete at the time of
publication or availability, due probably to the fact
that the primary interest of the physiologist is, naturally, physiology and not to keep abreast 1dth the latest
developments in electronics.
On the other hand, manufac-
turers of commercial instruments must face the necessity
of amortizing their development costs before introducing
updated material to the market which is (as compared to
3
other areas of electronics) rather limited.
A brief over-
view of past and existing techniques of the real time
threshold detection and signal processing is presented
here.
In the early years of electrophysiology, there were
no tools available for the experimenter or clinician to
record electrophysiological signals.
Einthoven's inven-
tion of the string galvanometer permitted the recording of
electrocardiograms (EKG's) in 1899 and later, in 1925, the
recording of electroencephalograms (EEG's).
At that time
visual inspection alone was the technique for analysis of
those recordings.
Rapid advances of electronics, such as
the introduction of the vacuum tube, made possible the
amplification and recordings of very small electrophysiological signals and also provided means for their analysis (Bures, et al., 1967).
Aside from visual analysis
of the signals displayed on the oscilloscope (introduced
in 1922) or recorded on a pen-type recorder, there have
been many techniques developed to aid the detection and
analysis of real time signals as follows:
1.
A passive resistor-capacitor (RC) integrator
(Beidler, 1953).
This simple circuit sums all activity
as it appears at the electrode tip and responds to changes
in both amplitude and frequency.
Thus unequal weighting
is given to events of different shape, amplitude, and
duration.
The noise contamination of the signal is also
4
summed and contributes to the output voltage of the circuit.
The time constant of the RC network must be com-
puted for the anticipated frequency range, and a compromise must be made between the smoothness of the output and
the responsiveness of the integrator.
The output of the
circuit is an analog voltage representing the frequency
of the signal.
Despite its drawbacks and primitive de-
sign, this integrator is probably still the most commonly
used device for analysis of multiple unit activity (HUA)
of the brain (Buchwald, et al., 1973).
2.
A
~assive
RC integrator or an active integrator
based on an operational amplifier preceded by a monostable
multivibrator (one shot).
In this circuit the monostable
multivibrator converts the incoming events to pulses of
uniform amplitude and duration, w-hich are iYl_ turn integrated by the RC integrator.
In this fashion, all events
are given equal 1·Teighting, and the output is a more accurate representation of the signal frequency.
The noise
and artifacts still contribute to the output and all
other
disadvfu~tages
of the previously discussed circuit
v
are present (Bures, et al., 1967).
3.
The addition of a voltage threshold discrimina-
ting device.
This is used to separate the signal from
baclcgr01.md noise and the signal is then processed as in
the preceding circuit.
The noise can no longer contribute
to the output; only events exceeding the threshold level
5
are integrated.
This type of circuit is being used for
m.ul tiple v.ni t activity studies (Landolt and Hillilcen,
1970;
Silve~~an,
et al., 1970; Hermann, et al., 1962;
Buchwald, et al., 1973) as 1·rell as for ru1.alysis of single
unit activity (Hacrides, 1972; 1'Toods and Dafny, 1974).
4.
A voltage window comparator preceding the output
generating circuitry.
The adjustable voltage 1i'lindo1i'r en-
ables the operator not only to prevent backgrotmd noise
from entering the system, but also to discriminate between events of different amplitudes.
This method is
used for multiple unit activity studies (Halas, et al.,
1971) and is thought by some to be particularly suitable
for single unit activity analysis (Brown, P.B., et al.,
1973; Hermann, et al., 1962; Bradley, et al., 1967).
A few· comments about the more sophisticated circuits
described under 3. and 4. should be made at this point.
Some designs (Halas, et al., 1971; Brown P.B., et al.,
1973; Landolt and Hilliken, 1970) use a val tage comparator
which has no hysteresis, based on an operational amplifier
as the threshold discriminating device.
:~Iul
tiple trig-
gerings of the monostable multivibrator are a possibility
(as noted in Halas, et al., 1971) While detecting slower
wave forms.
Other designs (Bradley, et al., 1967; Her-
mar_n, et al., 1962; Haer and Co., 1975) circumvent this
disadvantage by using a Schmitt trigger 1d th inherent
hysteresis as the voltage threshold discriminating ele-
6
ment.
This, hovTever, brings about another disadvantage,
e. g. , inability to differentiate be tv-Teen t-v,ro events spaced
closely together, as noted in Landolt's critique of Hermann's circuit (Landolt and l:Iilliken, 1970).
The design
described in this thesis eliminates both problems by a
method described later in the text.
All of the voltage v-Tindo1v comparator circuits must
use some lcind of internal logic, or "pulse height analyzer;'
to accomplish the vTindow effect.
This is done by delaying
generation of the output pulse by "-vrai ting" for a certain
time period, e.g., 100 usee (Brow.a., P.B., et al., 1973),
200 usee (Haer and Co., 1975), or 400 usee (Bradley, et
al., 1967), after the signal crosses the lovTer threshold
of the -rrindovf.
If, vTi thin the specified time period, the
signal recrosses the lower threshold again, leaving the
vTindow, the signal is considered "good, 11 and the output
pulse is generated.
If, on the other hand, the signal
crosses the upper threshold within the specified time
span after crossing the lower boundary, the signal is
considered "bad," and the generation of the output pulse
is aborted.
The disadvantage of this approach is obvious;
signal of high amplitude but low frequency could need more
time to transverse the windo·w than the specified time
period and, despite of being "bad," generate a false output pulse.
The pulse height analyzer (PHA) of the appa-
ratus proposed in this thesis does not have this dis-
7
advantage.
The principle is described later.
I;Iost of the devices described in 3. and 4. use an
integrator circuit to generate an analog voltage representing the frequency of the real time signal.
However,
an interval measuring circuit is employed to convert
interevent intervals, rather than frequency, to analog
voltage in one design
(Bro~m,
P.B., et al., 1973). Cumu-
lative binary counter can be used to generate the analog
voltage
(Bro~m,
K.A., et al., 1973), or the output of the
device can be in digital form (Halas, et al., 1971). The
use of an eight bit binary digital to analog converter
has been suggested (Bure~, et al., 1967), but the design
uses twenty-four vacuum tubes.
The apparatus presented
in this work uses twelve bit binary coded decimal (BCD)
cotmter and digital to analog converter to convert the
frequency or interevent interval to analog voltage.
This
data conversion technique is not only far more accurate
than the integration method, but also provides digital
output for further data processing.
After reviewing the published and commercial designs
and analyzing the nature of the
signa~
involved, the
following goals have been formulated for this worlc:
1.
To design and to build an apparatus which will
perform threshold detection of real time signals
and subsequent frequency and interval analysis
of such signals; which will provide a capability
8
of determining if the frequency or interval fall
within, above, or beloi'l a predetermined band;
and which will provide an interface ii'li th equipment for further signal processing, such as computer, digital data storage, polygraph, etc.
2.
To design and to build this apparatus in such a
way that it vdll be considerably more flexible
and easier to use than commercially available
equipment or published designs, and to keep the
cost Y.Tell below commercial devices.
3.
To design and to build this apparatus utilizing
the latest 1·rl.dely available technology, n&-nely
the Complementary !-fetal Oxide Silicon (CHOS)
logic family.
The vrorlc pres en ted here was initiated several years
ago as an attempt to improve upon existing designs.
The
original unit consisted of a voltage 1'lindo1v comparator
ii'li th an associated pulse height analyzer and was capable
of threshold detection and amplitude analysis of real
time as well as recorded signals.
The attempt proved to
be rather successful, since the resulting instrument was
frequency independent within the range of electrophysiological signals, used very few parts and needed no adjustments.
Later, a frequency
&~d
interval analyzer cir-
cuitry vras added to the basic lmi t, thus enhancing the
usefulness of the
instr~ent.
vfhile constructing the
9
frequency and interval analyzer, published circuits 1'rere
considered and again attempts -vrere made to improve upon
them.
The latest additions to the apparatus are a digital
magnitude discriminator, enabling the operator to determine if the frequency or interval of the signal lies
above, -rri thin, or belovr a predetermined band, and a three
digit display readout, which permits visual verification
of the frequency or interval of the signal.
Because of
the proliferation of micro and minicomputers in the past
two years, and the widely available accessibility to timesharing computer systems, an interface for these devices
is also included in the instrument.
The- CIY10S logic family was selected for construction
of this apparatus partly for its noise immunity, but mostly for its miniscule power consumption.
For example, the
current drmm by a typical CHOS quad gate connected to a
5 VDC supply is nil in the qtdescent state and is measured in only picoamperes (pa).
The same gate operated
at 1 megaher-tz (HHz) frequency vrill need only 0.4 milliamperes (mA), at 100 kilohertz (kHz) 0.04 mA, at 10 lruz
0.004 mA, etc.
In contrast, an equivalent Transistor-
Transistor-Logic (TTL) gate would need on the average
12 mA of current to operate.
It is interesting to note
that among all the circuits revie-vred, only one design
used CMOS logic (Heyes, 1974).
10
The minimal power requirements of the CUOS logic permit the use of a smaller and cheaper power supply and also
open the possibility of using batteries to power the apparatus.
This would not only mruce the instrument easily por-
table, but more importantly, by eliminating the use of the
117 VAC line, would greatly reduce or completely eliminate
potential shoclc hazard, especially if the apparatus v-rere
to be used on human subjects (UL 544, 1974).
There are many uses proposed for this type of apparatus.
In general, any signal that can be characterized
by frequency or amplitude can be processed by this instrument.
The signal does not necessarily need to be an
electrophysiological signal.
The apparatus may also be
used as a general purpose instrument to monitor any data
which can be converted into and represented by a fluctuating voltage, frequency, or pulse, as for example, bar
pressing in behavioral studies, respirations, or blood
pressure.
The obvious use in neurophysiology is for EEG monitoring, e. g., alpha and theta wave detection.
I-'Iul tiple
unit activity studies could easily be performed, as those
published by Silverman, et al., 1970; Olds, 1973; Buch1-Tald, et al. , 1973; and others.
Single unit activity
(\foods a11.d Dafny, 1974) could also be investigated depending on the resolution of the voltage wi.ndow comparator and the quality of the preceding recording equipment.
11
The properties of the instru.1nent also suggest the use in
various
biofeedbac~c
studies (Barber, et al., 1970; Heyes,
1974; Schneiderman, et al., 1974).
The apparatus could be used not only for research
data collecting and processing, but also for physiological
measurements in patients for diagnosis, evaluation, or
treatment, and biofeedback control.
Some of the possible
applications are discussed below.
£!Ioni toring of heart rate in angina and post myocardial
infarction patients:
An important part in this evaluation of these patients
is to determine the amount of physical activity that can
be tolerated vTi thout developing angina or myocardial ischemia.
This is most commonly done by a standardized
treadmill exercise test to determine the approximate
heart rate at -vvhich ischemic EKG changes or symptoms
occur (Kennedy, et al., 1976).
fitness
~~d
An exercise program (for
improved conditioning) can then be developed,
whereby the patient is instructed to perform certain
exercises up to the predetermined maximal heart rate.
A
smaller modified version of the signal processor can be
attached to the patient with hoolc-ups to chest EKG monitoring leads and can signal the patient when his heart
rate exceeds the maximum rate as he is exercising, and
that he should
i~"'!lediately
slovr do1'm or stop.
This is
much more convenient than the current method of having
12
the patient
t~~e
ter ex:ercise.
his ovm pulse during or
af-
i~ediately
This convenience w·ould encourage the pa-
tient to comply ·Hith the prescribed exercise program.
The maximal heart rate is also used to detenJine if
the patient can tolerate the amount of activity required
of him in his occupation or other daily activities.
The
patient cot.:tld be instructed to monitor himself vii th the
device which 1-TOUld signal him if his heart rate is too
rapid (thus indicating excessive exertion) before dangerous symptoms or ischemia occurs.
In this -vray the indivi-
dual can learn more quiclcly and effectively to tailor
his activities to avoid detrimental cardiac effects.
Honitoring of pacemalcer patients:
Pacemaker patients need to be monitored frequently
for pacemalcer malfunction.
This is usually done monthly
or vreelcly (depending on the age of the pacemalcer) either
by a telephone surveillance system, whereby the electrical activity of the pacemalcer is transmitted, or by direct
visits to the physician.
One of the early signs of im-
pending malfunction is the gradual prolongation of the
rate of discharge of the
pacema~er
(Bilitch, 1971).
Pa-
tients could have a miniature version of the signal analyzer vrhich ·Hould indicate ·when the patient 1 s heart rate
and/or pacemaker firing rate falls belo"t'i a preset rate.
Such a device is currently not in use in the medical com-
13
mtmity.
The patient could then immediately contact his
telephone surveillance service or physicia..'l before the
pacemal:er deteriorates further.
This wotlld be especially
valuable in a patient who has a pacemaker generator near
the end of its life expectancy.
If the device is still
worlcing well, reimplantation (i-rhich is a surgical procedure) could be postponed.
The two applications mentioned above are being considered for practical use and are being tested on a pilot
basis in the cardiac non-invasive laboratory at the Los
Angeles Com1 ty-Uni versi ty of Southern Califort.l.ia Nedical
Center.
(Preliminary data are presented later in the
text.)
1-1oni to ring of vi tal signs in critical care units:
:Patients in shoe};: need many hemodynamic parameters
monitored frequently, almost continuously, in order to
guide the physician to fine, but critical adjustments in
fluid therapy and medications (e.g., pressor agents, such
as dopamine or isoproterenol; or vasodilator medication
for afterload reduction such as nitroprusside) and to aid
in the decision if an intra-aortic counterpulsation balloon pump i'rould be helpful (Forrester, et al., 1976; Shoemrucer, et al., 1970).
:Parameters that can be continuous-
ly measured in a fully equipped intensive care 1.mi t are
mean, systolic,
~~d
diastolic pressures of the systemic
14
and pulmonary arteries and the heart rate, all of which
can be hooked up to the signal analyzer and set an alarm
when any of these are out of range.
Another condition requiring intensive care monitoring
is the management of malignant hypertension which requires
immediate, but controlled treatment to prevent or to ameliorate serious cerebral, renal, cardiac, and pulmonary
damage, some of which are irreversible.
The constant
intravenous infusion of a short acting drug with a quick
onset of action is mandatory in order to lower the blood
pressure quickly and smoothly.
A real danger in this
method however is that the blood pressure can be lowered
too rapidly or the patient can become dangerously hypotensive.
Thus,almost constant monitoring is needed
(Jagger and Braunwald, 1977).
The signal processor de-
scribed later can trigger an alarm when the blood pressure
exceeds or falls below certain levels, in time for the
infusion rate of the drug to be altered.
This applica-
tion is being considered as a complement of an already
commercially produced programmable infusion pump controller
(~odel
BCL PIPC 2002, Belcron Laboratories, Inc.).
Monitoring of cardiac rhythm in ambulatory patients:
Continuous cardiac monitoring in an ambulatory patient (Corday and Lang, 1974; Lang, et al., 1971) is performed when it is suspected that certain
sympto~s
occur-
15
ring in the individual may be caused by ischemic effects
due to transient arrhythmias.
To document an arrhythmia
as a causative factor, a monitoring device such as the Holter AVSEP (manufactured by Avionics) has been developed
which records the EKG on magnetic tape over a prolonged
time period (e.g., 10 or 24 hours) while the patient
conducts normal daily activities (Holter, 1961).
The pa-
tient notes the time and duration of activities and symptoms in a diary during the monitoring period to help to
determine the significance of any arrhythmias detected.
The tape is then rapidly analyzed (in 12 minute period for
a 24 hour tape) in
a computer
vals of the QRS complexes.
which measures R to R inter-
The apparatus described in
this thesis could be employed to measure R to R intervals.
At
~~y
time where these parameters are out of range, the
tape could be played back slowly at conventional speed
for further EKG analysis on conventional EKG equipment,
thus saving the considerable cost of a dedicated computer.
Intracranial pressure monitoring:
Hith the advent of continuous intracranial pressure
monitoring (Lundberg, 1960; James, 1976), it has become
evident that intracranial pressures vary widely and that
intracranial hypertension in patients ldth aydrocephalus
can be episodic and can sometimes not occur at all.
It
is not exactly clear at this time lfhat physiological fac-
16
tors can precipitate intracranial hypertension.
Vasomotor
changes, anoxia, changes in blood pressure or cerebral
blood flow, valsalva, and differing sleep patterns have
been proposed and are being studied.
Hydrocephalus patients need to be continuously monitored for prolonged periods in order to obtain a representative pressure profile and to detect sudden intracranial hypertension.
In this way pharmacologic therapy
and the need for ventricular shunting can be evaluated.
Methods have been proposed to analyze pressure recordings
by reporting them as gross ranges over a certain time
interval based on one reading over that time period and
constr~cting
1975).
pressure-time histograms (Brock, et al.,
A more elegant method would be to use the signal
processor which can be modified to detect pressure in
certain ranges and with the help of polygraph, record
the pressure changes over time.
Another approach may be
to measure the intracranial pressure at a vulnerable time.
Some studies suggest that elevation of intraventricular
pressure occurs during rapid eye movement (REI\11) sleep
(Symon, et al., 1975; Pierre-Kahn, et al., 1975).
In-
stead of measuring intracranial pressures blindly, one
could monitor the EEG of the patients during sleep.
The
signal analyzer could detect RE:a sleep by interval analysis of the EEG -yraves and initiate recordings of intracranial pressures.
CHAPTER 2
METHODS AND
A.
~iATERIALS
PRINCIPLE OF OPERATION
A filtered and amplified electrophysiological analog
signal is fed into a window comparator and, upon crossing
the thresholds of the window, is converted into digital
pulses.
The thresholds and the input signal are multi-
plexed in order to permit their display on a single channel oscilloscope.
Pulses from the window comparator are
examined by the logic circuitry of a pulse height analyzer
(PHA).
If certain preset conditions are met, the pulse
height analyzer generates a uniform output pulse of fixed
duration.
These pulses are then routed through steering
logic to a series of counters, where their frequency or
interval is determined.
Information from the counters is
stored in a memory system.
Timekeeping signals necessary
for frequency and interval measurements and memory updating are provided by a crystal controlled clock.
The data
contained in the memory system are utilized in several
ways as follows:
1.
Entered into a digital magnitude discriminator
(DMD) to determine if the incoming signal falls
17
18
within, above, or below a selected frequency
band or interevent interval length.
2.
Presented to the input of a digital to analog
converter.
The output of the digital to analog
converter (D/A) is an analog representation of
the frequency or interval of the on-line electrophysiological signal and can be recorded on a
polygraph or a similar instrument.
3.
Displayed digitally on the front panel.
4.
Extracted for storage or analysis by external
equipment.
The block diagram of the apparatus appears in
Figure 1.
B.
DESCRIPTION OF THE BUILDING BLOCKS AND THEIR FUNCTIONS
a)
Voltage window comparator
The usual analog electrophysiological pulse, e.g.,
muscle potential, neural spike, EEG wave, or EKG signal,
is defined by the pulse voltage surpassing a reference
voltage level.
The pulse exists as long as it.remains
above the reference and ceases when it crosses below it.
This function is accomplished by the voltage comparator
(Figure 2).
A voltage vdndow comparator is a specialized form of
a comparator designed to detect the presence of voltage
MULTIPLEX
OUT
DMD
OUT
.DIGITAL
OUT
DMD
>
MPX
MEMORY
update
UL
SIGNAL
IN
I II/
. . ·-
I•
PHA 1-----rTEERING
LOGIC
LL~
.--L
I
advance
0 ANALOG
OUT
"'
COUNTER
reaet
CLOCK
FIGURE 1
BLOCK DIAGRAM OF THE APPARATUS
_..
\0
20
between two usually adjustable threshold voltage limits,
i.e., vdthin the boundaries of a voltage window.
This is
accomplished by combining the outputs of two comparators,
one indicating greater than the lower limit, the other
indicating less than the upper limit (Figure 3).
As seen from Figure 3 B, an ordinary voltage window
comparator is quite useless for the detection of electrophysiological signals.
Its output changes state on every
penetration of either of the window boundaries; therefore
a signal with an amplitude greater than the upper threshold will generate two output pulses.
To be able to ex-
tract only signals with amplitudes within the window limits, and to ignore all others, the window comparator must
be
mod~fied
and its output tied to additional logic cir-
cuitry of a pulse height analyzer.
Since the speed of
operational amplifiers, the building blocks of comparators,
is often too slow for digital logic, it is beneficial to
insert a Schmitt trigger between the comparator output
and the input of the additional logic to prevent false
triggering •.~ Adding one more inverter per output permits
the selection of triggering on positive or negative going
pulses.
Design considerations:
In this voltage window comparator the operational
amplifiers are used in an open loop condition.
The volt-
age difference required to change the output state is very
21
A) SCHEMATIC
B) OUTPUT BEHAVIOR
FIGURE 2
VOLTAGE COMPARATOR
UL
Eout
UL
LL
Eln
Eln
LL
Eout
A) SCHEMATIC
B) OUTPUT BEHAVIOR
FIGURE 3 VOLTAGE WINDOW COMPARATOR
22
small, on the order of a few hundred microvolts.
There-
fore, the limiting factor in determining the exact threshold is the offset voltage of the amplifier, which may be
as much as ±10 mV.
If greater precision is required, the
operational amplifiers used should have provision for
offset adjustment and should be adjusted as close to zero
as possible, as it has been done in this case.
The stipulated range of input voltages for this design is +10 V to -10 V.
This requires an operational
amplifier with a differential input voltage rating of at
least ±20 V to accommodate the worst case limits.
One of
the amplifiers with such a rating is the very common 741
(with differential input capability of ±30 V) and is used
here.
Unfortunatelly, the 741 amplifier is internally
frequency compensated, and this compensation slows down
the open loop speed.
Speed, usually expressed as a slew rate in
V/~sec,
is
another important factor in selecting an operational amplifier for comparator duty and indicates how rapidly the
amplifier output can change state.
For example, the out-
put of the 741 amplifier with a slew rate of 0.5
will require 40
state.
~sec
V/~sec
to swing from a negative to a posttive
The 531 operational amplifier, without frequency
compensation and a slew rate of approximately 50 V/usec,
would be a much better choice, as far as speed is concerned, but the 531 has a differential input voltage range
23
of only ±15 V; and therefore does not meet the requirements for the anticipated input voltages of this instrument.
If a narrower range of input voltages can be tol-
erated (+7.5 to -7.5 V), the 531 operational amplifier
could be used, changing only the value of the resistor in
the voltage divider for the reference voltage (from 500
to 1000 ohms in this example) and assuring that the input signal does not exceed the input voltage limits.
Othervise, the 531 is a pin-for-pin replacement of the
741 operational amplifier and uses the same offset null
circuitry.
The voltage
~dndow
itself consists of two identical
comparators, labeled A1 and A2.
Their non-inverting in-
puts are tied together and serve as the signal input of
the window.
Since the input impedance of the window is
quite low (in the kiloohm range), a third operational
amplifier A3 (741 or similar) wired as a voltage follover
is used as an input buffer, increasing the input impedance
to approximately 400 megohms.
The reference voltage for
each of the t1vo comparators is derived from the output
of a ten-turn precision potentiometer of one kiloohm and
is fed to the inverting inputs of the amplifiers.
One
side of the ten-turn potentiometer is grounded, and the
other side is connected via a switch and a resistor (in
this case 500 ohms) to +15 V or -15 V.
This resistor
adjusts the voltage across the potentiometer to exactly
24
10 V, and the switch permits selection of either a positive or negative reference voltage.
The power supply
leads of the operational amplifiers are connected to a
well regulated ±15 V supply and are decoupled by 0.1
~F
ceramic capacitors in parallel with 10 uF tantalum electrolytics, to prevent feedback effects and other undesirable instabilities.
The outputs of the comparators are usually not compatible with logic circuitry because of a speed mismatch,
and spurious pulses could be generated while the comparator output transverses the undefined region between
logic 0 and 1 states.
Therefore, to provide a "snap"
action, outputs of the comparators in this apparatus are
led to a pair of inverting Schmitt triggers ST1 and ST2.
The Schmitt triggers used here are two-input NAND gates;
unused inputs are in this application tied to the positive
supply but could be used to gate the window.
To prevent
a negative voltage from the comparators reaching inputs
of the Schmitt triggers, diodes are connected between
the comparator outputs and logic inputs.
Furthermore, to
limit the positive excursions of the comparators to a
voltage safe for the logic circuitry, 3.9 V Zener diodes
shunt the logic inputs to ground, and 5 kiloohm resistors
prevent loading of the
compar~tors
and excessive currents
through the diodes.
The outputs of the Schmitt triggers are led to a
25
pair of inverters I1 ru1d I2 and a slope selector srdtch,
which provides alternate polarities of the comparator
outputs.
A positive level (logic 1) appears at the switch
output if the comparator input is more positive than the
threshold voltage (positive slope), or more negative than
the threshold (negative slope) and lasts as long as the
input signal bears the proper relationship to the threshold voltage.
The outputs of the switch, i.e., the outputs
of the comparators converted to logic levels, are then
fed into the pulse height analyzer and are also made
available on the front panel of the instrument in order
to permit the use of the comparators independently, i.e.,
as single comparators, stacking the comparators for multilevel val tage 1dndows, etc.
For the logic circuitry of this building block as
well as for the circuitry of subsequent blocks, proper
power supply decoupling practices should be observed.
The general rule is to use one 0.01-0.1
~F
ceramic disc
capacitor from Vee (usually pin 14 or 16 in DIP packages)
to ground for each of the more complex chips, i.e., counters, flip-flops, one shots, etc.; one 0.01-0.1
~F
ceram-
ic capacitor for each group of five simple chips, i.e.,
gates; and one 1-10 uF tantalum capacitor for each group
of five chips.
be employed.
If there is any doubt, decoupling should
The capacitors are cheap, and problems
caused by poor decoupling could be very hard to trace and
,...-----.. SLOPE
+ /
0
>.
POLARITY
I.
UL
y
SIGNAL
IN
1k ~
uc
o
LC
LL
l 1
+ 15V-
FIGURE 4 MODIFIED VOLTAGE WINDOW COMPARATOR
1\)
0\
27
rectify.
The schematic of the modified voltage window comparator is shown in Figure 4.
Integrated circuits used
here are:
b)
A1-3
741, 531, or similar operational amplifier
ST1,2:
4093 quad 2-input NAND Schmitt trigger
I1,2 :
4093 quad 2-input NAND Schmitt trigger.
Pulse height analyzer
The purpose of the pulse height analyzer is to gen-
erate a uniform output pulse only if and when a transient
event (such as a component of a QRS complex or a neural
spike) penetrates the lower threshold limit of the window
and recrosses, or
11
defenestrates" the lower threshold
again without first crossing the upper boundary.
This
implies that the output pulse must occur on the falling
slope of the examined signal at the moment of the defenestration.
Some sort of memory must be employed to "re-
member" the penetration and defenestration of the lower
threshold and the possible crossing of the upper window
boundary.
Additional logic is needed to determine from
the contents of the memory if the conditions warrant the
generation of the output pulse.
Upon reviewing the available literature, it was
found that commercial pulse height analyzers (Haer, 1975)
28
and published designs (Brown, P.B., et al., 1973; Olds,
1973; Heyes, 1974) are all frequency dependent, i.e.,
under certain conditions generation of false output pulses
could occur.
For example, in one of the commercial ana-
lyzers (Frederick Haer and Company, catalog #40-75-1),
a false output pulse is generated unless the penetration
of the upper window boundary follows the penetration of
the lovrer boundary ·within 0. 2 msec.
The design presented here, in spite of its extreme
simplicity, has eliminated these problems and is virtually
frequency independent, i.e., the upper speed limit is determined only by the logic family used (several }lliz for
C}10S, approximately 30 HHz for TTL, etc.), and there is
no lower speed limit.
Only tw·o flip-flops are used as
the memory element, cloclced by the lower and upper outputs of the voltage window comparator.
Additional logic
consists of two monostable multivibrators (one shots),
one inverter, and one NOR gate.
Design considerations:
As can be seen from Figure 5, the logic circuitry of
the pulse height analyzer is constructed from D-type positive edge clocked flip-flops.
Clock input of the flip-flop labeled FF1 is connected
to the output of the lower comparator and the clock input
of the flip-flop labeled FF2 to the output of the upper
29
....._
D
Q
FF2
uc ....
c
Q
A
rG>
,-; J
A
~
D
os1
Q
FF.,
LC
-
c
A
'----
OSz
-
FIGURE 5 PULSE HEIGHT ANALYZER
-""'
PHA OUT
30
comparator.
~f.aen
a pulse appears on the lo1·rer comparator
output signaling a crossing of the low·er boundary, the Q
output of the FF1 goes to logic 1 state.
Upon defenes-
tration, vdthout crossing the upper threshold, the falling edge of the lower comparator pulse triggers (via inverter I and gate G) the one shot OS2, which in turn resets the FF1, returning its Q output to logic 0 state.
The transition of the Q output from 1 to 0 triggers the
one shot os1, generating thus a pulse height analyzer
(PHA) output pulse of fixed duration.
The negative tran-
sition of the lower comparator output also resets the
FF 2 •
If, on the other hand, a penetration of the lower
threshold is follo·wed by a crossing of the upper boundary, the Q output of the FF2 goes to logic 1 state, triggers the os 2 via the gate G and resets the FF 1 •
While
a trigger pulse occurs at the Q output of the FF1, the
os1 is prevented from firing by logic 0 stat·e of the Q
output of the FF2, and the PHA pulse is therefore not
generated.
W.aen the falling edge of the signal subse-
quently leaves the windovr, the FF2 is reset, and the
whole cycle can be repeated again.
Wave forms of the
pulse height analyzer are illustrated in Figure 6.
A 555 timer is used in this design as the negative
edge triggered one shot os 1 •
The length of the
generated by the OS1 is set at 100
~sec.
PF~
pulse
The pulse length
could be easily changed to different values using the
31
UL
LL
I
SIGNALl
I
I
I
I
I
I
uc
LC
I
I
I
I
I
I
I
I
I
RFF2
I
QFF2
I
I
I
I
I
I
I
I
I
I
I
I
r
I
I
I
I
I
I
I
I
I
I
1
n
I
I
L
I
I
I
1
_j
I
I
os1
L
I
I
QFF1
I
I
I
I
I
I
QFF2
I
I
II
RFF
I
I
I
I
I
_j
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
!
I
I
I
I
I
I
FIGURE 6 WAVE FOAMS OF TME PULSE HEIGHT ANALYZER
I
I
I
I
I
I
I
I
32
formula
t
= 1 • 1RC
( sec .(l.F ) ,
where R is the resistor from discharge and threshold pins
of the 555 chip to positive supply, and C is the capacitor
from the same pins to ground.
OS2, the resetting one shot, is also negative edge
triggered and is constructed from a 4001 NOR gate and a
RC network in the input of the gate.
The pulse length is
adjusted to approximately 1 usee.
The schematic of the pulse height analyzer is in
Figure 5.
c)
Integrated circuits used here are:
FF1-2:
4013 dual D-type flip-flop
os 1
••
555 timer
os 2
••
4001 quad 2-input NOR gate
G
4001 quad 2-input NOR gate
I
4001 quad 2-input NOR gate.
liul tipl exer
In order to permit easy comparison of the input sig-
nal and the threshold levels of the voltage vdndow on a
single oscilloscope beam, a multiplexing circuit is incorporated in this apparatus.
The multiplexer samples the
input signal and the upper and loi·rer limits at a frequency rate of 100 lcHz a.i'ld presents the extracted information
to an oscilloscope.
The oscilloscope beam is
11
chopped"
33
at 100 kHz, and four traces are
generat~d
on the oscillo-
scope display, representing the pertinent signals.
Design considerations:
The multiplexer is based on a 4016 quad transmission
gate.
Since there are four transmission gates in the 4016
chip, the display of the pulse height analyzer output was
considered.
This can be easily done but at the cost of
two additional controls on the front panel, i.e., the gain
of the pulse height analyzer pulse and its position on the
oscilloscope display.
The desired information concerning
the input signal and the two thresholds is their mutual
relationship; therefore gain and position controls are
not needed here. As not to waste the fourth gate of the
chip, it is used in this apparatus to display a ground
reference.
The multiplexing frequency is obtained from an oscillator circuitry constructed from inverters I1 and I2 and
is fed into a modulo-4 walking ring counter.
The counter
is constructed from a dual D-type flip-flop FF 1 and FF2.
The states of the counter are decoded with four NOR gates
G1 through G4.
Each NOR gate turns on its associated
transmission gate TG1 through TG4 in sequence, idth only
one transmission gate operating at any given time.
The input signal limits of this apparatus are ±10 V.
Therefore, as not to damage the transmission gates, the
34
the input signal and the t·wo thresholds are halved by
voltage dividers before entering the gates.
Furthermore,
a negative :po1·rer supply must be provided, in order to accommodate signals of negative polarity.
The current re-
quiremen ts of the multiplexing circuitry are very lm'f,
and their negative supply can be simply derived from a
5.1 V Zener diode connected through a limiting resistor
to -15 V of the main :po-vrer supply.
The four outputs of
the transmission gates are connected together and are
presented as a single output on the front panel.
Because of the voltage dividers used, the amplitudes
displayed on the oscilloscope are exactly one half of the
am:pli tudes of the actual signals.
An amplifier with a
gain of two could be used to restore the displayed amplitudes to their original values, but the added cost and
complexity of the circuitry did not justify the addition
in this case.
The schematic of the multiplex circuit is shown in
Figure 7.
Integrated circuits used here are:
I1,2
4001 quad 2-input NOR gate
FF1,2:
4013 dual D-type flip-flop
G1-4 ••
4001 quad 2-input NOR gate
TG1-4:
4016 quad transmission gate.
35
22k
500k
~~~+-~------------.0
SIGNAL
c
TG4
t------1
FIGURE 7 MULTIPLEXER
MPXOUT
36
d)
Clock
The clock in this unit consists of a crystal con-
trolled oscillator.
A chain of decade dividers provides
stable frequencies needed for different frequency or interval measurement ranges.
A decision must be made here
if the instrument should be operating in a binary or binary coded decimal (BCD) mode.
Compared to the BCD ver-
sion, a binary instrument would be cheaper to build and
would use fewer parts for the same degree of accuracy,
but the interpretation of results (output in binary code)
or the setting of controls (for the digital magnitude discriminator) would be more cumbersome, since few electrophysiologists are comfortable with numbers expressed in binary form.
For the sake of simplicity, only the BCD ver-
sion of the instrument is considered in this work.
For the BCD instrument four ranges are proposed, one
for frequency and three for interval measurements as
follows:
Range:
Frequency:
Interval:
0-999
0.99-
Hz
9.99 msec
9.99- 99.9
99.9 -999
msec
msec
Design considerations:
The crystal oscillator is constructed from an invert-
IMHz
lOOkHz'
lOkHz
8
1kHz
1Hz
8
8
C2
CL
FIGURE 8 CLOCK
I...J,J
-.J
38
er I1 biased into its linear region by a 22 megohm resistor.
A 1\network, which includes a 1 HHz crystal, is con-
nected in the feedback loop from the output to the input
Another inverter r 2 is used as an output
of the inverter.
buffer to assure a full amplitude, square wave output.
The output of the oscillator is fed into a chain of
six decade dividers
c 1_ 6 ,
measurement standards:
1
which provide the necessary
Hz for the 999 Hz frequency
range, 100 kHz for the 9.99 msec interval range, 10 kHz
for the 99.9 msec, and 1 kHz for the 999 msec interval
ranges.
Four bit BCD counters are used as the decade
dividers and are synchronously driven in order to avoid
extensive propagation delays.
i 1Iore counters can be easily
added if different or extended measurement ranges are
needed.
The schematic of the clock is shown in Figure 8.
Integrated circuits used here are:
r1, 2:
c 1_6:
e)
4001 quad 2-input NOR'gate
4029
s~Achronous
BCD counter.
Steering logic
The signals from the ptuse height analyzer and the
cloclc are routed into the steering logic circuitry, vrhere
s1·rotching betueen the frequency and interval modes is provided.
The reason for incorporating the interval modes in
this instrument is the increased measurement accuracy of
39
the lower frequencies by measuring the length of the interval between individual pulses, instead of simply counting
the pulses in a given time window, which is the principle
of the frequency mode.
The steering logic also provides
timekeeping pulses for counter resetting and memory and
display updating.
Design considerations:
The timekeeping pulses are derived from three D-type
flip-flops FF 1 , FF2, and FF 3 , clocked at 1 ~"mz rate. The
data input D of the flip-flop FF1 receives either 1 Hz
clock pulses in the frequency mode, providing 1 sec time
gate for the 999 Hz range, or pulse height analyzer output
pulses in the interval mode.
These pulses are ORed in a
two input OR gate G1 with counter overflow pulses; in this
fashion the reset and update commands are automatically
provided if the frequency or interval ranges are exceeded.
The update memory command is a negative going pulse
1psec in duration and is obtained by NANDing the Q output
of the FF 1 and the Q output of the FF 2 in a two input NAND
gate G3 • The update command is immediately followed by a
counter reset pulse, again 1
ing.
~sec
long, but positive go-
This pulse is the result of NORing the Q output of
the FF 2 and the Q output of the FF 3 in a two input NOR
gate G2 •
The update display command is derived from the counter
UPDATE
DISPLAY'
C2
CL
COUNTER
OVERFLOW
1MHz
CLOCK
1Hz
)
EVENTS
PHA
I
ID
Ql '
FF1
I I
RESET
COUNTER
!C
UPDATE
MEMORY'
CLOCK
100kHz
lOkHz
1kHz
0
0
0
Sb
•
e
ADVANCE
COUNTER
•
FIGURE 9
STEERING LOGIC
.f:::0
41
reset pulse.
To prevent or minimize display blur, espe-
cially in the shorter interval modes, a divider chain
consisting of two decade counters c 1 and c2 is inserted
here.
For the frequency measurement range of 999 Hz the
reset pulse is divided by 2; the display is thus updated
every 2 sec.
For the 9.99 msec interval range the divi-
sion is by 100, resulting in display update every 0.1-1
sec; for the 99.9 msec and 999 msec the division is by
20 and 2 respectively, providing for display updating
every 0.2-2 sec.
Since the display latches/drivers re-
quire a negative going update pulse, the output of the
divider is inverted by an inverter I.
The schematic of the steering logic is shown in Fi-
gure 9.
FF1-3:
4013 dual D-type flip-flop
G1
4071 quad 2-input OR gate
G2
4001 quad 2-input NOR gate
G3
f)
Integrated circuits used here are:
••
4011 quad 2-input NAND gate
c 1 '2
4029 synchronous decade counter
I
4011 quad 2-input NAND gate.
Counter and memory
Appropriate pulses from the steering logic are coun-
ted in a counter, in this case a three digit BCD counter.
In the frequency measuring mode, the steering logic ap-
42
plies the pulse from the pulse height analyzer to the
clock input of the counter and also applies a 1
~sec
pulse derived from a 1 Hz clock to the reset input.
long
The
output of the counter is therefore a 12 bit BCD word representing the number of PHA pulses within a predetermined
time interval, in this case 1 sec.
In the interval meas-
uring mode, the 1 usee restting pulse is generated by the
PHA output.
Clock pulses of 100
are routed to the clock input.
~qz,
10 kHz, or 1 kHz
The BCD word on the out-
put of the counter thus represents the number of clock
pulses between two PHA pulses, i.e., the length of the
time interval between two events.
The memory circuit monitors the output of the counter
and, on command from the steering logic, stores the contents of the counter until a new command for updating
arrives.
This command is 1 usee long and precedes the
reset pulse of the counter, in order to give the memory
enough time to settle on the new data before the counter
is reset to zero.
The memory output represents stable
data in the form of a 12 bit (3 BCD digits) word which is
updated periodically (the output of the counter changes
continually) and can be used for interface with the outside world (e.g., digital data storage, computer analysis,
printers, etc.); provides signals for the digital display;
and is also routed to the inputs of the digital magnitude
discriminator and digital to analog converter for further
43
processing.
Design considerations:
The counter is constructed from three synchronous
BCD counters C1, 02, and 03.
The advance command from
the steering logic is simultaneously applied to the clock
inputs of all three counters.
The counters used do not
have a reset input; reset command is a positive going
pulse and is applied to the preset enable inputs of the
three counters, loading them with zeros.
The 999 count
of the counter is decoded by the three input NOR gate G1
and routed to the counter overflow input of the steering
logic.
Logic 1 (i.e., overflow) on the output of the
gate G1 also sets a set-reset flip-flop consisting of
gates G2 and G3.
Setting the flip-flop causes the over-
range indicator LED (light emmiting diode) on the front
panel to light; the flip-flop is reset manually by a
switch also located on the front panel.
The memory unit is built from three quad D-type
latches L1, L2, and L3.
Outputs of the counter are
brought to appropriate data inputs of the latches.
Wnen
the update command (which is negative going and 1 gsec
in duration and immediately precedes the counter reset
pulse) is applied to the store inputs of the latches,
the data is transferred from the data inputs to the outputs.
On the trailing edge of the update pulse, i.e.,
MSD
LSD
)
-
s
2
..
8
~
~
~
L1
2
~
r--
)
s
..
(
8
)
L2
r--
s
2
..
8
)
)
)
L3
UPDATE n.
-
r
ADVANCE
:
r--+~--~+---~
rl-
CO
1'
C 1 CO
Pf
- Cl
l
C 2 CO
PE
Cl
C3 col>-
I' ..
RESET
~ OVERFLOW
I ~~
RESET (
OVERRANGE
FIGURE 10
COUNTER
G,
_
)
GJ
J
·@
OVERRANGE
LED
~--'
COUNTER AND MEMORY
~
~
45
on the positive transition, the data is stored internally
until the next update pulse arrives.
The buffered memory output is presented on the front
panel for interface with additional equipment.
The schematic of the counter and the memory is shown
in Figure 10.
g)
Integrated circuits used here are:
01-3=
4029 synchronous BCD counter
G1
4025 triple 3-input NOR gate
G2,3:
4001 quad 2-input NOR gate
L1-3:
4042
D-type latch.
qu~d
Display
A three digit digital readout display system is used
in this instrument.
The purpose of the readout is to
visually display the frequency or the interval of the
events being analyzed.
The display is not intended to be
used as an accurate representation of the frequency or
interval, but more as an indicator of the approximate
range of the incoming signal.
If the readout 1vere to
display every measurement taken, blurring, especially on
shorter interval measurements, would occur.
analyzing events
~dth
For example,
an interval varying between 1 to 9
msec and updating the display after every measurement,
the readout would seem to be to the human eye a blurred
11
888."
For this reason, the readout displays every sec-
LED 1
a
c
d
e
c
d
e
5
UPDATE 0
'
t
g
g
a
5
Dl
I
I
I
I
2
..
8
•
5
02
I
I
I
I
2
..
8
LSD
03
'
2
..
8
MSD
FIGURE 11
DISPLAY
.p:0'1
47
ond measurement in the 999 Hz frequency and 999 msec interval ranges, every twentieth measurement in the 99.9
msec, and every hundredth measurement in the 9.99 msec
interval ranges.
Design considerations:
Three latch/decoder/drivers D1, D2, and D3 are used.
The decoders accept the BCD code from the memory on their
inputs, store the information in internal latches on the
update command from the steering logic, and convert the
BCD code into active high, seven segment readout code.
Limiting resistors, typically 150 to 330 ohms for a 5 V
power supply, in the readout lines limit the current
through the light emitting diode (LED) readouts.
The
update command for the display is a negative going pulse,
obtained by dividing the counter reset
co~~and
by 2, 20,
or 100, as discussed in the steering logic section.
The schematic for the display is shown in Figure 11.
The integrated circuits used here are:
D1_ 3 :
4511 seven segment latch/decoder/driver.
The LED readouts LED1-3 are a seven segment, common cathode type.
h)
Digital magnitude discriminator
The digital magnitude discriminator is useful in de-
termining if the pulse frequency or interval falls vdthin,
48
above, or below a selected band.
This task is accom-
plished by utilizing two sets of digital magnitude comparators.
Upper and lower band limits are established
by thumbwheel or similar presettable switches.
Each set of comparators compares the contents of the
memory with the setting of the selector switches and generates three outputs: A=B, A>B, and A<B.
By proper gating
of the outputs of the two comparator sets, the desired
information is obtained.
Design considerations:
The.lower digital magnitude comparator set consists
of three 4 bit binary comparators D1, D2, and D3.
Each
comparator compares two 4 bit words and provides outputs
to determine whether they are equal or which is greater.
The upper set is constructed from comparators D4, D5, and
D6•
In both sets, the
comp~rators
for the four least
significant bits have their A<E inputs grounded and the
A=B and A>B inputs connected to the positive supply.
The comparators for the higher order bits are cascaded
by connecting the three outputs A<B, A=B, and A>B of the
first comparator to the three respective inputs of the
next comparator, and so on.
The contents of the memory represent the 1-rord B
which is to be compared 11i th the word A.
The word A is
determined by setting of two banks of thumbwheel switches,
TS4
- 2
~A>B
A"'B
A<B
8
MSD
'i
··~
TS5
T 2 4
·~
TS 6
-
T
··~
A)B 1--
0.4
06
Os
ABOVE
,...
~
.42 ;;;.
1 n.
8n
.__
I
.--
.4 ,..
:::::
2 :::::
LSD
....
A{B
,...
8
.42 ....
,......
G
"
IN BAND
n
BELOW
I
~•>•
A=B
01
~A<B
I
.4
TS1
2
03
02
8
c
FIGURE 12
T 2 .4
TS 2
8
c
1
.4
TS 3
2
A>B
A(B 1--
8
c
DIGITAL MAGNITUDE DISCRIMINATOR
.f::-
\.0
50
one each for the lower limit (switches TS1, TS2, and TS3)
and the upper limit (switches TS4, TS5, and TS6).
The
outputs of the thumbwheel switches used are complements
of BCD; each bit output is pulled up to the positive supply by a 22 kiloohm resistor, and the commons of the
srri tches are grounded.
The A>B output of the lower most significant digit
(or four most significant bits) comparator D3 is presen ted on the front panel as bel01f band ou t:pu t.
The A<B
output of the comparator D6, for the upper most significant digit, is also available on the front panel as
above band output.
The rrithin band output is acquired
by ANDing the A<B output of the lower comparator D3 and
the A>B output of the upper comparator D6 in the AND
gate G.
The within, above, and below outputs go positive
if conditions, which they represent, are met.
The schematic of the digital magnitude discriminator
is shown in Figure 12.
The integrated circuits used here
are:
i)
D1-6:
4585 4 bit digital magnitude comparator
G
4081 quad 2-input
M~D
gate.
Digital to analog converter
A digital word contained in the memory represents
the frequency of the incoming signal or interval between
51
events.
This information can be converted into an analog
voltage by the digital to analog converter (D/A) and can
be then recorded on a polygraph or similar instrument.
Originally, a commercial converter was planned for this
apparatus, but the cost of a three digit D/A converter
was found prohibitive, at least for this project.
The
construction of a converter was therefore undertrucen.
The results obtained from the D/A converter here are
similar to those from more commonly used integrators, but
the analog voltage obtained by the converter is a more
accurate representation of the properties of the examined
signal.
Design considerations:
This design truces advantage of the fact that the
C~IOS
logic outputs swing all the way from ground to sup-
ply voltage.
In this converter, the memory outputs are
buffered by buffers B1-12 and fed into a R-2R resistor
ladder network and summed in the operational amplifier
A1 •
One of the advantages of the R-2R ladder over other
conversion methods is that the impedance of the ladder,
as seen from the summing input of the operational amplifier, is constant and equal to R.
Thus, the R-2R ladder
can be easily adapted to BCD logic by using subsections
of the R-2R network for each decade and then summing these
in parallel with additional decade weighted resistors, in
52
this case 9R for the middle digit and 99R for the least
significru1t digit.
Another advantage of the R-2R network
is that the accuracy of the converter is not dependent
upon the absolute value of all the resistors, but rather
only on their differences.
In this converter,
R~s
are
10 kiloohm. 1% precision metal film resistors.
Since the 5 V power supply is used here as the voltage
reference for the converter, it was felt necessary to
build a separate supply for the buffers B1-12•
This
po·wer supply is +5 V, derived from the +15 V supply by
utilizing a 7805 5 V voltage regulator.
In this way,
voltage fluctuations of the main supply, caused by current
consuming elements of the apparatus such as display readouts, cannot adversely affect the accuracy and stability
of the D/A converter.
The summing amplifier A1 has a trimming potentiometer
with a value of 3R in its feedbaclc loop, so that the output voltage can be adjusted to a desired level, in this
case -5 V full scale.
Output of the amplifier A1 is
buffered by the operational amplifier A2 , connected as a
voltage follower.
Output of the amplifier A2 is presented
on the front panel as the negative output of the digital
to analog converter.
The output of the amplifier A1 is
also inverted in a unity gain inverting operational amplifier A3.
The output of the amplifier A3 is buffered
by the voltage follo1-rer A4 and is available on the front
53
8
R
4
R
MSO
2
R
JR
2R
8
ANALOG OUT
R
+
R
LSD
FIGURE 13
DIGITAL TO ANALOG CONVERTER
54
panel as the positive voltage output of the D/A converter.
The schematic of the digital to analog converter is
shown in Figure 13.
Integrated circuits used here are:
B1_ 12 :
4050 hex noninverting buffer
A1-4 :
741, 747, or similar operational amplifier
with offset null capability.
j)
Po-vrer sup-ol;r
The pmv-er supply needed for this instrument is rath-
er simple.
The analog portion of the apparatus requires
±15 VDC, at approximately 50 mA.
Since this portion of
the power supply is also used as a reference voltage for
the voltage window comparator, good regulation and tracking is essential, as well as low ripple.
A dual traclcing
regulator vdth tracking better than 50 mV and ripple
below 1 mV is presented in Figure 14.
Integrated circuits
used here are:
A1,2:
741, 747, or similar operational amplifier.
Transistors used here are:
Q1 :
2N3904
Q2:
:f1JE3055
Q3:
2H3906
Q4:
2-iJE2955.
Supply for the logic portion of the apparatus is a
regulated +5 VDC.
Current requirement is approximately
+20V 0
t
,
/..
l
'
t
t
'
t
t
0+15V
I
0 GND
1k
+
+
6.3V
+
I
I
I
•
+
4.7k
t
I 100JJF
3.9k
10k
-20VO
•
•
\
~~__J_ __ j l - - - - - - - - l - - _ . _ - - - - - Y - 1 5 V
FIGURE 14
DUAL TRACKING VOLTAGE REGULATOR
\J1
IJl
56
200 mA, a major portion of which is used by digital display readouts and their current limiting resistors.
The
digital portion of the digital to analog converter has
its own +5 VDC voltage regulator and this voltage is also
used as the reference voltage for the converter.
The
current drain is negligible.
The povrer supply for the logic circuitry is shown in
Figure 15.
VR1,2:
Integrated circuits used here are:
7805 voltage regulator.
57
OUTI----o +5V
+12V o--+---IIN
+
O.h!F
1JJF
+ 15V
o--.-~
IN
VR2
OUT
c
FIGURE 15
POWER SUPPLY FOR LOGIC CIRCUITRY
+5V
CHAPTER 3
RESULTS
A.
SPECIFICATIONS OF THE APPARATUS
Series of tests were performed to establish the re-
solution, frequency range, and accuracy of the apparatus.
The results should provide a good estimate of the suitability of the instrument for various tasks.
The follow-
ing equipment was used for testing:
Tektronix Oscilloscope, Model 5103N, with
Dual Trace Amplifier, Model 5A18N
Dual Time Base, Model 5B12N
Dual Beam Storage, Model D13
Hewlett Packard Electronic Counter, Model 5221A
Tektronix Digital Mul timeter, !Jlodel m-1 501
Tektronix Function Generator, Model FG501
Tektronix Dual Power Supply, !-1odel PS503
A circuit was developed for testing purposes producing
two square wave pulses of approximately 10
~sec
duration.
The amplitude of the output pulses was independently
variable over the 0-5 V range.
The circuit was driven
by the FG501 function generator, thus permitting to vary
the frequency of the output.
58
59
Test results:
a)
Voltage window comparator:
Input impedance Zin
~
400 M!L
Input voltage range Vin ± 10 V
Reference voltage range Vref
±
10 V
The test results of the window comparator are in
Table 1.
Static performance was measured at six differ-
ent voltages for both lower and upper comparators.
The
worst case error was 3 mV; long time resolution was estimated to
be~
20 mV, due largely to the reference voltage
drift and instability of the reference potentiometers.
Dynamic performance was measured using a square pulse
approximately 10 usee long.
The hysteresis of the com-
parators was impossible to measure with the equipment on
hand, but appeared to be less than 1 mV.
b)
Pulse height analyzer:
Minimum frequency
Maximum frequency
Amplitude
DC
~
9.5000 kHz
discrimination~
20 mV
Output: 100 usee pulse, logic level
There is no minimum frequency limit.
The maximum
frequency accepted is determined by the width of the
output ptuse (in this case 100 Msec).
The amplitude dis-
crimination is largely determined by the resolution of
the voltage comparators.
60
TABLE 1
TEST RESULTS OF THE VOLTAGE 1HNDOW COlviPARA.TOR
A.
STATIO TESTS
Reference Voltage (Vref)
+1.000
-1.000
+5.000
-5.000
+10.000
-10.000
B.
v
v
v
v
v
v
Trigger Point (Vin)
Lower
Comparator
+1.00 16
-1.0014
+5.002
-5.002
+10.002
-10.003
v
v
v
v
v
v
Upper
Comparator
.oo 11 v
.oo 15 v
+5.002 v
+1
-1
-5.001
v
+10.001
-10.002
v·
DYNA}UC TESTS
Difference between
Vref and Vin
2.00
1.00
0.50
0.40
0.30
o. 20
o. 10
0.08
0.04
0.02
v
v
v
v
v
v
v
v
v
v
Frequency Limit
40.000 k.Bz
23.700 kHz
22.700 kHz
22.500 kHZ
22.300 kHz
22.000 k..,qz
19.300 k...qz
17.250 }U.qz
10.800 lc.Hz
5.300 kHz
v
61
c)
Master clock:
Frequency: 1
~1Hz
No drift 1·ras noticed over a four hour period measured at the 10 kHz output.
d)
Frequency and interval analyzer:
Range:
Frequency:
0 - 999
Interval:
9.99 msec
0.99 9.99 99.9
Hz
99.9
msec
msec
- 999
Accuracy of the frequency and interval analyzer is
minus O, plus one count at all ranges, e.g.,
full scale (999 output):
+ o. 1% - o.o%
1/10 scale (099 output):
+ 1.0% - o.o%
1/100 scale (009 output): +10.0% - o.o%
e)
Digital magnitude discriminator:
Range: 0 - 999
Resolution:
1
least significant digit (LSD)
Outputs: within, above, below range: 5 V CMOS logic
levels
f)
Digital interface to the outside world:
12 bit BCD word,
5 V CMOS logic levels
62
TABLE 2
ACCURACY TEST OF THE DIGITAL-TO-A.NALOG CONVERTER
LSD
BOD
in
o.o.
( mV)
Hiddle Digit
A.O.
(mV)
o.o.
(mV)
A.O.
(mV)
o.ooo
0
o.ooo
o.ooo
o.ooo
1
5.005
5.012
50.050
2
10.010
10.091
3
15.015
4
11SD
o.o.
(mV)
.A..O.
(mV)
o.ooo
o.ooo
50.07
0.5005
0.5070
100.100
100.01
1 .oo 10
1.0040
15.109
150. 150
150. 15
1. 5015
1. 5031
20.020
20.14
200.200
200. 18
2.0020
2.001
5
25.025
25.08
250.250
250.27
2.5025
2.502
6
30.030
30.11
300.300
300.30
3.0030
3.001
7
35.035
35.06
350.350
350.38
3. 5035
3.505
8
40.040
39.93
400.400
400.41
4.0040
4.009
9
45.045
44.97
450.450
450.46
4.5045
4.505
Abbreviations:
LSD= Least significant digit
r<IS:O = Host significant digit
BC:O = Binary coded decimal
c.O.= Computed output
A.O.= Actual output
63
g)
Digital-to-analog converter:
The test results of the digital to analog converter
are in table 2.
Outputs: 0 to +5 V, 0 to -5 V;
output impedance
B.
~
500!l
USE IN CARDIAC DATA Al\fALYSIS
Several suggested applications for use in electro-
physiology and clinical medicine were mentioned in the
introduction.
Two of the situations in clinical practice
in which the apparatus can be employed have been studied
in order to demonstrate its feasibility in actual practice and are presented here.
a)
Heart rate determination:
In order to determine the suitability to indicate
excessive heart rates in certain vulnerable patients,
serial heart rates were measured in patients undergoing
exercise testing and compared to a threshold heart rate
set on the signal processor.
The processor "\'las programmed
to release a signal when the heart rate exceeded the
threshold rate.
The results of the signal behavior
"~'lith
respect to varying heart rates are sholin in Table 3 and
show that the signal is emitted appropriately.
64
TABLE 3
PERFOffi1ANCE OF THE APPARATUS
IN DETECTING THE THRESHOLD HEART RATE
DURING Al.'JD AFTER EXERCISE
Threshold
Pt.
vlK
Condition
Exercise
R-R
Exercise
Interval
( msec)
( BPl,1)
(min) ( BP1cl) (yes/no)
353
160
500
0
2
3
4
5
6
7
8
9
100
150
158
167
175
175
175
176
176
176
no
no
no
yes
yes
yes
yes
yes
yes
yes
0
1
2
165
14o
130
yes
no
no
0
60
97
98
102
104
121
123
131
131
no
no
no
no
no
yes
yes
yes
yes
131
103
93
yes
no
no
1
120
1
2
3
4
5
6
7
8
Post
Exercise
Signal
Outputir-
·:rime
Post
Exercise
EA
Heart
Rate
Heart
Rate
0
1
2
65
f
TABLE 3--Continued
Threshold
Pt.
EH
Condition
Exercise
Time
( msec)
( BP:t-i)
(min) (BPH) (yes/no)
353
160
no
no
no
no
no
no
yes
yes
yes
yes
yes
yes
yes
2
125
120
no
no
0
1
2
3
4
5
6
7
8
9
10
11
130
150
160
170
175
200
200
180
200
200
200
200
no
no
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
0
1
2
175
150
145
yes
no
no
0
1
Post
Exercise
~~-
Output~!-
90
140
145
150
155
160
165
170
175
175
175
175
180
0
1
Post
Exercise
Exercise
Signal
Heart
Rate
2
3
4
5
6
7
8
9
10
11
12
Rr-1
Heart
Rate
R-R
Interval
353
160
yes: indicates signal output occurring ·when measured
heart rate exceeds threshold rate.
no: indicates signal output 11.2.1 occurring vrhen measured heart rate does not exceed threshold heart
rate.
'
66
b)
Cardiac pacemaker rate determination:
In order to determine the suitability to monitor
pacemrucer deterioration (manifested by increasing firing
intervals), the intervals between pacemaker pulses were
measured in different patients
~~d
compared to varying
intervals set on the signal processor in such a way that
the processor would signal when its chosen interval fell
below that of the pacemaker.
Results are sho1in on Table
4 and show that the apparatus is accurate in detecting
preset intervals within 1 msec.
67
TABLE 4
PERFORHANCE OF THE APPARATUS
IN DETECTING THE UPPER
LI~UT
OF Tiill PACEl1AKER SPIKE IN 1EERVAL
Patient
Spil~e
Upper Limit
Interval
Interval
Signal
Output~~
( msec)
(msec)
PG
804.0
801
802
803
804
805
806
yes
yes
yes
yes
no
no
TR
882.9
880
881
882
883
884
885
yes
yes
yes
yes/no
no
no
HD
932.0
930
931
932
933
934
yes
yes
yes
no
no
ED
868.6
866
867
868
869
870
yes
yes
yes
no
no
ET
824.9
822
823
824
825
826
827
yes
yes
yes
no
no
no
(yes/no)
68
TABLE 4--Continued
* yes: indicates signal output occurring when the pacemrurer spike interval exceeds the upper limit
interval set by the apparatus.
no:
indicates signal output ~ occurring when the
pacemaker spike interval does not exceed the upper
limit interval.
CHAPTER 4
DISCUSSION AND CONCLUSION
As it has been stated in the introductory chapter,
the construction of the apparatus presented here lias initiated as an attempt to improve on existing designs of
threshold detecting devices.
It is believed that the
voltage window comparator of this instrument is superior
to similar circuits, since it avoids the noted drawbacks
of published designs, e.g., multiple triggering on slow
wave forms (Halas, et al., 1971) or the inability to differentiate between
~wo
events spaced closely together
(Hermann, et al., 1962; Bradley, et al., 1967).
This is
accomplished by using comparators based on operational
amplifiers to drive the Schmitt triggers.
Due to its design, the pulse height analyzer is frequency independent over the frequency range encountered
in electrophysiological work; this feature was not
found in any of the reviei"Ted designs.
The digital processing of the signals makes this
instr~ment
far more accurate than analog frequency
~~d
interval analyzers and permits easy addition of other
signal processing circuits, such as the digital magnitude
69
70
discriminator, which is also believed to be novel in
electrophysiological instrumentation.
The specifications of this apparatus clearly indicate that it is fully capable of performing multiple unit
activity detection and analysis as well as single unit
activity studies.
Biofeedback experiments are another field of use
for this instrument.
For example it could be directly
used in heart rate operant conditioning studies (Schneiderman, et al., 1974).
The study on heart rate determination illustrates
the need for a portable threshold detector in an exercise
program for angina and post myocardial infarction patients
as previously mentioned in the introduction.
As from
Table 3 one can see that heart rate slows rapidly vdth
the cessation of exercise; note that even at time O, post
exercise, marked decreases in heart rate v-rere detected.
Iii th the current method of having patients taking their
own pulse over a period of ten to fifteen seconds just
after exercise, patients can greatly underestimate heart
rates and run into the danger of overexerting themselves
during exercise. A portable threshold detector can instantaneously monitor. heart rate by measuring R toR interval as demonstrated here and immediately signal when
the permissible heart rate is exceeded.
Also, the apparatus proved suitable for monitoring
71
the firing rate of pacemakers.
As stated in the intro-
duction, one of the early signs of impending malfunction
of the pacemrucer generator is a gradual prolongation of
its rate of discharge.
The deterioration of 0.5 beats
per minute (BPH) may be significant, depending over what
time period this change takes place (Bilitch, 1971).
For
the commonly used pacemaker setting at 75 BPM, this represents a change to 74.5 BPM or a change of interspike
interval from 800 msec to 805 msec.
this degree is well
~dthin
To detect change of
the capabilities of the
apparatus.
The machine is presented here as one unit mainly for
the purposes of demonstration.
Many of its parts, or
"building blocks," could be and should be used separately.
For example, the voltage window comparator with the pulse
height analyzer could be used for threshold detection
and amplitude analysis of neural discharges in single and
multiple unit activity studies.
The counter and the di-
gital magnitude discriminator could count bar pressings
or similar events and issue revrards or punishments in behavioral studies.
The d.igi tal magnitude discriminator vii th appropriate
input circuitry could determine if a patient 1 s heart rate
lies within a desired band.
It is assumed that an electrophysiological laboratory would indeed use this apparatus in a modular form,
72
having several of the voltage 1findow discriminators and
stacking them to obtain multilevel windows, also having
several pulse height analyzers, etc.
The pow·er supply
and the clock could be common for all modules.
It must be admitted here that some of the functions
of this apparatus could be better performed v-li th an instrument based on configuration detection.
The techno-
logy is available, but the cost is unfortunately still
prohibitive.
Nevertheless, microprocessors and memory
chips are becoming cheaper and cheaper, and this apparatus could possibly soon be improved upon by a microprocessor based front end, interchangeable v-lith the voltage
window comparator and pulse height analyzer, and capable
of analysis of the configurations of the on-line signals.
The apparatus described in this thesis is a result
of several years of improvements and additions.
It is
believed that it is superior to similar instrtunents both
in performance and simplicity of use.
The frequency in-
dependent pulse height analyzer mruces it unique in that
respect, and the use of only a few controls largely eliminate operator induced errors.
It is therefore anticipated
that this apparatus will prove a useful addition to the
arsenal of tools for the research electrophysiologist
and vdll also find its way into practical clinical
applications.
REFERENCES
1•
Barber, T.X., DiCara, L.V., Kamiya, J., l'Uller, N.E.,
Shapiro, D., Stoyva, J., editors; Biofeedback~
~ Control ~' Aldine-Atherton, Chicago, 1971
2.
Beidler, L.M.; Properties of chemoreceptors of tongue
of rat, J Neurophysiol 16:595-607, 1953
Bili tch, 1·1.; ! Hanual .9.f Cardiac Arrhythmias, Little,
Brown, and Co., Boston, 1971
4.
Bradley, Ttl., Conway, c., Glover, E., HcCormick, S.;
Discriminator and integrator instrument for on line
frequency analysis of single unit discharges,
Electroenceph Olin Neurophysiol 22:177-179, 1967
5.
Brown, K.A., Weber, D.S., Buchwald, J.S.; Chronic
recording and quantification of subcortical single
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Behavior, Phillips, IJl. I., editor, University of Iowa
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6.
Brown, P. B., Haxfield, B.I·J., !Jioraff, H.; Electronics
!£I Neurobiologists, MIT Press, Cambridge, 1973
7.
Brock, N., Diefenth!Uer, K., Zywietz, c., P811, itl.,
Mock, P., Dietz, H.; The application of pressuredistribution frequency analysis to the continuous
monitoring of intracranial pressure, Acta Neurochir
(Wien) 31:299-300, 1975
8.
Bruck, D.B.; Data Conversion Handbook, 1st edition,
Hybrid Systems Corp., 1974
Buchv-Tald, J.S., Holstein, S.B., Weber, D.S.; Multiple
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nigues, Part _!: Cellular Processes ~ Brain Potent~' Thompson, R.F., Patterson, l'1.H. editors,
Academic Press, New York, 201-242, 1973
10.
Billcstein, E.; Introduction!£ Biomedical Electronics,
The Bobbs-?Iervill Co., New York, 1973
11 •
Bures, J., Petran, l1l., Zachar, J.; Electrophysiolog~ f.lethods iU Biological Research, 3rd edition,
Academic Press, New York, 1967
y
IV
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74
12.
Corday, E., Lang, T.W".; Hemodynamic consequences of
cardiac arrhythmias, in The Heart, 3rd edition, Hurst,
J.~v., Logue, R.B., et al:-;-editors, HcGraw-Hill Book
Co., New York, 498-502, 1974
13.
Cromwell, L., 1ifeibel, F.J., Pfeiffer, E.A., Usselman,
L.B.; Biomedical Instrumentation and ~-1easurements,
Prentice-Hall, Inc., Engle·vv-ood Clilis, NelT Jersey,
1973
14.
Datel Systems, Inc., Engineering Product Handbook,
Canton, 1976-77
15.
Forrester, J.S., Diamond, G., Chatterjee, K., Swan,
H.J.C.; Hemodynamic therapy of myocardial infarction
(t"YTO parts), New Engl J Med 295:1356-1362 and 14041413, 1976
16.
Geddes, L.A., Baker, L.E.; PrinciPles of Applied£!£medical Instrumentation, 1iiiley and Son"S;" New York,
1968
17.
Goovaerts, H.G., Ross, H.H., van den Akker, T.J.,
Schneider, H.; A digital QRS detector based on the
principle of contour limiting, IEEE Trans Biomed Eng,
BHE- 23: 154-160 , ___ 1976
18.
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