6A-3
Channel Engineering for High Speed Sub-1.0 V Power Supply
Deep Sub-micron CMOS
TBaohong Cheng, Anand Inani, 'Ramgopal Rao, and Jason C. S. Woo
Department of Electrical Engineering, University of California,Los Angeles, CA 90095-1594
+Currently with APRDL, Motorola, Inc., Austin, TX *Currently with IIT, Bombay, India
Abstract
The effects of channel engineering on the device performance have been extensively investigated. The Lateral
Asymmetric Channel (LAC) MOSFETs show significantly
higher Idsal and gms,,,,lower IoD and superior short-channel
performance compared with Double-Halo (DH) and conventional MOSFETs by effectively utilizing the velocity overshoot effects. It is demonstrated that the device switching
speed of the LAC device at VD~=0.6Vis equivalent to that of
a conventional device operated at V ~ ~ = l . 5 v .
Introduction
Scaling VDD down to sub-1.0 V is the most effective way to
reduce the dynamic power consumption. To maintain high
current drive and gate switching speed at low VDD,low VT is
vital to maximize the gate overdrive. On the other hand low lot
is necessary for small static power [l]. As device dimensions
are scaled down to the 0.1 pm regime, velocity overshoot
becomes extremely important. Device design that exploits
non-equilibrinm transport phenomena is an effective way to
enhance the device performance [2]-[4]. In this work, a Lateral
Asymmetric Channel (LAC) structure is employed to
accelerate the tangential electric field at the source side and
consequently achieve very high carrier velocity. LAC profile
also results in excellent DIBL and S, yielding a low lof
Device Fabrication
Both LAC and conventional SO1 CMOS transistors were
fabricated on the same wafer to eliminate potential variations
arising from processing differences. Bulk CMOS devices
were also fabricated in parallel. The thicknesses of the gate
oxide, SO1 film, and buried oxide are 3.8nm, 50nm, and
180nm,respectively. Electron beam lithography was used to
define the poly fine lines down to 0.08pm. A large angle tilt
implant (LATI) was employed to adjnst the V, for both LAC
and DH MOSFETs after the poly gate formation while the V,
adjushnent of the conventional device was done before the
gate oxidation as shown in Fig. 1. The channel implant
conditions are given in Table 1. All the dopants were activated
by a single RTA anneal at 1020°C for 15s. Low thermal
budget Ge pre-amorphization Ti silicidation process was
employed with a final po of 5 Risq.
Results and Discussion
The carrier transport properties were simulated with an energy balance model for the three channel profiles in Fig. 2. A
much higher electron velocity at the source side in LAC device
has been achieved compared with the DH and conventional
devices (Fig. 3). This high electron velocity is induced by the
tangential electric field and its gradient at the sonrce side in the
LAC device (inset of Fig. 3). This ensures high current drive
at low v,,~
Fig. 4 shows the subthreshold characteristics of the three devices. These fully depleted devices on SO1 all have excellent
S values less than 70mVidecade. The DH device has the highest DIBL due to its low body doping level as confirmed by device simulations. The VT roll-off of the LAC NMOS and
PMOS devices (conventional devices) are less than 60mV
(179mV) and 160mV (325mV) down to L,f 0.08 pm (Fig.
5). The V, roll-off and DIBL are well controlled by the high
doping concentration on the source side in the LAC device,
69
4.93081 3-93-X/99
which acts as a dopant barrier limiting the penetration of Efield from drain-to-source, The asymmetric nature of the LAC
device is clearly seen in Fig. 6 from the experimental VT distributions derived from charge-pumping measurements [5].
Milch smaller DJBL and S of 94mVN and 90mVidecade (158
mViV and 100mVidecade for conventional device) are also
obtained in a 0.1 l p m LAC device on bulk substrate (Fig. 7).
The LAC device therefore has a lower lorWith thinner gate
oxide, both DIBL and S will fnrther improve. The high DIBL
seen in the reverse mode operation of the LAC devices requires some special considerations in circuit design.
The LAC device exhibits 15% higher Idsotcompared with a
conventional device for L e f = 0 . l l p m at 1.5V (Fig. 8). Fig. 9
shows a significant improvement in g,,,, over the conventional case by using the LAC profile for both NMOS and PMOS
on SOL This is attributed to an early velocity overshoot at the
source side in the LAC device. The % improvement in Idsal
(g
),,
dramatically increases as VDDis reduced. The LAC device can he considered as a very short, high-V, MOSFET
(heavier p-region of the halo profile) in series with a 10w-V~
MOSFET (lightly doped region on the drain side). The LAC
device has a Letsimilar to its Lgore when it is off, However,
when it is on and at low VDD, the Leg; determined by the highV,MOSFET, is much shorter compared with DH and conventional devices. The improvement in Idsal
and gmsnt is attributed
to the much higher drift velocity near the source side in the
LAC device.
Using a Figure of Merit (FOM) of Iom/(Cge,exVDD),the device performances of the LAC and conventional devices are
compared experimentally for both hulk and SO1 NMOS at
fixed V , ~ V ~ ~ V ~ V D (Fig.
~ V ~10).
, ,Both LAC bulk and
SO1 MOSFETs achieve the same performance at VDD=0.6V
as their conventional counterparts operated at 1SV. Excellent
short-channel performance also allows the LAC device to
have a low VTwhilemaintaining low loflA comparison of the
device performance of the three structures with VT of 0.1SV
and 0.2SV is made using 2-D device simulations at
V c c V D r V D D (Fig. 11). For the same Vr0.25V, the LA.C
device has much better performance compared with DH and
conventional devices. Scaling V ~ f r o m0.25V to 0.15V further
increases the LAC device performance. In the case of interconnect delay, a FOM of lo,,/VDDgives similar conclusions,
ConcIusi on
The LAC profile significantly improves device Ion and
gate switching speed by effectively utilizing velocity overshoot effects in deep snb-micron MOSFETs. LAC-MOSFETs
have also been shown to exhibit superior short-channel performance and subthreshold characteristics for channel lengths
down to the 0.lpm regime. These devices are highly snitahle
for high speed and low voltageilow power applications.
Acknowledgments
This work was supported by DARPA.
References
[ l ] Z. Chen, et al., IEDM Tech. Dig., p. 63, 1995.
[2] A. Hiroki, et al., lEDM Tech. Dig., p. 439, 1995.
131 B. Chew, et al., SO1 Couf., P. 113. 1998.
[4j J. P. JOG,et al., VLSI Symposium Proc., p. 178, 1996
[ 5 ] M. Tsuchiaki, et al., TED, p. 1768, 1993.
1999 Symposium on VLSI Technology Digest of Technical Papers
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on January 19, 2009 at 23:55 from IEEE Xplore. Restrictions apply.
t t t
\-.,
FOX
FOX
BOX
Conventional
(CON)
Lateral-Asymmetric
Channel
F++GX.
B
o
x
(LAC)
(C)
q+Gx
Double-Halo
B
o
x
(DH)
Fig. 1. Schematic diagrams of VTadjustment.
'ot5-0.1
-0.05
0
0.05
Lateral Position X (pm)
-0.1
0.1
0.1
Lateral Position X (pm)
Fig. 3. DriR velocity averaged over a depth
Fig. 2. Channel impurity profiles at 1.5nm of 50 nm from Si/Si02 interface. The inset
away from SiOz/Si interface. L,aO.lpm.
shows the tangential field (E,) distributions.
1
Table I : NMOS Channel implant conditions
Profile
0.05
0
-0.05
LAC
Implant Conditions
B 12Kev,8~10~~cm~~
BF2: 40 K e v , 4 ~ I O ' ~ c m
tileloo
~~,
BF,: 40 Kev, 3 ~ 1 0 mi2,
~ ' tilblO'
10-6
3
.f 10.8
0.2
0.1
SOI-PMOS
E
I o
c' -0.1
10-10
-0.2
:: -0.2
-0.4
-0.04
0
0.5
0
0.04
H
..............
................
0.6
........
F200
0.2
.....................
(forward)
0
loo
'0
1
0.4 0.6 0.8
1
L,~(lum)
Fig. I . Measured DIBL as a function of Le//
Fig. IO. Figure of Merit (FOM) vs. Power supply
200
100
f
1
0
0
0.5
1.o
1.5
Fig. 8. Measured IDS - VDs characteristics
for the LAC and conventional MOSFETs.
vGl=vGSvZm
(a)
3 300
1
...............
VDS (VI
0.2
0.8
f 400
3
m
i
0.6
LeN(Wm)
500
-
B
0.4
.
t
"a
300
-LAC
0.2
600
Lateral Position X (pm)
Fig. 5. Experimental V, profiles along the
channel as obtained from the Charge Pumping measurements in pre-stress. LerO.1 lpm,
>
0
1
vos (V)
Fig. 4. Subthreshold characteristics for the Fig. 5 . VT roll-off as a function of effective
three devices at VD+O mV and 1.5 V with channel length Lefat V D r 5 0mV.
LefO.l 1 pm.
5 -0.3
$
-1
0.1
0.2
0.3
0.4
0.5
L.N(w)
Fig. 9. Measured g,,,,,, as a function of L,f
t
Fig. 11, Figure of Merit (FOM) YS. power
supply (VDD) for different struchms and V,
VGFVDFVDD
1999 Symposlum on VLSi Technology Dlgest of Technical Papers
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