Drain Bias Dependence of Gate Oxide Reliability in
Conventional and Asymmetrical Channel MOSFETs in the
Low Voltage Regime
Anil K. G. , S. Mahapatra , I. Eisele , V. Ramgopal Rao and J. Vasi
Institute of Physics, Universitaet der Bundeswehr Munich, 85577
Neubiberg, Germany, Fax : ++49-89-60043877.
Department of Electrical Engineering, Indian Institute of Technology
Bombay, Mumbai - 400076, India, Tel : ++91-22-5767456.
Abstract
Drain bias dependence of gate oxide
reliability is investigated on conventional
(CON) and Lateral Asymmetric Channel
(LAC) MOSFETs for low drain voltages
that correspond to the real operating voltages for deep-sub-micron devices. For short
channel devices, the oxide reliability improves drastically as drain bias increases.
Device simulations showed that the vertical
field distribution in the oxide is asymmetric
for non-zero drain biases and this results
in an asymmetric gate current distribution
with the peak at the source end. By introducing an intentionally graded doping profile along the channel (LAC), the asymmetry in the vertical filed distribution can be
enhanced with consequent improvement in
gate oxide reliability.
MOS transistors or gated diodes [2]. For
short channel MOSFETs, the drain bias can
have a significant effect on the gate current by modifying the field in the dielectric at the drain end. Tailoring the electric f i eld by an intentional asymmetric channel doping is reported to improve MOSFET
performance and hot-carrier reliability [3].
There is a lack of understanding of the impacts of drain bias and channel doping profile on oxide reliability. In this work, drain
bias dependence of gate dielectric reliability for operating drain voltages is investigated and reported for conventional channel profile (CON) and asymmetric channel
profile (LAC) transistors for the first time.
It is shown that the reliability improves for
higher drain biases and that the improvement is greatly enhanced for the LAC devices.
1.
2. Experimental
Introduction
Gate oxide reliability studies are conventionally done on MOS capacitors. Area dependence of gate dielectric reliability is well
known [1] and to take this into account reliability studies may have to be done on
MOSFETs. Inversion stress on gate dielectric at room temperature has to be done on
The MOSFETs used in this study had
a minimum channel length of 0.2 m and
gate oxide thickness of 3.6nm. Both CON
and LAC MOSFETs were fabricated on the
same wafer for fair comparison. The fabrication procedure of the devices is described
in detail elsewhere [4]. Fig. 1 shows the
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simulated channel doping profiles of the
CON and LAC MOSFETs used in this study
and reveals the nonuniform channel doping
for the LAC devices. The simulated channel
doping for the LAC devices was confirmed
by Vl profile measurements [4]. Fig. 2
shows the output characteristics of CON and
V
LAC devices of channel length 0.2 m.
3.
Results and Discussions
Fig. 3 shows the simulated transverse
field in the gate oxide where it can be seen
that the oxide f i eld for operating drain voltages can indeed be engineered by a nonuniform channel doping. Fig. 4 shows the gate
current as a function of drain bias for two
channel lengths. For high V , the IŽ is one
order of magnitude lesser for the LAC as
compared to the CON, validating the simulation results. Fig. 5 shows the drain
bias dependence of breakdown voltage of
the gate oxide. V  was measured in inversion with source, drain and substrate tied
to ground. The breakdown voltage increases
with increasing drain bias and for the LAC
devices the increase is more pronounced.
Fig. 6 shows the V  distribution for CON
and LAC devices. The narrow V  distribution proves that the results in Figures 4
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For ultra thin oxides, SILC can be used
as a monitor for trap generation in the oxide [1]. SILC for the CON and LAC devices
stressed at the same gate overdrives and two
different drain biases as a function of stress
time are shown in Fig. 7. Whereas the LAC
and CON devices showed nearly identical
SILC for zero drain bias, it is reduced by
a factor more than 3 for CON and more than
6 for LAC stressed at Vg = 0.75V implying
reduced trap generation for LAC devices.
Stress time evolution of charge pumping
¾8¿
(CP) current (I ) was studied for stress at
VÇ =0 and 0.75V. The CP was done from
the source side with the drain floating and
from the drain side with the source floating to investigate the asymmetric nature of
¾8¿
stress [5]. The normalised values of I
are plotted in Fig. 8. For CON, the interface state build up at the source and drain
ends are nearly identical for VÇ =0V. For
LAC, the drain side shows higher degradation for VÇ =0 due to higher oxide f i eld re-
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and LAC devices. The narrower distributions than the factor of improvement shown
in Fig. 9 prove that these results are not
artefacts of statistical distribution of t] \ of
the oxide.
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4. Conclusions
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Acknowledgment
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A detailed study of oxide reliability of
gate oxide on CONventional (CON) and
Lateral Asymmetric Channel (LAC) MOSFETs were undertaken. It has been shown
that gate oxide reliability improves for short
channel devices with the application of a
drain bias, representative of the real operating voltage of the devices. Channel engineering that introduces a graded doping
along the channel with the peak at the source
end improves the reliability by virtue of the
reduced transverse eld in the gate oxide.
These results suggest a possible relaxation
of oxide reliability specifications for deep
sub-micron devices.
: .W8
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sulting from the lower V[ near the drain.
For both CON and LAC, for V\ =0.75V, the
interface state build up is more at the source
end than at the drain end and are explained
by the simulation results shown in Fig. 3.
Fig.
9 shows the normalised timeto-breakdown (t] \ ), considering softbreakdown, versus V\ plots for CON and
LAC devices. For the 0.25 ^ m device, as
V\ increased to 1V, t] \ improved by a
factor of 40 for CON and 100 for LAC. Fig.
10 shows the Weibull plot of t] \ for CON
The samples used in this study were provided by Prof. J. C. S. Woo of UCLA, USA.
Anil K. G. also acknowledges Siemens AG,
Germany for providing a research fellowship.
[1] G. Groeseneken et al., in Proc. ESSDERC,
1999, p. 72.
[2] E. Rosenbaum et al., IEEE Trans. Elec.
Dev., vol. 43, p. 70, 1996.
[3] R. Rao et al., in IEDM Tech. Dig., 1997, p.
811.
[4] B. Cheng et al., in Proc. VLSI Tech. Symp.,
1999.
[5] S. Mahapatra et al., Solid State Electronics,
vol. 43, p. 915, 1999.
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