Application of Look-up Table Approach to High-K Gate Dielectric MOS
Transistor circuits
D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, and V. Ramgopal Rao
Department of Electrical Engineering
Indian Institute of Technology-Bombay
Mumbai-400 076, India
[email protected]
Abstract
In this paper, we study the circuit performance issues of
high-K gate dielectric MOSFETs using the Look-up Table
(LUT) approach. The LUT approach is implemented in a
public-domain circuit simulator SEQUEL. We observed an
excellent match between LUT simulator and mixed mode
simulations using MEDICI. This work clearly demonstrates
the predictive power of the new simulator, as it enables
evaluation of circuits directly from device simulation results
without going through model parameter extraction.
1. Introduction
Development of physics based circuit models for deep
sub-micron MOSFETs is becoming increasingly difficult as
the device dimensions are scaled down. Earlier, it had been
possible to obtain compact models with a small number of
fitting parameters for circuit simulation by understanding
the physical phenomena in the devices. This is no longer
practical as the device dimensions enter the sub 100 nm
regime, since these devices have very complex structures
and doping profiles. To model the small geometry devices
accurately, one has to perform multidimensional analysis,
which always results in very complicated model expressions with many empirical parameters. Further, it is generally difficult to extract such a large number of parameters accurately from experimental data, and parameters extracted often produce parameters which are physically inconsistent. Because of the above difficulties with analytic
models, the look-up table (LUT) approach is being considered as an attractive alternative for circuit simulation [1, 2].
In this approach the terminal currents and charges are used
as Look-up table. A suitable interpolation scheme is used
to evaluate the current or charge at any point that does not
coincide with a table point. In this paper, we will describe
the application of the LUT approach to study the circuit performance of the high-K gate dielectric MOSFETs.
2. Look-up Table Method
In the LUT approach, our aim is to approximate the behaviour of a given device using finite number of table points
with a suitable interpolation algorithm. The table points
can be obtained from measurements, device simulations,
or from existing physical models. In semiconductor device
models, the controlling variables of the device are its terminal voltages and the dependent physical quantities are its
terminal currents and charges. The objective is to approximate this dependent physical quantity using an interpolation scheme. It is assumed that the device operates in quasistatic regime [5], i.e., the terminal currents and charges depend only on the instantaneous values of the terminal voltages. As we shall see in Section 4, this assumption is a
realistic one in many practical situations with sub-micron
gate lengths.
3. Extraction of Look-up Table from device
simulations
For MOSFETs, the terminal currents can be expressed as
Ix (t) = IX (VBS (t), VGS (t), VDS (t))
dQX (VBS (t), VGS (t), VDS (t))
+
dt
(1)
where X can be gate, drain, source, or substrate. IX is the
DC current that would result if the bias voltages were to
be held constant at their instantaneous values. Similarly,
QX is the terminal charge corresponding to the instantaneous values of the bias voltages. Note that, Eq. 1 does not
explicitly include the “past history” of the device; in other
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0
Vbs=0.0
Vbs=−1.0
−1
Vbs=−2.0
id(t) ( µA/µm)
−0.5
L = 2 µm
−1.5
−2
Vds = 1.0 V
−2.5
−3
−3.5
0
2
4
6
Time (nsec)
8
10
Figure 1. Transient drain current id (t) as obtained by simulating a NMOS transistor of
gate length 2 µm. The gate voltage VG was
made to vary linearly from -2 V at 0 nsec to 5
V at 10 nsec for Vbs = 0 V, -1 V and -2 V, keeping
Vds = 1.0 V.
Coul/ µm)
4
0
Vds = 1.0 V
−15
−4
Q d (10
words all NQS effects are ignored. In the LUT method, the
MOSFET is modeled as a table of DC currents ID , IG , IB
and terminal charges QB , QG , QD for the desired range of
bias voltages, and the terminal currents are computed using
Eq. 1 using a suitable interpolation scheme. The tables can
be generated by experimental measurements or device simulation; as no approximations are made in generating the
tables, the LUT model represents an “exact” QS model.
The current IX in Eq. 1 can be obtained by DC simulation for the required range of bias voltages. The charge
denoted by QX in Eq. 1 is much more subtle. It is not
simply the terminal charge obtained with device simulator.
To appreciate this point, consider particularly the bulk (or
“body”) terminal of a MOS transistor. The device simulator
will always produce a negligible value of QB since the electric field in the neutral region near
the bulk contact is very
small, producing a small QB = E ·dS. So, the use of QB
computed by DC simulation for LUT quasi-static model,
will always predict a vanishingly small Ib (t), irrespective of
bias voltages. This prediction is obviously incorrect: particularly when an applied voltage ramp takes the device from
accumulation to inversion, a significant bulk current must
flow. In order to extract the terminal charges accurately
from device simulations, we have used the terminal charge
extraction technique using transient simulations described
in [3]. For generating the current and charge look-up tables
for the examples discussed in this Section, we have used the
ISE-TCAD [6] package. In extracting the terminal charges
a gate ramp (from a low voltage to high voltage) with an
appropriate rise time τr was applied; τr was chosen to be
much larger than the transit time, thus ensuring that the device remains in the QS regime. It is instructive to look at an
example of the terminal charge extraction. Fig. 1 shows the
drain terminal transient current obtained using ISE-TCAD,
and the corresponding terminal charge extracted from the
transient current is shown in Fig. 2. In these simulations, a
gate ramp going from -2 V to 5 V was applied, with τr =10
nsec, and the simulated device had gate length of L= 2 µm.
Having computed the terminal currents and charges for
the device concerned at the “table points”, the next step is
now to implement the look-up table approach in a circuit
simulator. For this purpose, the SEQUEL circuit simulation program [7] was used, as it allows new device models to be easily incorporated. Interpolation between table
points (“grid points”) was carried out using the techniques
described in [1]. In the following, we will refer to this implementation simply as the LUT model.
The LUT model, as constructed using the above procedure, was validated by detailed comparison with device
simulation results. Gate and drain voltage pulses with various values of rise and fall times were applied to the device
for this purpose and it was verified that all transient currents
obtained with ISE-TCAD and the LUT model matched per-
Vbs=0.0
Vbs=−1.0
Vbs=−2.0
L=2 µ m
−8
−12
−16
−2
−1
0
1
2
3
Gate Voltage (V)
4
5
Figure 2. Terminal drain charge QD as a function of VG extracted from id (t) of Fig. 1.
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fectly. The rise and fall times of the applied VG and VD
pulses were chosen such that the device remained in the QS
regime.
It is well known that, as the gate length L is scaled down,
the oxide thickness must also be reduced in order to suppress the short-channel effects. For example, for L=50
nm, the oxide thickness needs to be as small as 0.8 nm
[8]. With such a thin gate oxide, direct tunneling occurs,
which will increase the power dissipation and will deteriorate the device performance and circuit stability [8, 9].
The use of high dielectric constant (“high-K”) gate insulators has been proposed [4] to alleviate the gate leakage
problem in sub 100 nm MOS transistors. With a high-K
dielectric replacing the oxide, one can increase the insulator thickness by a factor of KKox and still obtain the desired
gate capacitance. However, as studied recently, the device
performance is known to degrade considerably due to the
gate fringing fields, when a high-K dielectric material is
employed [10, 11]. Although, the device performance with
high-K gate dielectrics has been studied in detail [11], evaluation of circuit performance has not received much attention. This is due to the fact that accurate analytical models
for high-K transistors are not yet developed which take into
account the fringing field effects. The LUT model, on the
other hand, does not require analytical device models and is
therefore ideally suited for prediction of circuit performance
with high-K transistors. For the LUT model, the device
characteristics of the MOS transistors with different highK gate dielectrics were extracted using two-dimensional
device simulator MEDICI [12]. The simulated structures,
which are based on scaled device dimensions outlined in
the SIA road-map, have a gate length down to 70 nm and
oxide thickness of 1.5 nm. A spacer technology with heavily doped source/drain extensions is used. The source/drain
extension and deep source/drain junction depths are 30 nm
and 50 nm respectively. The permittivity of the gate dielectric (K) is varied from 3.9 to 100 keeping the “effective”
gate dielectric thickness constant at 1.5 nm. A calibrated
energy balance model is incorporated to consider the spatial variation of carrier energy in order to account for the
velocity overshoot and non-local transport phenomena. The
Fermi-Dirac statistics is used for the active carrier density
within the simulation structures.
Before applying the LUT approach to the high-K transistor circuits of interest, the LUT model was validated using
the mixed-mode capability of MEDICI [12]. In particular,
a CMOS inverter was simulated using both MEDICI and
the LUT model with an input pulse (τr =τf =10 psec). The
results are shown in Fig. 3, and an excellent match can
LUT
MEDICI
0.6
Vout (V)
4. Application to High-K Gate Dielectric MOS
Transistor Circuits
0.8
L = 70 nm
(W) n= 0.7 µ m
(W) p = 2.1 µ m
0.4
0.2
Tox =1.5 nm
0
0
0.2
0.4
Time (nsec)
0.6
Figure 3. CMOS Inverter (L= 70 nm and width
of PMOS and NMOS devices are 2.1 µm and
0.7 µm) with load capacitance of 10 ff, transient characteristics as obtained from MEDICI
and LUT. The rise and fall time of the applied
input pulse is 10 psec.
be clearly seen between the MEDICI and LUT results. This
shows that, for τr and τf as small as 10 psec, the LUT model
accurately predicts the circuit performance. One of the important parameters to be considered in the CMOS circuit
design is the propagation delay tp of the gate, as it defines
how quickly the gate responds to a change in the input and
relates directly to the speed and performance metrics. The
ring oscillator is the standard circuit for delay measurement.
The propagation delay tp can be obtained by measuring the
time period (T) of oscillations and by using the formula
T = 2tp N , where N is the number of inverters in the chain.
We have simulated a 25-stage ring oscillator to measure the
average inverter delay with different high-K gate dielectrics.
Fig. 4 shows the inverter delay as a function of K. With
increase in K, the parasitic capacitance decreases due to
higher physical gate dielectric thickness (lines of forces has
to travel more distance to reach source/drain regions from
gate electrode) [13]. Thus, the frequency of oscillations increases with increase in K value (see Fig. 5). Static-power
dissipation is another important issue in circuit design. This
is due to the leakage currents in the device. It is well established in the literature that the short channel performance
degrades with increase in K value which results in higher
sub-threshold currents. To study the effect of sub-threshold
leakage currents on the circuit performance, we have simulated dynamic gates. The operation of the dynamic gates
relies on the dynamic storage of the output value of the capacitor. In the precharge phase (when φ=0) the output node
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0.9
11
0.85
Delay (pico sec)
10.5
(W) p
(W) n
10
Vout (V)
= 1.5 nm
tox,eq
L = 70 nm
= 3.0
9.5
0.8
0.75
(W) p = 2.1 µ m
L = 70 nm
(W) n = 2.1 µ m
= 1. 5 nm
Tox,eq
9
0.7
8.5
8
0
20
40
60
80
Figure 4. Average inverter delay obtained by
simulating a 25 stage ring oscillator for different values of K.
K=100
0
20
40
Time (nsec)
60
100
K
Figure 6. Output voltage of a 2-input dynamic
NAND gate with time for different high-K gate
dielectrics.
is charged to Vdd and in the evaluation phase (when φ=1)
the output voltage is determined by the combination of inputs. Initially we precharged the output voltage of the 2input dynamic NAND gate to Vdd and then kept the gate in
evaluation phase for a long time with both inputs grounded.
Ideally the output voltage should remain at logic 1. But due
to leakage currents, this charge gradually leaks away resulting eventually in malfunctioning of the gate. As can be seen
from the figure 6, with increase in the value of K, this problem becomes more severe. It can also be observed that in
dynamic NOR gates this problem is more enhanced due to
the parallel combination of the evaluation transistor (Fig.
7).
K=3.9
0.8
0.6
Vout (V)
K=3.9
K=20
K=30
K=60
K=100
0.4
0.2
0
0
1
2
Time (nsec)
3
Figure 5. Output waveform of a 25-stage ring
oscillator made-up of MOS transistors with
gate dielectrics K=3.9 and K=100, obtained
by LUT simulator.
We have also simulated a domino logic gate with different high-K gate dielectric materials. The circuit shown
in Fig.8 consists of a φ block followed by a static inverter.
This ensures that all inputs to the next logic block are set
to zero after the precharge period. Due to the sub-threshold
leakage currents during evaluation period, V1 starts to fall
(discharges) even though Vin (N1 is off) is held at logic
0 and this discharging is faster for a circuit where high-K
dielectric is employed as a gate material. Thus, when V1
reaches below the threshold voltage of the static inverter, its
output (V2 ) goes to logic 1. This results in Vout being discharged to logic 0, which is not the correct state. Now with
a higher K material, this state is reached faster due to the
higher leakage currents (Fig. 9).
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0.8
0.6
K=20
Vout (V)
K=30
K=60
K=100
0.4
n
0.4
K=3.9
K=30
0.2
K=60
K=100
0
(W) p = 2.1 µ m
0.2
L = 70 nm
= 1.5 nm
Tox,eq
(W) n = 1.4 µ m
0
0
20
40
Vdd=0.8
P2
V1
Vin
Ps
N1
Vout
N3
Cout=0.01 pF
Ns
N2
φ V
2
20
40
Time (nsec)
60
Figure 9. Output voltage of a domino logic
gate of Fig. 8 with time for different high-K
gate dielectrics.
Figure 7. Output voltage of a 2-input dynamic
NOR gate with time for different high-K gate
dielectrics.
P1
0
60
Time (nsec)
φ
Vout (V)
K=3.9
0.8
0.6
L = 70 nm
= 1.5 nm
Tox,eq
(W) p= 1.8 µ m
(W) = 0.6 µm
5. Conclusions
A Look-up table based circuit simulator has been presented in this work. We also presented the simulation of circuits with high-K gate dielectric MOSFETs and analyzed
the performance of the circuits in terms of delay and leakage currents. It is observed that with increasing value of
gate dielectric constant the speed of operation of devices increases but at the same time the sub-threshold performance
degrades leading to higher leakage current and malfunctioning of dynamic circuits. The LUT simulator is therefore
an attractive alternative for circuit simulations employing
novel technologies, where analytical model development is
often complicated and time consuming.
Financial support from Intel Corp. and DST is gratefully
acknowledged.
N4
Figure 8. Circuit schematic of a Domino logic
gate.
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