Analysis of Breakdown Voltage and On Resistance of Super-junction Power
MOSFET CoolMOSTMUsing Theory of Novel Voltage Sustaining Layer
P. N. Kondekar, Student Member ZEEE, C.D. Parikh, Member ZEEE and M. B. Patil, Member ZEEE
Microelectronics Group, Department of Electrical Engineering, Indian Institute of Technology, Bombay
relationship and have SJ-MOSFET with at least 5 to 100
Abstmct-Conventional
VDMOS (Vertically Double
diffused Metal Oxide Semiconductor) Technology for power
times lower R,,,, as compared with VDMOST.
devices was constrained by the Silicon Limit. This is now
improved to have linear relation between On Resistance (L)
Source
Gate
Source
and Breakdown voltage (BV) instead of the quadratic
I
relation. Theory of novel voltage sustaining layers (SJI
\L....J
n+
Theory) recently published analytically models the super
P+ /
junction drift layers (SJ-drift layer). We have designed SJlayers based on this theory and used to construct the SJMOSFET: CoolMOS structure. The claim of the theory that
Pn-epi
the doping level in the drift layer can now be increased by at
least one order of magnitude without lowering BV is analyzed
in detail. With the new silicon l i t we now can increase BV
of a power device, just by increasing thickness of the SJ-drift
n+
layer. L and BV relationship as the thickness of the device
I
Drain
varies is analyzed with the help of simulation. The limitations
and constraints of applying SJ-theory for the CoolMOS
structure are discussed. The SJ-theory does not model the
Fig. 1 Cross-section of the SJ-MOSFET (CoolMOS)
,, and BV for a fixed geometry as doping level
behavior of R
changes. We observed that for a fixed geometry the rate of
It.
VDMOSDRIFT LAYERVS SJ -LAYER
reduction of the BV depends on the cell pitch. This rate is
large for the higher cell pitch. The effect of charge imbalance
created due the channel region in CoolMOS is also
The drift layer of conventional VDMOS (Vertically
investigated.
Double-diffused Metal Oxide Semiconductor) power device
can be modified to SJ-drift layer keeping its geometry and
Index &"-Super-junction
devices, CoolMOS, Geometry
doping levels same to obtain almost double breakdown
factor, On resistance, Breakdown voltage, Charge imbalance
voltage (BV). Further increase in the BV can be achieved
by simply increasing the thickness of the drift layer fepi.
I.
INTRODUCTION
This increases on resistance (&), since the drift layer is
divided in p and n pillar as shown in the Fig.2
Super-junction (SJ) MOSFET (also called as
c
CoolMOSq is attracting lot of attention. This concept
E3 18
pushed the power MOSFETs utility in higher Breakdown
!- 8 3 l B P'
Voltage (BV) and high wattage (Lower on state resistance
R.) applications by breaking the so-called Silicon Limit [
i
R.= BV *"I [l]
Y
Now a large P-N junction (Vertical) builds the electrical
field in both horizontal and vertical direction as the drain
bias is provided. P-pillar does not contribute toward onstate conduction but essential for achieving higher BV
despite higher doping of N and P regions.
In the off state the N and P pillars will be completely
depleted well before BV, reducing the charge inside the
depletion region. The electric field profile becomes flat,
instead of triangular as in conventional VDMOST. [ l ] [2]
This makes it possible to have [R. = BV] linear
0-7803-7262-X/02/$10.00
0 2002 IEEE.
7314
?si4
P
?U14
w
I-
L
c
Fig.2 V D M 0 S - M layer (a) Modifiedto SJ&
1769
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 4, 2008 at 01:47 from IEEE Xplore. Restrictions apply.
layer (b)
With doping level of SJ-drift layer increased by one
order of magnitude, the simulation result shows that at
least 5 times improvement in %., without losing much
advantage of increased BV. This is justified analytically
with help of theory of novel voltage sustaining layer [l] or
Super-Junction Theory (SJ-Theory).
Design and simulation of the conventional drift layer is
given in Table I for BV 390V, 200 W, 10 A VDMOS
power device. This can be shown as p+ n- n+ diode for off
state of the device, as in Fig.2 (a). Maximum doping
required in conventional drift layer is given by [2] [3]
E
TABLEI
DFSIGN
(
VDMOSDIU T LAYER
&xA
E,
Vlcm
2 . 8 ~ 1 0 0.0196
~
390
Simul.
375
The %, will be approximately 2 SZ for a 10 cm width of
the drift layer since the cross sectional area will be lo-*
cm'. The major contribution (>95%) to %, of high BV
devices comes from n-drift layer [2]. %, is defined at low
drain voltage V,,=lV and high gate voltage V,=lOV, so
that JFET effect resistance and channel resistance will be
minimum. The electric field along the drift layer is shown
in Fig. 3. Conventional triangular electric field profile was
the main reason for the so-called silicon limit (%a = BV2.5)
[4] [5]. Thus high BV power MOSFETs were not suitable
to use in actual applications due to high %,.
Here a P-pillar is inserted in the drift layer forming a
vertical p-n junction, which builds the electric field in both
vertical as well as horizontal direction. The P-pillar does
not take part in conduction when the device is ON, but is
necessary in order to increase BV of the device when
device is OFF.Due to full depletion of the SJ-layer at much
lower drain voltage than the BV, it will behave similar to a
very lightly doped drift layer. Simulation result of SJ-drift
layer with same geometry and doping profile shows that
BV of SJ-MOSFET will be 560V as against 390V for
VDMOS power device.
Here R,, almost doubled due to SJ-structure. Almost 3f I
2 times increase in the doping level without reducing the
BV of the device as compared to conventional drift layer is
possible using concept of SJ-layer. Here f is Geometry
factor as defined in [13. One order increase of magnitude
will result in almost 5 times improvement in the %, as
shown analytically. The simulation of SJ-drift layer with
same geometry but increased doping by one order shows
that BV remains almost same as 560V. %, will be only 0.4
52 (using equation 6 in next section) as against 2 SZ in this
case. The electric field profile and potential contours at
high voltage near breakdown are shown in Fig. 4 and 5
respectively.
0
I
3.5&,
Electrical Field in the VDMOS
Drift Layer for 3 7 9
2e5
-25.5
'
o
I
I
I
5
io
ij
3
25
30
Vertical Distqnce in the Drifr-laycr in microns
Fig.4 Electric field profile in SJ-Driftlayer
along the line shown in the fig.2 (b)
Fig. 3 Electric field along the line shown in fig.2 (a)
Concept of SJ-layer.
Keeping geometry and doping profile same the n-drift
layer of VDMOS is now modified to SJ-layer as shown in
Fig. 2 (b)
We can see that the electric field profile becomes flat
once the charge inside the drift layer reduces due to
depletion region across vertical p-n junction. Since the
width of p and n pillars are very small as compared with
height, the horizontal depletion takes place at lower drain
voltage. Once the drift layer is fully depleted, the field
increases vertically predominantly as drain voltage
increases till it reaches E, (Critical Electric Field) where
impact ionization is triggered. The potential contours and
uniformly distributed throughout the drift layer suggesting
flat electrical field profile. The intensity of contours
reduces as the drain bias increases in Fig. 5
1770
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 4, 2008 at 01:47 from IEEE Xplore. Restrictions apply.
Theoretically, one can predict 50% improvement in BV
assuming ideally flat electric field profile. Simulation result
shows 45% increase in BV. Unfortunately, since the drift
layer is now divided equally in P and N pillars , the &
will be doubled as compared to VDMOS. The simulation of
SJ-drift layer with same geometry but increased doping by
oneorder shows that BV remains almost same as 560 V,
thereby reducing the k,by at least a factor of 5.
pillar (kpi)one can change BV of the device. This is also
observed with simulation. From the boundary condition
used we can find the thickness of the drift layer required as
Then from the initially assumed value off we can find
out the cell pitch from equation 2. The maximum doping
level required for this is given by
Here, for same bpi in VDMOS and SJ drift layers, to
obtain the same E,, we can find ratio Ns,I N,, =3f 12. Thus
the doping in SJ-layer is higher than the conventional and
depends on the geometry of the device. Thus for f =O. 1, N,,
= 15 NCO,for f = 0.2, Nsj= 7.5 N,, and for f =0.3, we get
N, = 5 Nm. Practically the value of E, itself is very high
in SJ-layer as compared to conventional [4]. The value of
Area Specific On Resistance &A in terms of the geometry
and BV is given by
R o d = 2 . 6 ~ 1 0 - ~BVacm'
C,
We have tabulated the design for different BV using
three geometry factors as follows.
Fig. 5 Uniformly disbtibutedPotential Contours
in the SJ-Driftlayer near breakdown
HI.
(6)
TABLE II
DESIGN
AND SIMULATION OF SJ-DRIFT
LAYER
Theory of a novel voltage-sustaining layer [l] gives
analytical modeling of the SJ-drift layer. A simple design
methodology can be formulated on the basis of this theory.
Here the SJ-drift layer having P and N pillars with uniform
doping is modeled as unitary function. Two-dimensional
Poisson's equation with boundary conditions for the full
depletion of S l a y e r is solved.
The y-component of the electric field is important from
design point of view. Geometry Factor ( f ) is defined as
ratio of cell pitch to the thickness of drift layer and can be
approximated as in equation 2 if hpil2% >1
700
900
5 . 5 4 ~ 1 0 ' ~3 . 4 ~ 1 0 ~40.75
3 . 9 6 ~ 1 0 ' ~ 3 . 2 ~ 1 0 ~54.63
67.16
122.77
pm
6.23
8.09
11.9
16.1
dcm
TABLEIII
Volt
400
500
700
900
tcm3
v/cm
pm
4 . 9 1 ~ 1 0 ' ~ 3 . 4 ~ 1 0 ~23.14
3 . 6 5 ~ 1 0 ' ~ 3 . 3 ~ 1 0 ~30.02
2 . 3 3 ~ 1 0 ' ~ 3 . 1 ~ 1 0 ~44.45
1 . 6 6 ~ 1 0 ' ~ 3 . 0 ~ 1 0 ~59.59
2
45.51
77.75
174.3
318.66
TABLE.IV
The critical electric field in the layer is given by
Ec=1.24x106BV" (1+21.7f)-1/6
5.49
7.36
Forfi0.3
BV
Volt
(3)
Thus we can calculate E, for required BV by assuming
$ It can be observed that critical field E, for the device
depends on the BV and geometry. If Wn=Wpis kept fixed
i.e. if cell pitch is constant then by changing the height of
N
/cm3
E,
VIm
24.49
31.77
I
9.90
12.8
I
1771
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 4, 2008 at 01:47 from IEEE Xplore. Restrictions apply.
I
I
80.95
138.30
I
I
Simulation
These drift layers were simulated using ISE-TCAD [7]
and compared with analytical plot as shown in Fig. 6.
Since SJ-theory gives different maximum N for different
dimensions, a first order comparison is possible, we can see
that for the 6 0 . 1 the simulated BV are quite close to
analytical but for as f increases the simulated BVs are
smaller than the analytical. This is because if t.pi I 2%
approach unity, the critical electrical field in the device
given by equation 3 will be smaller. Physically this means
that the charges from the top and bottom comers near
junctions contribute to vertical field before complete
depletion of the drift layer forming P+N-N+ type of field.
This reduces the BV of the device. Thus we see larger
departure of BV from analytical as the cross sectional area
of the SJ-drift layer increases. For smaller f the doping
level are higher for same BV, suggesting lower R,,,.
I
l i
DBUT LAYER
P.PULAB
&lb
D E A N CQNlACI
Fig.7 The cross-sectionof the CoolMOS used for simulation.
AU dimensions are in microns
600
9 400
c
.
f-i
bpi
lun
20
30
1
40
,
.
I
50
60
-
2.O~lo'~ 4 . 0 ~ 1 0 ' ~ 6 . 0 ~ 1 0 ' ~ 8 . 0 ~ 1 0 ' ~ 1.0~10'~
Doping Concentration/cm3
Fig. 6 Analytical and Simulated BV of SElayers
IV.
SJ-LAYER USED FOR SJ-MOSFET
The SJ-layer designed is used to simulate the CoolMOS
structure as shown in Fig.7 using ISE- TCAD. We have
simulated the structure with C, = 5pm. In the figure, it is
shown that keeping the cell-pitch constant, we vary the
thickness of the drift layer in order to study the BV and
f
0.18
0.12
0.09
0.07
0.06
BVVol.
A
S
356 330
527 475
693 610
857 740
1017 880
R,, mSZcm2
A
S
3.09 4.29
4.53
6.25
5.95
8.35
7.36 10.22
8.78 12.15
N
/cm3
6.31~10'~
6.22~10'~
6.15~10'~
6.08~10'~
6.01~10'~
From the plots shown in Fig. 8 we can see that the
electric field profile gets stretched as bpiincreases (Keeping
doping level same), indicating proportional increase in BV
Thus we can conclude BV = tepi
along the vertical left.
edge of the device
Ron.
The operation of the CooMOS is same as VDMOS.
When the device is ON the conducting channel is farmed
in the P-body and electrons flow toward drain vertically
down toward the drain. The threshold voltage calculation is
same as the VDMOS [3] and is about 3.5 V. The simulated
&.V, characteristics show it as approximately 3.3 V. The
BV of this device as LPi increases (keeping doping level
fixed and cell pitch constant) is simulated and studied here.
The analytical calculation based on SJ-theory for the same
are shown in Table V.
0
10
20
30
40
50
SJ-layer height in ym
60
Fig 8 Electrical field profiles as thickness of drift layer increases
1772
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 4, 2008 at 01:47 from IEEE Xplore. Restrictions apply.
From the plot as shown in Fig 9 simulated %, is quite
high as compared to analytical prediction by SJ-Theory.
This is expected because SJ-Theory neglects the depletion
width at drain voltage of 1V and channel resistance and
JEFET resistance. %, is defined as the slope of the Id-Vd
curve in the linear region i.e. when Vds = 1V and V, =10
V. We can clearly observe the new silicon limit here i.e.
%, = BV instead of conventional %,a BV2.5
.
.
--
simulated for N=6e15
g 0.20
0
.E 0.18
400
Simulation Results
For a fixed cell-pitch q = 5 pm and t.pi =40 pm, is
observed that, as the doping Nuis increased from
l ~ l O ' ~6t 0
~lO'~,%,drops
rapidlyas shown in Fig.11.
.
--Analytical
c
N-drift layer simultaneously. Here, we have defined
Nno-d as the same level of doping i.e. INI=IPI=Nno~~.
We
have simulated CoolMOS structures for three different cell
pitch and the electrical field profile along the vertical left
edge of SJ-MOSFET as doping level (Nno-d ) increases
are studied.
800
600
Breakdown Voltage (Volts)
Fig. 9 & resistance Vs BreakdownVoltage
&-V,characteristicsin the linear region are shown in Fig
10. The 4-V, curve shows that the threshold voltage is as
calculated 3.2V and does not get affected by increasing the
thickness of the SJ-layer. The saturation drain current is
high in case of the 20pm device, since %,,is very low.
2
1
2
3
3c 4 . 0 ~ 1 0
4
5
.-m
I3 2.0x10'
0.0
L
0
1
2
3
Gate Voltage Vds in Volts
Fig. 10 IaV, in the linear region as t
V.
Fig. 11 The plot of N vs. BV and &for
a fixed geometry SJ-MOSFET
Since the depletion width of the junction is proportional
to N-"', it will be more at lower doping level; this reduces
the cross-sectional area of the conducting channel
increasing &. As the doping increases, depletion width of
the junction reduces, causing available cross section area to
be more. %, rapidly drops to lowest possible value at
highest doping level. We can see BV reduces almost
linearly for this case.
c 1.OX10-5- Vds=l Volt
.-
Doping Concentrationin Icm'
i
4
5
increases
DOPING
LEVELVARIATION
FOR A FIXED
GEOMETRY
The theory of novel voltage sustaining layer [ 11 does not
provide insight into the variation of Breakdown Voltage
and L, if the geometry of the device is fixed and the
doping level is varied in the SJ-drift layer i.e. P-pillar and
We have observed that area under the electrical field
curve (BV) reduces at faster rate in higher cell pitch. We
have given these plots of electrical field along the left
vertical edge of the device, here in Fig 12 (a), (b) and (c),
Where we see that as the cell pitch becomes smaller the
rate of reduction of the area under the curve i.e. BV
reduction becomes negligible with increasing Nno-d. This
observation also helps in designing the device geometry for
optimum breakdown voltage.
The rate of reduction of BV with Nno-d depends on cellpitch. For larger cell-pitch with higher doping the amount
of charge from the drift layer contributing to vertical field
1773
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 4, 2008 at 01:47 from IEEE Xplore. Restrictions apply.
component will be large and this causes to trigger impact
ionization process at lower drain voltage. Thus, we have to
use lower doping in order to get higher BV for large cellpitch; this is not suitable to obtain lowest possible &,.
Only Cp=5 pm and Cp=lO pm will be suitable for device
design. Simulation results for the rate of reduction of BV as
Nn-d increases by one order are shown in Fig. 13
L
1
h
3.0~101
E 2.5x10'
Y
2.0X10'-
a
E
1.5~10'-
m0
.-
z
1.0X10'-
0
a,
iij 5 . 0 ~ 1 0 ~ -
t
Fig. 13 Simulated BV as the doping level
changes by one order for different C,
0.0
0
10
20
30
Vertical Distance in SJ-layer km
40
VI.
STATIC
CHARGE
The SJ-theory assumes perfect charge balance [6]
between the P-pillar and N-drift layer as in perfect
symmetrical SJ-drift layer in Fig.2 (b) for obtaining
maximum BV.
The neck region (top of the N-drift layer) of CooMOS
creates charge imbalance due to which, N-drift layer
charge is larger than the P-pillar. This affects the net
obtainable maximum BV at a specified doping N. The
charge imbalance due to top neck region can be estimated
for the CoolMOS. One of the reasons for lower BV in
simulation is the charge imbalance. To improve BV there
are two ways, one is to reduce the doping level in both Ppillar and N-drift layer, which will reduce BV sensitivity
and thereby increase BV. This will increase the &,which
is not desirable. Another way is to reduce charge
imbalance by increasing P-pillar doping only to get
maximum BV.
N=le14
5
50x10
0.0
10
0
20
30
40
Vertical Distance in SJ-layer in pm
Fig. 12 (b)
= I
E
The ideal SJ-drift layer as shown in Fig 2(a) gets
modified in the actual CoolMOS structure as shown in Fig.
7. Charge imbalance is created due to channel region. The
ideal symmetrical SJ-drift layer of 40pm thickness and
Cp=5 pm is simulated and a CoolMOS structure using this
drift layer is also simulated with channel length of 1.8 pm
and junction depth of p-body 3 pm. The compensation
degree is defined in this case as CD % = (N-P)/
N,,-d*lOO.
The doping level of the P-pillar and N-pillar
is varied and off-state breakdown voltage is observed as
shown in Fig. 14.
P 2.0x10
.-
1.5~10
I
C,=5 pm
tea=40km
5.0~10
0.0
J
1
0
10
20
30
40
Vertical Distance in SJ-layer in pm
(C)
Fig. 12 a, b, c Electrical field profile along the left edge
of SJ-MOSFET for various cell pitch
1774
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 4, 2008 at 01:47 from IEEE Xplore. Restrictions apply.
An increase in the P-pillar doping corresponds to a
negative value of CD and that in the N-pillar doping to a
positive value of CD. The SJ-drift layer due its perfect
symmetry as shown in Fig.2 @) gives maximum obtainable
BV at N=P i.e. CD = 0%. Increase in doping level on either
side will reduce the BV, since the net charge imbalance
increases the y-component of the field causing impact
ionization process to trigger at lower drain voltage.
The most important observation here is that, for
CoolMOS structure the charge imbalance curve shifts left
as compared to ideal SJ-layer. The maximum obtainable
BV from CoolMOS is not at N=P but at P>N by
approximately 3.2%. This clearly indicates that due to the
neck region or channel region the amount of charge in Npillar is slightly more than P-pillar. In order to balance
this surplus charge laterally, we have to increases the Ppillar doping by 3.2%. The maximum obtainable BV in
case of CoolMOS is slightly less than the SJ-layer because
the net P-pillar height is reduced due to the P-body
diffusion.
REFERENCES
X. B. Chen and P.A. Mawby, ‘Theory of a novel
voltagesustaining layers for power devices’’,
Microelectronic Journal, 1998, ~01.29,pp.1005-1011.
D. A. Grant, Power MOSFETs Theory and
Applications, John Wiley & Sons. 1989.
B. J. Baliga, Modem Power Devices, John & Wiley
Inc.,1987.
L. Lorenz, M. Mar, J.P Stencil and A. Bachofner,
“Drastic Reduction of On-Resistance with CoolMOS”,
PCIM Europe, vo1.5, 1998.
G. Deboy et. al., “A new generation of high voltage
MOSFETs breaks the limit of silicon”, Proc. IEDM,
p.683, 1998.
[6] P. Shenoy, A. Bhalla and G. Dolny, “Analysis of the
effect of charge imbalance on the static and dynamic
characteristic of super junction MOSFET”, Proc.
ISPSD’98,pp.99-102, 1999.
[7] Integrated System Engineering, ISE-TCADManuals,
AG, Zurich, Switzerland 1999
The detailed static charge imbalance and its simulation
and results will be published elsewhere.
I
‘
I
’
I
-
1
’
1
-10
-5
0
5
10
GmpematimDegeea)%=(NP)/N*100
Fig.14 The off-state charge imbalance curve
ACKNOWLEDGMENT
We would like to express sincere thanks to General
Electric Company, Schenectady USA for their financial
support.
1775
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 4, 2008 at 01:47 from IEEE Xplore. Restrictions apply.