Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics
Nihar R. Mohapatra, Madhav P. Desai and V. Ramgopal Rao
Department of Electrical Engineering, Indian Institute of Technology, Bombay, 400 076, India
[email protected]
Abstract
This paper analyzes in detail the Fringing Induced
Barrier Lowering (FIBL) in MOS transistors with high-K
gate dielectrics using two-dimensional device simulations.
We found that the device short channel performance is
degraded
with
increase
in
gate
dielectric
permittivity(Kgate) due to an increase in the dielectric
physical thickness to channel length ratio. For Kgate
greater than Ksi, we observe a substantial coupling
between source and drain regions through the gate
insulator. This fact is validated by extensive device
simulations with different channel length and overlap
length over a wide range of dielectric permittivities. We
also observe that the overlap length is an important
parameter for optimizing DC performance in short
channel MOS transistors. The effect of stacked gate
dielectric and lateral channel engineering on the
performance of high-K gate dielectric MOS transistors is
also studied to substantiate the above observations.
1. Introduction
Continuous CMOS miniaturization necessitates the use
of high dielectric constant materials to replace thermally
grown silicon dioxide as gate dielectrics in gate stack
material system [1,2]. Some of the high-K materials such
as Al2O3 (Kgate~10), HfO2/ZrO2 (Kgate~25), La2O3
(Kgate~27), TiO2 (Kgate~60-100) have been widely studied
[3]. The main idea is to achieve an equivalent oxide
thickness of less than 15Å by combining higher K with
larger physical thickness to prevent direct tunneling.
Unfortunately, with increase in Kgate, the physical
thickness of the gate dielectric becomes comparable to the
channel length. So, the percentage of field lines
originating from bottom of the gate electrode and
terminating on the source/drain regions increases
compared to the field lines terminating on the channel.
These field lines finally induce an electric field from
source to channel thereby reducing the source to channel
barrier height. Also, a weaker coupling between gate and
channel due to fringing, increases the control of drain on
the source to channel barrier height. This phenomenon is
generally known as FIBL [4-6]. The reduction of channel
length further increases the physical dielectric thickness
to the channel length ratio. Thus, two-dimensional effects
become dominant, leading to poor short channel
performance.
Over the years, several attempts have been made to
understand the effect of FIBL on the device and circuit
performance of MOS transistors with high-K gate
insulators. Kencke et al [8] studied the effect of FIBL
with asymmetric devices having different source and
drain spacer dielectrics. They found that FIBL is caused
largely by drain side high-K spacers. Frank et al [9]
studied the FIBL and scaling behavior of MOS transistors
with high-K gate insulators. They demonstrate that the
design space is smaller and bulk MOSFETs can only gain
up to ~20% additional scaling by the use of high-K
insulators. Mohapatra et al [6,7] presented a quantitative
estimate of the fringing field effects by extracting various
capacitance components in the MOS system using MonteCarlo techniques. They suggested that FIBL can be
reduced by the use of low-K sidewalls for thick gate
insulators and confirmed the presence of an optimum Kgate
for specified off-current requirements in different
technology generations.
Although some work has been done on FIBL, these
studies do not adequately describe the physics behind the
FIBL effect, which is very important for designing a
device with high-K gate insulators. In this paper, we have
proposed a theory that gives a better insight into the FIBL
effect and explains the physics of MOS transistor with
high-K gate dielectrics. For this purpose, we have studied
the effect of channel length, junction depth and overlap
length scaling on the performance of deep sub-micron
MOS transistors with high-K gate dielectrics using the 2dimensional device simulator MEDICI. The effect of
dielectric stack and lateral channel engineering on the
transistor performance is also presented.
2. Simulation Structures
Device simulations are performed using the twodimensional (2-D) device simulator MEDICI [10]. The
simulated structures are based on the scaled dimensions
outlined in the SIA roadmap [11]. A spacer technology
(spacer width of 60nm) with heavily doped source/drain
extensions is used. The source/drain extensions and deep
source/drain junction depths are 30nm and 50nm
respectively. A retrograde profile with a low impurity
concentration at Si/SiO2 interface and a high peak
concentration at a finite depth below the interface was
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used to provide non-uniform channel doping profile. The
permittivities of the gate dielectric (Kgate) are varied from
3.9 to 100 keeping the effective gate dielectric thickness
constant at 1.5nm. For each channel length, the channel
profiles are optimized to achieve threshold voltage of
0.25volt for Kgate=3.9 (SiO2). The calibrated energy
balance model is incorporated to consider the spatial
variation of carrier energy in order to account for the
velocity overshoot and non-local transport phenomena.
The energy relaxation time used for the simulation was
0.2ps. The Fermi-Dirac statistics are used to determine the
active carrier density within the simulation structures. A
combination of coupled and uncoupled solution
techniques is used for the simulation of devices at room
temperature. To isolate the degradation essentially due to
fringing fields, the effects of poly depletion and quantum
mechanical effects are not taken into account.
3
-1
10
-2
10
ION/IOFF
DIBL
-3
2
10
S
-4
10
Vth
1
20
40
60
80
100
Gate Dielectric Permittivity (Kgate)
4
(b)
3
Figure 2 shows the physical distance (lphysical) of
point A in the channel (near the source) from different
electrodes of a MOS transistor through different paths.
Here, we defined the equivalent electrical distance (le) as
the ratio of physical distance (lphysical) and the dielectric
constant (Hr) of the medium.
le = lphysical / Hr
A
10
-1
10
ION/IOFF
2
-2
10
-3
10
S
-4
Vth
0
3.1 Physics of the FIBL Effect
0
LG=50nm
TOX,eff=1.5nm
DIBL
1
Normalized ION/IOFF
(a)
0
Normalized Vth, S, DIBL
0
10
LG=70nm
TOX,eff=1.5nm
4
10
Normalized ION/IOFF
Normalized Vth, S, DIBL
3. Results and Discussion
Lowering (DIBL, change in threshold voltage with
change in drain bias) and Ion/Ioff, normalized to their value
for Kgate=3.9 (SiO2) as a function of gate dielectric
constant for 70nm and 50nm MOS transistors. It can be
seen that with an increase in Kgate from 3.9 to 100, DIBL
increases exponentially compared to a linear increase in
the sub-threshold swing. We also observed a drastic
degradation in the short channel performance for Kgate >
Ksi. This feature can be attributed to FIBL as discussed in
the previous literatures. With reduction in the channel
length these effects are further enhanced resulting in
increased degradation in the characteristics.
20
40
60
80
100
Gate Dielectric Permittivity (Kgate)
1. Normalized Threshold Voltage (Vth),
Figure 1
SubSub-threshold awing (S), DIBL and Ion/Ioff as a
function of gate dielectric constant for (a
(a)) 70nm
(b) 50nm channel length NMOS transistors. The
effective gate dielectric thickness during this
simulation is kept fixed at 1.5nm.
Note that, the saturation current (Id,sat) and off current
(Ioff) of the device is matched with the reported values (by
judiciously choosing the model and model parameters) in
the SIA roadmap and/or literature before starting the
simulation. Figure 1 shows the threshold voltage (Vth),
sub-threshold slope (S) and Drain Induced Barrier
2. Schematic showing the coupling of a
Figure 2
point near source to gate and drain electrodes
through different paths.
From the figure, it can be seen that the drain electrode
is coupled to the channel through paths II (through gate
dielectric) and III (through silicon). The coupling through
the silicon is well known to the research community and
can be reduced by controlling the junction depth. But the
coupling through the gate dielectric is a strong function of
the physical thickness of the gate dielectric as well as the
drain-side overlap area. It may be noted that this coupling
is small (can be neglected) in conventional MOS
transistors due to smaller physical thickness of the gate
oxide.
In the case of MOS transistors with different gate
dielectric materials the equivalent electrical distance from
the gate electrodes to the channel (path I) is kept constant
by scaling the dielectric thickness accordingly. However,
the electrical equivalent distance between the drain and
channel (path II) is not scaled leading to a decrease in le in
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0.20
0.16
0.00
0.0
40
0
100
VG=0.4Volt
LG=70nm
TOX,eff=1.5nm
0.2
60
120
0.12
0.04
80
LG=70nm
TOX,eff=1.5nm
20
Kgate=3.9
Kgate=30
Kgate=60
Kgate=100
0.08
Kgate=3.9
Kgate=30
Kgate=60
Kgate=100
100
0.4
0.6
0.8
Drain Voltage (Volts)
1.0
3. Output characteristics of a MOS
Figure 3
transistor with different gate dielectrics.
To prove the coupling through gate insulator (path II)
in high Kgate MOS transistors, we have extracted DIBL for
different junction depths. This simulation is done for two
transistors having overlap length (Lov) of 1nm and 12nm.
To isolate the degradation essentially due to overlap
length, the effective channel length is kept constant at
55nm throughout the simulation. The difference in DIBL
('DIBL) between Lov=1nm and 12nm is calculated as a
function of junction depth for different Kgate. This is
plotted in figure 4. It may be noted that 'DIBL at a fixed
junction depth symbolizes the coupling between source
and drain through the gate insulator (coupling through
silicon remains constant, thus cancels out). From the
figure, it can be observed that for a constant physical gate
dielectric thickness (fixed gate dielectric constant),
'DIBL is independent of junction depth. But for a fixed
junction depth, 'DIBL increases with an increase in Kgate
due to higher physical gate dielectric thickness leading to
a stronger coupling between source and drain through the
gate insulator (path II). With increase in the channel
length this coupling further increases due to decrease in
the equivalent electrical distance resulting in higher
DIBL.
'DIBL (mV/V)
Drain Current (mAmp)
0.24
120
'DIBL (mV/V)
the lateral direction. Also, the strength of lines of forces at
the edges of the gate electrode (in the overlap region)
decreases due to higher physical dielectric thickness and
enhanced fringing. Thus, in high-K gate dielectric MOS
transistors the drain electrode is more tightly coupled to
the channel through the gate insulator and lateral electric
field lines from drain reach a larger distance into the
channel. This electrically closer proximity of drain to the
channel gives rise to higher short channel effect in high
Kgate MOS transistors as shown in the output
characteristics (figure 3) and figure 1.
LG=50nm
TOX,eff=1.5nm
80
60
40
20
0
10
20
30
40
50
Junction Depth (nm)
4 The difference in DIBL between
Figure 4.
transistors having Lov of 1nm and 12nm as a
function o
off junction depth for different gate dielectric
constant. The effective channel length of the
transistors is kept fixed during simulation.
Figure 5 shows DIBL and Ion/Ioff as a function of Kgate
for different gate to source/drain overlap length. As can
be seen from the figure, the sub-threshold behavior is
improved with decrease in the overlap length. This is
mainly due to the decrease in the coupling area between
source and drain (path II). Also, reducing the overlap
length decreases the accumulation and spread resistance
by a significant amount, thereby increasing the current
drivability [12]. Therefore, the overlap length could be an
important parameter for optimizing DC performance of
short channel MOS transistors with high-K gate
dielectrics.
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180
Kgate = 3.9
Kgate = 30
Kgate = 60
Kgate = 100
120
90
60
30
10
6
10
5
10
4
10
3
2
4
6
8 10 12
Overlap Length (nm)
160
DIBL (mV/V)
Ion/Ioff
0
Kgate = 3.9
Kgate = 30
Kgate = 60
Kgate = 100
0
Kgate=10
Kgate=25
Kgate=60
Kgate=100
Stack
120
High-K
SiO2
80
40
LG=70nm
2
4
6
8 10 12
Overlap Length (nm)
5 DIBL and Ion/Ioff of a 70nm NMOS
Figure 5.
transistor as a function of overlap length for
different gate diele
dielectrics.
ctrics.
3.2 Effect of Dielectric Stack on FIBL
Interfacial layers between the high-K dielectric and the
silicon system are intentionally and unintentionally
introduced in the material system. Intentional layers like
thermal oxides (Kgate ~ 3.9), silicon nitrides (Kgate ~ 7) or
oxy-nitrides (Kgate ~ 5) are introduced to have better
interface properties. Inadvertently formed interfacial
layers, however occur during dielectric deposition stages
or during post deposition annealing in oxygen ambient
and this layer may be composed of low quality nitrided
oxide/oxy-nitride and metal silicides depending on high-K
dielectric chemistry and growth conditions [3,13]. In this
work, we have also looked at the device performance with
stacked gate dielectrics. In the first part of the simulation
the bottom dielectric is kept fixed as SiO2 and the
permittivity of the top dielectric is varied from 10 to 100.
In the second part, simulations are done by alternating the
dielectric stack i.e. SiO2 as the top dielectric. The above
simulations are done for different physical thickness of
160
DIBL (mV/V)
DIBL (mV/V)
150
LG=70nm
oxide to effective dielectric stack thickness ratio (Tox/Teff),
keeping the equivalent dielectric thickness constant at
1.5nm. The results are plotted in figure 6. As can be seen,
with decrease in Tox/Teff ratio the sub-threshold
performance is severely degraded. Also the device
performance is improved when SiO2 is used as bottom
dielectric in the gate oxide stack. The reason for this can
be attributed to drain to source coupling through the
bottom insulator. For top SiO2 stack the coupling takes
place through the higher permittivity gate insulator, which
strongly influences the source/drain to channel barrier
height compared to the bottom SiO2 stack. Thus, it can be
concluded that the dielectric constant of the bottom
insulator predominantly affects the sub-threshold swing
and off-state current of a MOS transistor.
Inverted Stack
SiO2
High-K
120
80
40
0
20
40
60
80
100
Physical Thickness of Oxide/Effective
Dielectric Thickness (%)
6 DIBL of a NMOS transistor as a function
Figure 6.
of physical thickness to effective dielectric
thickness ratio. The simulation is done for different
gate dielectrics and with two differen
differentt stack
structures. The effective dielectric thickness is kept
fixed at 1.5nm during the simulation.
3.3 Effect of Channel Engineering on FIBL
Lateral channel engineering e.g. halo and pocket
implants is inevitable for sub 100nm MOS transistors to
improve the short channel performance. This is usually
achieved by implanting ions with a tilt angle after gate
patterning. These implants can be symmetrical (double
halo, DH) or asymmetrical (single halo, LAC) with
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MOS transistors the improvement through channel
engineering is less significant. Hence, it can be concluded
that the channel engineering has a very marginal effect on
the device performance of MOS transistors with high-K
gate dielectrics.
240
CON
LAC
DH
200
DIBL (mV/V)
respect to source/drain. Recently, very excellent short
channel performance was demonstrated in 0.1Pm nchannel MOS transistors with lateral channel engineering
[14,15].
In this work, we have also studied the device
performance of double-halo (DH) and LAC MOS
transistor with high-K dielectrics using 2-D process and
device simulations. The simulated doping profiles of a
70nm conventional (CON), DH and LAC MOS transistors
are shown in figure 7. The effective channel length in all
the cases is kept fixed at 50nm. The channel profiles are
optimized to achieve a threshold voltage of 0.22 Volts for
Kgate=3.9. With increase in drain bias the drain electric
field as well as the drain to channel depletion width
increases. Thus the coupling between drain region and
point A (figure 2) through silicon increases thereby
reducing the source to channel barrier height. The main
aim of channel engineering (higher doping near the
source/drain junction) is to shield the lines of forces from
drain and to reduce the above coupling.
160
120
80
LG=70nm
TOX,eff=1.5nm
40
0
-3
Net Doping (cm )
20
10
CON
LAC
DH
LG=70nm
19
10
18
10
17
10
0.16
0.20
0.24
0.28
Distance along the channel (Pm)
7 Simulated doping profiles of 70nm
Figure 7.
channel length CON, DH and LAC MOS transistor.
Figure 8 shows the DIBL and source to channel barrier
height as a function of gate dielectric constant for CON,
DH and LAC MOS transistors. As expected, for Kgate=3.9
(SiO2) LAC MOS transistors show better short channel
performance compared to CON and DH MOS transistors.
Since the channel length is very small, DH transistors also
show more DIBL compared to the conventional
transistors due to higher doping and thereby higher lateral
electric field (figure 9) near the drain junction. It can also
be observed that DIBL (increases) and barrier height
(decreases) degrade significantly with increase in Kgate
and are insensitive to the channel engineering. This
observation can be explained by noting that in MOS
transistors with high-K gate insulators the source is
coupled to the drain predominantly through the gate
insulator (path II) in addition to path III and the coupling
through gate insulator is not affected by channel
engineering. Since this coupling is stronger in high Kgate
Source/Channel Barrier Height (V)
21
10
20
40
60
80
100
Gate Dielectric Permittivity (Kgate)
0.56
CON
LAC
DH
0.52
0.48
0.44
0.40
LG=70nm
TOX,eff=1.5nm
0.36
0
20
40
60
80
100
Gate Dielectric Permittivity (Kgate)
Figure
8. DIBL and source/channel barrier height
height of
Fi
gure 8
CON, LAC and DH 70nm NMOS transistors as a
function of gate diele
dielectric
ctric permittivities.
4. Conclusion
A detailed analysis of FIBL in MOS transistors with
high-K gate dielectrics is done using extensive device
simulations. For the first time a theory is proposed which
gives better insight into the physics of FIBL phenomenon.
We observe that the degradation in the short channel
performance of high-K gate dielectric MOS transistors is
significantly enhanced due to the additional coupling
between source and drain through the gate insulator and it
can be controlled by optimizing the overlap length and the
bottom layer dielectric constant in stack structures. Our
work also shows that the performance gain is marginal
with channel engineering for MOS transistors with highK gate dielectrics.
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Lateral Electric Field (MV/cm)
Lateral Electric Field (MV/cm)
0.5
CON
LAC
DH
0.0
-0.5
-1.0
-1.5
0.18
LG=70nm
TOX,eff=1.5nm
Kgate=3.9
0.20
0.22
0.24
Distance along the channel (Pm)
0.5
CON
LAC
DH
0.0
-0.5
-1.0
-1.5
0.18
LG=70nm
TOX,eff=1.5nm
Kgate=30
0.20
0.22
0.24
Distance along the channel (Pm)
9. Simulated lateral electric field along the
Figure 9
CON,
ON, LAC and DH 70nm NMOS
surface of C
transistors for Kgate=3.9 and 30.
5. Acknowledgement
This work is funded by Intel Corporation through a
student fellowship to Nihar R. Mohapatra.
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