Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide
CMOS Technologies
K. Narasimhulu and V. Ramgopal Rao
Department of Electrical Engineering, Indian Institute of Technology Bombay,
Mumbai-400076, India
[email protected], [email protected]
Abstract
MOS Transistors with sub 100 nm channel lengths
need a gate oxide thickness in the range of 1 - 2 nm to
combat the short channel effects. However at these
gate dielectric thicknesses, the gate current is no
longer negligible. In this paper, we report the device
analog behavior with extremely scaled oxides for
integrating mixed signal circuits using the scaled
digital CMOS technologies. We show the performance
of common source amplifiers and current mirror
circuits with these technologies. Our results also show
that though thin oxides result in good voltage gains of
amplifier circuits, the increased gate leakage degrades
the performance of current mirror circuits. We also
analyze the performance of different classes of current
mirror circuits in the presence of gate leakage and
provide broad guidelines for analog circuit design in
the presence of gate leakage.
1. Introduction
It is well known that as the transistor channel length
is scaled, it is necessary to reduce the thickness of the
gate dielectric to control the undesirable short channel
effects. The continuous scaling of CMOS technologies
has resulted in transistors with gate dielectrics in the
range of 1-2 nm. However, at these gate dielectric
thicknesses, considerable gate leakage occurs which
degrades the circuit performance. Many researchers
have looked at the gate leakage effects on the digital
circuit performance with the scaled gate oxides [1] [2]. However, a few researchers looked at the effect of
gate leakage on analog circuit performance [3]. As
scaled CMOS is promising for System-on-chip
applications, it is essential to look at the performance
of scaled CMOS technologies for analog applications
by including the gate leakage constraints. Further, the
usage of longer channel length devices for analog
circuits, to maintain adequate output resistance,
increases the gate current as it is proportional to gate
area [4]. In this work, we have looked at the behavior
of MOS devices with gate leakage considerations from
the analog circuit performance point of view.
The details about process and device simulations
are presented in section II. The effect of oxide scaling
on the device analog performance parameters is
discussed in section III. The performance of amplifier
and current mirror circuits is reported in Section IV.
Finally, Section V concludes the work.
2. Simulation Structures
In this section the process and device simulation
details of the devices and circuits are discussed. A
standard uniformly doped channel device is simulated
to match the electrical characteristics of the ITRS
roadmap at 90 nm technology node [5]. We have
optimized the doping profiles of this device to meet the
roadmap targets. A drawn gate of length of 65 nm is
used, where the effective gate length is in the range of
45 nm. The junction depth, oxide thickness and S/D
depths are adjusted to be 25 nm, 1.5 nm and 55 nm
respectively. In order to understand the effect of oxide
thickness on the analog circuit performance, its
thickness is varied over the range from 1 nm to 3 nm
by keeping these optimized doping profiles fixed. We
have not used halo implants in the process, as they are
known to degrade long channel analog behavior [6].
The source/drain extensions and deep source/drains are
formed using As implantation with a dose of 2x1015
/cm2 at 5.5 keV and 5x1015 /cm2 at 27.5 keV
respectively followed by an annealing cycle for 10
min. at 950 0C. All the 2D simulations have been
carried out using ISE TCAD. DIOS process simulator
is used for simulating the device structure; MDRAW
tool is used for making the simulation grids and
DESSIS tool is used for device simulations [6].
Drift/diffusion transport and surface quantization
models are used for device simulations. All the circuit
simulations have been carried out using ISE mixed
mode simulator. For gate current simulations, the direct
tunneling model and lucky electron models available in
ISE are used. The model parameters are tuned to match
the gate current of the device with W/L of 10 µm/1µm
Proceedings of the 19th International Conference on VLSI Design (VLSID’06)
1063-9667/06 $20.00 © 2006 IEEE
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 2, 2008 at 05:14 from IEEE Xplore. Restrictions apply.
In this section the effect of oxide thickness on the
device small signal analog parameters and DC
parameters is discussed.
3.1. Small signal performance
1.0
VGT = VDS = 0.5 V
due to
W = 1 µm
µ degradation
0.5
1
LG = 65 nm
LG = 500 nm
1.0
1.5
2.0
2.5
0.0
Normalized gm
gm ( mS/µm )
10
3.0
tox ( nm )
Fig. 1. Device transconductance (gm) and its normalized
value (normalized to gm observed at tox = 3 nm) as a
function of gate oxide thickness. The drain bias and the
gate overdrive voltages were 0.5 V, and the device gate
lengths were 65 nm and 500 nm.
Fig 1 shows the device transcondutcance (gm) as a
function of gate oxide thickness at VGT = VDS = 0.5 V
for the two devices with channel lengths of 65 nm and
500 nm. On the right y-axis is shown normalized
transconductance with respect to gm of the device at tox
= 3 nm, for the two cases. The solid line without
symbols shows the transconductance without
additional mobility degradation. One can clearly see
the degradation in the transcoductance with reduced
oxide thickness. This is due to increased transverse
electric fields causing higher surface scattering,
degrading the mobility. Secondly, severe quantum
effects also reduce the transconductance. Notice that
degradation in the transcodunctance with respect to the
theoretical value is more for short channel device
compared to long channel devices. This shows the
dominant mechanism controlling the carrier mobility in
long channel devices is carrier scattering and phonon
scattering, where as in shorter channel devices, the
degradation of the mobility is due to surface scattering.
5
Id/gd ( V )
3. Effect of oxide scaling on the device
analog performance parameters
A mobility degradation of nearly 25 % is observed
when the gate oxide thickness is scaled from 3 nm to 1
nm for the device with 65 nm gate length. However, in
all the cases, transconductance increases with thin gate
oxides at a rate lower than predicted by long channel
MOS theory.
4
VGT = VDS = 0.5 V
3
2
Normalized Id/gd ( V )
with an oxide thickness of 2 nm. For the long channel
devices used for circuit simulations, all the device
process parameters are kept constant except the
channel length. We have simulated both NMOS and
PMOS devices.
CON LG = 65 nm
2
CON LG = 500 nm
1
1.0
1.5
2.0
2.5
3.0
tox ( nm )
Fig. 2. Device Id/gd and its normalized value as a function
of gate oxide thickness at a drain bias of 0.5 V and gate
over drive voltage of 0.5 V for the devices with gate
lengths of 65 nm and 500 nm. Dotted lines show the
values of Id/gd without second order effects.
Fig.2 shows the device Id/gd as a function of oxide
thickness at a drain bias of 0.5 V and a gate over-drive
of 0.5 V for the devices with gate lengths 65 nm and
500 nm. For a good analog device, high Id/gd is needed.
A higher value of this factor indicates the device ability
of having higher output resistance (smaller drain
conductance) at certain power dissipation. For any
technology, when the channel length is reduced, Id
should increase at a higher rate than the drain
conductance to have higher Id/gd values. Thus this
factor clearly depicts the short channel effects. The
normalized Id/gd is also shown in the same figure. For
shorter channel devices, considerable improvement in
this factor can be achieved with scaled oxides.
However for long channel devices, a reduction of this
factor is observed, when the gate oxide thickness is
scaled. Since the transistor is biased at same VGS-VT
for all the devices, where VT is the threshold voltage
measured at low drain voltages, the resulting currents
are smaller and hence a lower value of Id/gd is observed
for long channel devices as the gate oxide thickness is
scaled down. In addition to this, quantum effects also
degrade this factor further. However, at all the gate
oxides this factor is higher for long channel devices
compared to short channel counterparts. Also, one
Proceedings of the 19th International Conference on VLSI Design (VLSID’06)
1063-9667/06 $20.00 © 2006 IEEE
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 2, 2008 at 05:14 from IEEE Xplore. Restrictions apply.
1.0
Cgs ( fF )
0.8
0.6
LG = 65 nm
LG = 500 nm
1
1.0
1.5
2.0
2.5
0.4
0.2
Normalized Cgs
10
3.0
tox ( nm )
1.0
10
Cgd ( fF )
VGT = VDS = 0.5 V
0.6
0.4
1
0.2
1.0
1.5
2.0
2.5
Normalized Cgd
0.8
3.0
tox ( nm )
Fig. 3. Device capacitances Cgs, Cgd and their
normalized values as a function of gate oxide thickness
at a drain bias of 0.5 V and gate over drive voltage of
0.5 V for the devices with gate lengths of 65 nm and
500 nm. Solid lines show the values of all capacitances
without second order effects.
Fig 3 shows the device capacitances gate-to-source
capacitance (Cgs) and gate-to-drain capacitance (Cgd) as
a function of oxide thickness at VDS = VGT = 0.5 V for
the devices with gate length of 65 nm and 500 nm. The
normalized values of these capacitances (normalized to
capacitance at 3 nm gate oxide thickness) are also
shown. Though all these capacitances monotonously
increase with reducing oxide thickness, the actual
capacitances are smaller than their theoretical
counterparts, which is due to quantum and other 2D
effects in these short channel devices. It is also seen
that the similar trend is followed in gate-to-body
capacitances (cgb). All these capacitances change
bandwidth of the amplifier circuits, as will be shown in
subsequent sections.
3.2. DC Performance
In addition to the earlier discussion on ac
performance, with aggressively scaled gate oxides,
there exists a gate leakage current, which affects the
circuit performance. Mainly current mirrors are the
major sufferers with this non-zero gate current. We
express this quantity, as ID/IG and its effect on the
current mirror circuits is discussed in the subsequent
sections.
10
ID/IG
needs to look the performance of these devices at a
constant current bias for analog circuit applications.
This is further emphasized in the subsequent sections.
11
10
9
10
7
10
5
10
3
10
1
VGS = VDS = 1 V
tox ( nm )
1.5
3
1
2
250
500
750
1000
Gate Length ( nm )
Fig. 4. Transistor drain current to gate current ratio
(ID/IG) as a function of channel length at VGS = VDS = 1 V
for the devices with different gate oxide thickness.
Transistor width is taken as 10 µm for the simulations.
Fig 4 shows the drain current to gate current ratio
(ID/IG) as a function of channel length for different
oxide thicknesses at a gate and drain biases of 1V.
Notice a considerable fraction of IG in ID, in the long
channel devices as gate current is proportional to the
area of the device. This significantly affects the
performance of circuits such as sample and hold
circuits and MOS DACs. Physically ID decreases with
increasing the channel length and IG increases with the
channel length making ID/IG to fall with the long
channel devices. Though it clearly shows that using
short channel device reduces the gate current, it also
reduces the output resistance of the device, which is
another requirement of typical analog circuits. Hence
there is a distinct tradeoff between gate current and
output resistances in extremely scaled gate oxide
technologies making the design of analog circuits
difficult with conventional CMOS technologies.
4. Effect of gate oxide scaling on circuit
performance
In this section the effect of oxide thickness on the
performance of analog circuits such as amplifiers,
basic current mirrors and cascode mirrors is reported
with process, device and mixed mode simulations. The
various circuits considered in this study are shown in
Fig 5. For the circuits simulated, PMOS devices of
long channel (1 µm) and thick gate oxide (3 nm)
Proceedings of the 19th International Conference on VLSI Design (VLSID’06)
1063-9667/06 $20.00 © 2006 IEEE
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 2, 2008 at 05:14 from IEEE Xplore. Restrictions apply.
devices are used, as their purpose is to ensure constant
current bias and high load impedance. We have scaled
only the NMOS (driver transistors) and quantified the
performance trade-offs with the gate oxide thickness.
oxide thickness. However, the gain bandwidth is a
week function of tox due to the combination of
degradation in the mobility and increased capacitances.
It almost remains constant for short channel devices.
One can conclude that for an amplifier circuit, going
for thinner oxide results in increased voltage gains.
1.1
(a)
L G = 100 nm
Iout/Iref
W /t ox = 1 µ m/1 nm
1.0
t ox ( nm )
1
1.2
1.5
2
3
0.9
Fig. 5. The circuits considered for the device simulation
(a) common source (CS) amplifier with current mirror
load, (b) basic current mirror with PMOS current
reference and (c) cascode current mirror.
0.5
1.0
1.5
2.0
V DS ( V )
3
2
10
LG = 65 nm
LG = 500 nm
1
10
1
10
1.00
2
10
(b)
Iout/Iref
VDS = 0.5 V & ID/W/L = 10 µA
Gain Bandwidth ( GHz )
Voltage Gain
10
tox (nm)
L G = 1 µm
1
1.2 W/t ox = 1 µ m/1 nm
1.5
2
3
0.75
0.50
0.5
1.0
1.5
2.0 2.5
tox ( nm )
3.0
1.0
1.5
2.0
V DS ( V )
Fig. 6. Amplifier voltage gain and gain bandwidth as a
function of gate oxide thickness at a current bias of ID/W/L
= 10 µA. The driver transistors with gate lengths of 65 nm
and 500 nm are considered.
Fig. 7. The current transfer ratio (Iout/Iref) versus drain
output voltage (VDS) of simple current mirror circuit
with NMOS devices of different gate oxide thicknesses.
For (a) LG = 100 nm and (b) LG = 1 µm, Iref is kept at
100 µA.
4.1. CS amplifier with current mirror load
4.2. Basic Current Mirror
Fig 6 shows the effect of gate oxide thickness on
amplifier (shown in Fig 5(a)) small signal voltage gain
and gain bandwidth for a common source amplifier.
The driver transistors with two channel lengths 65 nm
and 500 nm are considered. The devices are biased at a
constant normalized current ID/W/L = 10 µA and a
drain bias of 0.5 V and the small signal simulations
have been carried out at a frequency of 1 MHz. The
PMOS device channel length is taken as 1 µm, so as
not to affect the amplifier voltage gain. With
decreasing of oxide thickness, small signal gains
monotonously keep increasing for both the channel
lengths due to the improved 2D effects with decreasing
While coming to the current mirrors, two
important factors need to be considered: gate current
and load impedance. Being a biasing stage, it should
mirror the reference current accurately and as a load
stage it should have very high output resistance.
However, as discussed earlier, these two parameters
trade-off each other when the technology is scaled. Fig
7 shows the basic current mirror’s (shown in Fig 5(b))
output current transfer ratio (Iout/Iref) as a function of
output voltage. NMOS devices used in the circuit have
difference gate oxide thicknesses ranging from 1 nm to
3 nm and gate lengths of 100 nm and 1 µm. Transistor
W is scaled so as to keep W/tox constant. For the circuit
Proceedings of the 19th International Conference on VLSI Design (VLSID’06)
1063-9667/06 $20.00 © 2006 IEEE
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 2, 2008 at 05:14 from IEEE Xplore. Restrictions apply.
with NMOS devices of 100 nm gate lengths, the
current transfer ratio degrades over the range for all the
oxide thicknesses due to short channel effects such as
DIBL and channel length modulation. In addition, the
output resistance also degrades drastically due to short
channel effects. However, output resistance can be
significantly improved with thin oxides. On the
contrary, though the output saturation characteristics
prevail, the transfer ratio degrades drastically for the
current mirror with long channel NMOS devices, due
to considerable increase in gate leakage. This is similar
to base current in BJTs and one needs to look for novel
circuit design techniques to reduce the gate leakage
effects. It turned out that at 1 nm gate oxide, current
transfer ratio has decreased to 55 % of the reference
value. This further gets degraded with the number of
output stages, as shown in the Fig. 8.
Fig 9(a) shows the current transfer ratio of the basic
current mirrors as a function of channel length for
various gate oxide thicknesses, biased with the
reference current of 100 µA. Iout is extracted at a drain
bias VDS = VGT + 0.3 V The NMOS transistor width is
scaled to maintain the constant current. Fig 9(b) shows
the output resistance of the current mirror circuit as a
function of channel length at a drain bias of VDS = VGT
+ 0.3 V. An optimum value of the channel length for
the best current mirroring can be seen to be 150 nm but
at this channel length, the output impedance reduces.
One can also see that improvement in output
impedance can be achieved with scaled oxides for
short channel devices but this improvement is not
substantial for long channel cases.
1.1
1.00
Iout/Iref
0.50
0.9
Iout/Iref
0.75
(a)
1
LG = 1 µm
VDS = VGT + 0.3 V
W/tox = 1 µm / 1 nm
tox ( nm )
1
1.2
1.5
2
0.25
2
4
6
8
10
t ox ( nm )
0.8
1
1.2
1.5
2
3
0.7
0.6
10
2
(b)
t ox ( nm )
10
3
3
1
1.2
1.5
2
3
Rout ( kohm )
Fig. 8 shows the current transfer ratio as a function
of number of output stages (right side NMOS arm of
the basic current mirror) at a drain bias of VGT + 0.3 V
and the NMOS gate length of 1µm. The number of
stages indicates the number of parallel transistors into
which the Iref needs to be mirrored. A drastic
degradation in Iout/Iref can be seen with more than 5
stages and tox of 1 nm due to the gate leakage. In
addition, one can notice that even with 1.2 and 1.5 nm
gate oxides, there is considerable degradation in the
transfer ratio with increasing number of output stages.
Also one can notice that as the current transfer ratio
degrades due to short channel effects for short channel
transistors and due to gate leakage in long channel
devices, one would expect an optimum channel length
at which the current mirror results in a transfer ratio of
nearly 1. We would also like to emphasize on this
aspect in this section.
10
Gate Length ( nm )
No. of output stages
Fig. 8 Current transfer ratio of basic current mirror
as a function of number of output stages. NMOS with
LG = 1 µm is used for simulations.
V D S = V G T + 0.3 V
W /L G = 1
0.5
10
I ref = 100 µ A
I bias = 100 µ A
V D S = V G T + 0.3 V
2
W /L G = 1
10
2
Gate Length ( nm )
10
3
Fig. 9(a). The current transfer ratio (Iout/Iref) as a function of
gate length, (b) small signal output resistance as a function
of channel length for the devices with difference oxide
thicknesses at a drain bias of VGT + 0.3 V and Iref = 100 µA.
4. 3. Cascode Current Mirror
Cascode current mirrors (shown in Fig 5(c)) are the
most commonly used building blocks in analog design
with the scaled technologies. These circuits show very
high output resistance, though at reduced output signal
Proceedings of the 19th International Conference on VLSI Design (VLSID’06)
1063-9667/06 $20.00 © 2006 IEEE
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 2, 2008 at 05:14 from IEEE Xplore. Restrictions apply.
swings. However, till now the gate leakage is not
considered in the current mirroring of these circuits.
Here we report interesting results by considering the
gate leakage in cascode current mirror analysis. Fig
10(a) shows the current transfer ratio of the cascode
mirrors as a function of output voltage for the devices
with different gate oxide thicknesses. The devices used
are of gate length 1um and W/tox is kept constant at 4
µm/3 nm. It can be seen that even with 1 nm gate
oxide thickness, the cascode mirror is able to result in a
current transfer ratio of 0.85, where as basic mirror
circuits show a value of 0.55. This higher tolerance to
gate current is due to transistor stack and inherent
reverse body bias reducing the effective gate over drive
on the device M2, shown in the Fig. 7(b). Fig 10(b)
shows the effect of NMOS device scaling on the
current transfer ratio of the cascode current mirror for
various gate oxide thicknesses. Degradation in this
ratio at long channel lengths can be observed, but this
degradation is lesser than that of short channel devices,
shown earlier. This shows the potential suitability of
cascode mirror circuits for the deeply scaled gate oxide
CMOS regime with increased gate leakages.
0.8
Iout/Iref
The effect of gate dielectric thickness on the
device analog performance is studied with the devices
scaled down to 100 nm regimes, using the process and
device simulations. The devices with thin oxides show
better output resistance in sub-micron regime but this
improvement is not significant in long channel devices.
We also conclude that though the thin oxides improve
the voltage gain of the amplifiers, the resulting gate
currents degrade the performance of current mirror
circuits. The combination of short channel effects and
gate leakages determines the optimum channel length
of the devices used for accurate current transfer ratio of
current mirror circuits. Further, we conclude that
cascode mirrors result in better current mirroring
operation even with the thin oxides.
Acknowledgements
One of the authors, Mr. K. Narasimhulu is
supported through a fellowship by Intel Corporation at
IIT Bombay.
6. References
1.0
[1] C. H. Choi, Ki-Yung Nam, Zhiping Yu, and Robert. W.
Dutton, “Impact of gate direct tunnelling current on circuit
performance: A simulation study”, IEEE Trans. Electron
Devices, pp. 2823-29, Dec. 2001.
(a)
tox ( nm )
0.6
1
1.2
1.5
2
3
0.4
1
[2] R. van Langevelde et. al., “Gate current: modelling, ∆L
extraction and impact of RF performance”, Proc. of IEDM
pp.289-93, 2001
V DS = 1.5 V
L G = 1 µm
W/tox = 4 µ m/3 nm
2
3
V DS ( V )
[3] Anne-Johan Annema et. al., “Analog Circuits in UltraDeep-Sub micron CMOS”, IEEE Journal of Solid-State
Circuits, vol.40, pp. 132-43, Jan. 2005.
[4] B. Razavi, “Design of analogue Integrated circuits”,
McGraw Hill Publishing Company 2001.
1.00
Iout/Iref
5. Conclusions
[5]. International Technology Roadmap for Semicon-ductors,
2002 updates.
tox ( nm )
0.95
[6] K. Narasimhulu, V. Ramgopal Rao, "Deep Sub-micron
Device and Analog Circuit Parameter Sensitivity to Process
Variations with Halo Doping and Its Effect on Circult
Linearity”, Japanese Journal of Applied Physics, April 2005.
(b)
1
1.2
1.5
[7]. ISETCAD Manuals. Release 8.0
W/L G = 4
0.90
V DS = 1.5
Iref = 100 µA
10
2
Gate Length ( nm )
10
3
Fig. 10(a). The current transfer ratio of as a function
output drain voltage for the cascode current mirror
having devices with gate oxide thickness of values shown
in the figure, (b) Iout/Iref versus gate length of the devices
used for the circuit simulation. VDS is kept at 1.5 V.
Proceedings of the 19th International Conference on VLSI Design (VLSID’06)
1063-9667/06 $20.00 © 2006 IEEE
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 2, 2008 at 05:14 from IEEE Xplore. Restrictions apply.