Effect of Fringing Capacitances in Sub 100 nm MOSFET's with
High-K Gate Dielectrics
Nihar. R. Mohapatra, A. Dutta, M. P. Desai and V. Ramgopal Rao
Department of Electrical Engineering, Indian Institute of Technology
Bombay-400076, India
Abstract
of the MOSFET capacitances. We have
extracted the gate to source/drain fringing
capacitances using a highly accurate 3D
capacitance extractor. We observe that the
inner fringing capacitances between the
gate and the source/drain play a key role in
degrading the short channel performance in
the case of MOSFETs with high-K gate
dielectrics. The potential impact of high-K
gate dielectrics on device short channel
performance is also analyzed in this paper
over a wide range of dielectric
permittivities.
In this paper we look at the
quantitative picture of fringing field efSects
by use of high-k dielectrics on the 70 nm
node CMOS technologies.
By using
Monte-Carlo based techniques, we extract
the degradation
in gate-to-channel
capacitance and the internal, external
fringing capacitance components for
varying values of K. Our results clearly
show the decrease in external fringing
capacitance, increase in internal fringing
capacitance and a slight decrease in
overall capacitance, when the conventional
Si02 is replaced by high-K dielectric. From
the circuit point of view the lower total
capacitance will increase the speed of the
device, while the internal fringing
capacitance will degrade the short-channel
pe8ormance contributing to higher DIBL
and drain leakage.
2. Simulation Setup
The capacitances are extracted using
a 3-D capacitance extractor. Here the
source, drain and gate are defined as cubic
conductors. The gate electrode length and
the source/drain electrode depths used are
70nm and 35nm respectively. A channel
plate is used to measure the gate to
substrate capacitance, which is kept at
15nm and lnm from the Si-Si02 interface
to represent depletion and weak inversion
conditions respectively. The gate dielectric
constant is varied from 3.9 to 200 keeping
the effective oxide thickness at 1.5nm. The
extractor solves the Laplace's equation for
the above electrode potentials using a
random walk algorithm [3,4] that directly
evaluates the interelectrode capacitance.
Device simulations to analyze the
short channel effects are done using a twodimensional (2-D) device simulator,
MEDIC1 [SI. The simulated structures,
which are fully scaled 70nm gate length
1. Introduction
Increased gate leakage is one of the
main limiting factors for aggressive scaling
of Si02 for deep sub-micron CMOS
technology [l]. Search is on for a suitable
high permittivity (high-K) gate dielectric,
which can replace SO2. However, it has
been shown recently that the higher
physical gate oxide thickness can result in
degradation of the electrical performance
due to increased fringing fields from gate to
source/drain [2]. In this paper, we have
attempted to gauge the impact of the gate
stack on the device by accurate simulations
0-7695-083
1-6/00$10.000 2000 IEEE
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Where, Cgpf and CgF' are the external
fringing capacitances, C g F and Cgdinf are
the internal fringing capacitainces of source
and drain respectively. as shown in Fig. 2.
MOSFETs following the technology
roadmap, are shown in Fig. 1. The
structures have a gate length down to
70nm. The source/drain junction depths are
fixed at 35nm. The device has a peak
channel doping concentration of 1.5x1Ol8
cm-3and a threshold voltage of 0.2V. The
permittivities of the gate dielectric are
varied from 3.9 to 200, keeping the
effective oxide thickness constant at 1.5
nm. The thickness of spacers used is 60 nm
on either side with Si02 as a spacer
material. To isolate the capacitance
degradation essentially due to the fringing
field, the effects of poly-depletion and
quantum mechanical effects are not taken
into account in the simulation.
-
-
y
1
Figure 1:
simulation.
'
t
Figure 2: Capacitances associated with the
device.
In Fig. 3, we show the variation of
Cofand C, with K value. The: figure clearly
indicates a decrease in Cof, an increase in
C, and indicating an overall decrease in
total capacitance with increasing K value.
The external fringing capacitance (Cof)
decreases due to the increiasing distance
(due to the higher physical oxide thickness)
traveled by field lines from gate to
source/drain for increasing K. This
decrease in Cofresults in reduced delay for
circuit operation. In the following figure,
'x' is the distance of the channel plate from
Woxide interface.
si02
High-K
C
I
1
Structures used for device
3. Results and Discussion
In Fig. 2, we show all the
capacitances associated with the device,
which are extracted from direct MonteCarlo simulations. The fringing capacitance
(C,)is the parallel combination of fringing
capacitance on the outer side (C,,f) and the
fringing capacitance on the inner side (Cs)
between the gate and source/drain
junctions, 'defined as
c, = c g s
........................
....................
....................
.(i)
--
I
0
I
0
Cf = C0f+
c,
exr
-Cof,
x = lnm
---....Cif, x = lnm
-.A-. Cof, x = 15nm
- 4- -. Cif, x = 15nm
50
100
150
K
(ii)
(iii)
Figure 3: Variation of external and internal
fringe capacitances with K.
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1
200
The higher C, in high-K dielectrics is due
to a larger number of field lines
of the
terminating on
the edges
source/drain depletion region. This induces
an electric field from source/drain to
channel reducing the barrier height as
shown in Fig. 4. We have also calculated
the barrier height for two different drain
biases, as shown in Fig. 5. Since the
threshold voltage (V,) of the device is
controlled by the injection of electrons over
this potential barrier, V, decreases with
increasing K as can be seen in Fig. 6 .
The variation of gate to channel
capacitance (C,J with K is shown in Fig 7.
0.25 7
h
0
c
0.2
L
$
3
9
-
0.15
c
0.1
r
0.05
F
01
50
0
100
200
150
K
Figure 6: Threshold voltage for varying K.
0.8
0.75
0.7
h
c
-
ev)
0.65
.-lu
E
a)
c
0.6
a
0.55
0
0 L-I
0.5 L
0
0.01
0.02
0.03
0.04
0.05
50
0
0.06
100
150
200
K
Distance from the Source (um)
Figure 4: Potential variation along the channel
for K = 3.9.
Figure 7: Variation of gate to channel
capacitance with K.
150
120
O
L
0
50
100
150
K
Figure 8: DIBL as a function of K .
Figure 5: Barrier height variation with K for
Vds = 0 and 0.8 volt.
As seen, C,, reduces with higher K,
decreasing the control of gate over the
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200
channel, which increases the 2-D effects.
This results in higher drain-induced-barrierlowering (DIBL) as shown in Fig. 8. Subthreshold slope also increases due to lower
C,, increasing the off-state leakage.
In this work, we have also extracted
the position of the virtual cathode (the point
where the total band bending from bulk to
the surface is minimum) for two dielectric
constants, from 2-D device simulation. The
distance of the virtual cathode point from
the source is plotted in Fig. 9 with different
drain biases applied.
l-K=3.9
I
I
device simulations and
Monte-Carlo
simulations. A quantitative estimate of the
fringing field effects has been provided for
the first time by extracting the various
capacitance components in the MOS
system from Monte-Carlo simulations.
From the circuit point of view, the lower
capacitances would reduce the delay, a
desirable effect, while the increased inner
fringing capacitances would degrade the
short-channel performance thus leading to
higher leakage currents and power
dissipation.
References
, - - - S -K=20OI
-
0.04 1
[l] H.S. Momose, M. ono, T. Yoshitomi,
“1.5nm Direct Tunneling Gate Oxide Si
MOSFET’s”, ZEEE Trans. Electron
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[2]
Baohong Cheng, Min Cao, Ramgopal
5 0.032
Rao, Anand Inani, P.V. Voorde,
c$
E
W.M.Greene, J.M.C. Stork, Z. Yu, P.M.
2 0.028
Zeitzoff, J.C.S. Woo, “The impact of
High-K Gate Dielectrics and Metal Gate
1
Electrodes on Sub-100 nm MOSFET’s”,
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0.02
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P. 1537, July 1999.
0
0.2
0.4
0.6
0.8
[3] Y.L. Lecoz, et al, ‘‘An improved
Drain Bias (Volts)
Floating-Random-Walk Algorithm for
Figure 9: Distance of virtual cathode point
solving
Multi-Dielectric
Drichlet
from the source with different drain bias for K
Problem”, ZEEE Trans. On Microwave
= 3.9 and 200.
Theory and Techniques, Vol. 41, No. 2,
P. 325-329, Feb 1993.
It is clear from Fig. 9 that in case of higher
[4] M. P. Desai et.al.,
“An efficient
K more of the field lines originating from
implementation of a 3 D capacitance
the drain terminate on the source rather
extractor”, Preprint, June 1999.
than on the gate reducing the peak barrier
[5] TMA MEDICI: Two-Dimensional
height and increasing 2-D effects.
Device
Simulation
program,
Technology Modeling Associates, Inc.
I
1
v
.c
~
4. Conclusion
The impact of high-K gate
dielectrics on device short channel effects
and performance is studied using2-D
Acknowledgements
This work is carried out under financial
support from INTEL Corporation, USA.
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