Device Optimization of Bulk FinFETs and
its Comparison with SOI FinFETs
C.R. Manoj, Meenakshi. N, Dhanya V. and V.Ramgopal Rao*
Indian Institute of Technology, (IIT) Bombay, Powai, Maharashtra, India 400 076
*
Tel: 91-22-2576-7456, email:[email protected]
II. SIMULATION DETAILS
-4
1x10
-5
1x10
-5
8.0x10
-6
10
-5
6.0x10
-5
-7
4.0x10
10
-5
2.0x10
-8
10
0.0
-9
0.0
0.2
0.4
0.6
0.8
VG (V)
(b)
Fig 1. 3D perspective view of the simulated bulk FinFETs and
(b) its 2D cross section
1.2
1.0
Stage Delay
Experiment - 23ps
Simulated - 22ps
2.N.Tp
0.8
0.6
0.4
0.2
0.0
-0.2
RO ouput using LUT approach
500.0p 1.0n
1.5n
2.0n
2.5n
Time (Seconds)
(a)
(b)
Fig 2. (a) Plot showing the calibration of the TCAD tool set
with default and tuned set of parameters (b) Matched ring
oscillator simulation results with the experimental data
To cross check the validity of our TCAD tuning
exercise we performed the circuit simulation of a 41
stage ring oscillator [6] using the Look Up Table (LUT)
approach [7]. The LUT data was generated from the
TCAD tool using the calibrated tuned set of parameters.
The stage delay of the fabricated FinFET ring oscillator
and that of the simulated one was found to be exactly
matching which validates our TCAD tuning exercise.
Table1. Table showing the dimensions of the devices used in
the simulations.
Lg (nm)
Fin width
(nm)
Tox (nm)
45
15
32
11
22
8
1.2
1.1
1.1
Spacer
Length
(nm)
VDD (V)
22
16
11
1.0
1.0
1.0
60nm
60nm
60nm
fin height
(nm)
1 E19
(b)
(a)
(c)
B ulk
1 E18
upper fin region
1 E17
Low er fin region
-0 .04
(a)
10
1.0
FinFET Ring Ocillator Output , Vout (V)
default
after tuning
experimental
ID in log scale (A/um)
-4
1.0x10
Doping #/cm
The structures used for bulk FinFET simulations are
shown in Fig 1(a) and (b). 3D simulations have been
carried out using well calibrated TCAD parameters for
the bulk FinFETs. Drift-Diffusion carrier transport
models are used [4] with mobility models accounting for
doping dependent and field dependent degradations.
The default parameters of the simulators are not suitable
for FinFETs especially because of their vertical nature
of the fins. This is because, the current flow is
dominated by (110) plane where the electron mobility is
lower compared to the (100) plane. We calibrated the
parameters such as mobility and contact resistivity by
benchmarking our TCAD simulations with a set of
experimental data of FinFET devices [5].
-4
1.2x10
3
FinFETs are the leading candidates for sub 32nm
technology node owing to their increased immunity to
short channel effects and better scalability [1]. Most of
the fabricated FinFETs are on SOI substrates. But
fabrication of FinFETs using the bulk CMOS substrates
instead of SOI technology is also of interest since it
reduces the process costs [2]. But bulk FinFETs have the
disadvantage of sub channel leakage for very short
channel lengths. Reported work on Bulk FinFETs, use
highly doped channel for preventing the leakage. Body
doping just beneath the fin is also considered a possible
way to prevent this leakage [3]. In this work, we
evaluate the effect of different body doping profiles in
un-doped channel bulk FinFETs, for controlling the sub
channel leakage and propose the optimization of the
same. We also bring out the other advantages of body
doping such as an increased immunity to body effect
from the circuit performance point of view. We also
show that device parasitics play a crucial role in the
optimization of nano scale bulk FinFETs.
ID in linear scale (A/um)
I. INTRODUCTION
0.0 0
0.04
0.08
D epth (um )
Fig.3. Plot showing the different body doping profiles used in
the simulations
978-1-4244-1728-5/07/$25.00 ©2007 IEEE
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10
10
-6
-7
6 .0x 10
-4
5 .0x 10
-4
4 .0x 10
-4
3 .0x 10
-4
2 .0x 10
-4
1 .0x 10
-4
-8
0.0
0.2
0.4
0.6
V g (V)
0.8
1.0
Fig. 4. Simulated Id-Vg of bulk FinFET with three
different body doping approaches considered.
-5
7.4x10
-5
7.2x10
-5
7.0x10
-5
6.8x10
-5
6.6x10
-5
6.4x10
-5
6.2x10
-5
6.0x10
-5
5.8x10
-5
5.6x10
-5
10
Ion
Ioff
16
10
17
10
18
10
10
-7
10
-8
19
Body Doping
Fig 5. Variation of Ion and Ioff w.r.t body doping showing
the optimum value of the body doping
48
DIBL
SS
120
SS (mV/decade)
3D simulations have been performed over a range of
proposed technology nodes, both for SOI FinFETs and
bulk FinFETs as shown in Table 1. FinFET dimensions
are optimally selected (see Table 1) such that the Ioff at
each technology node considered in this study meets the
ITRS requirements. In this work we compare three
different possible body doping approaches such as
profile (a), (b) and (c) as shown in Fig. 3. From Fig. 4 it
is clear that profile (a) is the worst among all profiles.
This is because high doping of 1x 1018 cm-3 present in
the channel causes degradation in Ion due to mobility
degradation. Also this heavy channel doping along with
the heavy S/D doping causes a significant increase in the
band to band tunneling (BTBT) current. In profile (b)
and (c) we apply the heavy body doping, only to the
lower portion of the fin (i.e. outside the channel) & deep
into the Si body unlike the previous work [1]. From
Fig.4 it is clear that profile (c) gives the best Ioff. This
approach shows that bulk FinFETs with lightly
doped/undoped fins can be realized even down to the
22nm node, with a deeper body doping profile. Another
striking advantage of the new body doping profile over
the reported doping profiles is that it will minimize the
sub channel gate leakage which could be a serious issue
for bulk FinFETs. Fig. 6 shows the variation of short
channel performance as a function of the value of the
body doping used. When we increase the body doping
initially we get improvement in DIBL and SS. But when
the doping level exceeds 1x1019/cm3, the leakage current
increases (see Fig. 5) owing to increased band-to-bandtunneling (BTBT) currents. Hence we propose that there
is an optimum body doping which is around 1x1018/cm3
.The study has been performed over a wide range of
technology nodes varying from 65nm node down to the
22nm node. From Fig. 7 it is clear that the body doping
approach is quite beneficial for scaled technology nodes
where the difference in Ioff between the SOI and the unoptimized bulk FinFETs becomes significant. The
approach presented in this work helps regain the
performance advantage with bulk Finfet technologies.
7.6x10
Ioff (Amperes)
10
-4
44
DIBL (mV/V)
-5
7 .0x 10
110
40
100
36
32
90
10
16
10
17
10
18
10
19
Body Doping (/cm3)
Fig 6. Variation of DIBL and SS w.r.t body doping
showing the optimum value of the body doping
3.0x10
-7
2.5x10
-7
2.0x10
-7
Ioff (A)
1x10
profile (a)
profile (c)
profile (b)
large portion of the physical fin height not to be
available for effective device width which is not
desirable. To study the impact of Tins on the leakage
performance, we performed simulations with Tins
varying from a lower extreme of 2nm to an upper value
of 150nm.
Ion (Amperes)
1x10
-4
Id-Vg , lin (A/um)
Id-Vg , log ( A/um)
III. RESULTS & DISCUSSION
1.5x10
-7
1.0x10
-7
5.0x10
-8
B ulk FinFET w ith N b= 1e18cm -3
Bulk FinFET w ith Nb=1e16cm -3
SO I FinFET
Ioff im pro vemen t
d ue to b ody do ping
20
30
40
50
60
70
Gate length Lg (nm )
Fig 7. Plot showing the Ioff variation w.r.t to different
channel lengths for SOI devices, bulk devices and bulk
devices with body doping applied.
Fabricated bulk FinFETs have a large value of
isolation oxide thickness (Tins) to minimize the parasitic
leakage under the isolation region. But this causes a
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500
400
300
200
100
0 20 40 60 80 100120140160
Isolation Oxide Height ,Tins (nm)
Fig. 8 Plot showing the variation of Ioff w.r.t Tins value
for the case (i) with body doping and (ii) without body
doping approaches.
80.0a
Cof + Cpar (F)
70.0a
(a)
(b)
Fig. 9. Figure showing the various parasitic capacitances
such as Cof Cif and Cpp present in the bulk FinFET.
32.0a
50.0a
30.0a
Cif with doping
Cif without doping
28.0a
40.0a
white symbols --with doping
dark symbols --without body doping
30.0a
26.0a
24.0a
0 20 40 60 80 100 120 140 160
Insulator Thickness, Tins (nm)
Fig 10. Variation of the extracted parasitic capacitances
as a function of Tins value for both body doped and
without body doping approaches
-7
2.0x10
1.5x10
Ioff (A)
0.204
square symbols--(without body doping))
circle symbols--(with body doping))
-7
0.200
-7
1.0x10
0.196
-8
5.0x10
0.192
0.0
0.188
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4
Vsub (Volts)
Fig. 11. Variation of Vt as a function of substrate voltage
with and without the body doping approaches
1.8
1.6
with spacer alone B
with passivation oxide & spacer C
10
8
1.4
Cgg (fF/um)
To confirm the increased fringing fields for larger Tins
values, we have extracted the fringing capacitance from
the bottom of the gate electrode to the lower portion of
the fin region. Fig. 9 shows the different parasitic
capacitances in bulk FinFETs such as the outer fringing
capacitance (Cof), the inner fringing capacitance (Cif)
and the parallel plate capacitance (Cpp). Cof is due to the
field lines terminating in the S/D and bulk Si regions
from the vertical sidewalls of the gate electrode region,
Cif is due to the field lines terminating in the lower fin
region from the bottom face of the gate electrode and
Cpp is due to the field lines terminating on the planar part
of the Si region. Fig 10 shows the variation of these
capacitances as a function of Tins values. As can be seen
from Fig. 10, when Tins is very small Cpp will be the
34.0a
60.0a
20.0a
With no body doping applied, the lower extreme of
Tins resulted in a higher leakage owing to the inversion
of Si region in the planar region of the devices (see Fig.
8). The leakage also increases heavily for higher values
of Tins owing to the fringing fields both from the gate
and drain regions into the lower fin region under the
gate region. We repeated the simulations with the
optimized value of the body doping reported in this
work and found that the variation in Ioff with respect to
the Tins is minimal unlike the undoped body case. This
means that with body doping approach we can actually
use a relatively shorter value for Tins. Hence with the
new body doping profile, we can use a larger fraction of
the actual physical height of the fin structure, for
increasing the effective device width (Weff) minimizing
the layout area. .
36.0a
Cof + Cpar with doping
C of +Cpar without doping
Cif (F)
Without body doping
With body doping
Vth (Volts)
700
600
1.2
6
1.0
0.8
4
0.6
0.4
50 100 150 200 250 300 350
Fin pitch (nm)
2
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Inverter Delay (ps)
Ioff (nA/um)
800
dominating parasitic capacitance among all other
components. However, as Tins increases the sum of Cof
and Cpp decreases logarithmically where as Cif will
increase linearly. This is due to the fact that, for larger
Tins values more field lines will divert into the lower
portion of the fin compared to the case with smaller Tins
values. This larger fringing field is not beneficial for
bulk FinFETs. From Fig. 10 it is clear that the body
doping also helps to decrease the Cif value at larger Tins
values. Fig. 11 shows another advantage of the body
doping approach from the perspective of body effect
sensitivity. With the body doping, it shows that the
already weak body effect in bulk FinFETs is further
suppressed, which is useful for circuit applications.
Although the amount of Vt variation with respect to
Vsub is smaller as compared to the planar devices, it
assumes significance since the absolute value of the Vt
at the 22nm technology node will be roughly 200mV.
Fig. 12. Plot showing the variation of Cgg value and
inverter delay (with FO=1), as a function of pitch.
We have also studied the effect of fin pitch on the
device parasitics in bulk FinFETs. Our simulations
show that passivation oxide has a profound impact on
the device parasitics. This is because of the 3D nature of
the device. Therefore, in the presence of the passivation
dielectric, there exists a significant component of
parallel plate capacitance between the gate electrode and
S/D electrodes. To understand the effect only due to
passivation oxide, we performed AC simulations to
extract the total capacitance at the gate terminal Cgg.
With no passivation dielectric present, Cgg showed the
expected behavior with fin pitch as it saturates after
some value of the fin pitch. However, with the
passivation dielectric present, it showed a linear increase
with the pitch, owing to the parallel plate nature of the
capacitance. To estimate the impact of this on the circuit
performance we performed mixed mode inverter
simulations with unity fan out. We find that the effect of
fin pitch on the inverter delay is very significant as the
parasitic capacitance (hence the delay) increases linearly
with fin pitch (see Fig. 12), owing to the proximity of
S/D & gate electrodes in nano-scale bulk FinFETs.
[6] Collaert N, Dixit A, Goodwin M, Anil K.G, Rooyackers
R., Degroote B, Leunissen L.H.A, Veloso A, Jonckheere R, De
Meyer K, Jurczak M, Biesemans S, “A functional 41-stage
ring oscillator using scaled FinFET devices with 25-nm gate
lengths and 10-nm fin widths applicable for the 45-nm CMOS
node”, IEEE Electron Device Letters, Vol. 25, pp. 568-570,
Aug. 2004.
[7]. Agarwal S.N, Jha, A, Kumar D.V, Vasi J, Patil M.B,
Rustagi S.C, “Look-up table approach for RF circuit
simulation using a novel measurement technique”, IEEE
Transactions on Electron Devies Volume 52, Issue 5, pp. 973
– 979, May 2005.
IV. CONCLUSIONS
With careful body doping optimization of bulk
FinFETs, we show that these devices can be scaled
down to the 22 nm technology nodes. Higher value of
body doping does not always give better Ion/Ioff ratio due
to the BTBT currents. Hence body doping needs to be
carefully optimized for bulk FinFETs to maximize the
Ion/Ioff ratio. The 3D nature of bulk FinFETs gives rise to
additional device parasitics, which need to be minimized
by scaling down the fin pitch.
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