Development of A 3D Simulator for Metal Nanocrystal (NC) Flash Memories under
NAND Operation
A. Nainani, S. Palit, P. K. Singh, U. Ganguly*, N. Krishna*, J. Vasi and S. Mahapatra
souvikgee.iitb.ac.in
Department of Electrical Engineering, IIT Bombay, India. *Applied Materials, USA. Email:
Abstract
A 3D simulator for metal Nanocrystal (NC) flash is
developed and verified with published experimental data. The
simulator is capable of extracting physical parameters and
predicting their impact on cell performance. The simulator is
used to optimize cell design and analyze performance with
scaling, NC randomness and NC numberfluctuations.
Introduction
NC Flash with metal dots have recently received
attention as a promising candidate to replace conventional FG
Flash [1-2]. Metal dots offer higher density of states leading
to better dot size scalability, also deeper quantum well for
improved retention. Use of high-k materials (especially for
control oxide) improves the program/erase (P/E) window.
Discrete nature of charge storage (in isolated NCs) results in
asymmetric enhancement of field near the NCs [3]; which in
turn enhances the tunnel current during P/E. There exists a
lot of literature on the materials and fabrication aspects of
metal NC devices [4], but not much to understand
electrostatics (in 3D) and explore cell design. In this work we
report the development of a simulator for predicting device
operation under NAND (FN) scheme, taking into account the
3D nature of NC flash. The simulator is capable of extracting
physical parameters (effective mass, barrier height, NC work
function) by matching experimental data and predicting their
impact on device performance. Simulation results are verified
with experimental data for a variety of stacks [2, 4].
Impact of cell design on write speed (Tp) and P/E
window (AVT) is studied for variations in tunnel oxide (TO),
control dielectric (CD), NC dot diameter ((p), and NC density
(area coverage). Effect of channel length (L) and width (W)
scaling is analyzed. Effect of randomness in NC placement
andand
NC
number
which have been perceived as
C nuberfluctuations,
challenges to scaling, is quantified.
Simulator Flow
I
.
1-
I II/
1-
1-4244-0439-X/07/$25.00 © 2007 IEEE
I
Simulator Verification and Stack Optimization
Experimental transients for Au dots in SiO2 [4] at
different program voltages are predicted reasonably well by
the simulator (Fig. 4a) using published values of physical
parameters in SiO2. The saturation AVT's are matched for Au
NCs (cp=5nm) in sio2 [4], Ag NCs (cp=6.6nm) in SiO2 [4]
and W NCs (cp=5nm) in HfAlO [2] (Fig. 4b).
Table-I compares 4 different gate stacks for Pt NCs
(cp=5nm, TO=4nm, CD=l nm and area coverage= 25%). An
all SiO2 stack gives small AVT and is slow to program. An all
high-k (A1203) stack offers comparatively larger AVT (lower
coulomb blockade) and faster programming (but reliability is
a concern using high-k for TO). AVT can be optimized using
SiO2 as TO and A1203 for CD. Embedding NCs in SiO2 as
compared to A1203 (Table-1, row (3) vs. (4)) increases AVT
as inter dot coupling reduces (Eq.1). Scaling TO thickness
significantly impacts programming speed (Fig. 5). A thinner
TO results in higher program current and more AVT for a
given charge in NCs, though reliability concerns would likely
put a lower limit of 4nm. Scaling CD keeping field constant
pualoelitof4mScinCDkpngildosat
decreases AVT slightly while the speed remains unaffected
(Fig. 6).
W, L and Dot
NC dots are taken to be spherical in shape and a
combination of dielectrics can be placed for TO and CD in
the gate stack (Fig. 1). (1) Device structure is generated using
specified parameters and dots are placed using Monte Carlo
with a specified maximum 0/0 of randomness. (2) At any time
step, charges on the NC dots can be related to dot potentials
using the capacitances with gate, substrate, S/D, and inter-dot
capacitances as per Eq.l [5]. FASTCAP [6] iS used to extract
.
the capacitances. (3) For a given NC potential, an analytical
description of the potential distribution between two adjacent
conductors (at a time) is made using Bispherical co-ordinates
(described in detail in [7]). (4) This potential distribution is
used to calculate the in/out and inter-dot (with neighboring
dots only) tunneling currents as described in Fig. 2. Coulomb
blockade is accounted for in calculating the currents while
quantum confinement is ignored as NC dot size below 4nm is
not considered. (5) NC dot charges are updated using the
currents obtained in (4), and (2)-(4) are repeated till charge
saturation or end of simulation time. (6) The charge transients
are given as input to the device structure generated in
SENTAURUS [8] to extract VT. Fig. 3 summarizes the flow.
1_\
.1
size, scaling
Time evolution of NC dot charges ( 4Onmx4Onm
device with Pt dots, cp=5nm) shows corner and edge dots both
at the S/D and channel edges get charged more as compared
to dots in center (Fig.7). This iS due to higher cou-pling of
(acrnter!eg doths withthgeates andessebrs winter do couplngrdo
( etrdthsegtnaetnihoswieacre o
ol a he)trsi q .ATicesssihl mr
importantly does not degrade) with L and W scaling (Fig. 8).
947
This can be attributed to the increase in percentage of edge
NC dots with scaling, which store more charge as compared
to dots in the center. This trend was observed experimentally
as reported in [5]. Scaling dot size from 6.6nm to 4nm while
keeping area coverage constant (at 25%) does not impact AVT
as reduction in charge per dot is compensated by increase in
the number of dots (Fig. 9).
Randomness in dot placement
Fig. 10 shows Monte Carlo placement of NC dots
(cp=5nm) with 20% and 3000 randomness (maximum allowed
2D variation in dot placement as compared to average interdot distance) in a W/L=40nmx40nm cell. The spread of AVT
increases slightly with increasing randomness from 20% to
400/ across 100 samples, but remains within 0.3V for a high
400/ randomness (Fig. 11). This immunity to randomness in
NC placement can be explained by the self consistent nature
of the device. As NC dots move away from each other the
inter dot coupling reduces and gate coupling increases, which
increase the charge on the dots. Similarly if NC dots come
close the inter dot coupling increases and gate coupling
decreases, resulting in lower charge on the dots. Overall there
is little effect on the AVT and programming transient (not
shown). We observe that for a fixed randomness (300/O)
increasing the number of simulations from 10 to 103 has little
effect on the spread of AVT (Fig. 12), extrapolating to 106
samples we still expect spread to be contained within a small
window.
Area Coverage and retention after Hard Breakdown
Missing dots
Effect of a dot missing is studied on systems having
a few (9-16) NCs (Fig. 15). A NC missing from the S/D end
and corner is worse than NC missing from the channel edge
or center (Fig. 16). For a 30nmx30nm (9NCs) system, worst
case fall in AVT is 6.9% when an edge dot is missing, which
is less than the expected 11% (1 in 9 dots). This can be
explained again from the self consistent nature of NC Flash.
The neighboring dots of a missing NC get charged more as
they now see lower inter dot coupling and higher coupling to
the gate. Further improvement can be obtained by scaling the
dot size (increasing the no of dots from 9 to 16) as shown in
Fig. 16, as AVT window remains unaffected by dot size
scaling (Fig. 8).
Summary and Conclusion
To summarize a 3D simulator is developed and used
to explore the performance optimization of NC flash cells.
We observe that large AVT with fast programming is possible
using an optimized cell design. NC Flash is predicted to scale
well with W/L due to fractional increase in the percentage of
edge dots which store more charge. NC flash is shown to
posses an inherent immunity to randomness in the dot
placement and missing dots making it an excellent candidate
for NAND MLC application.
Acknowledgements
G. Mukhopadhyay (Dept. of Physics, IIT-Bombay)
for help in formulation of electrostatics. Synopsis for
donating SENTAURUS licenses to IIT-Bombay.
Programming becomes faster on reducing the area
coverage (NC density) as sparser dot couple more with the
References
gate (Fig. 13). Saturation AVT (inset, Fig.13) first increases
(as no. of dots in a given area increases), then saturates (dot
crowding reduces the coupling with the gate while inter-dot [1] Z. Liu, IEEE Transactions on Electron Devices, vol. 49,
coupling increases) and finally falls (as the device approaches pp. 1606-1613, September 2002.
[2] Samanta et al., IEEE International Electron Device
FG) on increasing the area coverage.
The impact of charge loss from a set of NCs due to Meeting 2005, pp. 170-173, December 2005.
inter-dot tunneling to a particular NC on a breakdown path [3] C. Lee et al., IEEE Electron Device Letters, vol. 26, pp.
(see Fig. 15), increases on increasing the area coverage (Fig. 879-881, December 2005.
14). A 25 00 area coverage (cp=5nm Pt NC dots, embedded in [4] C. Lee, PhD Thesis, Department of Electrical
A1203 CD with SiO2 as TO) results in 10% AVT closure in 10 Engineering, Cornell University (2004).
years after the breakdown occurs. However, embedding the [5] P.K. Singh et al., IEEE International Conference on
NCs in SiO2 results in higher barrier for inter dot tunneling Physical and Failure Analysis 2007, pp. 197-20 1, July 2007.
and reduces the inter dot coupling. For Pt NCs (cp=5nm) [6] FASTCAP
embedded in SiO2 with A1203 as CD, 10% AVT closure in 10
years after the breakdown occurs can be met with area [7] A. Nainani et al., IEEE International Conference on
. .
.
.
O
Meoy Technology
T
aand Design 2007, pp. 25 1-254, May
coverage of 3600. As seen previously embedding dots in Si02 ~~~~~~Memory
2007
(Table-1, row (3) vs. (4)) increases the overall AVT window.
[8] TCAD tool chain from Synopsis.
[9] Z.H. Huang et al., Physical Review Letters, vol. 41, pp.
3 1-41, January 1990.
"http://www.rle.mit.edu/cpg/research-codes.htm".
948
~ ~>
-C13 ....Cln
VI')
CTI Cl- C12
I -Cl2-Cl3
-Cln) (VI
C2n V2
-C21 CT2 -C23
-C31
-
WCnI
C32
Cn2
CT3
- C3n
C3.
Where,
CT
Q + QFI
(I+Qfit
Q2 + QF2
|NCCFRWIH1
FOR WICH
V3 = Q3 + QF3
Vn
I=
GATE
A
CAPACIATNCES
f(fT(E, x)2mdx)S(E)dEt
0
)/
OUTx|
T(E, x) = Tun. Probablity
EXTRACTED
S(E)
=
Supply Function
Qn +QFn
i
CTI=L C
l+CG i+CBi +CD + CS,
QFi
=
INTER-DOT
CGi VGi + CBi VBi + CDi VDi + Cs, Vs,
Random placement of
_
FASTCAP [6] to extract
capacitances - inter-dot,
ith gate, src, drain, bulk
<
Sat./
5
|
(a)
(a)
2nmn
CD = 27nm SiO2
30
3.0L
TO
2.5
Use 3D Electrostatics [7] and
WKB [9] to calculate the
tunneling currents - in / out/
inter-dot. Update charges and
time elapsed
1 .5
- --VG=8Vsim
* VG=8V exp
VG=12VSm
< v*G=12VAexp
, tG=o o L 4~~~~~~~~~~~
0.5
A V
0.0
10-7
104-6
1-5 10-4 10-3
time (s)
1o-2 no-1
S
2 Simulation
IExperiment
Au in
Sio2 Ag in SiO2
7
8
1.2
0.8L
0
l 0.4
0.4
1 00
pI
8
12 16
9
8
Programming Voltage
12
Fig. 4. (a) Simulated and experimental transients for Au NCs [4] (dot size=5nm,
density=4x1 011/cm2). (b) Saturation AVT's are matched with simulation for various stacks of [2,4].
8
6
CD-I
Im Al02
5nm Pt NCs V20V
23
nm3'
G
TO=4nm
SiO~~~7- 5n t C
5 --l- TO =4nm
-0--TO =5nm
4
6
TO =6nm
5-
>43E
4
2
1
2
CD
L-
1
0°
0
10-8 10-7 10-6 10-5 10-4 10-3 10-2 0- 1 100
Fig. 3. Description of Simulator Flow.
>
G
G1
6V sim
3-
Charge transients for> 2
NCs. VT extracted using
SENTAURUS
.
.
'TO =SiO
_j
(b)
(b
24
2.0
< 1.0
05
end of
3.2 W in HfAIO
SiO2
=
>
Compute Dot Potentials using
Capacitance matrix & Charges
I
t on the dots [Eq. 1]
x
Fig. 2. WKB is used to obtain tunneling currents
integrating for all electron energies and tunneling
paths obtained from Newton's laws of motion [9].
Fig. 1. Structure used for simulations.
Eq. 1. Relating dot charges with potentials on
the dots. FASTCAP [6] is used for capacitance
extraction.
~~~~~~~~~~~IN
SUBS.
SID
time(s)
10-8
io-7
CD =
A
3
15nmV =24V
CD=11nmrVG20V
10-6
io-5 io-4 io-3
time(s)
10-2
10-1
Table 1. Comparison of different gate
Fig.5. Changing tunnel oxide thickness effects the Fig.6. Scaling control oxide keeping fields
stacks with Pt (5nm) NC's, and fixed
program speed greatly. AVT of 5.7V in less then constant, reduces AVT slightly, but has little
tunnel (4nm) and control oxide (11 nm)
.1 ms possible using 4nm Si02 as tunnel material. effect on programming speed.
C/CQ
physical thicknesses and area coverage
(25%). (3) dots embedded in A1203 (4)rQ(
dots embedded inSiO2
t=180.5ms
Tunnel Control AVT(
4xn
(1
4x11
4xFo
Tp
)
3x a o
(4nm) (1
r
(is) VG=20V.
V
V nE
x118
2x1018
T
2
SiO2
SiO2
)Isg(NC)
A1203 A1203
4.3
1.2
o
6.1
0.08
*
*
1X10-18
1X10188
o
7 * t
A
6
.
AvA
A
_
U-- Ers
--M-- ErsVT
W
> 4 L Scaling
WScaling
H W=4Onm ~~~-W-Program VTL4n0
<13
t
2L
.
.
*
l
1
6.0 W/L=40nm/40nm
[TO= 4nm SiO2, CD= 1 1 nm Al23
5.8
_
.
0
AVT
*
.
_
*
*
6x10*18
9 ots
80
-565xl01
a)Xx
VT
>Erase
Program VT
*
7x108
t * VT shift
52 F
.
*
5.2
*
4x100
<5
0 16 dots
-u-Charge /dot 3118
x
T
/
25dots
60 70 80 90
30 40 50 60 70 80 90
5.0
4
5
2x10-18
6
W (nm)
dot size (nm)
L (nm)
Fig.8. AVT increases with L & W scaling, as % of edge dots which store more charge than Fig.9. AVT remains constant scaling the dot size
dots in center increases with scaling.
keeping area coverage constant (25%).
30
40
50
20 % Randomness
25
@10*
0
*@M
.
(a) 20%
(#>20
*
4,
Fig.10. Placement of dots in a 40nmx40nm
device with different % of randomness
W/L;=40nm/40nm
101 GDO=1nmAl2O2.~m
0n
14
30%nO
2
o10 |
5.4
5.6
5.
AVT(V)
6
4
6.2
Fig.12. For fixed randomness (30%)
increasing number of simulations from 10 to
1 03 does not effect the spread of AVT .
.05.556
.5
.557
AVT (V)
5.8
5.8
AVT (V)
randomness the tail bits are contained in a 0.3V window.
2 / *.C0
E
20 30 40 50 60 70
()
38%5
& 80
31%
-
raCvrg
25%/-
F8
nmA
% are coverag t;$4
n
6.0
.057
AVT (V)
|___
,,3
TO,,nm/pSiO2,,
3
10
5.2
0~) 0
Figli . The AVT spread increases slightly with increasing randomness. Even for 40%
Randomness
=
20-
.0w.558W.556Z56
~~~~~.056
40 % Randomness
25
20
0
(b) 30%
30 % Randomness
25
0-8
10
07
10
,,,, ,,,
A ~
1 0-
1
i05 04
c
time (s)
,,,
A
K /-0m4n
2
1 0-
12
Fig. 13. Effect of area coverage (dot density)
on AVT and programming speed.
11 I tstt: *
F~~
W
102
0n
n
103 104 105
106
time (s)
107 1 08
10
Fig. 14. Effect of hard breakdown. 25% area
coverage (Snm NCs) results in 10% AVT
closure in 10 years post hard breakdown.
~~~6 _30x30nm, 9NCs(5nm)
D s
Center
Oh. Edge Corner SID Edge
Fig. 15. Figure labeling the positions of the dots. Arrows show the
current flow due to inter-dot tunneling in case of hard breakdown on
the center dot.
Position of the missing NC
Fig. 16. Effect of a missing dot is studied for devices having a few (916) NCs. For a 30nmx30nm (9NCs) system, worst case fall in AVT iS
6.9%, less then expected 11% (1 in 9 dots).
950