Reliability of Ultrathin JVD Silicon Nitride MNSFETs Under High Field Stressing K. N. ManjulaRani, V. Ramgopal Rao and J. Vasi Department of Electrical Engineering, Indian Institute of Technology, Bombay Mumbai 400 076 INDIA email: rani@ee . iitb.ac . in Abstract- In this paper, we study the reliability of n-channel MetalNitride-Silicon FETs fabricated using ultrathin Jet Vapor Depusiled (JVD) Silicon Nitride gate dielectric under constant voltage stressing. Due to the s t m . shills in thmshold voltage and tramconductance as well as interface slate generation are observed. Our study shows that dogradation is polarity dependent. MNSFETs show lower degradation when the applied strrps voltage is positive. We have also compared the performance of MNSFETs with conventional MOSFETs under identical s t i e s mnditiam. Under p i tive stmsing, MNSFETs clearly outperform L e MOSFETs hut under negative stressing MNSFETs show mom degradation. I. INTRODUCTION Alternate high-K gate dielectrics are needed to replace conventional SiOl in MOS transistors. Some of the alternative gate materials that have k e n investigated are silicon nitride, and tantalum, hafnium and zirconium oxides. However, the degradation and reliability of high-K dielectrics need to he explored in depth. Jet Vapor Deposited (JVD) Si3N4 has shown promise as an alternate dielectric with improved hot carrier performance as compared to conventional MOSFETs [I]. It has been shown to be resistant to boron penetration [2]. Conventional MOSFETs with ultrathin SiOz gate dielectric have shown increased interface state generation under high-field stressing causing gm and Vth shifts. In MOSFETs, the degradation and hence the charge-to-breakdown Q B D is known to he polarity dependent [3]-[7]. In this paper, we study the polarity dependent reliability of n-channel MNSFETs and compare performance of MNSFETs with MOSFETs under equivalent stress fields. Fig. 1. Re-suess Id-Vgsand gm charactenstics of MNSFET and MOSFET data. The charge pumping current was measured by applying a trapezoidal waveform of lMHz frequency to the gate-with a rise and fall time of 25011s. N,, was calculated from the charge pumping current. IV. RESULTS 11. DEVICES The devices used in this study are n-channel, n+ poly-Si gate transistors fabricated using an identical CMOS process except the gate deposition process. One set of transistors has Si3Na as the gate dielectric deposited using the JVD process[2] followed by annealing at 800°C for 25 min in Nz (referred to as MNSFETs). The second set of transistors has SiOz grown at 800°C followed by an in-situ anneal in Nz (referred as MOSFETs). The MNSFETs have an Equivalent Oxide Thickness (EOT) of 3.lnm and the MOSFETs have a gate oxide thickness of 3.9nm. The transistors have W x L = l o x 0.18pm2. 111. EXPERIMENT A. Prestress characteristics of MNSFETs and MOSFETs The pre-stress Id-V,., gm-Vgaand charge pumping characteristics of MNSFET and MOSFET are compared first. The prestress Id-V,. and gm-Vgacharacteristics of the transistors are shown in Fig 1. Both g, and Id are normalized with CO=.The threshold voltage of MOSFET and MNSFET obtained from the maximum slope of Id-Vda characteristics is 0.43 and 0.47V respectively. The pre-stress transconductance g,,, of MOSFETs is comparable to that of MNSFETs. The prestress I, is shown in Fig. 2. The average pre-stress N;, is of the order of 12x 10'ocm-z in MOSFETs and ahout4-6x 10" cm-2 in MNSFETs. The MNSFETs and the MOSFETs have comparable prestress characteristics except for the interface state density N i t which is slightly higher in the case of MNSFETs. The transistors were subjected to high-field stressing with constant voltage applied to the gate with the source, drain and substrate grounded. The stress was interrupted periodically to monitor the changes in the gate threshold voltage Vlh, transcon- B. Post-stress performance of MNSFETs and MOSFETs ductance gm and Nil. The values of Vth and gm were obtained The performance of MNSFETs and conventional MOSFETs from the Id-Vgs characteristics measured at a drain bias of 50 is illustrated under identical equivalent positive stress of +12 and mV. The peak transconductance was calculated from the Id-VgB +14MV/cm. -AN,t defined as ( N ; l - N ; t , ~ is)plotted in Fig. 3. 0-7803-7722-2/03/$17.00 02003 IEEE. 168 Proceedings of IO' IPFA 2003, Singapore Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 2, 2008 at 05:18 from IEEE Xplore. Restrictions apply. Fig. 2. Pre-suess I,, plotted w . a function of Vios. Fig. 3. Comparision of effect of positive Stress 6 elds on N t in conventionnl MOSFETsandJVDMNSFETs. AN;t = (.N,,-Nit,o) i s plotted as a funtion of lime. Ag,,, which is defined as I(gmoz-gmoz,o)lis shown in Fig. 4. It is clear that for positive fields, MNSFETs show better performance compared to MOSFET’s. Next, we compare the performance of MNSFETs with MOSFETs under negative stress fields equal to -11 and -1ZMVlcm. The change in Nit, A n i t is plotted in Fig. 5 . The change in g, is shown in Fig. 6. We can see that for negative stress fields, MNSFETs do not always outperform MOSFETs. C. Polarity dependence ojpost-stress MNSFETs The stress voltage polarity dependence in MNSFETs is illustrated for effective fields of +lZMV/cm and -12MVkm respectively. The charge pumping current Icp and drain current Id-vgb is illustrated in Figs. 7, 8, 9 and 10 respectively. The charge pumping current for positive stress is lower than that for negative stress by a factor of 4. The change in threshold voltage is also lower for positive stress. The normalized increase in Nit defined as (Nit-Nit,o)/Nit,o. transconductance ((gmoz-gmaz,O)(igmoz,o and threshold voltage (&h-&h,O)/&h,O are plotted as a function of stress time in Fig. II . We can see that compared to gate positive stressing, gate negative stressing produces higher Nit, g, and V t h shifts. V. DISCUSSION With varying stress time, ANi, and Ag, show power law (crt”) dependence for both MNSFETs and MOSFETs for both positive and negative stress. For positive stress (inversion), the exponent value n for MNSFETs varies between 0.35-0.38 for AN,, and 0.3-0.4 for Ag, which are similar to the n value (0.3) observed in p-MNSFETs subjected to constant voltage FN stress under inversion [8]. Our results show that under gatepositive stress (inversion), MNSFETs show lesser ANjt degradation than MOSFETs which has n value of 0.53. We can see that both the magnitude and rate of degradation is smaller for MNSFETs for positive stress. In case of MNSFETs, values of n for A&, is about 0.3-0.4 which is almost same as n values of ANil. In case 0-7803-7722-2/03/$17.00 02003 IEEE. Fig. 4. Camparision of effect of positive stress fields on & in MOSFETs and I V D MNSFETs. Ay, = l(ymo,-ymor,o)l i s plotted as a funtion of time. of MOSFETs, values of n are about 0.4-0.46, slightly lower than that of ANil. Compared to MOSFETs, MNSFETs show lower magnitude and slightly lower values of n. Fig 3 and Fig 4 clearly illustrates that JVD nitrides perform better than MOSFETs under positive gate voltage stress. The threshold voltage Vth is an important parameter in the operation of a transistor. Both interface states and bulk trapping-contribute to the variation in the threshold voltage. We have separated the two contributions and plotted AVit and AV,& Figs. 12 and 13 respectively. AKt shows power law dependence for both MNSFETs as well as MOSFETs. In case of MNSFETs, AVOt.inirially increases rapidly and saturates suggesting that there are bulk traps which are filled up during stressing. This behaviour rules out bulk trap 169 Proceedings of I d IPFA 2003, Singapore Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 2, 2008 at 05:18 from IEEE Xplore. Restrictions apply. J V O MNSFET, E = + l Z M V i c m 10X0.18L" t0,=3.?n m ( E 0 T ) 20.10- 0.0 -0.5 0.0 0.5 1.0 1.5 V,~(VOltS) Fig. 5. Comparision of effect of negative suess fields on Nt in conventional MOSFETs and IVD MNSFETs. A N ( t = ( N i t - N i t , ~is) plotted a a funtian of time. Fig. 7. I,, platted a a function of stress time for a JVD MNSFET stressed at E=+12 MVIcm. 'or0 0 JVO MNSFET(E--IIMVlsm) MOSFET (E=-l?MVlcm) JVD MNSFET (Es-1IMVlcm) MOSFET (E--lIMVlcm) 4 5 0.0 0.5 1.0 1.5 Fig. 8. I,, plotted as a function of stress time far a JVD MNSFET stressed at E=-I2 MVIcm. Fig. 6. Comparision of effect ofnegative mess fields on &, in MOSFETs and JVD MNSFETs. Agm= l(gmaz-g.,,.,=,o)l is plaaed,as a funtion of time. generation. In case of MOSFETs, the initial bulk trap density is lower. With stress, MOSFETs show bulk trapping which increases with time, indicating that there is trap generation. Under negative stress, the magnitude 4 N i t is higher for MNSFETs than MOSFETs. The exponent is about (0.3) for nitrides compared to MOSFETs (0.4). The exponent value of 4g, is 0.3 for both MNSFETs and MOSFETs but the magnitude is lower for nitrides: Under negative voltage stress, MOSFETs show positive charge trapping while MNSFETs show net negative trapped charges. The degradation of Vth is higher in MNSFETs than M O S E T s as illustrated by Fig. 14 and Fig. 15 respectively resulting in degraded performance of MNSFETs. MOSFETs also show polarity dependent degradation as 0-7803-7722-2/03/$17.00 02003 IEEE. shown in Figs. 3, 4, 5 and 6. Here also we see that the damage due to negative stress is higher compared to the positive stress. Polarity dependent degradation in ultrathin MOSFETs is attributed to the defects in the gate/dielectric interface[4], presence of a structural transition layer at the substrate/dielectric interface[5], or due to the difference in the electron energy dissipated at the anode which in turn depends on the anode Fermi level [6], [7].According to the anode Fermi-level model, damage is maximum for p-type anodes where the electron impact generates hot holes. The defect generation rate is higher when the density of holes is larger in the anode [9]. We have used the AH1 model to explain the polarity dependent degradation in MNSFETs. The band diagram of MNSFET in accumulation and inversion is shown in Fig. 16. MNSFETs show lesser 4 N i t and 170 Proceedings of IO" IPFA 2003, Singapore Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 2, 2008 at 05:18 from IEEE Xplore. Restrictions apply. J V D MNSFET. E=+1PMVlcm 10'' 1.,=3 lnm(E0T) Tlms(aes0nds) Id-V,, plotted as a function of stress time for a JVD MNSFETs stressed BI E=+12MVkm. Fig. 9. Fig. I I. Pal8rity dependence of degradation of max. nansconducE=llZlMV/cm. Normalized transconduclance l ( ~ ~ . . - ~ ~ ~ = , o ) plotted l / ~ ~ as ~ a= function , ~ of time. tance in JVD MNSFETs at JVD MNSFET.E=-l ZMVIcm ta,=3.1 nm(E0T) Fig. IO. Id-Vgaplotted as a function of stress time for a JVD MNSFETs stressed at E=- I2MVIcm. Fig. 12. Effect of positive smss fields on AV;, in conventional MOS 4g, degradation than MOSFETs under positive stressiing. This may be due to the higher bond breaking energy of Si-N bonds. However, under negative stress 4Nit and AKh shifts are higher than oxides which may be due to the increased hot-bole flux due to the smaller hole barrier height in nitrides (1.9eV as compared to 4.9eV). If an electron arrives with an energy of 3eV, impact ionizes to create a hole with a maximum energy of 3-1.1=1.9eV comparable to the SiNfSi barrier of 1.9eV. Compared to this, hole flux in SiOz/Si would be smaller where barrier height for holes is 4.9eV. VI. CONCLUSION MNSFETs perform better compared to the MOSFET's under positive bias which is important for n-channel devices. The 0-7803-7722-2/03/$17.0002003 IEEE. FETs and JVD MNSFETs plotted as a funtion of time. nitrides show smaller Nit generation compared to the oxides under identical fields. The transconductance degradation is lower compared to MOSFETs. Also there is no bulk trap generation in MNSFETs and hence threshold voltage shifts are also smaller. We can therefore conclude that the JVD MNSFETs can easily out perform MOSFETs under gate positive condition, that is when the transistor is in inversion. However the degradation of Vth in MNSFETs is larger compared to MOSFETs under negative stress fields, that 'is when-the surface is in accumulati& although transconductance degradation is lower. By controlling the initial bulk trap density, JVD MNSFETs can be expected to outperform MOSFETs. 171 Proceedings of 10" IPFA 2003, Singapore Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 2, 2008 at 05:18 from IEEE Xplore. Restrictions apply. 0 0 0 / I Fig. 13. Effect of positive mess fields an Vet in conventional MOSFETs and JVD MNSFETs plotted as B funtion of time. Fig. 15. Effect of negative stress fields on AV,{ in conventional MOSFETs and JVD MNSFETs plotted as a funtian of time. Gate I i Si Fig. 14. Effect ofnegative stress 6 eldson AV;, inconventional MOSFETs and JVD MNSFETs plotted as a funtian of time. Fig. 16. Band diagram of a NMOS-MNS transistor under a) Accumulation and hilnvsnion. VII. ACKNOWLEDGEMENTS We would like to thank Prof. J. C. S. Woo, UCLA for the .p, Ma, Yale university for JVD deposition. samples and 151 [6] REFERENCES 111 121 [31 141 S . Mahapam V. Ramgopal Rao. K. N. ManjulaRani. C. D. Parilih, J. Vasi, B. Cheng, M.Kharc. and J. C. S. Ww. "IWnm channel length MNSFETs using a Jet Vapor Deposited Ultra-Thin Silicon Nimde Gate Dielecmc,"Symp. VLSI Tech. Dig..June 1999,pp. 79-80. T. P. Ma. "Making Silicon Nitride 6 h a viable gate dielecuic:' IEEE T m .Elecrmn Devices, vol. 45, pp. 680-690. Mar.1998. 1. H. Shiue et. al. :'A shldy of interface trap generation by FowlerNordhiem and Suhsuate~Hot-Carrierstresses for 4-nm thick g m oxides:' IEEE T m s . Electron Devices vol. 46, p. 1705, 1999. Y. Hokari,"Suess voltage polarity dependence of thermally grown thin 0-7803-7722-2/03/$17.00 02003 IEEE. [71 181 [9] 172 gate oxide wear-out:'IEEE Trans. Elecrmn ~ e v i c e s ,vol. 35. pp. 12991304, Aug. 1988. L. K. Han,M.. Bhat et. al.,"Polarity Dependence of Diel&! Breakdown in Scaled SiO,,"IEDM Tech. Dit., pp. 617-620, 1994. D.J. DiMaria, "Explanation for the polarity dependence of breakdown in ultrathin silicon dioxide fi 1ms;Appl. Phys. Lett., 68 (21). pp. 3004-3006, 1996. Ernes1 Wn and Iordi Sune. "New insights in Polarity-Dependenl Oxide Breakdown far Ulmathin Gate 0xide:'IEEE Ekctmn Device Letters, vol. 23, pp. 494-496, 2002. lgar Polischuk, Qimg Lu. Yee-Chia Yeo, Tsu-Jae King and Chenming Hu,"InUimic Reliability Projections for a Thin JVD Silicon Nitride Gate Dielectric in P-MOSFET," IEEE Tms.on Devices and Materials Reliobiliry, vol. 1. pp. 6 8 . Mar 2001. J. D.Bude, B. E. Weir and P. J. Silveman,'%xplanatian of stress-induced damage in thin oxides," IEDM Tech. Dig., pp. 179-182, 1998. Proceedings of IO" IPFA 2003, Singapore Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 2, 2008 at 05:18 from IEEE Xplore. Restrictions apply.
© Copyright 2025 Paperzz