Analysis of Floating Body Effects in Thin Film SO1 MOSFETs
using the GIDL Currlent Technique
Mohan V. Dunga, Aatish Kumar, and V. Ramgopal Rao
Department of Electrical Engineering, IIT Bombay
IIT Bombay, Powai, Mumbai - 400076, India.
Phone: (91) 22-5767456 Fax: (91) 22-5723707 Email: [email protected]
Abstract: In this paper, we present an analysis of floating
body effects in lateral asymmetric channel (LAC) and
conventional homogeneously doped channel (uniform) SO1
MOSFETs using a novel Gate-Induced-Drain-Leakage
(GIDL) current technique. The parasitic bipolar current gain
p has been experimentally measured for LAC and uniform
SO1 MOSFETs using the GIDL current technique. The
lower parasitic bipolar current gain observed in LAC SO1
MOSFETs is explained with the help of 2-D device
simulations.
1. Introduction
An SO1 MOSFET with thin Si film offers several advantages
over bulk devices, which include reduced short-channel
effects, low voltage operation and increased current drive.
One of the challenges of SO1 CMOS technology is
understanding and controlling the floating body effects.
These effects are the counteraction of the perfect isolation
properties in a SO1 MOSFET and are caused by the majority
carriers that are generated by the high drain field and get
accumulated in the body. If the minority carrier lifetime is
high in the silicon film, the parasitic bipolar junction
transistor [l] present in the NPN structure of the MOSFET
amplifies the hole current generated by impact-ionization
near the drain. This further increases the net drain current
and is known to cause second kink in the drain current. The
lateral parasitic bipolar transistor gain p has a major impact
on the breakdown voltage of SO1 devices and is also
responsible for hysteresis and latch-up in severe cases.
LAC SO1 devices tend to offset these harmful effects by
reducing the drain field and thus impact ionization. In
addition to that, LAC devices also prevent short channel
effects like
roll-off, DIBL and reliability issues like hot
carrier effects. LAC SO1 MOSFETs therefore promise many
advantages over homogeneously doped SO1 MOSFETs [2][4]. It is thus necessary to examine how the floating body
effects differ in LAC SO1 from uniform SO1 MOSFETs. In
order to measure the lateral bipolar transistor current gain p
of LAC SO1 MOSFETs, Gate Induced Drain Leakage
(GIDL) mechanism has been used.
>o
Fip;.:Depletion regions in the gate-drain overlap
repion in SOT nnder GTnl, hias
&
Tunncling
clcctcon
Hole
Fig.: Band diagram near the gate-drain overlap
region under GIDL bias
Re:ferring to Fig. 1, this leakage current for negative bias is
due to tunneling current in the deep depletion region. In this
gate-to-drain overlap region, the tunneling of valence-band
electrons into the conduction band generates electron-hole
pairs. This occurs because of the high vertical electric field
in .the gate-drain overlap region. Fig. 2 shows band diagram
near the gate-to-drain overlap region at high
and device
in the off state or in accumulation.
v,
The GIDL current due to Band-to-Band tunneling follows
the: relationship given by [6]:
2. GIDL
In an n-MOSFET when the gate potential is very low or
negative, in which case the front channel is off or in
accumulation and a high drain potential is applied, tunneling
current flows from drain to substrate. Since this is a form of
undesired leakage current caused at low gate voltages it is
called Gate Induced Leakage Current (GIDL) [5].
0 - 7 8 0 3 - 6 6 7 5 - 1 /01/$10.00 0 2001 IEEE.
I
SUBSTRATE
I,,
= AE,
exp(- B / E ~ )
(1)
where A is a constant and B equals about 21.3 MVIcm. E,
can be expressed as
ET
254
= (VDC -
v,
)/(3TOX
)
(2)
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where V D=~(VD-V~).
VsUw is the surface potential of the
depleted region at the onset of B-B tunneling and is equal to
1.2 Volts.
significant, which is not the case with long channel devices.
This indicates a method for extraction of p for an SO1
device. By finding the ratio of drain currents of a short
channel device and long channel device under GIDL bias,
the value of p can be obtained. This is a very good method
since it does not require a body contact.
Due to the vertical field present in the overlap region, these
electrons and holes are collected by the drain and substrate,
respectively. As the gate voltage is made more negative or
the drain potential is increased, the vertical field increases
leading to an increase in GIDL leakage current. Reduction in
current was obtained for LDD devices under GIDL bias.
This is due to reduction in the electric field in the gate-drain
overlap region. GIDL was used earlier to characterise
interface traps and later on to measure oxide charge trapping
using GIDL transients [7].
I
I
\ -
SUBSTRATE
I
4. Results Obtained for Bulk MOSFET
The GIDL behaviour was first studied for Bulk MOSFETs.
Devices used in the experiments had channel lengths of 10
pm, 5 pm, 1 pm and 0.25 pm. A GIDL bias of -1.0 Volt was
applied and drain voltage was swept from 0 to 3volts. The
GIDL currents measured for different channel lengths are
shown in fig. 4. The GIDL current was more or less constant
with respect to the channel length. This indicates the validity
of the statement that GIDL remains constant with varying
channel lengths. This can be explained by the fact that
Band-to-Band tunneling depends on VDc and hence is
independent of channel length. Also, since the holes flow
into the substrate, there is no parasitic bipolar action in bulk
MOSFET. Thus, it is correct to assume that GIDL current
remains constant with respect to channel length.
I
I
I
Fig.: Schematic of current flow in a SO1 MOSFET
under GIDL bias
3. GIDL in SO1 MOSFET
The origin of GIDL remains identical even in the case of
SO1 MOSFETs [SI as in the case of bulk MOSFETs. The
front channel in the device is kept in off state or in
accumulation. Fig. 3 shows the schematic diagram of current
flow in an SO1 n-channel MOSFET in GIDL mode with the
front channel tumed off. The high electric field in the gatedrain overlap region causes electron tunneling fiom valence
band to conduction band. The electrons, as in the case of
bulk device, move out from the drain. However, the holes,
unlike in bulk device, cannot flow out to the substrate due to
the buried oxide present. As a result, the holes flow to the
floating body and forward bias the source-body junction.
This junction is the emitter-base junction of the parasitic
BJT. The GIDL current, thus, serves as the base current for
the lateral bipolar transistor as shown in Fig. 3. This GIDL
which is independent of the channel length, is amplified by
the gain of the lateral BJT. The resultant current at the drain
is thus given as:
Fin. 4: GIDL curre%yor bulk MOSFET with
GIDL bias of VG= -1 .O V
1.41
- 0.50 V
-V,=
-v,=-
1.oov
1E-5
1E-6
1E-7 h
9
-
1E-8-
0
lE-91E-10
1E-11
(3)
I
where p is the gain of the lateral BJT
0.0
0.5
.
I
1.0
-
I
1.5
'
I
2.0
'
1
2.5
.
I
3.0
VJV,
The current gain of the lateral BJT increases as the base
width decreases. Therefore, for short channel devices, p is
0-7803-6675-1/01/$10.000 2001 IEEE.
Fig. 5: GIDL current variation with Gate Voltage
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5. Effect of variation of VGon GIDL
Fig 5 shows the variation of GIDL current with change in
applied gate voltage. As the applied gate voltage VG
increases, the vertical field in the gate-drain overlap region
increases. This leads to an increase in the Band-to-Band
tunnelling current. Since the base current increases, the
resultant off-state leakage current also increases. The results
have been plotted for a Uniform SO1 MOSFET. Similar
trends were noted for bulk and LAC SO1 MOSFET also.
7. P'osults obtained for LAC SO1 MOSFET
F,b. 7 shows the output characteristics of uniform SO1
MOlSFET and LAC SO1 MOSFET. The kink effect in the
case of LAC SO1 MOSFET is exhibited at higher drain
voltages depicting a suppression of floating body effects in
these devices.
6. Results Obtained for Uniform SO1 MOSFET
GIDL experiments were performed to measure the lateral
parasitic bipolar gain present in the Uniform SO1 MOSFET.
The devices used had channel lengths 10 pm, .5 pm, 1 pm
and 0.25 pm. The gate oxide thickness was 3.9 nm and the
channel width was 20 pm. A GIDL bias of -1.0 Volt was
applied and drain voltage was swept from 0 to 3 Volts. The
drain currents measured for different channel lengths are
shown in fig. 6. As the channel length decreases, the offstate leakage current increases. For devices of lengths 10 pm
and 5 pm, currents are low due to an absence of lateral BJT
gain p. As the channel length decreases, the base width of
the lateral parasitic bipolar transistor also decreases. Hence,
the GIDL current is amplified and is higher than that for
long-channel devices. This can be seen for devices of lengths
1 pm and 0.25 pm in which currents are high due to the
presence of amplification factor. Comparing the devices of
lengths 10 pm and 0.25 pm, we see that for low VD, the
currents are equal. This is because p is very small at very
low collector current levels. The current gain p increases
with increasing collector current level. The value of p is
obtained using equation (3), assuming that IGrDLis constant
with respect to channel length. This was proved in the earlier
section using the GIDL currents present in bulk MOSFETs.
For VD = 2.7.5 Volts, the value of p is 28.75 for L = 0.25 pm
device and for L= 1 pm device, p is 1.52. Thus, the value of
p increases with decrease in channel length and the resultant
enhancement of off-state gate-induced-drain-leakage current
becomes significant for short-channel SO1 MOSFETs.
1E-5
4
1E-7,
0.0
1 .o
0.5
1.5
(v)
vDS
Fig. 7: Output Characteristics of LAC and
Uniform SO1 MOSFETs
In order to determine the efficacy of LAC SO1 in reducing
the parasitic bipolar action, GIDL measurements were also
performed on them. The devices used had channel lengths 10
pm, 5 pm, 1 pm and 0.25 pm. GIDL bias of -1.0 Volt was
appllied and drain voltage was swept from 0 to 3 Volts. Fig 8
shows the off-state leakage current trends in LAC SOL
Lateral parasitic bipolar gain was calculated using equation
(3). The value of p for L= 0.25 pm device is 5.6 and for the
L=l pm device, it is equal to 2.0. This measured value of p
is llower than that of uniform SO1 MOSFET. As the length of
the device decreases, the effectiveness of lateral asymmetric
channel doping increases. It thus shows that the LAC SO1
MOSFET shows immense promise towards reduction of p of
the lateral bipolar transistor and in minimisation of floating
body effects.
-
1E-6 1
-
1E-7 ;
--L
1E-5
L = 0.25 pm
4 - L = 1 pm
--L=5pn
-L=
10pm
1E-81
e
.
9
-P
1E-9 -
1E-8 7
L = 0.25pm
= 5pm
-L=
10pm
1E-9;
1E-107
1E-10,
1E-11
1E-11
1,-121
1E-12-4
I
0.0
0.5
'
I
1.0
'
I
'
1.5
I
2.0
'
I
.
2.5
2
0.0
VJV)
1.0
1.5
2.0
2.5
3.0
V,(W
Fip. 6: GIDL current enhancement in uniform
SO1 MOSFET for VG = - 1.O V
0-7 803-6675-1/O 1/$10.00 0 2001 IEEE.
0.5
Fig. 8: Suppression of GIDL enhancement in LAC
SO1 MOSFET
256
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This can be attributed to lower electric field in the gate-drain
overlap region as compared to Uniform SO1 MOSFET. Fig.
9 shows the electric field variation along the channel for
uniform and LAC SO1 MOSFETs. The peak transverse
electric field for LAC SO1 MOSFET is lower, indicating a
wider drain depletion region (due to the lower doping near
the drain side of the channel). This results in reduced Bandto-Band tunnelling and thus lower hole production. Since p
is a function of current and the current levels are lower in
LAC SOI, the value of p in LAC SO1 is less compared to
uniform SOL At high drain voltages, where impact
ionization comes into play, the asymmetric doping profile
offers lower field near drain in the case of LAC which thus
leads to suppression of floating body effects in LAC SOI.
2t
0
.3
E
-LAC1: Tilt=lOO
n
CON
1
a,
W
3
;
Y
c?
el
0
-0.1
-0.05
0
0.05
0.1
Channel Profile and Ge Pre-amorphization Salicide
Technology”, Proceedings of the IEEE SOI Conference,
October 5-8, Stuart, Florida, USA, 1998
[3] B.Cheng, A.Inani, V.Ramgopa1 Rao, and J.C.S.Woo,
“Channel Engineering for High Speed Sub-1.O V Power
Supply Deep Sub-Micron CMOS”, Technical Digest,
1999 Symposium on VLSI Technology, June 14-19,
Kyoto, Japan
[4] B.Cheng, V. Ramgopal Rao, B.Ikegami, and J.C.S.Woo,
“Realization of sub 100 nm asymmetric Channel
MOSFETs with Excellent Short-Channel Performance
And Reliability“ Technical Digest, 28 th European
Solid-State Device Research Conference (ESSDERC),
Bordeaux, France, 1998
[5] T. Y. Chan, J. Chen, P. K. KO, and C. Hu, “The impact of
gate-induced-drain-leakage on MOSFET scaling”,
IEDMTech. Dig.,Dec. 1987, p. 718.
[6] S. M. Sze, “Physics of Semiconductor Devices“, 2nd ed.,
New York: Wiley, 1981.
[7] T. Wang, T. Chang, L. Chiang, C. Wang, N. Zous, and
C. Huang, “Investigation of Oxide Charge Trapping and
Detrapping in a MOSFET by Using a GIDL Current
Technique”, IEEE Trans. Electron Devices, vol. 45,
pp. 1511-1517, 1998.
[SI J. Chen, F. Assaderaghi, P. -K. KO, and C. Hu, “The
enhancement of Gate-Induced-Drain-Leakage current in
short-channel SO1 MOSFET and its application in
measuring lateral bipolar current gain p”, IEEE Electron
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Lateral Position (pm)
Fig. 9: Electric field variation along the channel for
Uniform and LAC SO1 MOSFETs
8. Conclusions
The enhancement of off-state gate-induced drain leakage
current is significant for short-channel SO1 MOSFETs. The
parasitic bipolar current gain values for uniform and LAC
SO1 MOSFETs have been experimentally evaluated using
GIDL current technique. LAC SO1 MOSFETs have been
shown to give rise to reduced floating body effects as a
result of lower channel doping near the drain region. The
extracted parasitic bipolar gain values are an order of
magnitude lower for the LAC SO1 MOSFETs.
Acknowledgements: Authors wish to acknowledge
Baohong Cheng and Jason Woo of the University of
California, Los Angeles for providing the samples used in
these experiments.
References
[ 11 J. -Y. Choi, and J. G. Fossum, “Analysis and Control
of Floating-body Bipolar Effects in Fully Depleted
Submicrometer SO1 MOSFETs”, IEEE Trans.
Electron Devices, vol. 38, pp. 1384-139‘1, 1991.
[2] B. Cheng, V. Ramgopal Rao, and J. C. S. Woo, “Sub
0.18 um SO1 MOSFETs Using Lateral Asymmetric
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Proceedings of 8” IPFA 2001, Singapore
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