INT. J. ELECTRONICS,
1999,
VOL.
86,
NO.
10, 1233± 1247
A novel high power self-commutated static var compensator for load
compensation
KISHORE CHATTERJEE{ , B. G. FERNANDES{ and
GOPAL K. DUBEY{ }
A novel high power self-commutated static var compensator for load compensation
is proposed. The harmonics are eliminated by combining low frequency high power
devices and high frequency low power devices. A modi® ed control strategy is also
proposed for applications involving high and faster rates of change in var demand.
Detailed simulation studies for single phase and three phase topologies are
presented.
1.
Introduction
The traditional methods of reactive volt-ampere compensation consisting of
switched capacitor or ® xed capacitor and phase controlled reactor coupled with
passive ® lters are increasingly being replaced by new approaches utilizing the concept
of synchronous link converters (Kanetkar et al. 1994). This new class of compensator,
which has seen an overwhelming response from researchers, is known by several
terminologies including `var generators’ (Laszlo 1979), `advanced static var generators’
(Edwards et al. 1988), `synchronous solid state var compensators’ (Moran et al. 1989),
`PWM inverter var compensators’ (Joos et al. 1991), `STAT-CON’, etc. Although this
class of compensator provides improved performance over the traditional methods
of var compensation, it still has the serious drawback of injecting low order harmonics
into the utility. The problem becomes acute at high power levels. Several pulse width
modulated (PWM) techniques of harmonic elimination (Moran et al. 1989, Joos et al.
1991, Kojori et al. 1992) cannot be realized at high power levels owing to the switching
frequency limitation of high power devices. To reduce low frequency harmonics, either
parallel operated converters (Sumi et al. 1981, Hasegawa et al. 1993, Mori et al. 1993,
Suzuki et al. 1993, Fujita et al. 1996) or multilevel converters (Cho et al. 1991, Menzies
and Zhuang 1995, Lai and Peng 1996, Lee et al. 1996, Peng et al. 1996) are being used.
The disadvantages of parallel operated converter topology are: (1) the transformer
connection at the input side of the compensator becomes complicated and bulky,
(2) as the number of harmonics to be eliminated increases, the number of parallel
units is also required to be increased, which implies a poor performance/cost ratio
and (3) the structure of control becomes complicated.
The limitations of the multilevel converter topology are: (1) as the number of
harmonics to be eliminated increases the performance/cost ratio falls, (2) voltage
Received 10 August 1998. Accepted 15 December 1998.
y Department of Electrical Engineering, Indian Institute of Technology, Powai, Mumbai,
India.
z Department of Electrical Engineering, Indian Institute of Technology, Kanpur, India.
} Corresponding author. e-mail: gdubey@iitk. ac.in
Internationa l Journal of Electronics ISSN 0020± 7217 print/ISSN 1362± 3060 online # 1999 Taylor & Francis Ltd
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K. Chatterjee et al.
imbalance among the di€ erent levels of capacitors, (3) increase in active component
count (diode clamp topology) or increase in passive element count (¯ ying capacitor
topology) and (4) complexity in control.
Moreover in all the cases reported in the literature, the harmonics are eliminated
in an oƒ ine mode of control, as a result of which a relatively small error in the
hardware realization of device switching instants results in a signi® cant increase in
the harmonic content.
In order to overcome the above-mentioned limitations, a novel technique of
harmonic elimination is proposed wherein low frequency high power devices and
high frequency low power devices are combined to extract a superior performance.
The basic philosophy of the scheme is that two compensators are used in parallel of
which one is realized by GTOs while the other is realized by high frequency devices
like insulated gate bipolar transistors (IGBTs), MOSFETs or BJTs depending on the
current level to be handled. The GTO compensator (or the main compensator) is
operated with PWM control based on selective harmonic elimination technique so
that only a few low order harmonics get eliminated. Since the number of harmonics
to be eliminated by this main compensator is less, the switching frequency also
remains low. The high frequency parallel or auxiliary compensator is operated in
the current controlled mode to eliminate the next higher order harmonics generated
by the main compensator. The auxiliary compensator does not handle the fundamental reactive current so its kVA rating remains low. This concept of utilizing the
parallel auxiliary compensator for harmonic elimination is introduced in Dubey et
al. (1996) and Kanetkar and Dubey (1995) but there the auxiliary compensator
operates in indirect current controlled mode which makes the control structure
complicated and the volt-ampere rating high.
2.
Operating principle
The principle of operation of the proposed scheme is explained with the help of
single phase topology which can also be extended to three phase topology. The
power circuit con® guration of the single phase topology is shown in ® gure 1. The
main compensator is operated with selective harmonic elimination technique, so as
to eliminate 3rd, 5th, 7th, 9th and 11th harmonics. The switching instants are ® xed
and the fundamental component of the compensator current is controlled by controlling the magnitude of dc link voltage rather than controlling the modulation
index. The parallel compensator is operated in current controlled mode and provides
on line elimination of the higher order harmonics generated by the main compensator. A sinusoidal reference current iref in phase with the utility voltage is synthesized and the source current is is forced to follow this reference within a hysteresis
band. The source current is sensed and compared with the reference current. The
error thus obtained decides the switching pattern of the parallel compensator.
Suppose at some instant of time is is less than i ref , in order to increase is , S 3 and
S 4 are turned on so that the parallel compensator current icp increases. Now from
® gure 1
is
ˆ
icm
‡
icp
‡
iL
…
1†
therefore, increment of icp implies increment in i s . When is hits the upper bound of
the hysteresis band, S 3 and S 4 are turned o€ and S 1 and S 2 are turned on, which will
decrease is . Thus by controlling the switching pattern of the parallel compensator,
Novel high power static var compensator
1235
Figure 1. 1 ¡ ¿ topology of the proposed compensator.
the source current is rendered near sinusoidal. The same principle is also valid for the
three phase case but here the main compensator is programmed to compensate 5th,
7th, 11th and 13th harmonics. The power circuit con® guration of the three phase
topology is shown in ® gure 2. The schematic control block diagram of the compensator is shown in ® gure 3. The dc link reference voltage, V dcref is obtained from the
reactive volt-ampere calculator circuit and is compared with the actual dc link voltage. The error is used to control ¯ (load angle), the angle between the rms utility
voltage, V s and the rms fundamental component of the main compensator output
voltage, V cm 1 , so that requisite amount of real power is drawn from or supplied to
Figure 2. 3 ¡ ¿ topology of the proposed compensator.
1236
K. Chatterjee et al.
Figure 3.
Control block diagram.
the utility to nullify the error. The reference current amplitude I ref is the sum of the
amplitude of the real component of the load current I L real and the real component
of the main compensator current I cm real . The information regarding the amplitude
of the real component of the load current is obtained from the reactive volt-ampere
calculator. The amplitude of the real component of the main compensator current is
obtained as follows: considering ® gure 4, the rms current drawn by the main compensator is given by
…
…
Icm
…
rms†
†
†
Vs ¡ Vcm 1 €
Z€ ³
ˆ
¡
¯
…
2†
where ¯ is the angle by which Vcm 1 is lagging Vs , Z ˆ R ‡ j!L M , R is the overall loss
1
component of the system and ³ ˆ tan ‰ … !L M † =R Š . Therefore,
¡
Icm
Figure 4.
…
rms†
ˆ
…
Vs
¡
kV dc cos ¯ †
‡
jk V dc sin ¯
Z€ ³
Single line diagram of the main compensator.
…
3†
1237
Novel high power static var compensator
where k is the modulation index of the main compensator. On simpli® cation
I cm … rms†
I cm … real†
ˆ
‡
I cm … qadrature †
p
…

2
4†
where,
I cm … real†
ˆ
p


‰…
2
Vs
2
V dc k cos ¯ †
¡
‡
…
kV dc sin ¯ †
2 1= 2
Š
Z
cos tan
¡
kV dc sin ¯
1
Vs
As V s , k and Z are system constants, I cm
V dc and ¯ . Therefore,
I ref
…
¡
real†
I cm … real†
ˆ
‡
kV dc cos ¯
¡
³
is determined from the knowledge of
I L… real†
…
5†
…
6†
or,
iref
ˆ
f
I cm … real†
I L … real† g sin !t
‡
The same expression is valid for three phase topology as well but here while obtaining I ref , the dc link voltage to be considered is not V dc but V dc = 2. Then
… 7†
iref ph-A ˆ I ref sin !t
…
3.
†
i ref … ph-B†
ˆ
I ref sin … !t
¡
1208 †
…
8†
ir ef … ph-C†
ˆ
I ref sin … !t
‡
1208 †
…
9†
S imulation studies
In order to predict the performance characteristics of the proposed compensator
detailed simulation is carried out for single phase and three phase topologies. A
dedicated computer program has been developed for the purpose.
3.1. Single phase topology
Steady state behaviour of the compensator while compensating (1:67 ‡ j 9:2) kVA
of load connected to a 230 V utility is shown in ® gure 5. The source current when the
auxiliary compensator is not connected is shown in ® gure 5(C). Figure 5(E) and (F)
give the comparative study of the harmonics eliminated with and without the auxiliary compensator.
Figure 6 shows the transient response of the scheme for a load change from
(1:67 ‡ j 9:2† kVA to … 1:67 ‡ j 17:0† kVA.
The volt-ampere rating of the main compensator and the auxiliary compensator
for the two loads are given in Table 1. It can be observed from Table 1 that the voltampere rating of the main compensator is much higher than the load reactive voltampere which is being compensated. This phenomenon can be explained as follows:
if the resistance representing the loss component of the compensator is neglected,
then from equation (2), the rms magnitude of the compensating current can be
approximately written as
I cm
ˆ
j
Vs
¡
V cm j
!L M
…
10†
1238
K. Chatterjee et al.
Figure 5. Steady state behaviour: (A) dc link voltage, (B) source voltage and source current,
(C) source current without the auxiliary compensator, (D) auxiliary compensator current, (E) harmonic spectra of the source current, (F) harmonic spectra of the source
current without auxiliary compensator.
where V cm is the rms value of the output voltage of the converter associated with the
main compensator. As V cm is generated by pulse width modulating the dc link
voltage, its rms value is same as the dc link voltage level, i.e. V dc .
Therefore, volt-ampere rating of the main compensator is given by
SM C
ˆ
ˆ
I cm V dc
j
Vs
¡
V dc j
!L M
V dc
…
11†
…
12†
whereas reactive volt-ampere associated with the load is given by
QL
ˆ
I cm 1 V s
Equation (11) shows that the lagging var supplied by the main compensator is
V s and
proportional to the di€ erence between the voltages, V s and V dc . V dc
I cm 1 is less than I cm . Therefore by comparing equations (11) and (12) it can be
Novel high power static var compensator
1239
Figure 6. Transient behaviour for a load change of (1:67 ‡ j 9:2† kVA to (1:67 ‡ j 17:0† kVA:
(A) dc link voltage and dc link voltage reference command, (B) source voltage and
source current, (C) auxiliary compensator current, (D) load current.
1240
K. Chatterjee et al.
VA rating
Load
(kVA)
…
…
1:67 ‡ j9:2†
1:67 ‡ j17:0†
Table 1.
Main
compensator
(in kVA)
Auxiliary
compensator
(in kVA)
Auxiliary compensator
as % of
main compensator
23.5
74.35
1.543
4.219
6.56
5.567
Volt-ampere ratings of the main compensator and the auxiliary compensator for
two loads.
Q L . Hence the volt-ampere rating of the synchronous link
inferred that S M C
converter based var compensator will always be higher than the load reactive voltampere which is being compensated.
3.2. Three phase topology
Figure 7 shows the transient behaviour of the scheme for a load change of
(1:67 ‡ j 6:9) kVA/phase to (1:67 ‡ j 17:0) kVA/phase while ® gure 8 shows the
response for a decrement in load from (1:67 ‡ j 17:0) kVA/phase to (1: 67 ‡ j 6:9)
kVA/phase. The volt-ampere ratings of the main compensator and auxiliary compensator for the two loads are shown in Table 2. In all cases the hysteresis window
height is kept 1.0 A and the maximum switching frequency of the auxiliary compensator devices is found to be around 5 kHz.
From the above observation it can be inferred that a superior performance
characteristic is obtained by virtue of the proposed compensation technique. The
volt-ampere rating of the auxiliary compensator is found to be low and is compatible
with the rating of the high frequency devices like IGBTs. Moreover it is found that
the transient behaviour of the scheme is better. This is due to the fact that during
transients, the auxiliary compensator supplies the necessary var demand of the load.
As the peak current rating of a device is almost twice that of its continuous current
rating, drawing of high current for a short duration from the auxiliary compensator
can be permissible. However for high power applications involving fast and large
change in var demand this can be detrimental for the high frequency devices. This
problem is addressed by incorporating a slight modi® cation in the control strategy.
4.
M odified control strategy
From ® gures 6(C), 7(D) and 8(D) it can be seen that the auxiliary compensator
current increases during transients. Now if the transient period is identi® ed and
VA rating
Load
phase
(kVA)
…
…
1:67 ‡ j6:9†
1:67 ‡ j17:0†
Table 2.
Main
compensator
(in kVA)
Auxiliary
compensator
(in kVA)
Auxiliary compensator
as % of
main compensator
46.24
165.30
2.05
8.79
4.43
5.31
Volt-ampere ratings of the main compensator and the auxiliary compensator for
two loads.
Novel high power static var compensator
1241
Figure 7. Transient behaviour for a load change of (1:67 ‡ j 6: 9† kVA/phase to (1: 67 ‡ j 17:0†
kVA/phase: (A) dc link voltage and dc link voltage reference command, (B) Ph± A
source voltage and Ph± A source current, (C) Ph± A, Ph± B, Ph± C source currents,
(D) Ph± A, Ph± B, Ph± C auxiliary compensator currents.
1242
K. Chatterjee et al.
Figure 8. Transient behaviour for a load change of (1:67 ‡ j 17:0† kVA/phase to (1:67 ‡ j 6:9†
kVA/phase: (A) dc link voltage and dc link voltage reference command, (B) Ph± A
source voltage and Ph± A source current, (C) Ph± A, Ph± B, Ph± C source currents,
(D) Ph± A, Ph± B, Ph± C auxiliary compensator currents.
Novel high power static var compensator
1243
Figure 9. Transient behaviour for a load change of (1:67 ‡ j 9:2† kVA to (1:67 ‡ j 17:0† kVA:
(A) dc link voltage and dc link voltage reference command, (B) source voltage and
source current, (C) auxiliary compensator currents.
1244
K. Chatterjee et al.
Figure 10. Transient behaviour for a load change of (1:67 ‡ j 17:0† kVA/phase to
(1:67 ‡ j 6:9† kVA/phase: (A) dc link voltage and dc link voltage reference command,
(B) Ph± A source voltage and Ph± A source current, (C) Ph± A, Ph± B, Ph± C auxiliary
compensator currents.
Novel high power static var compensator
1245
Figure 11. Transient behaviour for a load change of (1:67 ‡ j 17:0† kVA/phase to
(1:67 ‡ j 6: 9† kVA/phase: (A) dc link voltage and dc link voltage reference command,
(B) Ph± A source voltage and Ph± A source current, (C) Ph± A, Ph± B, Ph± C auxiliary
compensator currents.
1246
K. Chatterjee et al.
gating pulses to the auxiliary compensator devices are disabled during this period,
high current drawn by the auxiliary compensator can be avoided. This scheme is
implemented as follows.
The error between the dc link voltage reference and the sensed dc link voltage is
near zero during steady state operation. Now during transients the error increases
for an increment in var demand and decreases when there is a fall in the var demand.
The error is sensed from the output of the comparator (® gure 3). When it crosses an
upper limit or a lower limit, the gating pulses to the auxiliary compensator are
inhibited. When steady state is reached and error is within the prescribed limits,
the gating pulses are enabled and the system operates as described earlier.
Simulation studies are carried out for this modi® ed control strategy. Figure 9
shows the transient behaviour of the single phase topology for increment of var
demand of the load. While ® gures 10 and 11 depict the transient behaviour of the
three phase topology for increment and decrement in var demand of the load. From
the simulated results it can be seen that as the auxiliary compensator is not connected
during the transients, the response of the compensation is slightly inferior and harmonics get introduced during this period.
5.
Conclusion
A new scheme of load compensation for high power applications is proposed.
Superior performance characteristic is derived from the scheme by e€ ectively combining high power low frequency and low power high frequency switching devices.
Detailed simulation studies are carried out to demonstrate the viability and e€ ectiveness of the scheme.
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