IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 8, AUGUST 2007
731
Border-Trap Characterization in High-κ
Strained-Si MOSFETs
Debabrata Maji, S. P. Duttagupta, V. Ramgopal Rao, Senior Member, IEEE,
Chia Ching Yeo, and Byung-Jin Cho, Senior Member, IEEE
Abstract—In this letter, we focus on the border-trap characterization of TaN/HfO2 /Si and TaN/HfO2 /strained-Si/Si0.8 Ge0.2
n-channel MOSFET devices. The equivalent oxide thickness for
the gate dielectrics is 2 nm. Drain–current hysteresis method
is used to characterize the border traps, and it is found that
border traps are higher in the case of high-κ films on strainedSi/Si0.8 Ge0.2 . These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of
high-κ films on strained-Si are also proposed.
Index Terms—Border traps, charge pumping, hysteresis, interface trapping, strained-Si, 1/f noise.
I. I NTRODUCTION
H
IGH-κ GATE dielectrics, such as hafnium oxide (HfO2 ),
have been extensively studied as possible replacement for
silicon-dioxide (SiO2 ) gate dielectrics for the scaled CMOS
technologies. Specifically, the superior thermal stability and
electrical characteristics of the TaN/HfO2 gate stack have been
well studied [1], [2]. However, such high-κ devices suffer from
degradation in channel mobility [3]. In order to enhance the inplane mobility of both electrons and holes compared to bulk,
a strained-Si layer is deposited on a relaxed-Si1−x Gex -buffer
layer [4], [5]. However, in the case of strained-Si on Si1−x Gex ,
Ge diffusion to the Si/ HfO2 interface may result in an increase
in the interface state and fixed-charge densities for these devices
[6]. Furthermore, the presence of border traps [7], which can
exchange charge with Si on a time-scale ∼1 s, can increase 1/f
noise as reported in the study in [8]. The evaluation of border
traps and interface traps is, thus, a critical reliability concern in
the case of high-κ/Si or high-κ/strained-Si MOSFET devices.
Interface quality, along with the 1/f noise of TaN gate and Hfbased dielectric, is discussed in the study in [9], [10]. In this
letter, we report a detailed characterization of border traps in
TaN/HfO2 /Si and TaN/HfO2 /strained-Si/Si0.8 Ge0.2 MOSFET
devices. We have used drain–current hysteresis [11] and 1/fnoise methods to characterize the border traps.
Manuscript received April 27, 2007; revised May 29, 2007. The review of
this letter was arranged by Editor K. De Meyer.
D. Maji, S. P. Duttagupta, and V. R. Rao are with Department of Electrical
Engineering, Indian Institute of Technology, Bombay 40076, India (e-mail:
[email protected]; [email protected]; [email protected]).
C. C. Yeo and B.-J. Cho are with the Department of Electrical and Computer
Engineering, National University of Singapore, Singapore 117576 (e-mail:
[email protected]).
Digital Object Identifier 10.1109/LED.2007.902086
II. E XPERIMENTAL
A. Device Fabrication
The devices are fabricated on a strained-Si layer of 10-nm
thickness epitaxially grown on top of a Si0.8 Ge0.2 relaxedbuffer layer. This relaxed-buffer layer is grown on a thick SiGegraded layer, where the Ge concentration is varied from 0% to
20%. In this letter, HfO2 was deposited at 400 ◦ C, followed by
a postdeposition annealing at 500 ◦ C for 60 s. The S/D regions
were formed using solid-phase-epitaxy (SPE) regrowth methods followed by a furnace anneal at 550 ◦ C for 10 min in N2
ambient. After the SPE process, the wafers have subsequently
undergone an rapid thermal annealing at 650 ◦ C for 10 s, followed by a forming gas anneal at 350 ◦ C. The surface roughness
is measured by atomic force microscope, and the rms value
of roughness is about 1.3 nm. This value of rms roughness is
quite normal for strained-Si, and we have also not observed any
visible evidence of dislocations or island formation. There is no
high-temperature-annealing step in the fabrication process. The
interfacial layer growth between high-κ and silicon substrate is
therefore expected to be minimum and is about 5 Å.
B. Charge-Pumping Measurements
The devices are subjected to a variable-base chargepumping pulses in order to study the interface quality. For
the charge-pumping measurements, the high-voltage level
(VHL ) of the applied pulse is fixed, and the low-voltage
level (VLL ) is varied. Measurements are done at different
frequencies. In Fig. 1, we note that the frequency-normalized
charge-pumping current (ICP /f ) does vary with frequency.
This leads to the conclusion that ICP is affected by the gate
leakage current. Hence, accurate measurement of interface
traps is quite difficult. Because of this, we also estimated
the value of ∆Dit independently from the subthresholdswing measurements. The value of ∆Dit is observed to
be roughly in the range of mid to high 1011 cm−2 · eV−1
for the control, as well as for the strained-silicon MOSFETs.
The Dit values for the virgin samples compare favorably with
the published literature where the reported values for Dit are
in the high 1011 cm−2 · eV−1 range [12]–[14]. Ge diffusion to
the high-κ interface has been postulated to be a cause for the
degraded interface in the case of strained-Si devices [6].
C. Hysteresis and 1/f-Noise Measurements
For the hysteresis measurement, Keithley K617 electrometer
is used to measure the drain current, while HP6622A and
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IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 8, AUGUST 2007
Fig. 1. Icp /f versus frequency plot for 200 × 5 µm2 TaN/HfO2 /Si MOSFET
and TaN/HfO2 /strained-Si/Si0.8 Ge0.2 MOSFET.
HP33120A are used to supply VDS and VGS , respectively.
The substrate is connected to ground. The gate voltage is
varied from accumulation to inversion to obtain the forward
ID –VGS characteristics and from inversion to accumulation to
get reverse ID –VGS characteristics. Gate bias is swept at a rate
of 50 mV/s during the hysteresis measurement. The drain bias
VDS is kept at 0.1 V. To study the dependence of stress voltage
on hysteresis, constant voltage stress is applied to the gate
terminal. During the stress measurements, the source, drain, and
substrate terminals are tied together and connected to ground.
Stress voltage has been applied to the gate terminal for a fixed
duration of time using HP33120A. Hysteresis characteristics
are monitored at regular intervals of time by interrupting the
stress bias. The 1/f-noise measurements have also been performed on these devices to understand the effect of border traps
on the device-flicker-noise properties. The transistors are biased
at a VDS of 0.1 V. The gate bias is varied, and 1/f noise is
measured as a function of gate-bias voltages. The frequency
range is 15 Hz–1.5 kHz.
III. R ESULTS AND D ISCUSSION
The ID –VGS hysteresis characteristics of both HfO2 /Si and
HfO2 /strained-Si devices with channel length L = 10 µm are
plotted in Fig. 2. Drain–current hysteresis measurements are
performed after fixed stress intervals at VGS = 3 V. In Fig. 2,
it can be clearly seen that the prestress threshold voltage of the
strained-Si sample is higher compared to the control-Si sample.
From the band alignment [15], it is obvious that strained-Si
must show a smaller Vt . If Ge is segregated at the interface,
negative fixed charge is generated [6], which can cause a
higher Vt , as observed in Fig. 2. This means that negative fixed
charge due to Ge out diffusion could be a dominant effect
in determining Vt rather than the band alignment. A typical
value of effective mobility for strained-Si devices measured
in our samples is about 200 cm2 · V−1 · s−1 at an effective
field of 0.4 MV · cm−1 , whereas it is 160 cm2 · V−1 · s−1 for
control-Si devices. A positive shift in threshold voltage is also
observed, which suggests that electron trapping is a dominant
mechanism during the constant-voltage stress. Subthreshold
swing in the strained-Si sample is also higher compared to the
control-Si sample for both the prestress as well as the poststress
Fig. 2. Drain–current hysteresis characteristics for the 100 × 10 µm2
TaN/HfO2 /Si and TaN/HfO2 /strained-Si/Si0.8 Ge0.2 MOSFETs and bordertrap density Nbt for the TaN/HfO2 /Si and (inset) the TaN/HfO2 /strainedSi/Si0.8 Ge0.2 MOSFETs, plotted as a function of stress time.
conditions. This has also been shown to be due to the Ge out
diffusion from the SiGe layer, which creates additional interface
states [6]. In Fig. 2, as the stress time is increased, the positive
shift in ID –VGS for strained-Si is observed to be smaller
compared to the control-Si sample. This can be explained from
the fact that strained-Si has a larger conduction band offset with
the HfO2 as compared to the control Si. Therefore, the larger
band offset gives rise to a lower substrate injection of electrons
for the case of strained-Si MOSFETs.
The density of border traps per unit area (Nbt ) can be calculated from the hysteresis measurements using the following
equation [11]:
Nbt =
∆VGS .COX
q
(1)
where q is the electron charge, COX is the capacitance of the
device per unit area, and ∆VGS is the change in gate voltage at
constant current 1 × 10−6 A in the weak-inversion region. The
surface band bending at this current level is found to be 0.54
and 0.59 eV for virgin HfO2 /Si MOSFET and HfO2 /strained-Si
MOSFET, respectively. It is clearly shown in Fig. 2 that the
magnitude of hysteresis is higher in the case of HfO2 /strainedSi MOSFET compared to the HfO2 /Si MOSFET. This result
holds true for virgin, as well as stressed, devices. Fig. 2 (inset)
shows the Nbt as a function of stress time extracted from the
hysteresis measurements using (1). This shows that border
traps increase with stress time in both cases, but the absolute
value is higher in the case of HfO2 /strained-Si MOSFETs.
We have compared the prestress 1/f noise in HfO2 /Si
MOSFETs and the HfO2 /strained-Si MOSFETs. The results
are verified on at least three to four devices in each case.
The drain–current power spectral density for both the sets of
devices is measured. The drain–current power spectral density
(SID ) versus frequency (f ) is plotted in Fig. 3(a). The border
traps have been known to communicate randomly with the
conduction-band electrons via the interface states [11]. As a
result, the number of channel carriers fluctuate, giving rise
to a higher 1/f noise in the strained-Si/HfO2 case compared
to the Si/HfO2 MOSFETs. The increase in noise observed
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MAJI et al.: BORDER-TRAP CHARACTERIZATION IN HIGH-κ STRAINED-Si MOSFETs
733
Fig. 3. (a) Drain–current noise power spectral density (SID ) for the TaN/HfO2 /Si and TaN/HfO2 /strained-Si/Si0.8 Ge0.2 MOSFETs, which is measured at
2 ) as a function of gate-to-source bias (V
VDS = 0.1 V. (b) Normalized drain–current power spectral density (SID /ID
GS ) at 31 Hz.
may well be contributed partly by the threading dislocations
[16]. Since the threading dislocations are known to create
trap centers within the channel, they play a similar role as the
interface traps and, therefore, have a very low time constant.
On the other hand, the border traps studied in this letter will
have time constants on the order of seconds, which results in
the hysteresis behavior in the dc I–V characteristics. Hence,
while the threading dislocation density (TDD) may contribute
to the flicker noise, the defects created due to the TDD are
not expected to give rise to the hysteresis behavior, which is
essentially attributed to the border traps.
2
) versus
The normalized power spectral density (SID /ID
VGS is plotted for both HfO2 /Si and HfO2 /strained-Si devices
2
remains
in Fig. 3(b). In Fig. 3(b), for Si/HfO2 sample, SID /ID
almost constant for the lower gate-voltage region, and the
plateau observed is a characteristic of the number fluctuation
theory [12], [17]. One can also observe that the 1/f noise is
higher in the case of HfO2 /strained-Si MOSFETs compared to
the HfO2 /Si MOSFET devices. This further confirms the presence of higher number of border traps in TaN/HfO2 /strained-Si
devices. The higher Nbt for HfO2 /strained-Si devices is likely
to be caused by 1) Ge diffusion to the interface [12] and 2)
stress at the interface due to the presence of strained-Si layer.
IV. C ONCLUSION
The characterization of border and interface traps
for TaN/HfO/strained-Si/Si0.8 Ge0.2 MOSFETs and the
TaN/HfO2 /Si MOSFET devices has been performed. There is
evidence that the strained-Si layer induces a higher density of
border traps and interface traps when a high-κ film is deposited
on the strained-Si region. We have confirmed the presence of
higher border-trap density in the strained-silicon MOSFETs
using a drain–current hysteresis technique, which is further
validated by the 1/f-noise measurements.
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