Highly conducting doped poly-Si deposited by hot wire CVD and its
applicability as gate material for CMOS devices
Samadhan B. Patila, Anand V. Vairagara, Alka A. Kumbhara, Laxmi K. Sahua, V. Ramgopal Raob,
N. Venkatramanic, R.O. Dusanea,*, B. Schroederd
a
Department of Metallurgical Engineering and Materials Science, Indian Institute of Technology, Mumbai 400076, India
b
Department of Electrical Engineering, Indian Institute of Technology, Mumbai 400076, India
c
Advanced Center for Research in Electronics, Indian Institute of Technology, Mumbai 400076, India
d
Department of Physics, University of Kaiserslautern, Kaiserslautern, Germany
Abstract
Highly conducting p- and n-type poly-Si:H films were deposited by hot wire chemical vapor deposition (HWCVD) using
SiH4qH2qB2H6 and SiH4qH2qPH3 gas mixtures, respectively. Conductivity of 1.2=102 (V cm)y1 for the p-type films and
2.25=102 (V cm)y1 for the n-type films was obtained. These are the highest values obtained so far by this technique. The
increase in conductivity with substrate temperature (Ts ) is attributed to the increase in grain size as reflected in the atomic force
microscopy results. Interestingly conductivity of n-type films is higher than the p-type films deposited at the same Ts . To test the
applicability of these films as gate contact Alypoly-SiySiO2 ySi capacitor structures with oxide thickness of 4 nm were fabricated
on n-type c-Si wafers. Sputter etching of the poly-Si was optimized in order to fabricate the devices. The performance of the
HWCVD poly-Si as gate material was monitored using C–V measurements on a MOS test device at different frequencies. The
results reveal that as deposited poly-Si without annealing shows low series resistance.
Keywords: Doped poly-Si; Hot wire CVD; Poly-Si gate; Boron penetration
1. Introduction
Thin film poly-Si is thought to yield stable solar cells
and high current thin film transistors for flat panel
displays. In present VLSI devices, poly-Si grown by
conventional LPCVD at 650 8C is used as gate material
rather than Al metal. The thermal budget of LPCVD is
very high since it requires high substrate temperature
)600 8C for poly-Si deposition. However, this material
can be deposited by PECVD and hot wire chemical
vapor deposition (HWCVD) at low substrate temperature (Ts) ;250 8C w1,2x.
Recently it was demonstrated that the HWCVD can
be used for the deposition of doped mc-Si:H or poly-Si
at low Ts w2,3x. These studies show conductivities of
the order of ;1 (V cm)y1 w4x, 10 (V cm)y1 w5x and
12 (V cm)y1 w6x. However, such films have not yet
been employed in MOS devices as gate material. An
important issue in CMOS device technology is the boron
penetration from the poly-gate into the channel, thus
affecting the transistor performance due to reduction in
the carrier mobility of the channel. One way to reduce
boron penetration is to improve the poly-Si material w7x.
It is with the aim to establish the potential of the
HWCVD for depositing poly-Si gate that we have
undertaken this work, the results of which are presented
in this paper.
2. Experimental
Doped poly-Si films were deposited using Matheson
grade SiH4, B2H6 and PH3 along with hydrogen dilution.
Corning 7059 and c-Si substrates were used to enable
determination of grain size by atomic force microscopy
(AFM) and low angle XRD, conductivity, optical bandgap, chemical bonding and hydrogen content. MOS
devices were fabricated with poly-Si as gate and char-
64
Table 1
Parameters used for the deposition of poly-Si films
Gases used
(H2ySiH4) Flow rate ratio
10% B2H6 or (1% PH3 in H2)
Substrate temperature (Ts)
Filament temperature (TF)
Total gas pressure
Distance between filament and substrate
SiH4, H2, B2H6 and PH3
20
1.3 sccm
150–350 8C
1800 8C
70 mTorr
5 cm
acterized. Deposition parameters used are shown in
Table 1.
Capacitors were fabricated on N1 0 0M n-type silicon
substrates with an oxide thickness of 4 nm and a p-type
poly-Si layer with thickness of 400 nm. C–V measurements were done with the help of an Agilent 4263B
LCR meter (100 Hz–100 kHz), Keithley 175 auto
ranging multimeter and Agilent 8631A power supply
interfaced to a Pentium II processor through GPIB.
3. Results and discussion
3.1. Material characteristics
Fig. 1a and b show AFM images of the p-type polySi samples deposited at substrate temperature (Ts) of
Fig. 1. AFM images of p-type poly-Si (a) deposited at 150 8C (average grain size 100 nm) and (b) deposited at 350 8C (average grain
size 300 nm).
Fig. 2. XRD patterns for p-type poly-Si films.
150 and 350 8C, respectively. It is seen that the grain
size of p-type poly-Si films varies from 100 to 320 nm
as the temperature is varied from 150 to 350 8C. Also
it can be seen from Fig. 1b that the grain size distribution
in the films deposited at 350 8C is quite narrow. XRD
results are shown in Figs. 2 and 3 for the films deposited
at different substrate temperatures. The X-ray data
results indicate a preferred orientation in N1 1 1M direction for all the films. This data also confirms the increase
in grain size (as determined by the Scherrer’s formula)
with Ts, which is also observed in the AFM. Another
important observation from XRD is that the grain size
for n-type poly-Si samples is higher than that of p-type.
In Fig. 4, we compare the grain size variation obtained
from XRD with that from AFM. Grain size as determined by AFM measurements is larger by an order of
magnitude than the XRD data. Difference between the
grain sizes determined by the two techniques was
observed even in an earlier study w8,9x.
Fig. 5 shows variation in conductivity (sRT) of polySi films with substrate temperature. The sRT increases
significantly from 3.2 (V cm)y1 at Tss150 8C to 107
(V cm)y1 at Tss350 8C. The n-type films show higher
sRT which varies from 5 (V cm)y1 at Tss150 8C to
226 (V cm)y1 at 350 8C.
Fig. 3. XRD patterns for n-type poly-Si films.
65
Fig. 4. Variation in grain size of p-type poly-Si with substrate
temperature.
As can be seen from Fig. 5 conductivity values for
the n-type poly-Si films are higher than that of p-type
poly-Si samples deposited at the same substrate temperatures. An obvious reason for this is the smaller grain
size in p-type films w10x, lower hole mobility and higher
grain boundary scattering.
3.2. Fabrication and characterization of capacitors
Capacitors (0.75 mm diameter) having structure cSiySiO2 (4 nm)yHWCVD p-poly-SiyAl were fabricated
by argon sputter etching. Al with thickness more than
three times the thickness of poly-Si was deposited as a
masking material during argon etching. This was done
since sputter yield for Al is almost three times to that
of poly-Si. By the time poly-Si etches away from
unmasked area, significant Al left at the masked sites
helps for the purpose of contact. Fig. 6 shows poly-Si
capacitors fabricated using poly-Si gate and SiO2 thickness of 4 nm.
Fig. 7 shows a C–V plot of poly-Si gate capacitor
deposited at Tss250 8C. The C–V measurement of as
deposited specimen shows that HWCVD poly-Si offers
a very low series resistance (indicated by the low value
of threshold voltage). This ensures the fact that as
deposited, in situ doped poly-Si by HWCVD can be
used as gate material in CMOS devices. Whether the
HWCVD p-type poly-Si offers any advantage regarding
the boron penetration was further studied.
Fig. 5. Conductivities of p type (d) and n-type (j) poly-Si deposited
at various substrate temperatures.
3.3. Suppression of boron penetration
Boron penetration is a reliability concern in dual
gated CMOS technology. Boron penetration occurs during the high temperature cycle employed for activating
the implanted boron atoms in a normal device fabrication
process. Different procedures w11,12x such as use of
nitrided oxide or recrystallization of poly-Si gate material are being adopted to prevent boron penetration.
Boron penetration can be monitored by a shift in flat
band voltage in the C–V curve of the MOS capacitor.
We have attempted to study boron penetration by annealing the MOS capacitors at 900 8C for 15 min. We have
compared the boron penetration in a number of MOS
capacitors having the poly-Si gate with a different grain
size, by annealing these at 900 8C for 15 min. In Fig.
8, we show the C–V plots for these MOS capacitors,
where the poly-Si grain size varies from 100 to 320 nm.
It is clearly seen that the shift in the flat band voltage
(from what would have been an ideal value) is lowest
for the capacitor having poly-Si with largest grain size.
Since the dopants diffuse preferentially along the polySi grain boundaries, an increase in the poly-Si grain
size would reduce the grain boundaries available for
diffusion during annealing. The observed shifts strongly
indicate the decrease in boron penetration with increase
in the grain size of the poly-Si. These results indicate
that HWCVD poly-Si has an added advantage as gate
material since it suppresses the boron penetration
considerably.
Fig. 6. Structure of the completed capacitors after metallization and Ar sputter etching.
66
poly-Si films showing higher conductivity than p-type
films. The material with large grain size, when employed
as gate in a MOS device offers low series resistance
and also leads to a reduced boron penetration during
thermal annealing at high temperature.
Acknowledgments
Authors are grateful to Dr M. Scheib, IFOS, Kaiserslautern, Germany for the XRD data. Work was carried
out with financial help under the project from University
of Kaiserslautern. One of the authors (S.B.P.) acknowledges Council of Scientific Research (CSIR), Government of India for financial support.
Fig. 7. C–V curve for a MOS-capacitor with poly-Si (deposited at
250 8C) as gate.
Fig. 8. Shift in VFB due to boron penetration, for a MOS-capacitor
with poly-Si films of different grain sizes, deposited by HWCVD.
4. Conclusion
Highly conducting (s;102 (V cm)y1) p- and n-type
poly-Si films were deposited by HWCVD with n-type
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