Cooling Mechanisms in 3D ICs: Thermo-Mechanical Perspective
Satish G. Kandlikar1, Dhireesha Kudithipudi2 and Carlos A. Rubio-Jimenez1
1
Department of Mechanical Engineering
2
Department of Computer Engineering
Rochester Institute of Technology, Rochester, NY, USA-14623
Abstract—Three-dimensional (3D) integrated circuits (IC) impose
several challenges in thermal management. Stacking vertical layers
significantly increases the heat dissipation per unit volume and the
thermal footprint per unit area. The internal layers in the stacks are
susceptible to high thermal gradients due to the low thermal
conductivity interfaces and the distance from the heat sink. Several
factors affect the thermal behavior of the 3D IC, including the
through silicon vias, bonding, and cooling mechanisms. In this
paper, we provide a detailed review of existing cooling
mechanisms and their applicability to 3D ICs. We also propose
two parameters to account for the thermal interactions among the
devices and stack layers for incorporation in the 3D IC cooling
system design: Thermal Intensification Factor (TIF) accounts for
the increased heat flux due to multiple ICs along the heat transfer
path, and Thermal Derating Factor (TDF) accounts for the
increased thermal resistance introduced by the multiple layers.
Also, a new flow passage design with variable fin density is
presented to reduce the surface temperature non-uniformity along
the coolant flow length.
Keywords-Thermal
Microchannels, 3D ICs.
I.
Management,
Cooling,
of through silicon vias (TSV), and the thickness of silicon
contribute to the thermal budget. In addition, 3D ICs have
higher thermal resistance along heat conduction paths to the
heat sink causing larger temperature rise. The higher the
number of strata greater is the effort in dissipating the heat,
causing non-uniform performance, power, and reliability
profiles. The temperature affects the reliability of 3D ICs in
the following ways (i) diffusion effects (ii) dielectric
breakdown (iii) ion movement (iv) electromigration (v)
thermal cycling and (vi) performance drift.
TSV,
INTRODUCTION
Three-dimensional (3D) integrated circuits (IC) are
garnering significant attention in the recent past due to their
several potential benefits. To realize a functional 3D circuit a
number of innovative process technologies including wafer
thinning, etching and filling of high aspect ratio holes in
silicon, and wafer bonding are needed [1]. The main
advantages of 3D ICs are reduced global interconnect
lengths, increased circuit functionality, heterogeneous
integration, smaller chip-footprint, greater power efficiency
and new 3D circuit architectures [2-5]. Despite these
advantages over planar 2D ICs, there are several challenges
associated with 3D ICs. The two most significant challenges
are (i) quality of the wafer-wafer bonding and (ii) thermal
management in these architectures. Technology scaling and
high integration density make the thermal management of
3D ICs particularly interesting and a multi-layer design
problem.
Increasing number of power sources and the close
proximity of the heat sources from vertically stacked cores in
3D ICs exacerbates the thermal management problem in
these systems; which can be detrimental to the performance
as well as the reliability. The problem can be alleviated to an
extent by choosing between face-to-face integration [1] or
back-to-face integration [6] of the cores; analogous to
placing a cold core on top of a hot core or vice versa. The
number of strata in the 3D stack, the density and resistance
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Figure 1. Representation of 3D IC with heat sink on the top.
A high-level representation of a generic 3D IC is shown
in Figure 1. In 3D ICs, integration can be achieved via
vertically stacking heterogenous/homogenous cores in a
single chip or multiple chip modules can be monolithically
stacked in 3D. Each stack can have logic, memory, or hybrid
devices integrated depending on the system requirements.
TSVs enable communication between the different layers
and play a pivotal role in the thermal management of the 3D
ICs. The cooling layers between the stacks minimize the heat
dissipated from the neighboring layers by coolants and
thermal vias.
There is a good body of evolving research on the thermal
modeling and analysis in 3D ICs. Existing literature focuses
on full chip thermal modeling and numerical analysis [1,713], optimal placement of TSVs for heat minimization [514], task scheduling for balanced heat distribution [3], CAD
tool designs, etc. However, there has not been much focus on
the cooling mechanisms and their impact on the 3D ICs,
from a thermo-mechanical perspective. This paper provides a
detailed analysis on the different cooling mechanisms and
their feasibility for 3D ICs. We also present the idea of nonuniform temperature distribution across a core due to coolant
fluids in the stacks. To minimize these heat variations and
non-uniformity, a micro pin fin heat sink design is proposed.
In addition, new metrics to measure the thermal
characteristics of these systems are introduced.
II.
PARAMETERS AFFECTING THERMAL ISSUES
IN 3D ICS
The 3D IC encounters some unique thermal challenges
that impact the system performance and reliability. In
particular the following parameters and their impact on
temperature are discussed in detail in the following
subsections: (a) interface circuitry (TSV) (b) non-uniform
heat distribution and (c) coolant fluid.
A. Through-Silicon Vias
TSVs are the vertical channels for heat, power and data
delivery. TSV fabrication includes thinning of the wafer
substrate to a thickness of sub-60 m. The TSVs have a pitch
size ~5-25 m and requires microbumps in the vertical
stacks. Typical TSV lengths vary between 10 to 100 m.
TSVs are embedded in a silicon substrate. Depending on the
application, the substrate can be either heavily-doped or
lightly-doped. For example, in digital applications to
guarantee that the entire substrate is equal-potential and
alleviate latch-ups, heavy doping can be performed. There is
a silicon-dioxide insulator layer between the metal fill and
the silicon substrate. Copper filling helps with the thermal
but has low throughputs and takes long time. All the TSVs
are embedded in low-k dielectrics [15]. TSVs are most
susceptible to mechanical failure as they experience
mechanical stresses during the fabrication process. The
repeated thermal cycling also introduces fatigue failure
mechanism in these fragile microstructures. Therefore the
placement of TSVs is crucial for minimizing the power and
thermal budget of a 3D IC.
The coolant channels sometimes compete with the TSV
space and impose constraints on their locations. For example,
if TSVs are located on the land regions only of a
microchannel configuration, then a substantial region
covered by the channels is not available for TSVs. The
channels are designed to carry a large amount of heat with
little pressure drop. This requires larger, meaning deeper,
channels for a given overall size of the chip. Making
channels deeper also causes the TSV lengths to increase and
the interconnect delay is adversely affected. Cooling systems
without these constraints are preferable, otherwise a designer
needs to make judicious optimization of the overall size and
placement of TSVs and coolant channels. Few researchers
have used thermal vias to reduce the thermal problems, by
electrically isolating the vias and reducing the effectivethermal resistances [16-17].
B. Non-Uniformity in Temperature
The heat flow in the vertical direction in 3D ICs causes
some temperature non-uniformity, especially if the cooling
layers are not alternately stacked with the IC layers. In
addition, when the local temperature non-uniformity due to
hot spots is superimposed on this underlying temperature
variation, it will result in significant temperature non-
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uniformity along the fluid flow direction. The cooling system
design therefore needs to be modified to reduce these effects.
In case of the two-phase cooling, this temperature nonuniformity is significantly reduced, as the coolant
temperature will in fact decrease along the flow direction due
to lowering of the saturation temperature. This variation in
saturation temperature needs to be combined with the
variation in the heat transfer coefficient along the flow length
of the evaporating coolant before the temperature variation
of the substrate can be accurately determined.
Although the temperatures on the entire chip are below
the allowable limit, the in-plane thermal non-uniformity will
affect the stresses induced at the TSV junctions. The
differential expansion of the underlying substrate between
adjacent TSVs, and the resulting stresses need to be carefully
evaluated for establishing the allowable limits for
temperature gradients.
There is another cause of temperature non-uniformity
caused by the temperature differences between two adjacent
channels. If a fluid flowing in a channel receives more heat
than its adjacent channels, then there will be a temperature
difference between the channel surfaces near the outlet,
resulting in large temperature gradients in the lateral
direction to the channels. These non-uniformities will result
in performance variations in different circuits across the
chip. If the critical path circuits are affected by such
temperature variations then it might lead to generating
garbage output values. For example, consider a stack in the
3D IC that has hybrid devices integrated: logic and memory.
If the non-uniformity will increase the temperatures on the
memory units then the data write and read performances
might be destructive on the extreme. Realistically, a thermal
management unit will be activated to address such
unexpected spikes. However, if the ranges are below the
thresholds then the thermal management unit might not be
activated. Therefore, it is important to address these
challenges during the design phase.
III.
COOLING MECHANISMS
A. Cooling Options for 2D IC Chips
The three possible coolants to use in 3D ICs are air,
single-phase liquid, or a boiling liquid. Air is preferable
because of the simplicity in the overall system design and
operation. However, the power dissipation levels of air are
quite low. This may not be an issue in cases where the
system speed is of great importance, but the overall power
dissipation is low e.g. mobile devices and notepads.
Single-phase cooling with liquid is perhaps the best
solution available for use with microchannel coolers. It is
preferable to use water from a heat transfer perspective
because of its superior heat transfer characteristics. However,
water may become a concern if there are any chances of
leakage from the system such that water may come in direct
contact with chips. To avoid this danger, dielectric fluids
such as refrigerants are often employed. Since the thermal
conductivity and other heat transfer characteristics of the
dielectric fluids are considerably lower than water, the heat
removal capability with these liquids is significantly reduced.
Boiling a liquid as it picks up heat from the devices is a
very efficient technique because of the large latent heat
associated with the phase change process. The mass flow
rates are considerably reduced. Another advantage of a twophase system is the uniformity of the coolant temperature.
When employed in channels, the saturation temperature of
the fluid decreases in the flow direction due to the pressure
drop along the flow length. Water again has the most
desirable thermal characteristics because of its large latent
heat. However, the saturation temperature of water at 1
atmospheric pressure is 100°C, which is higher than the
upper limit of junction temperatures for the chips. Water may
be used under sub-atmospheric pressures to provide a lower
operating temperature. The issues related to leakage into the
system, and large specific volume of the vapor need to be
properly addressed. Low pressure water remains among one
of the possible alternatives.
Using refrigerants with more operating pressures slightly
above atmospheric is another viable alternative. The
dielectric properties of the refrigerant are desirable in
bringing the coolant closer to an IC. The latent heat of
evaporation for refrigerants is generally almost an order of
magnitude lower than that for water. Thermal performance
for the refrigerant systems is therefore not as attractive as
with water. However, it is a good alternative for cooling ICs.
For high heat flux removal, single-phase and two-phase
systems with water and refrigerants are receiving attention.
Water based coolants are attractive because of their favorable
thermal properties such as high thermal conductivity, high
specific heat, and in the case of flow boiling systems, a high
latent heat. Water also has a high dielectric constant of 78.5
and is thereby amenable as a coolant.
B. Design Approach for 3D IC Stacks
Cooling of a 3D IC stack uses the 2D IC cooling
technologies as its basic building block. However, the 3D
architecture introduces thermal interactions among the
devices and additional thermal resistances that need to be
considered. Two new parameters are introduced that take
into account these effects. The objective of a good thermal
design approach is to bring these interaction terms close to
unity so that a cooling system is effective in a 3D
configuration by reducing the hot spots and provide more
uniform temperature distribution.
Heat removal from the top layer in a conduction cooling
system is similar to the cooling techniques employed for
planar IC chip cooling. Because of the multiple devices
appearing in the heat flow path, and because of additional
thermal resistances, two factors are introduced.
The Thermal Intensification Factor, TIF, takes into
account the presence of multiple heat generating devices
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present in the thermal path from the bottom layer to the top
layer. Assuming each device is generating same heat flux,
then TIF would be 0.5; however, heat spreading or presence
of other evices in the vicinity might alter the TIF value. If the
device placement is made judiciously to avoid series paths
and device interactions, then TIF would approach 1.
(1)
where q”3D-U is the uniform heat flux based on the total
power dissipated in a 3D IC stack divided by the active
cooled area, and q”3D-H is the maximum heat flux in a hot
spot of the 3D stack considering the device overlap and
interaction effects. This factor in effect considers the
localized cooling of the hot spots. For heat balance of the
coolant loop, it is appropriate to use the uniform heat flux
q”3D-U, while for calculating maximum device temperature
for safe operation, use of the maximum heat flux in a hot
spot q”3D-H is recommended.
The Thermal Derating Factor, TDF, considers the
additional thermal resistances introduced in a 3D stack.
Since the coolant is placed over the top layer, an equivalent
heat flux that would be representative of a single IC layer is
used in the design calculations.
(2)
Alternatively,
(3)
TDF depends on the additional resistances introduced in
a 3D IC due to (i) conduction resistance in the additional
dies, after factoring in the conduction in TSVs and TVs, (ii)
interface resistance between the layers, (iii) additive effect
due to multiple heat sources in the heat conduction path,
which depends on the device placement strategy employed.
The equivalent 2D maximum heat flux corresponding to the
maximum heat flux in a 3D stack is given by:
(4)
It is imperative that for the energy balance calculations
for the coolant, q”1D-U is used and for the local hot spot
temperature calculations with heat transfer coefficients and
other thermal resistances, q”1D-H is used. Thus, to design a
microchannel system on the top layer to meet the thermal
requirements, the design should be based on q”1D-H. The
value of TIF is greater than 1, and TDF is less than 1. This
requires a cooling system for a 3D IC stack to be designed
for a larger heat flux removal capability than a 1D planar
chip. For a good 3D IC stack design, both TIF and DIF
should be close to 1.
C. Evaluation of Cooling Options
For the high heat flux systems, three options that are
attractive are single-phase jet impingement, microchannels
with single-phase flow, and microchannels with two-phase
flow. Kandlikar and Bapat [18] present a critical evaluation
of these techniques for removing heat fluxes of the order of 1
kW/cm2.
Jet impingement using liquid is an effective technique in
which high speed jets issue from nozzles and impinge on the
target kept at some distance away from the jet. A single jet
provides efficient heat removal in the immediate vicinity of
the central region of a jet. The liquid film becomes thicker
farther away from the jet centerline, thereby introducing
increased thermal resistance. Using multiple jets that are
closely placed effectively overcomes this problem. The
multiple jet configurations can be fabricated using
microfabrication technology. Further improvements in the
heat transfer performance of multiple jets can be achieved by
introducing enhanced surfaces on the target plate.
The main drawback of the jet impingement cooling
technique is the high pressure requirement to drive the jets
and the system design could become quite complex with
multiple headers for supplying and removing liquid. The
required pressures in some of the designs were between 70
and 500 kPa. For the 3D IC cooling, jet impingement is not
well suited mainly because of the large space requirement for
the jets and the manifolds behind them. This additional space
requirement for jet impingement cooling will work against
the benefits gained from the 3D architecture.
Spray cooling is another option that has been investigated
in literature for planar chip cooling application. In this
system, fine droplets of liquid are sprayed on a substrate
where the liquid spreads and evaporates rapidly. The heat
transfer rates could be as high as 250 W/cm2 with water. The
pressure and space requirements for these systems are even
higher than the jet impingement systems. Spray cooling
option is thus not suitable for 3D IC cooling as well.
Microchannel cooling option was another option
evaluated by [18]. It provides some unique benefits of high
performance and possibility of integration within the
multiple die layers.
i) Conduction Cooling of 3D ICs
Stacking multiple die layers makes heat removal a
difficult task. For total heat fluxes in the range of 100-200
W/cm2, high heat flux removal IC cooling systems may be
viable. Since heat generated in the inner dies is removed by
conduction to the top layer, this technique is called as
conduction cooling. It should not be confused with other
systems where heat flows in the in-plane direction and then
is removed by employing heat pipes or other techniques.
Figure 2 shows some of the options available for
removing heat from a 3 layer die set. The dies may be
mounted face-to-face or face-to-back depending on the
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overall heat load and placement of different heat producing
devices in relation to the overall assembly.
Aggressive air cooling
desing with compact HX
Face-to-back packaging
Aggressive air cooling
desing with compact HX
Hybrid face-to-back and face-to-face packaging
a)
Coolant inlet and outlet
Pool boiling with vapor
space condensation
Hybrid face-to-back and face-to-face packaging
b)
Top cover for
microchannels
Microchannels on the
backside of a chip
Hybrid face-to-back and face-to-face packaging
c)
Figure 2. Integrated conduction cooling of 3D ICs with other cooling
systems: (a) aggressive air cooling with compact HX, (b) pool boiling with
vapor space condensation, (c) microchannel cooling.
The hybrid packaging shown in Figures 2(a) and (b)
allows for the shortest TSV, but the thermal effects of
devices facing each other may have to be considered. In the
first design (a), the top die is treated like a high power chip
and an aggressive air cooling with a compact heat exchanger
is employed. The limit for air cooling is around 80-100
W/cm2. For low power applications, other less aggressive air
cooling options may be pursued.
The system shown in Figure 2(b) employs pool boiling
heat transfer. The top die interfaces with the pool boiling
liquid, either directly or through an intermediate container
base. It may be desirable to incorporate some pool boiling
enhancement technique, such as artificial cavities or open
microchannels. Recent work by Cooke and Kandlikar [19]
has yielded a heat removal rate of 300 W/cm2 and a heat
transfer coefficient of 280,000 W/cm2°C with water. A
chamber with vapor space condensation and an external
coolant loop removes the heat away from the system.
The third system shown in Figure 2(c) employs
microchannels etched in the silicon on the back-side of the
top layer. The arrangement is similar to a planar IC chip
cooling. In this case, the aggressive design with multiple
inlet and outlet headers and offset strip fins employed by
Colgan et al. [20] may be employed. Although the heat
transfer rates obtained in a single chip cooling of 790-1000
W/cm2 may be achieved, the maximum temperature
encountered in the bottom layer of the stack is expected to
limit the heat fluxes that can be dissipated as dictated by the
TIF and TDF discussed earlier. As seen from the above
examples, the heat generated in each layer flows to the top
layer in conduction cooling. Heat is then dissipated using the
established techniques.
decade. Because of the small dimensions, the flow is laminar
in chip cooling application. As the flow channel dimensions
become smaller, the heat transfer coefficient improves in
inverse proportion. However, the pressure drop also goes up,
in an inverse cubic proportion as the diameter decreases. To
overcome this problem, short flow lengths are employed.
a)
Single-pass arrangement
b)
Split-flow arrangement
c)
Offset strip fin geometry in microchannels
Moreover, the wafer thinning in a multiple layer structure
is implemented to reduce the TSV lengths. Wafer thinning is
also advantageous from the cooling perspective as it reduces
the thermal resistance of the silicon substrate. At high heat
fluxes, this resistance is not insignificant and wafer thinning
offers benefits from both electrical and thermal design
viewpoints. For low to medium heat flux systems,
conduction cooling is thus seen as an attractive option for a
3D IC stack.
ii) Microchannel Cooling
Following the definition presented by Kandlikar and
Grande [21], channels with hydraulic diameters in the range
10-200 µm are classified as microchannels, and those in the
range from 200 µm to 3 mm are termed as minichannels.
Because of the small thickness of the wafer, microchannels
are commonly employed on the back of a chip for direct
cooling. An exhaustive history and a critical review of
developments in this field are represented by Kandlikar [22].
Currently practical solutions utilizing single-phase liquid
flow in microchannels are available for meeting planar IC
cooling needs of up to 790-1000 W/cm2. A brief overview of
the microchannel cooling technology with single-phase flow
with liquid and flow boiling is presented below.
iii) Single-Phase Microchannel Cooling
Single-phase cooling options with water or water-based
solutions have received considerable attention in the last
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d)
Offset strip fin geometry in microchannels
Figure 3. Plain and enhanced microchannels and their performance [23].
Kandlikar and Upadhye [23] proposed a two-pass
arrangement which reduced the flow length and flow rates by
half. In addition, the plain microchannels were replaced by
an offset strip fin geometry to provide higher heat transfer
rates with low pressure drops. Figures 3(a)-(d) show the
single-pass and the split-flow geometry, the offset strip fin
geometry and the heat load versus pressure drop
performance for these arrangements. The split-flow
geometry with offset strip- fin geometry is able to dissipate
300 W with a pressure drop of 24 kPa. A heat transfer
coefficient of around 500,000 W/m2°C was experimentally
determined by Steinke and Kandlikar [24] for this geometry.
Colgan et al. [20] employed offset strip fin geometry with
multiple inlet and outlet headers to dissipate 790 W/cm2
from a chip. Their conceptual design is shown in Figure 4.
Figure 5(b). An active cooling area of 10 mm x 10 mm is
considered.
a)
Sketch of micro pin fins heat sink
Figure 4. An advanced chip cooler design with offset strip fins and
multiple headers [20].
iv) Flow Boiling in Microchannels for Cooling 3D ICs
Flow boiling in microchannels has been extensively
studied in the last decade. Concerns regarding the flow
instability and the lower than expected heat transfer
coefficients and critical heat fluxes have hindered its
practical implementation. Some of the techniques such as
addition of active nucleation sites and introduction of inlet
restrictors have shown promise, e.g., Kandlikar et al. [25],
Kosar et al. [26].
v) Temperature Uniformity Considerations
The temperature uniformity is an important consideration
in the design of 3D-IC stacks. Although high heat transfer
coefficients can be achieved with a single-phase coolant,
coolant and substrate temperatures rise along the flow length.
Increasing the coolant flow rate reduces the coolant and
consequently the chip surface temperature non-uniformity,
but increases the coolant pressure drop. A new flow channel
design with variable fin density is presented here to reduce
the temperature non-uniformity without excessive pressure
drop penalty.
The conventional pin fins with uniform fin density is
shown in Figure 5(a) and the new propose design with
increasing fin density along the flow length is shown in
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b)
Sketch of micro pin fin network with variable fin density
Figure 5. a) Conventional uniformly spaced pin fins and b) proposed new
design with increasing fin density along the flow length
360
Fluid
Novel micro pin fin heat sink
Micro pin fins heat sink
Microchannel heat sink
350
Temperature [K]
The earlier systems investigated have focused on
introducing subcooled liquid into microchannels. After
reaching saturation condition in the microchannel, it would
begin to boil. This configuration allows for a liquid pump.
However, if a refrigeration loop is incorporated with a
throttle valve at the inlet of the microchannels, there are no
instabilities. Such arrangements are also attractive as the
refrigerant temperature in the evaporator could be below the
room temperature thereby increasing the heat fluxes that can
be removed from of the unit. The condenser of the system
would then be able to dissipate heat directly to the air.
340
330
320
310
300
290
0.0
0.5
x/L
1.0
Figure 6. Temperature variations of fluid and substrates of different heat
sinks along the flow direction, q”=100 W/cm2, Tinlet=293 K, flow rate =1.5
mL/s
The conventional heat sink is formed by 6534 rectangular
pin fins (50 m width, 100 m length and 200 m height).
The transversal (perpendicular to flow direction) and
longitudinal (parallel to flow direction) pitches are 100 m
and 150 m, respectively. The base has a 200 m thickness.
The micro pin fin heat sink with variable density is
formed by 4752 flat pin fins (50 m width, 100 m length
and 200 m height) placed on 3 sections:
1. 330 pin fins are placed on 33 transversal and 10
longitudinal rows at this section (from the fluid inlet)
with ST and SL of 300 m and 150 m, respectively.
2. 2244 pin fins are placed on 66 transversal and 34
longitudinal rows at the second section (middle of the
heat sink) with ST and SL of 150 m.
3. 2178 pin fins are placed on 99 transversal and 22
longitudinal rows at the third section (near the fluid
outlet) with ST and SL of 100 m and 150 m.
80.0
70.0
DP [kPa]
60.0
50.0
40.0
30.0
20.0
10.0
0.0
Microchannel
heat sink
Micro pin fins Novel micro pin
heat sink
fin heat sink
Figure 7. Comparison of coolant pressure drop for the three heat sinks for
mass flow rate =1.5 mL/s.
A numerical analysis using FLUENT software is
performed considered 1.5 mL/s of water in laminar regime
and single phase. The fluid inlet temperature was set at 293
K. The heat flux applied was 100 W/cm2. The results of the
(i) heat sink and coolant temperature variation, and (ii)
pressure drop are presented in Figures 6 and 7 respectively.
Conventional microchannel heat sink formed by 33 channels
with 200 m height, 10 mm length, 100 m space between
channels and  = 1.0 is considered for comparison. Since the
heat transfer coefficient and surface area are uniform
throughout for the uniform density pin fins, a rise in coolant
temperature leads to a corresponding increase in the heat
sink temperature as shown in Figure 6. Similar trend is
observed for a microchannel heat sink, although the heat sink
temperature is higher due to relatively large microchannel
sizes employed. Decreasing the microchannel size will result
in lower heat sink temperatures, but the temperature rise will
be same along the flow direction. In the new design, the
increasing fluid temperature along the flow length is offset
by the increased heat transfer rate due to increased fin
density along the flow length. This results in a more uniform
temperature variation. Comparing the values from Figure 7,
the temperature variations are: 38°C for microchannels, 17°C
for uniform pin fins, and only 8°C for the new design shown
in Figure 5(b). It employs a step-wise variation in fin
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density; a continuously increasing fin density variation may
yield an even lower temperature variation.
vi) Thermal Modeling of 3D IC Stack
A number of researchers have modeled the thermal
performance of a 3D IC stack cooled by microchannel
interlayers. A number of advanced simulation models have
been presented in the literature and they provide valuable
guidance for future development in this field [16,27-31].
IV.
CONCLUSIONS AND FUTURE RESEARCH NEEDS IN 3D
IC THERMAL MANAGEMENT
The 3D IC stacks present some new challenges in the
thermal management. The cooling mechanism is
considerably altered due to additional consideration of
thermal interactions among devices, hot spots, modifications
in the thermal paths and introduction of additional thermal
resistances. Some of the research needs in this emerging area
are listed herein.
 The placement of IC devices in different layers is
perhaps the single most important factor in the
successful thermal management of 3D IC stacks.
 Two new parameters, Thermal Intensification Factor
(TIF) and Thermal Derating Factor (TDF) are introduced
to account for the thermal interactions among devices
and additional thermal resistances introduced due to 3D
stacking.
 Design strategies and procedures need to be developed
for device placements to yield a low value of the TIF to
limit the hot spot temperatures and reduce the demands
on the cooling system design.
 Thermal designs need to be developed to yield a low
value of TDF, close to one, to increase the thermal
dissipation rate.
 The microchannel cooler employed in interlayers need to
be developed to meet the 3D IC stack requirements of
allowable pressure and pressure drop. Enhancement
techniques, and novel designs such as utilizing
increasing pin fin density along the flow lengths need to
be developed and optimized for the pressure drop, heat
transfer, and temperature uniformity constraints
 New designs of manifolds are needed for ascertaining
uniform flow distribution in each channel of a
microchannel cooler chip.
 Packaging is a critical issue in assuring leak-proof,
reliable thermal management cooling system.
 Novel Thermal insulating materials such as Graphene,
which can be used as interconnects or heat spreaders for
better thermal conductivity.
 Suitable coolants need to be developed. Water based
coolants have better heat transfer performance. For these
coolants, the electrical integrity and durability of
packaging needs to be ascertained.
V.
REFERENCES
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