Estimation of process variation impact on DG-FinFET Device
performance using Plackett-Burman Design of Experiment Method
(Invited Paper)
A.N.Chandorkar l *, Sudhakar Mandel, Hiroshi Iwai 2
1 pepart~ent ofElect~ical Engineering, Indian Institute of Technology Bombay, Powai, Mumbai -400076, India
Frontier Collaborative Research Center, Tokoyo Institute of Technology, 4259, Nagatsuta, Midori-Ku, Japan
*Email: [email protected]
Abstract
This paper studies various Double-Gate (DG) FinFET
structures optimized for better "off state" and "on state"
performance. In this work, we study the impact of
process variation on the performance of DG-FinFET
device with 20nm gate length. This was achieved
through calibrated TCAD simulations. We show that the
spacer thickness variation has the highest impact on Ion
of the DG-FinFETs. In this work, we also have
demonstrated
the
suitability
of method
of
Plackett-Burman Design of Experiments (PB-DOE), for
accurate estimation of the impact of the large number of
process parameter-variations on DG-FinFET device's
electrical performance.
1. Introduction
Moore's law till this day has remained as a driving
force to scale CMOS technology beyond 45nm
technology node to meet power, speed and packaging
density of current state of art integrated circuits. At such
lower technology node use of conventional planar single
gate MOSFETs is becoming extremely difficult due to
enhanced Short-Channel Effects (SCEs)[l ]-[3]. In
addition to SCEs, planar MOSFETs suffer from random
dopant fluctuations (RDF) in the channel area, which is
believed to be the main source of threshold voltage
mismatch among the devices, fabricated on the same
wafer [4]-[5]. Various structures of the DG-FinFETs are
the most promising candidates for the replacement of
conventional single gate planar MOSFETs due to their
higher immunity to SCE. A typical DG-FinFET device
architecture as shown in Fig.l uses undoped ultrathin
body (UTB) to control SCEs within acceptable limit via
gate work function engineering. Such undoped UTB
mitigates the effect of random dopant fluctuations on
threshold voltage mismatch.
In literature various attempts have been made to
optimize DG-FinFET device structure for better control
of SCEs. Vishal et al. [2] suggested optimization of
DG-FinFET device through minimal underlap. This
work also suggests the trade off between effects of the
SCEs and the speed. Katuikho et al. [6] have optimized
the structure of the DG-FinFET through source/drain
doping profile by controlling the straggle of the implant
and the offset from the gate edge and obtained the
optimal straggle and the offset for given body thickness.
All these studies thus reveal the importance of underlap
in DG-FinFETs to control SCEs within acceptable limits
when gate lengths are scaled further down to and beyond
20nm. In addition to optimization of DG-FinFETs for
better SCEs, such study finds an opportunity to study
extensively process variation impact on device and
circuit performance. Shiying et al. [4] have studied the
sensitivity of various process variations on the
performance of the DG-FinFET using Monte Carlo
Simulations. Emanuele et al. [7] have shown the impact
of line edge roughness (LER) on FinFET matching
performance. However, in such studies authors
considered only few parameters such as oxide thickness
(Tox), UTB thickness i.e. the Fin thickness (Tfin) and the
gate length (Lgate). However, in reality, many other
parameters such as Tgate, Xspacer etc needs to be
considered. In this work, we have used a new technique
called the Plackett-Burman (PB-DOE) technique to
identify most sensitive process parameters causing
variability in the device and the circuit performance. The
new method is more versatile than the earlier suggested
ones for such studies, as it allows simultaneously
multiple process variations and arrives at influence of
each of them on the multiple performance parameters
desired.
This paper is organized as follows. Section II gives
the implementation of PB-DOE technique on FinFETs
with gate length of 20nm. Section III validates the PBDOE approach to find the sensitivity of process
parameters on device performance. Section IV explains
the implementation of PB-DOE approach with more
number of process parameters. The conclusion and
future scope of this work is given in section V.
2. Validation of Plackett-Burman
Experiment Technique
Design
of
2.1 Plackett-Burman DOE
The PB-DOE [8]-[9] is used to quantify the impact of
process variations on device responses such as lon, loff.
This quantitative analysis enables to identify the most
significant process parameters, which causes the
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variability in device and circuit performance. The
PB-DOE method uses the orthogonal arrays to analyze
the process parameter impact with minimum number of
experimental runs. For example, with this method, N
numbers of runs are required to estimate effects of (N-I)
number of process parameters. A typical PB-DOE for 8
experimental runs with 7 process parameters is shown in
Table 1. In this table PI to P 7 indicates process
parameters and "+" and "-"signs are used to represent
the high-level and low-level values of the corresponding
process parameter. The rows in table represent the
experimental run with corresponding values of the
process parameter. The response of the each
experimental run is indicated by Y 1 to Y8.
Table 1: Plackett-Burman DOE for 8 runs
esponses
PPP
1- 8:
1- 2: rocess Paramet ers, YYR
PI
P2
P3
P4
Ps
P6
P7
y
1
+
+
+
-
+
-
-
YI
2
-
+
+
+
-
+
-
Y2
3
-
-
+
+
+
-
+
Y3
4
+
-
-
+
+
+
-
Y4
5
-
+
-
-
+
+
+
Ys
6
+
-
+
-
-
+
+
Y6
7
+
+
-
+
-
-
+
Y7
8
-
-
-
-
-
-
-
Ys
2.2 Analysis of Plackett-Burman DOE
The PB-DOE is used as screening experiment to screen
out the less significant process parameters. The effect of
each process parameter on given response is obtained by
finding sum of squares (SS) of each process parameter
using the following expression.
SS(P) = [avg(Y +) - avg(Y- )]2
with that obtained by Monte-Carlo technique
implemented on the same structure and the dimensions
of the device as given by Shying et ale [4]. The
DG-FinFET structure used for this validation of
approach is shown in Fig 1. The statistics of the
approach of Shying et ale [4] and that of our PB-DOE
approach while obtaining the sensitivity of process
parameters is summarized in Table 2. In Shying's
approach, Monte Carlo method is used to obtain the
standard deviation a of Ion , lofT, sub-threshold slope S
and the threshold voltage. The contribution of each
process parameter to the variability Le. standard
deviation of lon, lofT, Vth and sub threshold slope is also
reported. We then apply the PB-DOE method, to obtain
contribution of each process parameter on the variability
of the lon, lofT,Vth and sub-threshold slope S. Since our
initial objective is to validate the PB-DOE approach, we
use same number of variables as used in the study of
Shying et ale [4], so that we can compare the trends from
both these approaches and decide how effectively PBDOE approach captures the variability trends. Hence we
do not consider the variations in the parameters such as
Tgate, Xspacer, Xsd and Ysd .
Fig.l. FinFET Device structure used for device
simulation
Table 2: PIackert-Burman DOE for 3 process parameters
Parameter
Nominal
Values
PI-Lgate
P2-Tfin
P3-Tox
P4-Tgate
20.0nm
5.0nm
I.Onm
30.0nm
P5- Xspacer
IO.Onm
P6-Xsd
75.0nm
P7-Ysd
75.0nm
(1)
where SS (P) is sum of squares of process parameter P,
avg (Y+) is the average value of response when process
parameter P is at high level and avg (Y-) is the average
value of response when process parameter is at lower
level. The SS of all process parameters give the
contribution of each process parameter to the variability
in the given response.
2.3 Implementation of Technique of Plackett-Burman
of DOE
We have first validated our PB-DOE method by
comparing its results for the same DG-FinFET structure
Shiying &
Boker
approach
30'
variation
2.0nm
I.Onm
O.1nm
Not
considered
Not
considered
Not
considered
Not
considered
Plackett-Burman
DOE
Low level High
level
18.0nm
4.0nm
O.9nm
29.999nm
22.0nm
6.0nm
1.lnm
30.001nm
9.999nm
IO.OOInm
74.999nm
75.001nm
74.499nm
75.00Inm
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:=
1DI
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.....-
~:~kett-:I:::~:PP::::
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Process Parameters
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Fig 2 (a)
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Shl
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Fig 3 (b)
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Process Parameters
Process Parameters
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Fig 2 (C)
Fig 2 (d)
Fig 2. Implementation of PB-DOE method, showing
contribution of each parameter to N-FinFET device
variability
Equality of two approaches has been obtained by
implementing in our PB-DOE matrix by using almost the
same values for both the low-level and the high-level
values of the corresponding parameters, as indicated in
the Table 2. Thus this allowed us to obtain impact of
parameters Lgate, Tfin and Tox on lon, IotT, V th, and
Sub-threshold slope, as reported in [4]. The results of our
implementation on N-FinFET and P-FinFET are shown
in Fig.2 and Fig.3 respectively. These figures show the
individual contribution variability of Lgate , Tfin and Tox
to IotT, Ion, Vth and sub threshold slope. From Fig 2 and
Fig.3, it is clear that, the reported approach [4] and our
Plackett-Burman approach show almost the same trend
for the circuit parameters as stated above for the
N-FinFET and the P-FinFET under investigation.
Hence we conclude that our PB-DOE approach is
adequate to estimate the contribution of individual
process parameters on the variability of the given
response with reasonable accuracy. In the reported work
sensitivity of only three process parameters are
considered. The complexity of the Monte Carlo
simulations forced earlier workers to limit the
simulations with only a few process parameters.
However in our case no such limitation is observed even
considering variability of large number of process and
device parameters. Like we have included in our work
other parameters of FinFET such as Xspacer, Tgate etc,
which are also important, and need to be considered.
3. Plackett-Burman
Parameters
with
Large
number
of
21
1D
~
D
~
Process Parameters
Pr~Pa~mem~
3.
~
Lga"
Tfln
Process Parameters
Lg_
Tftn
Process Parameters
Fig3(c)
Fig3(d)
Fig 3. Implementation of PB-DOE method, showing
contribution of each parameter to P-FinFET device
variability
parameters P4 to P7 for which are low-level values.are
considered as -10% and high-level values are considered
as +10% of their nominal values. The contribution of the
individual process parameters to the variability in 10tT, 10m
Sub-threshold slope Sand Vth , is obtained using the
same method as explained in earlier section II. The
results of our simulations are presented as histograms as
shown in Fig.4 (a) to Fig.4 (d) respectively. It is
interesting to note that, the results our PB-DOE method
which considers more number of parameters for
variability, show a different trend, for the variability of
responses compared to one which uses lesser number of
them, as were obtained earlier in the section II. Fig.4 (a)
to Fig.4 (d) shows the contribution of different process
parameters to 10tT, lon, Sub-threshold slope S and Vth
variability due to 3 and 7 number of process parameters.
In the case of 3 number of process, Fin thickness Tfin
shows the highest contribution to the Ioff, lon, and
Sub-threshold slope and Vtb variability. This is similar to
what has already been reported in [4]. However, the
individual contribution to the variability changes
significantly when all the 7 process parameters are
considered. In Fig 4 (b) shows that Tfin shows lower
impact on Ion variability (unlike the already reported
trend) and spacer shows the highest contribution to the
Ion variability. Hence, with an extended PB-DOE, we
show that a variation in spacer thickness has highest
impact on FinFET device performance. In order. to
confirm our finding we have used a more exhaustive
individual parameter approach and Monte Carlo
approach. This is explained in section IV.
In this section we have implemented PB-DOE method
with seven process parameters with their "low" and
"high" level values as given in Table 2 except for
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30
60
20
60
50
40
30
20
10
40
40
30
20
o
Process Parameters
Fig 4 (a)
Fig 4(b)
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Tox
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Tox
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Fig 5(a)
Fig 5(b)
Fig. 5 Comparison of PB-DOE method with Monte
Carlo and Individual approach
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ToxTgaleSpacerXtId
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110
100
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80 r=========~
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O~~~--:-r-.,.........,.__---.,...........-,.......l
LgaR
n Tox TgablSpacerXsd
Process Parameters
Fig 4 (c)
Fig 4(d)
Fig 4. Implementation of PB-DOE on N-FinFET with 7
parameters
4. Monte Carlo and Individual Parameter Approach
In this approach we have considered one process
parameter at a time, which is then varied from low-level
to high-level as per Table 2. For each process parameter
we carried two simulations with its low value and high
value. For 7 process parameters 14 simulations are
carried. The contribution of each process parameter to
the change in Ion and Vth is obtained. Similarly we
performed Monte Carlo simulations with same statistics
as given in Table 2. The results of individidual approach,
Monte Carlo method and PB-DOE method are shown in
Fig 5. The results of our PB-DOE approach, the
individual parameter approach and Monte-Carlo
technique show the same trend with reasonable accuracy.
The slight inaccuracy can be attributed to the parameter
interactions in PB-DOE approach. However, the MonteCarlo technique uses larger computer resources and also
much more simulation time. However the above
experiments were conducted to prove that our
Plackett-Burman technique is simpler, less exhaustive
and as accurate as standard Monte-Carlo technique. One
can observe that the Fig 5(a) validates that the spacer
thickness variation shows the highest contribution to the
Ion variability. This is attributed to large change in series
Source/Drain resistance due to spacer thickness variation
as reported in [10].
performances of FinFET device. Our new PB-DOE
approach is also validated against the reported results the
literature, which uses Monte-Carlo method. We extended
the PB-DOE approach for larger number of relevant
process parameters in FinFET fabrication and studied the
impact of these process parameters on the variability of
the circuit responses. An interesting result obtained by us
using the Plackett-Burman approach shows that Ion
current of an N-FinFET and P-FinFET is more sensitive
to spacer thickness variation than the variation of the
fin-thickness, which is unlike the reported trends. This
will certainly have a significant impact on the process
variations on the speed of FinFET circuits, which will be
crucial in Circuit design.
References
[1]
Edward 1. Nowak, Ingo Aller et. aI., "'Overcoming silicon scaling
barriers with double-gate and FinFET Technology," IEEE
Circuits and Devices Maga=ine, January/February 2004.
[2]
Vishal
Trivedi,
Jerry
Fosum,
"Nanoscale
FinFETs
with
Gate-Source/Drain Underlap," IEEE Transactions on Electron
Devices. Vol. 52, No.1, January 2005.
[3]
1.G.Fossum et aI., "'Physical insights on design and modeling of
nanoscale FinFETs," in IEDM Tech. Dig., Dec.2003.
[4]
Shiying Xiong, Jeffery Bokor,"Sensitivity of Double-Gate and
FinFET devices to process variations,"
IEEE Transactions on
Electron Devices, Vol. 50, No. 11, November 2003.
[5]
A.N.Chandorkar et.al , "Impact of process variations on Lekage
[6]
Katsuhiko Tanaka et al. , " Source/Drain Optimization of Double
Power in CMOS circuits in Nano Era,"
ICSICT 2006
Gate FinFET Considering GIDL for Low Standby Power
Devices," IEICE ELCTRON., VoI.E90-C APRIL 2007.
[7]
Emanuele Barvel1i et aI., "Impact of Line-Edge Roughness on
FinFET Matching Performance," IEEE Transactions on Electron
Devices, Vol. 54, No.9, September 2007.
[8]
Raymond H Mayers and Douglas C Montgomery, "Response
5. Conclusion and Future Scope
[9]
Sudhakar Mande and A.N.Chandorkar et. aI, "Response Surface
In this paper we have successfully applied
Plackett-Burman Design of Experiments method for
studying and to quantify impact of process variations on
[10] Wei Ke et.al, "Source/Drain series resistance of nanoscale
Surface Methodology," Wiley Series in Probability and Statistics
Methodology for statistical characterization of nano CMOS
devices and circuits," Proceedings of IWPSD 2007.
ultra-thin-body SOI-MOSFETs with undoped or very low doped
channel regions," Semiconductor Science and Technology 2006.
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