Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern
Sensitive Faults in Memories
Rajeshwar S. Sable1, Ravindra P. Saraf2, Rubin A. Parekhji3 and Arun N. Chandorkar4
1
Tejas Networks Pvt. Ltd. , Bangalore, India. Email: [email protected]
Intel Technology India Pvt. Ltd., Bangalore, India. Email: [email protected]
3
Texas Instruments (India) Pvt. Ltd., Bangalore, India. Email: [email protected]
4
Indian Institute of Technology, Mumbai, India. Email: [email protected]
2
Abstract
Traditional tests for memories are based on conventional
fault models, involving the address decoder, individual
memory cells and a limited coupling between them. The
algorithms used in these tests have been successively
augmented to consider stronger coupling conditions. Built-in
self-test (BIST) solutions for testing memories today
incorporate hardware for test pattern generation and
application for a variety of these algorithms. This paper
presents a BIST implementation for detection of
neighbourhood pattern sensitive faults (NPSFs) in random
access memories (RAMs). These faults are of different classes
and types. More specifically, active, passive and static faults
for distance 1 and 2 neighbourhoods, of types 1 and 2, are
considered. It is shown how the proposed address generation
and test pattern generation schemes can be made scaleable
for the given fault type under consideration.
Keywords: Built-in self-test for memories, neighbourhood
pattern sensitive faults, programmable BIST.
1. Introduction
Shrinking feature sizes and increase in the levels of
integration have significantly impacted the design and test of
random access memories (RAMs). While memory cells and
architectures have become increasingly compact, they are
now also susceptible to increasingly diverse failure
mechanisms. This has rendered the traditional memory test
methods inadequate, either in terms of their defect coverage
or in terms of the test application time. Built-in self-test
(BIST) methods for testing RAMs, based on conventional
March tests and their extensions, are becoming popular. These
tests are easy to implement, have a cycle count complexity
which is linear to the number of bits or words addressed, and
provide good fault coverage for functional faults and some
structural faults, covering the address decoder, individual
memory cells and a limited coupling between them [1]. BIST
also offers other well-known advantages, which will not be
repeated here [2,3]). Existing BIST implementations for
memories are, however, inadequate for some other fault
models like stronger and widespread coupling faults. Hence,
to ensure the desired defect coverage in a memory core, it is
necessary to consider these newer fault models and provide a
matching BIST implementation for effective test generation.
It is also important to make this implementation
programmable for the desired combination of fault coverage
and test time so that BIST can be efficiently used.
This paper describes a BIST technique for the detection
of neighbourhood pattern sensitive faults (NPSFs) in random
access memories. Although the NPSF model is not new, it is
now becoming important in deep-submicron processes,
especially for DRAMs [4]. Also, the fault model scales with
the neighbourhood size. Traditional March tests are not adequate
for detection of such NPSFs [1,5]. Hence the proposed BIST
mechanism for detecting NPSFs is designed to correspondingly
match the faults being considered. The salient features of this
BIST implementation are: (a) It uses the well-known tiling
method and employs a parallel access mechanism to memories
to reduce the cycle count. (b) It employs a bit-slice architecture
for the test pattern generator to generate a Eulerian sequence for
covering the cells in the neighbourhood. (c) The BIST
implementation, based on the proposed address and test pattern
generation schemes, is scaleable for four different NPSF models,
(based on distance 1 and 2, and types 1 and 2), for active,
passive and static faults. This implementation covers stuck-at
faults, transition faults, inversion coupling faults, idempotent
coupling faults and static coupling faults, besides the NPSFs
mentioned above. As complete rows of cells are accessed for
read and write operations, this test is better suited for wider
memories. (According to the authors, this is the first time that
such a BIST implementation for NPSFs is being reported).
This paper is organized into six sections. Section 2 provides
an overview of NPSFs, their classes and types, and challenges in
their detection. Section 3 describes the basic BIST technique for
detection for one class of NPSFs, together with its
implementation. This implementation is extended in Section 4 to
include other types of NPSFs. The overall BIST operation is
summarised in Section 5. Section 6 concludes the paper.
2. Overview of Neighbourhood Pattern Sensitive Faults
A pattern sensitive fault is a conditional coupling fault in
which the content of a memory cell or the ability to change its
content is influenced by a certain bit pattern in other cells in the
memory [1]. Here the data retention and transition of the victim
cell are affected by a set of aggressor cells. A neighbourhood
pattern sensitive fault (NPSF) is a special case of pattern
sensitive faults, wherein the influencing (coupling) cells are in
the neighbourhood of the influenced (coupled) cell. The coupled
cell is called the base (or victim) cell and the coupling cells are
called the deleted neighbourhood cells. (The neighbourhood
includes all the cells in the deleted neighbourhood as well as the
base cell). Refer to Figure 1. Here the cell V represents the base
or victim cell, while the cells B, W and C represent the deleted
neighbourhood.
2.1.
Classification of NPSFs
Different NPSFs can be grouped based on the nature of
faults in the base cell and on the neighbourhood:
Active NPSF: The base cell changes its content due to a change
in the deleted neighbourhood pattern. To test these faults, the
base cell should be read in state 0 and state 1 for all possible
transitions in the deleted neighbourhood.
Passive NPSF: The content of the base cell cannot be changed
due to a certain neighbourhood pattern. Every base cell has to be
Proceedings of the 17th International Conference on VLSI Design (VLSID’04)
1063-9667/04 $ 20.00 © 2004 IEEE
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on October 24, 2008 at 06:52 from IEEE Xplore. Restrictions apply.
written and read for 0 and 1 for all possible combinations of
the deleted neighbourhood pattern for testing these faults.
Static NPSF: The content of the base cell is forced to a
certain state due to a certain deleted neighbourhood pattern.
For all possible combinations of the deleted neighbourhood
pattern, the base cell should be read in state 0 and state 1 for
testing these faults.
We now consider two neighbourhoods for NPSFs,
leading to five possible fault models. Refer to Figure 1.
C1
B1
B1
W1
V
W2
B2
C1
B1
C2
W1
V
W2
C3
B2
C4
B2
W1 W2
V
C5
W3 W4
B3
B4
(a) D 1 T 1
V= Vict im cell
(b) D 1 T 2
(c) D 2 T 1
B1 -B4 = Bit lin e N eigh bo urh o o d cells
C2
C6
B1
B2
W1 W2
V
C9
B3
C1 0
C1 3 C1 4 B4
C3
C7
B1
C4
C8
C1
W3 W4
W1 W2
C1 1 C1 2
C3
C1 5 C1 6
(d) D 2 T 2
W 1 -W 4 = W o rdlin e N eigh bo urh o o d cells
B2
V
B3
C2
W3 W4
C4
B4
(e) D 2 RT 2
C1 -C1 6 = Co rn er cells
Figure 1. NPSF models for BIST implementation.
D1T1: Neighbourhood of Distance 1 and Type 1. The
neighbourhood includes five cells, namely the base cell and
four cells physically adjacent to it. (Figure 1(a)).
D1T2: Neighbourhood of Distance 1 and Type 2. Here eight
cells physically adjacent to the base cell are considered, to
have a neighbourhood with a total of nine cells. (Figure 1(b)).
D2T1: Neighbourhood of Distance 2 and Type 1. The
neighbourhood includes nine cells, namely the base cell and
eight cells physically adjacent to it. (Figure 1(c)).
D2T2: Neighbourhood of Distance 2 and Type 2. Here
twenty-four cells physically adjacent to the base cell are
considered, to have a neighbourhood with a total of twentyfive cells. (Figure 1(d)).
D2RT2: Neighbourbood of Distance 2 and Reduced Type 2.
The D2T2 model is reduced to consider only twelve
physically adjacent cells, to have a neighbourhood with a total
of thirteen cells. (This may also be termed as neighbourhood
of Distance 2 and Extended Type 1 – D2ET1. Refer to Figure
1(e)).
From a proximity point of view, the D2T1
neighbourhood is not considered in this paper.
2.2. Detection of NPSFs
Some attempts have been reported in the literature to
supplement traditional March tests. Instead of only the all
zeros and all ones background patterns, the modified March
tests proposed in [6] use multiple data background patterns
and have test lengths of either 96.n and 100.n for type 1
neighbourhood, (where n is the number of bits addressed).
This number increases for the type 2 neighbourhood. The
technique of parallel testing, proposed in [7] uses a restricted
type 2 neighbourhood that divides the eight cells of distance 1
neighbourhood into three groups based on their location, i.e.
horizontal, vertical and diagonal neighbours. All the cells
across groups are read and written simultaneously. The test
length is reduced; however, a lesser number of NPSFs are
covered as a result of this cell grouping. The row March
algorithm in [8] has high coverage of conventional faults, but,
additionally, only S-NPSFs are covered. Pseudorandom tests
[9] typically have a huge complexity for an acceptably low
escape probability.
3. BIST Implementation for NPSFs
We first illustrate the BIST implementation for the D1T2
neighbouhood. The memory bitmap is covered using the tiling
method [1,7] in which a memory is completely covered by
tiles of 3x3 cells, and the test patterns are applied to all the
rows in horizontal tiles simultaneously. This method reduces
write operations from n*2k to (n/k)*.2k for static NPSFs, and
from n*k*2k to n*2k operations for active and passive NPSFs
together, where k is the size of neighbourhood and n is the total
number of memory cells [1]. The incomplete tiles as well as the
overlapping tiles are also completely covered by the test
patterns. This is formally proved in [10].
3.1. Address Generation Mechanism
In this implementation, a complete row of cells is accessed
from the outputs of sense amplifiers. This enables writes and
reads to the complete row of the memory cell array. The address
generation and data application mechanism is shown in Figure 2.
Since there is only one transition between two consecutive
patterns, the data in only one of the three rows of a tile changes.
Hence a counter is used for generating the row address, such that
the next state is obtained by incrementing the present state by
three. Two consecutive data patterns are compared and the
comparator output is used to derive the initial state of the
counter through the combinational logic. Depending upon the
row of a tile in which the pattern changes, the initial state of the
counter can either be zero, one or two. The counter then
generates the next set of addresses, three rows apart, until it
overflows.
0
1
2
3
4
5
6
7
8
C o m p a r a to r
0
1
2
3
4
5
6
7
8
N e x t d a ta p a tte r n
P r e v io u s d a ta p a tte r n
C o m b in a tio n a l lo g ic
fo r s e ttin g in itia l
c o n d itio n o f c o u n te r
C o u n te r fo r
a d d r e s s g e n e r a tio n
A d d r e s s to
m e m o r y u n d e r te s t
Figure 2. Address generation mechanism.
The same pattern sequence is applied to every tile. Hence
all the cells in a particular row for each horizontal tile can be
compared together. In the fault free condition, all the
corresponding cells have the same data. Dissimilar data
indicates an error. The number of cycles required for this test is
4609*r read cycles and 4609*r/3 write cycles, i.e. a total of
(4/3)*r*4609, where r is the number of rows in a memory cell
array. For a RAM with multiple array architecture, this test can
be applied in parallel to all arrays. Hence a larger memory can
be tested in the same number of test cycles as required for a
single array. The total number of test patterns required is 4609
for a 3x3 tile and the total number of cycles required is 198187
for a 32x32 bit memory.
3.2. Test Pattern Generation Mechanism
For detecting all possible NPSFs, a 0o1 and 1o0
transition must be generated for the each deleted neighbourhood
cell in each tile for all possible patterns of other cells including
the base cell in the deleted neighbourhood. An efficient set of
test patterns can be created by having only one transition in the
neighbourhood between two successive patterns. Such a set can
be generated by using a Eulerian sequence [1]. A Eulerian
sequence is a walk over a Eulerian graph, (i.e. a graph in which
nodes correspond to individual bit patterns, and there exists a
bidirectional edge between any two nodes with Hamming
distance of one), which traverses each arc (in each direction)
exactly once. The length of a k-bit Eulerian sequence is (k*2k)+1
[1]. In this implementation, a 9-bit Eulerian sequence is required
Proceedings of the 17th International Conference on VLSI Design (VLSID’04)
1063-9667/04 $ 20.00 © 2004 IEEE
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on October 24, 2008 at 06:52 from IEEE Xplore. Restrictions apply.
for the nine cells in a 3x3 tile and hence the number of test
patterns is 4609.
The implementation of a deterministic test pattern
generation (TPG) unit is described in Section 3.3. The
proposed unit generates the 9-bit Eulerian sequence by
implementing Hay’s algorithm [1]. A part of this sequence is
presented in Table 1 and is constructed by reading the
contents of the first pattern column, (shown by arrow),
followed by the second pattern column and so on. (X, G and T
denote the pattern (in G), the Gray code group and the
transformation, respectively). The first column of 512 patterns
is generated using a 9-bit Gray counter. This column, by
exploiting the above algorithm, can generate the patterns in
the other columns. The patterns in the next column are
generated from those in the present column by performing
one bit right shift followed by inversion of Most and Least
Significant Bits (MSB, LSB).
Table 1. Nine bit Eulerian sequence
Figure 3. Test pattern generator.
3.3. Implementation of Test Pattern Generator
The block diagram of proposed TPG unit is shown in
Figure 3. The unit consists of a 9-bit Gray counter, 9-bit
parallel input/output right shift register, control circuit, and
output register. The unit has three input signals, namely
pat_en (pattern enable), clk (clock) and reset. It has two
output signals; pat_out (pattern output) which gives the 9-bit
pattern and pat_end (end pattern) which indicates the
termination of the pattern generation process. A BIST
controller controls the testing process. The BIST controller
uses pat_en to send a request to the TPG to provide the next
test pattern of the Eulerian sequence. This pattern is used for
the subsequent test data write operation to the memory array.
The BIST controller uses reset during the initialization phase
of the testing process in order to reset the internal counter and
registers of the TPG unit. The operation of each block of the
TPG unit is explained below.
3.3.1. Rotate and Output Circuit
The rotate and output circuit is shown in Figure 4. The
Gray counter provides 512 sequential patterns of the second
column of Table 1 under the control of pat_en signal. Every
pat_en signal enables the counter to count up in order to
provide a new pattern. When the final pattern of the sequence
has been reached, i.e. 100000000, the counter restarts. These
patterns are sent either to the output register or loaded into the
shift register under the control of pat_en and up_clk signals. If
one or more rotate operations must be performed for the desired
test pattern, the control circuit provides an equal number of
successive rot_clk signals to rotate the contents of shift register.
Figure 4. Rotate and output circuit.
The output of the Gray counter is directly fed to the output
register to generate the first column of patterns. For the second
column, the output of the Gray counter is loaded into the shift
register and shifted out by one bit before being sent to the output
register under the control of rot_clk, rotate and mux_ctl signals.
The patterns for the rest of the columns are similarly generated.
3.3.2. Control Circuit
The 9-bit status register with its LSB input permanently
connected to logic 1, holds the rotation status of the TPG,
indicating the number of rotate operations that must be applied
to every pattern generated by the Gray counter according to the
progress of the test pattern generation process. The number of
bits inside the status register with value 1 indicates the number
of rotate operations that must be performed on shift register.
Thus the state 000000000 in the status register means no rotate
operation, while states 000000001, 000000011, …, 011111111
mean one, two, …, and eight rotate operations, respectively. The
MSB of the status register going to 1 indicates the completion of
the test pattern generation process, and pat_end signal is
activated. The status register is shifted out by signal up_clk each
time the Gray counter returns to its initial state, i.e. 000000000.
The 8-bit step register is used to generate the appropriate
number of successive rot_clk signals for right shift of each
pattern generated by the Gray counter based on the current status
of the TPG. The pat_en signal initiates the shift process under
the control of clk signal. In each step of the shift operation inside
the step register, when a 1 is encountered from the LSB to the
MSB, the rot_clk signal is activated depending upon the
contents of the status register, using the And-Or array shown in
Figure 5.
Figure 5. Control circuit.
4. BIST Implementation for Selective NPSFs
The implementation described in Section 3 can be extended
to generate another Eulerian sequence with a different number
of bits. This scaleability is exploited to generate sequences for 5bits, 13-bits and 25-bits to additionally target D1T1, D2RT2 and
D2T2 faults, respectively. The block diagram for the complete
BIST implementation, incorporating the address generator, test
pattern generator and test response evaluator, is shown in Figure
Proceedings of the 17th International Conference on VLSI Design (VLSID’04)
1063-9667/04 $ 20.00 © 2004 IEEE
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on October 24, 2008 at 06:52 from IEEE Xplore. Restrictions apply.
6. Note that the select input line to the BIST controller must
be set to target the specific fault model.
The mechanism for D1T2 fault detection can be extended
to detect D1T1 and D2T2 faults. The mechanism for D2T2
fault detection can further be extended to detect D2RT2
faults. Generic extensions include changing the value of k=n,
for an n-bit Eulerian sequence, and correspondingly changing
the number of D flipflops in the rotate and output circuit. Also
the width of the status and step registers will change, together
with the size of the And-Or array in the control circuit. Based
on the tiling method, the rows are changed and the address
incremented. (Additional details can be found in [12]. These
are not included here for lack of space).
Tes t s tart
Clock
Select0
Select1
BIST controller
Test respons e
evaluator
Tes t end
Control s ignals
Addres s and data
generator
Address and data
multiplexer
System write data lines
Sys tem addres s lines
Memory under
test
Sys tem read data lines
Figure 6. Block diagram for BIST implementation.
5.
BIST Operation
A generic algorithm for BIST operation has been
developed. It supports a scaleable BIST implementation for
the detection of D1T1, D1T2, D2T2 and D2RT2 faults. (More
details on the algorithm can be found in [12]. These details
are again not included here for lack of space).
The BIST implementation proposed in Section 3 for
D1T2 faults has been realized in VHDL and simulated [11].
The approximate gate count for this implementation
consisting of the next address generation logic and test pattern
(Eulerian sequence) generation logic is about 900 gates. This
number does not include the logic in the BIST controller,
generic portions of the address generator and test response
evaluator. The latter are not considered as an additional
overhead, since they are necessary for any BIST operation.
The number of comparators for test response evaluation will
depend on the memory word size, and this logic is also not
included. Simulation has been performed to confirm the
suitability of this implementation [11]. We now make three
observations:
(a) The logic overhead in the proposed BIST implementation
is notably low. This is due to the algorithmic nature of the test
pattern generator and address generator.
(b) While the gate count is low, it can be seen that the cycle
count for the full BIST operation is notably high. This
highlights the fact that BIST for NPSFs is relatively costly in
terms of the test cycles as against the extra test logic.
(c) The implementation scales almost linearly to the number
of bits in the neighbourhood, due to the bit-slice (scaleable)
architecture used in this technique.
Table 2. Cycle count for NPSF detection for different fault
models
Fault
model
Number of
test patterns
Number of
write cycles
Number of
read cycles
D1T1
D1T2
D2RT2
D2T2
161
4609
106497
838860801
5313
50699
3727395
5872025607
15456
147488
17039520
26843545632
Approximate test
time
@100
@500
MHz
MHz
0.208ms
0.042ms
2ms
0.4ms
200ms
40ms
330s
66s
As an illustration, the number of test patterns and clock
cycles required to test a 32x32 memory for various NPSF
models is given in Table 2. It can be seen from the above table
that the proposed BIST implementation is amenable for large
word length, i.e. wide memories. BIST provides a convenient
mechanism for off-line testing, wherein the tester infrastructure
is not dedicated to the device under test. Under this condition,
test times constraints can be relaxed. Also, in several cases, it
may be adequate to detect D2RT2 faults as against D2T2 faults,
effectively reducing the test time by a factor over one thousand.
6. Conclusion
This paper describes a new BIST methodology for the
detection of neighbourhood pattern sensitive faults in random
access memories. The highlights of this technique include (a) a
bit-slice BIST implementation which is scaleable both for
implementation and test application depending upon the faults of
interest, (b) low cost implementation of the address generator
and test pattern generator, and (c) ability to detect distance 1 and
2 faults of types 1 and 2. This programmability is important
since NPSF detection is costly in terms of the number of cycles.
Future work in this direction includes the definition of a
programmable architecture for memory BIST to encompass
traditional March tests with NPSF tests, optimizations in the test
pattern generation logic, and optimizations in the address
generation logic for large memories.
Note: This work was done when the first two authors were
students at Indian Institute of Technology, Mumbai, India.
References
1. A.J.Van De Goor, Testing of Semiconductor Memories:
Theory and Practice, ComTex
Publishing, The
Netherlands, 1999.
2. P.H.Bardell, W.H.McAnney and J.Savir, Built-in Test for
VLSI:Pseudorandom Techniques, John Wiley& Sons, 1987.
3. C.E.Stroud, A Designer’s Guide to Built-In Self-Test,
Kluwer Academic Publishers, 2002.
4. B.F.Cockburn, “Tutorial on DRAM Fault Modeling and
Test Pattern Design”, Proc. Intl. Workshop on Memory
Technology, Design and Testing, 1998, pp. 66.
5. R.Dekker et al., “A Realistic Fault Model and Test
Algorithm for SRAMs”, IEEE Trans. on CAD, 1990,
pp.567-572.
6. K-L.Cheng, et. al., “Efficient Neighbourhood Pattern
Sensitive Fault Test Algorithms for Semiconductor
Memories”, Proc. VLSI Test Symposium, 2001, pp.225230.
7. P.Mazumder, “An Efficient Built-in Self Test for RAMs”,
Proc. Intl. Test Conference, 1987, pp.1072-1077.
8. M.Franklin and K.K.Saluja, “Testing Reconfigured RAMs
and Scrambled Address RAMs for Pattern Sensitive
Faults”, IEEE Trans. on CAD, 1996, pp. 1081-1087.
9. R.David et. al., “Random Pattern Testing Versus
Deterministic Testing of RAMs”, IEEE Trans. on
Computers, 1989, pp. 637-649.
10. R.P.Saraf, An Architecture for Programmable Memory
BIST, M.Tech. Dissertation, Indian Institute of Technology,
Mumbai, 2002.
11. R.S.Sable, Memory Testing: BIST and Iddq Test
Techniques, M.Tech. Dissertation, Indian Institute of
Technology, Mumbai, 2003.
12. R.S.Sable, R.P.Saraf, R.A.Parekhji and A.N.Chandorkar,
“Built-in Self-test Technique for Selective Detection of
Neighbourhood Pattern Sensitive Faults in Memories”,
Internal communication, 2003.
Proceedings of the 17th International Conference on VLSI Design (VLSID’04)
1063-9667/04 $ 20.00 © 2004 IEEE
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on October 24, 2008 at 06:52 from IEEE Xplore. Restrictions apply.