Reliability Studies on Sub 100 nm SOI-MNSFETs
S. Mahapatra', V. Ramgopal Raol, J.Vasi', B. Cheng', and J.C.S. Woo3
Department of Electrical Engineering, Indian Institute of Technology, Bombay-400076, India.
'Advanced Products Research & Development Lab, Motorola, 3501 Ed Bluestein, Austin, TX 78721,USA
Department of Electrical Engineering, University of California, Los Angeles, CA 90095-1 594, USA.
I
Ahstract - SO1 MNSFETs with channel lengths down to 100
nin and having a Jet Vapor Deposited (JVD) silicon nitride (Si3N4)
gate dielectric are fabricated and characterized. The JVD MNSFETs
show comparable performance in coinparison to conventional S i 0 2
SOI-MOSFETs, in tenns of low gate leakage, Si3N4/Si interface
quality and lun/luf, ratio. In addition, the MNSFETs show better hot
carrier reliability coinpared to conventional MOSFETs. Our results
explore the worthiness o f J V D SiiNl as gate dielectric for future low
power ULSl applications.
K e y w o d - MOSFET, silicon on insulator (Sol),jet vapor
deposition (JVD), hot-carrier degradation (HCD)
A two-step titanium silicidation process with Ge preainorphization is iinpleinented to control the silicide depth and
reduce the series resistance. Identical bulk MOSFETs and
MNSFETs were also fabricated during the same process run for split
C-V measurements and interface characterization using charge
pumping. The electrical equivalent of gate oxide thickness (EOT)
(as measured in inversion froin split-CV measurements) was 3.9 nm
for conventional SiOz and 3.1 nm for JVD nitride as shown in
Figure 1. The thickness of the SO1 film and buried oxide are 35 nm
and 370 nin respectively.
I. INTRODUCTION
Figure 2 shows the output characteristics of a 100 nm channel
length SO1 JVD MNSFET and conventional MOSFET. Due to
differences in EOT of the Si3N4and SiOl films, the drain currents
are nonnalized to gate capacitance for fair comparison. It can be
seen that the JVD MNSFETs show identical drain current drive as
coinpared to S i 0 2 MOSFETs.
111. RESULTS AND DISCUSSION
SO1 devices are of great interest, especially for low power and
low voltage applications where the goal is to have higher drive
current and transconductance with minimal short-channel effects.
However, gate oxide scaling without the associated gate leakage is
very crucial for SO1 MOSFETs to maintain the low power
advantage down to sub 100 inn nodes. In this regard, Jet Vapor
Deposited (JVD) Si3N4showed promising characteristics as a gate
insulator [I], where more than an order of magnitude lower gate
leakage has been observed in the sub 3.5 nm gate dielectric
thickness regime, compared to conventional SiOz of equivalent gate
capacitance. Recently, a bulk CMOS process having channel length
down to 100 nm and having a JVD Si3N4gate dielectric has been
demonstrated [2,3]. In this paper, we report SO1 MNSFETs
fabricated using JVD Si3N4gate dielectric. Our comprehensive set of
electrical measurements presented in this paper on both SOIMNSFETs and its identical bulk counterpart show the salient
features of JVD nitride MNSFETs, namely; improved transistor
performance, good Si-Si3N4 interface quality, and excellent short
channel and hot-carrier reliability.
IT. DEVICE FABRTCATION
Two sets of SO1 n-channel FET's were fabricated in the same
device run in identical fashion except for the gate insulator. E-beam
lithography was used to define channel lengths down to 100 nm.
JVD nitride and thennal S i 0 2 (conventional oxide) were used as
gate dielectrics.
............. . ,
,,
Figure 2. Output characteristics of 100 nin channel length
SO1 conventional MOSFET and JVD MNSFET.
4x10'
'
-a, 3x10'
'
-
U-
0.06-
'
2
"s1x102
-
.
Oxide
-JVD nitride
0.04 -
U)
0.02 -
0.00 1
0
- 2x10~
v
cl
1
v,
.
I
-
........ ...... Oxide
0.0
0.4
0.8
3
1.2
1.6
.
v,
(VI
Figure 1. Split-CV ineasureinents in bulk conventional MOSFET
and JVD MNSFET to determine gate capacitance in inversion.
2000 IRW FINAL REPORT
8'
1x10~
n,
a
- 0
-
0.
-0.4
, I
1.0 1.5 2.0
I
.
-0.5 0.0 0.5
a
- 3x103lg
CF
-g 2x10'
4x103
(V)
Figure 3 . Transconductance as a f h c t i o n of gate bias for 100
nin channel length SO1 conventional MOSFET and JVD
MNSFET measured at low and high drain biases.
0~7803~6392~21001$10.00
'2000 IEEE
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29
Reliability Studies on Sub 100 nm SOLMNSFETs
Mahapatra et al.
Figure 3 shows the low-field transconductance (g,,,) as well as
the saturation transconductance (g,,,,sdt)as a function of Vci for 100
nin channel length JVD and conventional SO1 transistors. As before,
the measured values are normalized to gate capacitance for fair
comparison. Compared to S i 0 2 MOSFETs, both the low-field and
saturation transconductance for the JVD devices are lower at low
gate biases, and a cross-over . i s observed at higher Vci values.
Similar observation was made and explained by other workers [4].
Figure 4 shows the saturation transconductance, scaled to gate
capacitance, as a function of channel length. Note that SO1 JVDMNSFETs perfonn excellently all the way down to 100 nm channel
lengths in comparison to the conventional SOI-MOSFETs.
1 M H z and transition times of 250 ns. The substrate was shorted to
ground, and the sourceidrain current was measured. Measurements
were performed on transistors having different channel lengths.
Results are shown in Figure 6, which substantiates the extremely
good SiiSilN, interface obtained by using the JVD deposition
process.
600 I
h
Qn
v
I
-
a
300
200
100
0.05 0.10 0.15 0.20 0.25
L (pm)
E
1
m
n
.
Figure 6. Detennination of pre-stress interface-state density
in bulk JVD MNSFET and conventional MOSFET as
measured using charge pumping.
Oxide
JVD nitride
-B-Et
.
n
.
u
.
n
0.1 0.2 0.3 0.4 0.5
Channel length (pm)
Figure 7 shows the DlBL and VT roll-off measured for both
JVD and conventional SO1 transistors as a function of channel
Figure 4. Saturation transconductance as a function of channel
length. Almost no degradation in DIBL and VT roll-off for JVD
length for SO1 conventional MOSFETs and JVD MNSFETs.
nitrides shows the effect of fringing fields to be negligible, which
has been recently identified as a potential problem in replacing SiO?
Figure 5 shows the sub-threshold slope (S) and ID.sat/lof ratio
by high-K gate materials in deep submicron MOSFETs [6]. The
for the two sets of SO1 transistors as a function of channel length.
excellent short-channel performance of JVD MNSFETs is an
additional motivation for the choice of JVD nitrides at the 100 nm
No degradation in S is observed for JVD nitride SO1 transistors
indicating a good Si/SiN interface. The identical values of ID.*at/lo~ and below technology nodes.
in JVD nitride SO1 MNSFETs assures the low-power advantage of
SO1 technologies as maintainable down to the sub 100 n m
technologies.
0.00
0.20
-0.02
n
95
'
1o5
U
g
m
>
-0.04
E
-0.06
>
:
0.10
m
al
a
2 0.15
.
90.
-0.08
n
-0.10
E 85.
Io2
Channel length (pm)
Figure 5. Subthreshold slope and IDSAT/IOFF as a function
of channel length for SO1 conventional MOSFETs and
JVD MNSFETs.
The Si/Si,N, interface quality has been verified by a direct
ineasureinent of interface state density on bulk JVD-MNSFETs
using charge pumping [ 5 ] . Measurements were performed using a
fixed base level and varying top level gate pulse having frequency of
k
+
%
r
6
ul
3
-0.12
v
80
2
v
0.05
cn
<
0.1
0.2
0.3
0.4
0.5
Channel length (pm)
Figure 7 . DIBL and VT roll off as a function of channel length
for SO1 conventional MOSFETs and JVD MNSFETs.
The hot-carrier performance of SOI-JVD nitride MNSFETs
has also been studied in comparison to conventional S i 0 2 SOIMOSFETs, as shown in Figures 8 and 9. Stressing was performed at
Vc;=VD/2 condition for different times. Note that for bulk
MOSFETs, this condition is known to be responsible for inaxiinuin
avalanching and interface-state generation [7]. Due to the thin gate
oxides used in this study, we do not expect inuch permanent charge
30
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Reliability Studies on Sub 100 nm SOI-MNSFETs
Mahapatra et al.
trapping and related threshold voltage shifts, so these devices were
not stressed at other conditions (Va=V, or Vc;=V,). Note that both
for JVD MNSFET and conventional MOSFET, the well-known
power-law degradation is observed for all the measured parameters.
The lower degradation in threshold voltage, subthreshold slope,
transconductance and drive current for the JVD SO1 MNSFETs can
be clearly seen for all stress times.
1
1
-0- JVD
0.085
0.1 D
e
0.090
Nitride
0.095
0 . 00
DISTANCE ALONG THE CHANNEL (pm)
0)
0.1
0
10
JVD nitride
100
stress time (s)
1
0.01
Figure 10. Generated interface-state density distributions
along the channel as measured using charge pumping in
100 nm channel length bulk conventional MOSFET and
JVD MNSFET.
1013
1000
Figure 8. Threshold voltage shift and degradation in
subthreshold slope as a function of stress time for 100 nm
channel length SO1 conventional MOSFET and JVD MNSFETs.
V,=V,l2
h
N
6
L = I O O nm
60
1
v
a
L=100 nm
2
n,
0. 7 -
.
I
stress time (s)
n,
a
0.0
--d
10
p
JVD nitrige 0.0
100
stress time (s)
1000
Figure 9. Degradation of peak transconductance and saturation
drain current as a function of stress time for 100 nin channel
length SO1 conventional MOSFET and JVD MNSFET.
We believe the lower degradation of transistor parameters in
JVD SO1 MNSFETs compared to that of conventional SO1
MOSFETs is due to lower interface trap generation at the Si/Si3N4
interface. This fact is further substantiated by direct determination of
stress induced interface trap density distribution in bulk MOSFETs
using charge pumping as shown in Figure IO, and the time evolution
of the peak and spread of the interface trap profiles as shown in
Figure 11. This proves that the JVD Si/Si3N4 interface clearly shows
a lower degradation indicating improved robustness against hotcarrier stress in spite of its lower energy barrier (2.1 eV) compared
to the conventional oxides.
Figure 11. Evolution of interface-state density peak and spread
as a function of stress time, measured on a 100 nin channel
length bulk conventional MOSFET and JVD MNSFET.
TV. CONCLUSIONS
Thin film SO1 substrate MNSFETs with channel lengths down
to 100 nm using a JVD Si3N4 gate dielectric are fabricated and
characterized. Extremely good drive current, transconductance, short
channel and hot carrier performance of JVD-SO1 MNSFETs in
comparison to the conventional Sol-MOSFETs make them
excellent candidates for future low power applications. .
Acknowledgment: Authors wish to acknowledge Prof. T.P.Ma
for JVD depositions at the Yale University.
References:
[ I ] T.P.Ma, IEEE Trans. Elect. Dev., v.45,p.680, 1998.
[2] S.Mahapatra et al., 1999 VLSl Tech. Syinp., p.79, Kyoto, Japan.
[3] S.Mahapatra et al., IEEE Trans. Elect. Dev., to appear.
[4] M. Khare et al., IEEE Electron Device Lett., v.20, p.57, 1999.
[5] S. Mahapatra et. al., 1999 ESSDERC, p.592, Leuven, Belgium.
[6] B.Cheng etal., IEEE Trans. Elect. Dev., v.46, p.1537, 1999
[7] S.Mahapatra et al., IEEE Trans. Elect. Dev., v.47, p.171,2000.
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