PEDS 2007
Implementation of a
PWM
Single-carrier Multilevel
Technique Using Field Programmable
Gate Array (FPGA)
P. Y. Lim
N. A. Azli and L. Y. Teng
School of Engineering and Information Technology
Universiti Malaysia Sabah
Sabah, Malaysia
lpy 4ums.edu
Energy Conversion Department
Faculty of Electrical Engineering
Universiti Teknologi Malaysia
Johor, Malaysia
naziha dieee.org
Abstract The application of Field Programmable Gate
Array (FPGA) in the development of power electronics
circuits control scheme has drawn much attention due to its
high computation speed, shorter design cycle and higher
density. A single-carrier multilevel PWM technique has been
recognized for a modular structured multilevel inverter
(MSMI). This paper presents the implementation of the
PWM technique using FPGA. A simulation study has been
conducted on the operation of the MSMI based on this
technique using MATLAB/Simulink. For hardware
implementation, the gate signals of the MSMI power devices
have been generated using MAX+PLUS II software and
downloaded into an FPGA device (FLEX1OK20) from Altera.
The gate signals generated by the FLEX1OK20 have been
verified as similar to that obtained from the simulation study.
Keywords FPGA, modular structured multilevel
inverter, single-carrier multilevel PWM technique
I.
INTRODUCTION
Multilevel inverters have drawn much of attention in
recent years particularly in high voltage and high power
applications. This is due to several of its advantages
compared to the conventional two-level output inverters in
handling high power conversion. The main feature of a
multilevel inverter is its ability to operate at high DC-bus
voltages when using series connections of power devices
and reduced output voltage harmonics by switching
between multiple voltage levels. Generally, the
development of a multilevel inverter system can be
broadly divided into two issues namely, power circuit
topology and switching technique. For circuit topology,
three main types of development have been reported [1]:
(i) diode-clamped multilevel inverters (DCMI), (ii) flying
capacitor multilevel inverters (FCMI) and (iii) modular
structured multilevel inverters (MSMI) or typically known
as the cascaded H-bridge multilevel inverters.
The second aspect that defines the multilevel inverter
performance is the switching technique. This is closely
related to the harmonic profile of the multilevel inverter
output voltage waveform. Work on extending various
switching techniques that have been applied on the
conventional inverter topology such as sinusoidal Pulse
Width Modulation (SPWM), selective harmonic
elimination PWM (SHEPWM), optimized PWM
1-4244-0645-5/07/$20.00©2007 IEEE
(OPWM) and space vector PWM (SVPWM) to the
multilevel inverter topology has been reported in literature
[2]-[4].
A multicarrier multilevel PWM technique with three
carrier disposition schemes was suggested in [2] as Phase
Opposition Disposition (POD), Phase Disposition (PD)
and Alternative Phase Opposition Disposition (APOD). A
single-carrier multilevel PWM technique has also been
proposed in [5] for an MSMI for fuel cell applications.
The technique has also been highlighted in [6] and [9] as a
basis to a regular sampled PWM switching strategy for the
MSMI. For practical implementation purposes, the
switching techniques for the multilevel inverters have
been realized using various tools. The OPWM switching
technique for instance has been implemented on an MSMI
using a Digital Signal Processor (DSP) as elaborated in
[7]. The same switching technique has also been
successfully implemented using an FPGA [8].
Microcontrollers have also been used as a gate signal
generator based on the sinusoidal PWM switching
technique for an MSMI [9]. Furthermore, development of
MATLAB/Simulink blocks used in conjunction with
MATLAB/Real-Time Workshop and dSPACE/Real-Time
Interface to generate the gate signals for an MSMI has
been reported in [10].
The previous work have shown that the hardware
implementation using the various tools described earlier is
capable of producing gate signals that are in good
agreement with the simulation results. However, in some
implementation, the accuracy of the signals produced is
affected due to the sampling rates. Some of the work
presented generation of gate signals output by referring to
a look-up table. In this case time is consumed due to the
offline calculations of the switching angles for the MSMI.
In microcontrollers, additional hardware is needed to
improve the performance due to the insufficiency of the
functions provided [9]. Furthermore, there is a speed
restriction due to the limited number of processing units in
the microcontroller that causes difficulties in running
concurrent tasks.
This paper presents the implementation of a singlecarrier multilevel PWM technique for an MSMI using
FPGA. It describes the hardware development of the gate
signals generator. The performance of the gate signals
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generator is evaluated in terms of the outputs obtained
from the FPGA device in comparison to that obtained
from the results of a simulation study using
Matlab/Simulink.
II.
MODULAR STRUCTURED MULTILEVEL INVERTER
TOPOLOGY
Fig. 1 shows the configuration of a single-phase 5-level
MSMI. The MSMI is unique when compared to other
types of multilevel inverters because it consists of several
modules that require separate DC sources. When
compared to other types of multilevel inverters, the MSMI
requires less number of components with no extra
clamping diodes or voltage balancing capacitors. As
shown in Fig. 1, each module of the MSMI is formed by a
single-phase full-bridge inverter. The number of levels is
unlimited by stacking up the modules.
The output voltage of an MSMI is equal to the
summation of the output voltage of the respective modules
that are connected in series. The number of modules (M),
which is equal to the number of DC sources required,
depends on the number of levels (N) of the MSMI. The
relationship between N and M for an MSMI is described
by (1). For example, for an output voltage consisting of
five levels which include +2VDC, +VDC, 0, _VDC and 2VDC, the number of modules needed is 2.
M=
(N
2
when ma is greater than 0.5. Otherwise, the MSMI will
give a 3-level output. In this case, the modulation scheme
works exactly as the classical unipolar PWM switching
technique by giving the 3-level output +VDC, 0 and -VDC
for the MSMI. Apart from that, the harmonics
performance of the switching technique is very identical to
the multicarrier multilevel PWM technique with POD
scheme.
Fig. 2 illustrates the single-carrier multilevel
modulation strategy. The modulation signals have the
same frequency (fo) and amplitude (Am). The sinusoidal
signals are sampled by a triangular carrier signal with
frequency f, and amplitude A, once in every cycle.
Intersection between the sampled modulation signals and
the carrier signal defines the switching instant of the
PWM pulses. In order to ensure quarter wave symmetric
properties of the PWM output waveform, the starting
point of the modulation signals is phase shifted by one
period of the carrier wave. In addition, the frequency
modulation ratio (mf) must also be an even number [8].
For an N-level inverter, ma and mf for the single-carrier
multilevel modulation strategy are defined as:
(1)
Am
(N -1)
2
fc
mf
,
(2)
(3)
fo
Further details on the single-carrier multilevel PWM
technique can be obtained from [5].
VDC
V(p.u)
.-N~~
b
A4C
A,5
VDC
6. !LI
Module 2
,,,
V
~a
de
Fig. 1 Single-phase 5-level MSMI configuration
t(ms)
III. SINGLE-CARRIER MULTILEVEL PWM TECHNIQUE
Fig. 2 Single-carrier multilevel PWM technique
a - the carrier signal
b - absolute sinusoidal modulation signal
c - sampled sinusoidal modulation signal of b
d - shifted absolute sinusoidal modulation signal
e - sampled sinusoidal modulation signal of d
Basically, this switching technique for the MSMI is
based on the classical unipolar PWM switching strategy.
A significant difference in this switching technique is the
use of a single-carrier and two sampled sinusoidal
modulation signals. The position of the modulation signals
can be controlled by changing the value of the modulation
index (ma). The MSMI will produce a 5-level output only
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IV. HARDWARE IMPLEMENTATION USING FPGA
Fig. 3 shows a basic block diagram on how the
hardware implementation of the single-carrier multilevel
PWM technique for the MSMI is designed. Before
creating the block diagram, tools and materials provided
by the Altera's UP1 board has been recognized. Referring
to Fig. 3 the inputs to the circuit are ma and mf. The
parameter ma is controlled externally by an 8 bits ADC
because of the absent of an analog to digital conversion
function on the UP1 board. The parameter mf is controlled
by a 25.175 MHz on-board oscillator. The generation of
the modulating signals and triangular carrier are
configured in the FLEX1OK FPGA device. Output of the
I/0 pins of the FLEX1OK are the gate signals for each of
the MSMI power devices.
which are the modulating signal generator 1, modulating
signal generator 2, triangular carrier generator and the low
frequency signal generator. The modulating signal
generators are responsible for generating 2 sampled
modulating signals while the triangular carrier generator
will produce a sampled triangular output. Both of the
sampled modulating signals are compared separately with
the sampled triangular carrier.
Comparators are labeled as LPM COMPARE with 16
bits input. Subsequently, output from the comparators are
ex-ORed with the low frequency signal to generate the
gate signals for the power devices of module 1 and
module 2 of the MSMI. Low frequency gate signals are
generated directly from the low frequency generator block
labeled as LOW_FRE.
Basically, an LPM_COUNTER acts as a clock
frequency divider to supply clock signals to other block
sets. The input of this counter is assigned to the on-board
oscillator. In addition, a multiplexer is used to select the
clock input to the triangular carrier generator. The
parameter mf is controlled by selecting different types of
clock to the triangular carrier generator. In this work, the
available mf are limited to 20, 40, 80 and 160 only. This is
mainly due to the clock input of the design that is
provided by the fixed on-board 25.175 MHz oscillator.
Fig. 3 Block diagram of the hardware environment
Fig. 4 illustrates the FPGA circuit design blocks for gate
signals generation based on the single-carrier multilevel
PWM technique. In general, it consists of 4 main blocks
Fig. 4 FPGA circuit design blocks for gate signals generation
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.1
Fig.
5
shows the subsystem of the
MODULATING SIGNAL GENERATOR 2 block set.
It contains 3 function blocks labeled by 7bit,
LPM_ROM and LPM_MULT. Basically, the FPGA is a
digital device, so all the design is based on digital
representation. In this work, the digital representation
scheme is the same as the representation used in an
ADC whereby IV is represented by 85 in decimal value.
Therefore, 1 decimal value represents 11.8mV in the
actual voltage value. In this subsystem, the modulating
signal is sampled by 244 steps per cycle. As stated
before, the modulating signal generated is an absolute
signal whereby the signal repeats after half cycle. As a
result, 122 steps value representation are required.
Offline calculations are made based on (4) to obtain all
the step values. The step values are calculated by
increasing u from 0 to 121.
GENERATOR 2. This modulating signal input is added
to a constant 1. The adder produces a sampled
modulating signal with the same pattern as the signal
from MODULATING SIGNAL GENERATOR 2 but it
is shifted up by magnitude 1. This way, components
being used to generate the modulating signal for module
1 of the MSMI are reduced. It also minimizes the space
used for the design so that it can be fit into the
EPF1OK20 device. The output signal from this block set
will be compared with the triangular carrier to generate
the gate signals for module 1 of the MSMI.
Fig. 7 illustrates the block circuit development of the
TRIANGULAR CARRIER GENERATOR. The basic
idea of the design is similar to the modulating signal
generator. A 7bit counter labeled as tria7bit is used
together with an LPM ROM to generate the triangular
carrier signal. The triangular signal is sampled by 98
steps per cycle. This indicates that the counter should be
able to count up from 0 to 97. Values for every step
sample were calculated offline. All the values calculated
are stored into an MIF file and kept in the LPM ROM.
The frequency of the clock input can be selected using
the switches on the UPI board. The mf value can be
determined by selecting the clock input to the counter.
f(u)=(sin(((180/488)+(360/488) x u) x i/180)) x 85
lorl
inclk
,.j.6
E[
=
!""kie:
i
LRA ROM
0
inct
'I
(4)
AIT.01
A Uo
Fig. 5 Subsystem of the MODULATING_SIGNAL
GENERATOR 2
Fig. 6 Subsystem of the MODULATING_SIGNAL
GENERATOR]
All the step values are then stored into the
LPM_ROM by creating an MIF file. The 7bit counter is
designed to count up from 0 to 121. The counter reads
the sampled modulating signal value which is stored in
the ROM to generate a sampled modulating signal. The
modulating signal output from the LPM ROM block is
transferred to the LPM MULT multiplier. The sampled
modulating signal is multiplied by an amplitude value
from the ADC. As a result, a modulating signal that
represents different ma values can be generated.
Fig. 6 shows the subsystem of the
MODULATING SIGNAL GENERATOR 1. Basically,
it consists of an LPM ADD SUB function block and an
LPM_CONSTANT block. The LPM ADD SUB is set
to operate as a 16 bits adder. This block function is
simple whereby the input of the adder labeled as
u[15..0] is fed from the MODULATING-SIGNAL
mv.
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ihL3
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W. .,W,X,:E. C,
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.............~~~~~~~~~~~~~~~~~~~~~~~~~~.................
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i~~~~~~~tfsA
Fig. 7 Subsystem of TRIANGULAR CARRIER GENERATOR
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measured within the MATLAB/Simulink environment
while for the experimental results, a measurement
function in the digital oscilloscope has been used to
measure every pulse width.
Table 1 shows the comparison among the pulse width
measured for ma
0.4 while Table 2 shows the
comparison for ma 0.8. Referring to Table 1, the
highest percentage differences of pulse width are given
by pulses 1 and 10 which are 3°O and 3.388%
respectively. For the other pulses, the percentage
difference is around 1%. The average percentage
difference is 1.278%. Referring to Table 2, 5 pulses are
generated in half a period for the MSMI module 1. The
average of percentage difference in pulse width is quite
low whereby for module 1 is around 0.92% and for
module 2 is 1.79%. For module 2, 6 pulses are
generated in a half period. The highest percentage
difference is 30.
Overall, the pulse widths percentage difference
between the simulation and experimental results for both
cases described above are still within the acceptable
level with the average of between 0.92% and 1.278%. It
must also be noted that the measurement made within
the MATLAB/Simulink environment is subject to a
maximum of 4 decimal points only. Further work is
required to evaluate the performance of the FPGA based
gate signal generator based on the single-carrier
multilevel PWM technique for the MSMI. Testing the
FPGA based gate signal generator on the actual MSMI
circuit may provide further verification on its feasibility
based on the MSMI output voltage harmonic spectrums
for various ma and mf values.
Fig. 8 shows the developed LOW_FRE block. This
subsystem is responsible to generate the 4 low
frequency gate signals for the MSMI power devices.
These 4 signals always remain as a low frequency signal
without being affected by ma. A 7bit counter and an
LPM ROM are used to fulfill this purpose. The
LPM_ROM will generate logic low output for the first
half cycle of a sinusoidal signal and logic high output
for the second half cycle.
Fig. 8 Subsystem of the LOW FRE
V. RESULTS AND ANALYSIS
Before comparing the experimental results and the
simulation results, the performance of the gate signal
generator should be stated. Normally, the sampling rate,
timer interrupts and switching instant resolution are
taken into account for the performance evaluation. In
this work, the sampling time achieved is 81.96pts. Thus
the switching instant resolution obtained is 1.480.
The gate signals waveforms obtained from the
simulation results using MATLAB/Simulink are
compared with that generated by the EPF1OK20 device.
Comparison are made for the gate signals waveforms
based on variations of parameters ma and mf = 20 and
40 respectively. Fig. 9 shows the gate signals obtained
for the power devices in module 1 of the MSMI for ma=
0.4 and m -20 based on simulation and experimental
results. With ma less than 0.5, all four gate signals for
the power devices in module 2 of the MSMI are at low
frequency and do not contribute to its output voltage.
Fig. 10 shows the gate signals for the power devices in
each of the MSMI module when ma is set at 0.8 while
maintaining the same value of mf. Based on the results
obtained, the gate signals generated by the EPFlOK20
device are found to be in good agreement with that
generated through simulation. The number of pulses in
each of the gate signals are the same for both the
simulation and experimental results.
With mf = 20, comparison is also made by measuring
the pulse width of the gate signals from the simulation
output and the EPFlOK20 device. In this work, pulse
width for the simulation signals are viewed and
....
(a)
Fig. 9 Gate signals for module 1 of the MSMI forMm0.4 and
mf= 20 (a) simulation (b) E.PF1OK2O device
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VI.
CONCLUSIONS
The work presented has shown that the
implementation of the single-carrier multilevel PWM
technique for the MSMI using FPGA is able to produce
proper gate signals for the MSMI power devices with
high computation speed and accuracy on the output
generated. Outputs from the FPGA FLEXlOK20 have
been verified by the results obtained from the
MATLAB/Simulink simulation. A sampling time of
81 ts corresponding to 1.480 resolution for the gate
signals pulse widths has been achieved.
VII.
(a)
Fig.
10 Gat sinl fo moul 1 (uppr an moul 2...
Ma
Puse,
I
=
._mf=2
S m. I I
ar i ti
f2 2-2
3
4
0-5603
~3
0.71,2L3
0-5632
6
0.~~~7834
0.7782
0-5
0.63
0 66
366
0594
052
0.68
8
9
0.71(6
)0-7834
02778
_,0_
21_
02 1228
41
_3_38
Table 2 Comparison on pulse width of gate signals for
ma 0.8, mf = 20
InPHIOUK20device trn 1: 0
Pwlse MkATLAB/Simnulik
00
Width
Pulse
Module 1,
l
2
3
4
5
Module
2
3
4
5
fi
output
I
m
0I2622
~07531
5.9371
U 7532
0-2622
0-1262
A04271
57830
l)
0.5784
0-4269
l) 1:266i
(Ms)
REFERENCES
[1] J. Lai and F. Z. Peng, "Multilevel Converters-A New Breed
of Power Converters." IEEE Transactions on Industry
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[2]Carrara, G., Gardella, S. and Marchesoni, M., "A New
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[3] Azli, N.A. and Yatim, A. H. M., "Optimal Pulsewidth
Modulation (PWM) Online Control of a Modular Structured
Multilevel Inverter (MSMI)", Proceedings of the 4th IEEE
International Conference on Power Electronics and Drive
Systems PEDS'01, 22-25 October 2001, Bali, Indonesia.
W_ v,.,, [4] Schibli, N.P., Nguyen, T. and Rufer, A. C., "A Three Phase
Multilevel Converters for High Power Induction Motors." IEEE
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[5] Naziha Ahmad Azli and Abdul Halim Mohd Yatim,"A
Modular Structured Multilevel Inverter for Fuel Cell
Applications.", Jurnal Teknologi D. 32., 2000.
[6] Naziha Ahmad Azli, Abdul Halim Mohd Yatim and Faridah
Mohd Taha, "Regular Sampled Pulsewidth Modulation (PWM)
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Source Inverter (VSI)", Proceedings of World Engineering
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[7] Naziha Ahmad Azli and Abdul Halim Mohd Yatim, "DSPbased Online Optimal PWM Multilevel Control for Fuel Cells
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Conference of the IEEE Industrial Electronics Society, 29 Nov. 2 Dec. 2001, Denver, USA.
[8] F. Salim and N.A. Azli, "Development of an FPGA Based Gate
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[9] J. A. Aziz and Z. Salam, "A PWM Strategy For The Modular
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[10] N. A. Azli and M. S. Bakar, "A DSP-based Regular Sampled
Pulsewidth Modulation (PWM) Technique for a Multilevel
Inverter", Proceedings of 2004 International Conference on
Power System Technology, Singapore, 21-24 November 2004.
x
Output
tf (ms)
0-2662
0.3475
5.9392
0.7475
0-2662
1-53
0.74
0.04
76
1-53
0.12288269
7,'1
0.41 98
0-5734
1085
0 5734
0-4198
0 1228
0.86
'1.66
3-00
841
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