CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
MULTIPROCESSOR COMPUTATIONAL SYSTEM
A graduate project submitted in partial satisfaction of the
requirements for the degree of Master of Science in
Engineering
by
Harish S. Nachnani
May 1988
The Graduate Project of Harish S. Nachnani is approved:
(Prof/ Yuh Sun)
,j
(Prof.
Chair)
California State University, Northridge
Acknowledgement
I wish to express my sincere appreciation to those who have served
on my graduate committee, especially to my major advisor, Professor
Robert Wong.
To my Mother, Father and Sisters, my other fellow colleagues whose
contribution and help has made this project a success.
iii
TABLE OF CONTENTS
Page No.
ACKNOWLEDGEMENT •••••••.••••••••.••.•.•••••••••••••.•••••.•••• iii
ABSTRACT ..•..••.•••.••••••...•..•..•..•••.••.•••..••••..•••.• vi i i
Chapter
INTRODUCTION .•••.•.•••..••••••.••••••••••••..••...• 1
2
3
HARDWARE DESIGN .•.••..••.•.••.•••••••••.••••••••.•• 2
2. 1
cPU I s ......................................... 2
2.2
Memory • . . • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • . . • • • • 2
2. 3
Common Memory Bank •.••••••••••••.••••••••••••• 4
2. 4
Register F i 1e ••.•••.••••••••••••••••••••••••.• 5
2.5
1/0 Ports ••••••••••••••••••••••••••••••••••••• 6
2. 6
Decoders ••••.••••••••••••••••••••••••••••••••• 7
SOFTWARE DESIGN •••••••••••••.••••••••••.••••••••••• 8
3.1 Power Up Diagnostics ........................... 8
3.1.1
1/0 Port Test ........................... 8
3.1.2
Local Memory Test ••••••••••••••••.•••••• 8
3.1.3
Common Memory Test •••••••.••••••••••••• 18
3.2.0perating Software •.•.••••••••••.•••.••.•..••. 20
3.2.1
Data Input Routine .••••••.•••.••.•....• 20
3.2.2
Task Scheduler •••••••••••••.•••...••••. 21
3.2.3
Task Execution Routine ••••••••••••..•.• 22
3.2.4
Matrix Addition Subroutine •••••..••.••• 23
3.2.5
Matrix Subtraction Subroutine .••••••.•. 25
3.2.6
Matrix Transpose Subroutine ••.••••.•••• 27
3.2.7
Output Display Routine •••••••••.••••••• 29
iv
4
SYSTEM OPERATIONS .••••••••••••••••.•••••••••••••• 30
5
CONCLUSION •••••••••••••••••••••.•••••••••••.••••• 34
References ........................•...........•.....•...••...... 37
APPENDIX
A
SYSTEM SCHEMATICS ••..•••••••••••••••..••...•.•••• 38
B
PROGRAM LISTINGS ••.••.••••••••••••••••••••••••••• 51
v
LIST OF TABLES
Table No.
2.1
Page No.
Memory and 1/0 Mapping ..•..••.••.•..••...•....•.•..• 3
L1 ST OF FIGURES
Page No.
Figure No.
3. 1
Main Program Flow Chart ......•..................... 9
3. 1a
Power Up Diagnostics Block for CPU 1 ..........•... 10
3. 1b
Power Up Diagnostics Block for CPU 2/CPU 3 ........ 11
3. 1c
Real Time Mode Block for CPU 1 .................... 12
3.1 d
Task Scheduler Block .............................. 13
3. 1e
Real Time Mode Block for CPU 2/CPU 3 .............. 14
3. 1f
Task Execution Block ..............•............... 15
3.2
1/0 Port Test Flow Chart .......................... 16
3.3
Local Memory Test Flow Chart ..••............•...•. 17
3.4
Common Memory Test Flow Chart ..................... 19
3.5
Matrix Addition Subroutine Flow Chart .......•.••.. 24
3.6
Matrix Subtraction Subroutine Flow Chart .•...•.... 26
3.7
Matrix Transpose Subroutine Flow Chart .••........• 28
vii
ABSTRACT
MULTIPROCESSOR COMPUTATIONAL SYSTEM
by
Harish S. Nachnani
Master of Science in Engineering
This project demonstrates the use of more than one processor in a
system to speed up data processing and data computations. Matrix
addition , subtraction and transpose are used to demonstrate the use
of several processors operating in parallel to speed up the computations. This report covers hardware and software design of the system.
The system has a special feature of power up diagnostics to verify
the hardware is functioning properly. This eliminates any errors in the
results due to hardware mal-function.
The system was designed and constructed. Software was written.
Test results indicate that the system performed properly as designed.
viii
,,
CHAPTER 1
INTRODUCTION
It is often necessary to process data at a faster rate to increase
the effective computing speed. This is done by allowing several
processors to execute at the same time. The simplest method to acheive
this is to operate two or more CPU's sharing a common memory. The
system consists of three 8-bit (8085A) microprocessors which share a
common memory in addition to a local memory of their own. The microprocessors are driven by an operating system stored in the Eproms.
The system also has a register file in the memory which is used as
interface buffer between CPU's.
The system goes through a power up diagnostics test to make sure
the basic hardware components such as memory, 1/0 ports, register file
are functional. CPU 1 acts as the controlling CPU and performs the
task of reading input data, displaying results and assigning tasks to
CPU 2 and CPU 3.
This report describes the hardware components of the system,
the diagnostics and operating software and the procedure
to operate
the system. The system block di·agram and schematics depict the
hardware design in detail.
'
CHAPTER 2
The multiprocessor computational system is a 8-bit
multiprocessor system. The major components of the system are CPU•s
(8085A), Local ram, Common ram, Register file, Address/Data bus
controller, 1/0 ports and Decoder logic.
2.1 CPU's:
The multiprocessor computational system consists of three
8-bit microprocessors. Each CPU is driven by a 6 Mhz clock and the
operating software stored in the Eproms. Each CPU has a local ram
which is used for stack operations and saving input data and results.
A push button switch is provided to reset all three CPU's.
CPU 1 is the cant ro 11 i ng CPU. It performs the functions of
reading the input data, interfacing with CPU 2 and CPU 3 and assigning
tasks to CPU 2 and CPU 3. It also displays the results of the
Computations performed by CPU 2 and CPU 3. CPU
copies the input
data from its local ram to common ram. CPU 2 and CPU 3 perform the
task of reading the input data from the common ram, perform
matrix
addition, subtraction and transpose, notifying their status to CPU 1
and copying results from their local rams to common ram.
2.2 Memory:
The system memory consists of two sections: the local ram and
Eproms. Three 2716 Eproms are used
in the system. Each CPU is assigned
one Eprom. The 2716 Eproms are 2K X 8 bit ultra violet erasable and
electrically programmable read only memory components. The diagnostics
2
USAGE
ADDRESS
Eprom
OOOOh - 07FFh
Local Ram
F800h - FFFFh
Common Ram
4000h - 47FFh
Control Port
EFh
Input Port (only for CPU 1)
F7h
Display Port 1
FDh
Display Port 2 (only for
FEh
CPU 1)
Taple .2.1 Memory and 1/0 Mapping
3
I
I
and the operating software are stored in the Eproms. Location OOOOh
is the beginning address of the diagnostic program. On issuing a
hard reset to the CPU's the processor starts executing code from
location OOOOh. Each CPU latches AO-A7 address bits using a 74LS374
latch. The output of the latch is connected to the address pins A1
through AS of the Eprom. The remaining address 1 ines A9 through A11
are connected directly from the CPU to the Eprom as these lines are
not used in a multiplexed mode by the 8085A CPU's. The data bus pins
of the Eproms are connected directly to ADO-AD7 pins of the CPU.
The chip select signal for the Eprom is generated by the decoder
logic. The Eproms are loaded with the micro code using Eprom programmer
card plugged into a personal computer.
Each CPU has a 6116 (2K X 8 Bits) static ram. The rams are used
for stack operation, saving input data and other program variables.
The address pins of the ram are connected to the output of the
address latch. The remaining three address 1 ines A8 through A10 are
connected directly from the CPU to the static ram. The data pins
D0-07 are connected directly to ADO-AD7 pins of the CPU. The chip
select signal is generated by the decoder logic. Table 2.1 depicts
the memory mapping for the CPU's
2.3 Common Memory Bank:
The common memory bank consists of a 6116 (2K X 8 bits) static
ram. The common memory bank can be accessed by any one of the three
CPU's via the common address bus (ACBUS) and common data bus (DCBUS).
A hardware and software control is implemented to make sure no two
4
CPU 1 s access the common ram at the same time. The hardware control
is a combinational logic of exclusive OR and AND gates. The software
control uses register file space to exchange semiphore values between
CPU 1 s. Bi-directional tri-state buffers (74LS245) I.C. •s are used as
data latches while tri-state (74LS374) latches are used as address
latches. Each CPU has its own address latch. The output of the address
latch is connected to the common ram. The address latches are clocked by ALE signal generated by the CPU 1 s. The address latches and data
latches are selected by the same chip select signal used for selecting the common ram chip by the CPU, thus making sure that the address
and data bits of the CPU attempting to select the common ram are used
as address and data values by the common ram. The type of operation
to the common ram determines the data transfer direction for the
data latch. The read/write signal from the CPU determines the direction
of data transfer for the data latch. The address map for the common
ram is the same for all three CPU 1 s. For example the variable MAXRL
is located at address 8000h for all the CPU 1 s enabling all the CPU 1 s
to share the same data.
2.4 Register File:
The register file is used as inter-CPU buffer. The register file
space consists of eight 74LS670 I.C.•s. The 74LS670 1 s are used in set
of two to form 8 bit data. The 74LS670 1 s have a seperate set of read
and write data 1 ines thus enabling the CPU 1 s to read and write the same
location at the same time. Four 74LS670 1 s are used by CPU 1 to read
the data written by CPU 2 and CPU 3. Thus the read lines are connected
5
to the data bus of CPU 1. The write 1 ines of the first two 74LS670 1 s
are connected to CPU 2 while the write lines of the next two 74LS670 1 s
are connected to CPU 3. Thus CPU 1 can access the locations for read
operation without interfering the write operations performed by CPU 2
and CPU 3 to the same location. The read 1 ines of the next set of
74LS670 1 s are connected to CPU 2 while the write 1 ines are connected
to CPU 1. Thus CPU 2 is able to read the data written by CPU 1 without
interfering the write operations performed by CPU 1 to the same
location. The read 1 ines of the last set of 74LS670's is connected to
CPU 3 while the write lines are connected to CPU 1. Thus CPU 3 can read
the data written by CPU
without interfering the write operation
performed by CPU 1. CPU
uses the first four address 1 ines AO through
A3 to address the eight register file locations. Locations 8000h-8003h
are assigned to CPU 2. Locations 8004h-8007h are assigned to CPU 3.
The same address lines along with R/W signal are decoded to generate
the chip select signal for the 74LS670's. CPU 2 can access four register
file locations 8000h-8003h while CPU 3 can access the remaining four
register file locations 8004h-8007h. The register file locations are
used to exchange values of semiphores between CPU's. The main purpose
of having the register file space is to avoid bus contention for
accessing common ram.
2.5 1/0 Ports:
Each CPU has its own set of 1/0 ports. CPU 1 has four 1/0 ports.
The two output ports are connected to seven segment hex displays thus
forming a four digit decimal display. One of the input ports is connect-
6
ed to push button switches PSW2, PSW3 and PSW4 used by program control
while the other input port is connected to eight single pole double
throw switches. Each switch represents one bit of input data. CPU 2
and CPU 3 have one input port and one output port. The output port is
connected to seven segment displays thus forming a two digit decimal
display. The input port is connected to push button switch PSW2 which
is used by program control.
2.6 Decoders:
The decoder logic consists of AND, OR and inverter gates. Each CPU
has its own decoder logic. The decoder provides chip select signals for
Eprom, local ram, common ram, 1/0 ports and register file space by
decoding CPU signals such as RD, WR, 10/M and address 1 ines. Each CPU
has its address latch to latch the address as the 8085A processor
places the address and data value on same 1 ines. 74LS374 I.C. •s are
used as address latches. The decoder logic also provides WR signal for
the local ram. The common ram chip select and WR signals are multiplexed to make sure only the chip select and the WR signal of the CPU
attempting to access the common ram goes through to the common ram.
7
{.1
CHAPTER 3
SOFT\vARE DESIGN
The Software package consists of two major modules, the diagnostics
software and the operating software. Figure 3.1 through 3.1f depict
the Main program flow chart and give an overall picture of the software
design for the system.
3.1 Power Up Diagnostics:
The power up diagnostics module is executed at power up time and
whenever a reset is issued to the system. The diagnostics module
consists of the following tests: 1/0 port test, Local memory test,
Common memory test.
3.1.1 1/0 Port Test:
Figure 3.2 shows the 1/0 port test flow chart. This test is carried
out to verify if the hex displays can display all decimal digits. The
test outputs a decimal digit pattern of 0 through 9 for the least
significant digit" The test is repeated for the most significant digit.
In case of CPU 1 the display consists of 4-digits. The test is repeated for all four digits.
3.1.2 Local Memory Test:
This test verifies the proper read/write operations to local ram
which is used by stack operations, to save input data and local variables. The start address of the local memory is loaded in register pair
HL. The byte counter and ERRFLG are initialized to zero. Figure 3.3
8
'
I'
\.
t
START
)
...,,;- CPU 2
CPU 1
In it i a 1 i ze
Environment
In it i a 1 i ze
Environment
...,,
1 CPU 3
In It i a 1 i ze
Environment
'v
Power Up
Diagnostics
Block
Power Up
Diagnostics
Block
-..r
Power Up
Diagnostics
Block
I
1..0
.....
.....
,,
r
r
I"
Rea 1 Time
Mode
Block
Rea 1 Time
Mode
Block
--
--·-
--
---
-
Figure 3.1 Main Program Flow Chart
r
"'"
Rea 1 Time
Mode
Block
Power Up
Diagnostics for
CPU 1
Signal CPU 2 to
perform common
ram test
Initialize flags
CF2 = CF3 = 0
1/0 Port Test
NO
done ?
Local Ram Test
NO
Signal CPU 3 to
perform common
ram test
Did
System
Pass local
Common Ram
Test
NO
Display 88h
indicating completed
diagnostics
End of
Diagnostics
Figure 3. 1a Power Up Diagnostics Block for CPU 1
10
Power Up
Diagnostics for
CPU 2 and CPU 3
Common Ram Test
Initialize Flags
1/0 Port Test
NO
Loca 1 Ram Test
S i g na 1 CPU 1 ,
completed common
ram test.
NO
Display 88h
Indicating completed
diagnostics.
NO
commtest
End of Diagnostics
Figure 3. 1b Power Up Diagnostics Block for CPU 2/CPU 3
11
(
Real Time Mode
Block for CPU 1
'
7
-.I/
, II
In it i a 1 i ze F1ags
CF2 = CF3 = 0
TSKCNT = 0
Is
CPU 2
done
NO
?
YES
,I,
.... /
Read in maximum value
of number of elements
in a row /column of
input matrices.
Signal CPU 3 to
read input data.
NO
Is
CPU 3
done
?
Read input data
YES
and copy it to
common ram.
Task Scheduler
Block.
Display input data
read.
Read in next set
of data.
I
Signal CPU 2 to
read input data.
Figure 3.1c Real Time Mode Block for CPU 1.
12
Task Scheduler
Block
TSKCNT
=
Is
NO
NO
NO
CPU 2
ideal ?
CPU 3
idea 1 ?
Has
CPU 3
comp 1eted a .
task
?
Has
CPU 2
completed a
task ?
Assign common address
and data bus to CPU 3
to copy results of
previous task to common ram.
NO
Assign common address
and data bus to CPU 2
for CPU 2 to copy
results of the previous task to common
ram.
Assign task to
CPU 3.
Assign task to
CPU 2.
End of task
Scheduler block
Figure 3.1d Task Scheduler
13
Real Time Mode
Block for CPU 2/CPU 3
(
NO
Is
CPU 1
signa 11 i ng to
read input
data ?
YES
Copy input data from
common ram to local
ram.
Display data,
Signal CPU 1,
completed reading input
data.
Enter Ideal Mode
Task Execution
Block
Figure 3.1e Real Time Mode Block for CPU 2/CPU 3
14
Task
Execution Block
NO
"------~
Check if
task is assignged ?
Decide which task
to performed
?
Perform
Task
Signal CPU 1,
Task Completed.
NO
Copy results from
local ram to common
ram.
Enter Ideal Mode
Figure 3.1f Task Execution Block
f.S
Start of
Diagnostics
Counter
~
0
Counter
AC C .:E-
f
Output -E- ACC
Counter =
Counter + 10
Increment
Counter
Increment
Counter
NO
IS
Counter< 91
Counter
ACC
+
~
00
Counter
Output -E- ACC
Figure 3.2 1/0 Port Test Flow Chart
16
( HL)
+-
STARTADR
COUNTER~
0
ERRFLG
0
+
WRITE <:( ( HL)) ~
DATA
0
ERRFLG ~ 1
(HL)
+
(HL) + 1
Increment
Counter
IS
NO
COUNTER
=
ERRFLG
=
Max ?
NO
YES
Figure 3.3 Local Memory Test Flow Chart
17
depicts the local ram test flow chart. The test data pattern used in
this test is the value of the lower 8 bits of the address. Each time
a location is written the counter is incremented by one until the
maximum 1 imit is reached. The data is read back immediately after
writing to the location. If the data read back does not match the lower
eight bits of the address then the ERRFLG is set to one. At the end of
the memory test the value of the ERRFLG is checked. If the ERRFLG is
set to one that indicates a read/write memory error has occurred thus
the local ram test is executed again. This process continues until the
memory test completes without any errors.
3.1 .3 Common Memory Test:
This test verifies
the proper read/write operations of the common
memory bank which is used to store input data and computational results.
The start address of the common memory bank is loaded in the register
pair HL. The byte counter and ERRFLG are initialized to zero, Figure
3.4 depicts the common memory test flow chart. The test data pattern
used in this test is the value of the lower eight bits of the address.
Each time a location is written the counter is incremented by one until
the maximum 1 imit is reached. The data is read back immediately after
writing to the location. If the data read back does not match the
lower eight bits of the address then the ERRFLG is set to one. At the
end of the memory test
the value of the ERRFLG is checked.· If the
ERRFLG is set to one that indicates a read/write memory error has;
occurred thus the common ram test is executed again. This process
continues until the memory test completes without any errors.
18
(HL) ~
STARTADR
0
ERRFLG ..(:- 0
COUNTER~
\VRITE DATA
( ( HL))
(HL) '(-
+-
0
(HL)
+
Increment
Counter
Is
ERRFLG =1
END OF
DIAGNOSTICS
Figure 3.4 Common Memory Test Flow Chart
19
3.2 Operating System:
Once the system executes the power up diagnostics without any errors.
it goes into a real time mode. At this stage all CPU's are ready for
executing tasks assigned by CPU 1. CPU 1 reads in the input data and
copies it to the common ram. CPU t then signals CPU 2 to read in the
input data. After CPU 3 completes reading the input data CPU 1 assigns
the matrix computation tasks to CPU 2 and CPU 3.
3.2. 1 Data Input Routine:
The data input routine performs the task of reading in the input data
from the input port and saving jt in the local ram. At completion of th
this task CPU 1 then copies the input data to the common ram. The input data routine resides in CPU
Eprom. At completion of the power up
diagnostics all CPU's display 88h on their display ports indicating
that the user can enter the input data now. The input routine enters a
loop in which it constantly is reading in the value of the control port
r'
to check which PSW switch was depressed.\Jsing switches DSWO through
OSW7 the input data is entered. Push button PSW2 is depressed after
-,,
every switch set up indicating CPU 1 to read in the data.\ CPU 1 displa..._...:>
ys the data read to enable the user to verify the entry made. The user
has an option of changing the data by depressing push button switch
PSW3. On depressing PSW3 switch the input routine decrements the input
_d~tamemory
store address and the input data counter , then displays
the pervious data entry. The user at this point can enter the desired
data by setting up switches DSWO through DSW7 and depressing switch
PSWl
The program remains in the input data routine until all the data
20
(l
. has been entered. The number of data enteries is decided by the first
value entered. The first value entered represents the number of elements in a row. All the matrix computation routines assume the number
of rows in the input matrix is equal to the number of columns in the
input matrix. Thus when the total number of enteries equals the total
number of elements for the two intput matrices and one entry to
specify the maximum number of elements in a row, the program exits the
input routine. The input data counter is decremented by one after every
data entry and when the input data counter equals zero the task scheduler routine is executed.
3.2.2 Task Scheduler:
The task scheduler routine is a part of the.:CPU 1 operating software.
Figure 3.1d shows the task scheduler routine flow chart.; This routine
resides in CPU 1 ,Eprem. The task scheduler assigns task to CPU 2 and
CPU 3 depending on which one is in a ideal mode. The task assignment
semiphores, TSKf.PU2 for CPU 2 and TSKCPU 3 for CPU 3 are set to 10h
by CPU 2 and CPU 3
respectiv~ly
in a ideal mode. These semiphores are
stored in the register file space. The local variable TSKCNT is the
task counter used by the operating software of CPU 1 and is stored in
the local ram of CPU 1. The variable TSKCNT is set to the maximum
number of tasks to be carried out for a given set of input data. Test
is carried out to verify the value of the TSKCNT variable before
assigning a task to a CPU. If the TSKCNT variable does not equals one
the task scheduler continues assigning tasks. In this system the tasks
to be performed on the given set of input data are pre-determined and
21
'
are assigned a number. The number assignment for different tasks is as
follows: 1 for addition operation, 2 for subtraction operation, 3 for
transpose operation on matrix A and 4 for transpose operation on matrix B. Test is carried out by CPU 1 to check if CPU 2 is in ideal mode.
If CPU 2 is in ideal mode, CPU 1 further verifies the value of semiphore CF2 to find out if the previous task assigned to CPU 2 is completed. If the previous task is completed CPU 1 assigns the common address and data bus to CPU 2 for it to go ahead and copy the results of
the previous task from its local ram to the common memory bank. If
no previous task was assigned to CPU 2, then the value of the semiphore CF2 is zero. Once CPU 2 completes copying the results to the
common memory bank a new task is assigned to it by CPU 1. CPU 1 then
checks to see if CPU 3 is in ideal mode. If CPU 3 is in ideal mode,
CPU 1 further verifies if the previous task assigned to CPU 3 is completed by reading the
value~of
semiphore CF3. If CF3 is set to zero then
it is assumed that no task was assigned to CPU 3. If CF3 equals 73h
then CPU 1 assigns the common address and common data bus to CPU 3 for
it to copy the results of the previous task from its local ram to the
common memory bank. This cycle of assigning tasks to CPU 2 and CPU 3
continues until the TSKCNT variable equals to one. The task scheduler
flags for CPU 3 and CPU 2 thus making sure no CPU is running in a ideal
mode while the tasks are queued. CPU 1 remains in the task scheduler
routine until all the tasks are completed.
3.2.3 Task Execution Routine:
The task execution routine performs the function of executing the
22
,, .
the tasks assigned by CPU 1 and updating status. This routine resides
in the Eproms of CPU 2 and CPU 3. Values of task assignment semiphores
are read continously by CPU 2 and CPU 3 to verify if a task is assigned
to them by CPU 1. CPU 1 sets the task assignment semiphore of the corresponding CPU to 1 for addition operation, 2 for subtraction operation,
3 for matrix A transpose and 4 for matrix 8 transpose operation. The
task exectuion routine performs the assigned task by calling the subroutine and signals CPU
of completion of the task. Once the task is
completed the CPU is in a wait mode awaiting access to the common address and common data bus for the common memory bank to copy the results
from the local ram to the common memory bank. At completion of copying
the results the task execution routine sets the task assignment flag
to 10h signaling CPU 1 that the CPU is in a ideal mode.
3.2.4 Matrix Addition Subroutine:
This subroutine performs the task of adding the two input matrices
A and B. The subroutine resides in the Eprom of CPU 2 and CPU 3. Figure
3.5 depicts the matrix addition subroutine flow chart. The subroutine
is called by the main program if CPU 1 sets the task assignment semiphore for the corresponding CPU to 1. The subroutine adds the corresponding elements of the two input matrices and saves the resultant
elements in the local ram. This process continues until the operation
of addition for all the elements of the input matrices is completed.
On completion of the computation task the subroutine transfers control
back to the main program.
23
)
( ADDROT
~II
Compute beginning address
of Matrix A in local ram.
HL ..(- A address.
~
Compute beginning address
of Matrix B in local ram.
HL <:- B address.
1
~
Counter ~
elements.
Increment HL.
Increment DE.
Increment BC.
Maximum number of
-f
it
HL -E- Local Ram
address of results
DE ""-- Common ram
address for results.
Copy results to
common ram.
Add corresponding matrix
elements:
--v
Save result in local ram.
( BC) +- Result.
{-
"'
Decrement Counter
Is
Counter
Signal CPU 1 '
task completed.
NO
,lt
=0
(
?
RET
YES
Figure 3.5 Matrix Addition Subroutine Flow Chart
24
('
A +
ij
-=
B
AR
ij
ij
In the above equation A and B are the two input matrices and AR is the
resultant matrix.
3.2.5 Matrix Subtraction Subroutine:
This subroutine performs the task of subtraction of the two input
matrices A and B. The subroutine resides in the Eproms of CPU 2 and
CPU 3. Figure 3.6 depicts matrix subtraction subroutine flow chart.
The subroutine is called by the main program if CPU 1 sets the task
assignment semiphore for the corresponding CPU to 2. The subroutine
subtracts the corresponding elements of the two input matrices. The
sign flag is checked after every subtraction operation and the value
is saved in the local ram along with the results of the computations.
The results are stored in the local ram as shown below:
SR
11
Sign
SR
12
Sign
SR
13
SR
21
Sign
SR
nn
Sign
where SR
·represents the first element of the resultant matrix,
11
Slgn represents the sign of the first element, SR
represents the .
12
25
(
)
SUBROT
~
~
Save sign value
( BC) + Sign.
Compute beginning address
of Matrix A in local ram.
HL + A address
-Jt
=
1
'-
7'
Compute beginning address
of Matrix B in local ram.
DE ~ B address
II
Save sign va 1ue
( BC)
+ Sign.
~
,if
Counter ~- Maximum number
of elements.
Is
Counter
0
L.-
,v'
=0
=
?
0
NO
Subtract corresponding
ma t r i x e 1em en t s .
Increment HL.
Increment DE.
Increment BC.
'"
Save result in local ram.
Result.
( BC) +
A
f
Decrement Counter.
Increment BC.
HL of- Loca 1 Ram
address of results.
DE ~ Common ram
address of results.
Copy result to
common ram.
',,
Is
Sign= 1
~
1
YES
Signal CPU 1 '
task completed.
?
0
-
(
~
RET
Figure 3.6 Matrix Subtraction Subroutine Flow Chart
26
YES
second element of the resultant matrix and so on.
A
= SR
- B
I
J
ij
I
J
In the above equation A and B are the two input matrices and SR is the
resultant matrix. On completion of the computation the control is transfered back to the main program.
3.2.6 Matrix Transpose Subroutine:
This subroutine performs the operation
of~computing
the transpose
for a given input matrix. The subroutine resides in the Eproms of CPU 2
and CPU 3. This subroutine is called if the task assignment semiphore
is set to 3 or 4 by CPU 1. Task 3 performs transpose of input matrix
A while task 4 performs transpose of input matrix B. At the end of this
operation the elements of the
resultant matrix are stored in the local
ram. The transpose of the matrix is performed by exchanging the elements
of the row with the elements of the column. The memory location for
each element is computed and the contents of the location are swapped
with the contents of the memory location of the corresponding column
element. The process i 5 repeated unt i 1 all the rows and columns are
swapped. On comp Ie t ion o f t h is task the control is transferred back to
the main program. Elements of the resultant matrix are as fellows:
A A A
... A
11 12 13
1n
A A A
... A
11 21 31
nl
A A A
... A
21 22 23
2n
A A A
... A
12 22 32
n2
A=
AT =
A A A
... A
31 32 33
3n
A A A
... A
13 23 33
n3
A A A
... A
41 42 43
4n
.A
14
27
A A
... A
24 34
n4
l
TXROT
,It
Compute beginning
of matrix in the
1oca 1 ram.
HL ~ Matrix Address
Counter~ Maximum number
of elements in the
matrix.
First element remains
same. Save result.
(DE) <(- Result.
HL + Local Ram address
of the results.
DE ~ Common ram address
for the results.
Copy results to common
ram.
S i g na 1 CPU 1 ,
task completed.
Increment DE.
Decrement Counter.
Compute address of
next element in the
column. Save result.
(DE) - Result.
Increment DE.
Decrement Counter.
Is
Counter = 0
(
RET
)
>-Y~E~s~--~
?
0
Figure 3.7 Matrix Transpose Subroutine Flow Chart
28
Matrix A is the input matrix while matrix AT represents the transpose
of matrix A.
3.2.7 Output Display Routine:
The output display routine is a part of the main program for CPU 1.
The output display routine displays the results of the matrix computations. CPU 1 has a display consisting of four digits. The most significant digit represents the sign of the value being displayed. If the sign
of the value displayed is negative the most significant digit is 1 else
if the sign of the value displayed. is positive then the most significant
digit is 0. The output display routine displays the results of the
addition operation, then subtraction, transpose A and finally transpose
B. The row elements of the resultant matrix are displayed first from
left to right. The second row elements are displayed next and so en.
The output display routine is also called if PSW4 switch is depressed.
29
".
CHAPTER 4
SYSTEM OPERATIONS
The computational system goes through a power up diagnostics when
power in turned on or on issuing a reset. CPU 1 acts as the controlling·
CPU. The power up diagnostics consists of three tests: the 1/0 port,
local ram test and common ram test. When the power switch is turned ON
or if the reset push button PSW1 is depressed all three CPU's go
through power up diagnostics. The first test executed is the 1/0 port
test then comes the local memory test and finally the common memory
test. The common memory test is performed in a sequential order. CPU
executes the common ram test first. During this period
CPU 2 and CPU 3
are polling to read in CF2 and CF3 variable values from the register
file space. CF2 and CF3 are the semiphores stored in the register file
space. After completing the common ram test CPU 1 sets CF2 flag to 51h
signalling CPU 2 to go ahead and execute the common ram test. During
this time period CPU
is in a polling mode awaiting CPU 2 to complete
the common ram test. CPU 1 constantly reads the value of CF2 semiphore
to check if its set to 61h. At completion of the common ram
te~t
CPU 2
sets CF2 semiphore to 61h signal! ing CPU 1 that the common ram test is
completed and the common address bus (ACBUS) and the common data bus
(DCBUS) are available. CPU 1 at this point sets CF3 semiphore to 71h
signal! ing CPU 3 to execute the common ram test. At completion of the
common ram test CPU 3 sets CF3 semiphore to 81h. This procedure is
adopted to avoid bus contention. If an error occurs in any of the above
test cases the system will not enter the real time operating mode. It
will loop to the test case which detected an error until the test pass-
30
es without errors. Once the power up diagnostics are executed error
free a value of 88h is displayed on the display port of each CPU. At
this point the system is ready for computational purposes. The input
data is entered at this point via CPU 1. The first data entry is the
value of the maximum number of rows the input matrices A and B have.
The program makes the following assumption:
Number of rows
=
Number of columns
=
Data entered.
Switches DSWO through DSW7 are used to set up the input data value.
Push button switch PSW2 is depressed after each set up signal! ing CPU
to read the data. The backspace feature can be acheived by using switch
PSW3. Depending on the maximum number of rows in the input matrices
CPU 1 initializes the computational enviornment. All the input data
is copied from the local ram of CPU 1 to the common memory bank. After
completing the task of copying input data to the common memory bank
CPU 1 signals CPU 2 to copy the input data from the memory bank to its
local memory by setting CF2 semiphore to 52h. During this time period
CPU 1 is in a ·polling mode awaiting CPU 2 to complete the task of
copying the input data. Upon completion of copying the input data CPU 2
sets CF2 semiphore to 62h. CPU 1 then signals CPU 3 to copy the input
data from the common memory bank to its local memory by setting CF3
semiphore to 72h. CPU 1 is in polling mode awaiting CPU 3 to complete
the task of copying input data. Upon completing the task of copying
input data CPU 3 sets CF3 semiphore to 82h. CPU 2 and CPU 3 upon
completion of the task of copying input data set TSKCPU2 and TSKCPU3
semiphores to 10h indicating to CPU 1 that they are in ideal mode.
TSKCPU2 and TSKCPU3 are semiphores stored in the register file space.
31
TSKCPU2 is the task assignment semiphore for CPU 2 while TSKCPU3 is the
task assignment semiphore for CPU 3. CPU 1 assigns task first to CPU 2
then to CPU 3 and enters a loop until all the tasks are completed. Each
time a task is assigned CPU 1 decrements its task counter. CPU 1 is
constantly polling to semiphores TSKCPU2 and TSKCPU3 to find which CPU
is done with the previous task. Upon completion of all the tasks CPU 1
displays the results and is awaiting next set of input data. The user
has an option of viewing the results again by depressing push button
PSW4.
The following is a set of steps to operate the system:
1. Power on the sytem by flipping switch MSW to ON position.
2. Issue a reset to the system by depressing push button switch PSW1.
3. Enter the run mode by depressing push button switch PSW2.
4.
~/ait
until all the CPU's enter the real time mode i.e. wait until
all the CPU's display 88h on the display. During this period of
time all the CPU's are executing the power up diagnostics.
5. Set Switches DSWO through DSW7 to the maximum number of rows in
the input matrices. Depress switch PSW2. The user has an option of
re-entering the data by depressing switch PSW3.
6. Enter elements of the input matrix A first. The order of entry is
as follows: A
, A , A
represents
13
14
the first row . Then enter the second row elements and so on.
11
, A
12
, A
13
A
A
• A
14
11
12
]. Enter elements of input matrix B in the same order as that of
matrix A.
8. Wait for the results to be displayed. All results will be displayed
on the display port of ·CPU 1: .The order of display for the result-
32
ant matrix elements is as follows: R , R , R , R
11
12
21
... and
22
so on. The results of the different operations are displayed in
the following order:Addition, Subtraction, Matrix A transpose
and Matrix B transpose.
33
CHAPTER 5
CONCLUSION
The multiprocessor computational system demonstrates the use of
several processors to acheive higher computation and data processing
speed. The system is designed using TTL (LS) series integrated circuits
to minimize logic gate delays and improve overall system performance.
With modifications to the software the system could be used for
computation of complex matrice problems, data sorting, parsing, image
processing and robotic applications. The operating software could be
enhanced by implementing a DBUG and real time monitor.
The chip count for the multiprocessor computational system is
approximately 100. Bi-coupl ing capacitors are provided for integrated
circuits to minimLze noise with a current drive of approximately 2.5
amperes.
Following sets of input data were tested to evaluate the system
performance:
1.
Matrix
A
- Input
=
3
7
12
27
B=
8
6
14
21
Results - Output
Addition:
AR
=
Subtraction:
11
13
26
48
BR •
Transpose A
AT=
f
-5
-2
6
Transpose B
3
12
BT ='
34
8
14
I
Transpose B (continued)
Transpose A (continued)
2.
Matrix
I
27
7
21
6
- Input
12
3
5
7
8
14
5
3
tJ
A=
2
B=
,..
15
9
4
6
7
2
3
Results - Output
Subtraction:
Addition:
AR =
14
12
9
10
-6
8
14
21
6
2
20
5
9
-10
.,
3
Transpose B:
Transpose A:
AT =
7
12
7
:;J
3
8
3
5
14
6
2
r
BT =
15
9
6
2
4
7
3
3. r\atrix - Input
A=
12
4
21
7
5
7
2
44
20
9
13
7
2
;J
r-
25
4
B=
35
10
8
23
4
3
17
5
3
'+
3
4
5
4:
I
Results - Output
Subtraction:
Addition:
22
12
L~4
11
9
10
3
49
37
14
16
11
3
9
28
5
AR=
2
-4
- 2
4
BR=
3
-4
3
39
10
3
22
3
Transpose B:
Transpose A:
10
4
1i.'
8
3
5
4
3
3
12
5
20
2
4
7
9
5
21
2
13
25
23
7
44
7
4
4
BT=
AT=
5
4
The test results indicate that the system performed according
to the hardware and software design specifications.
36
".
References
1.
8080/8085 Assembly Language programming Manual,
Intel Corporation, 1981
2.
MCS-80/85 Family User's Manual, Intel Corporation
October, 1979
3.
Memory Components Handbook, Intel Corporation
t984
4.
Structured Computer Organization,
AndrewS. Tanenbaum,
Second Edition
31
APPENDIX
A
SYSTEM SCHEMATICS
38
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Figure A-12 Decoder/Reset Circuitry
R.c-3
_T_
83-36
APPENDIX
B
PROGRAM LISTINGS
51
LASI'I3 11/01/84 Page 001
1
;fitiiilittttitiittttttttiiiillttitttlt.ttttt.titlttttitittltiitltlll
2
3
;It
;It
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
;It
u
MULTIPROCESSOR COMPUTATIONAL SYSTEM
CPU 1 MICROCODE
;It
t.l
if
t.l
;ltttttttttttttttitttttttttttttttttttttitttttttittttittttttltttttt/
i I/0 PORT DEFINITIONS
OOFD
OOFE
OOEF
OOF7
=
=
=
=
oport
opor t 1
cport
iport
equ
equ
equ
equ
; output port
; output port 1
; control port
; input port
Ofdh
Ofeh
Oefh
Of7h
; REGISTER FILE SEMIPHORE DEFINITIONS
8000
8001
8004
8005
=
=
=
=
CF2
TSKCPU2
CF3
TSKCPU3
equ
equ
equ
equ
;
;
;
;
08000h
08001h
08004h
08005h
CPU1-CPU2 Handshake Flag
Task Assignment flag for CPU 2
CPU1-CPU3 handshake flag
Task Assignment Flag for CPU 3
; COMI'ION RAM DEFINITIONS
4000
4001
4020
4030
4050
4060
=
=
=
=
=
=
MAXRC
IPUTC
ARC
SRC
ATC
BTC
equ
equ
equ
equ
equ
equ
04000h
04001h
0402011
04030h
04050h
04060h
;
;
;
;
;
; l'laximum number of rows
Beginning of Matrix A elements
Matrix addition results
Matrix Subtraction results
Matrix ATranspose results
Matrix B Transpose results
;
;
;
;
;
;
;
Maximum number of rows
Beginnning of matrix element input
Matrix addtion results
Matrix Subtraction results
Matrix ATranspose results
Matrix B Transpose results
Task Table
; LOCAL RAM DEFINITIONS
F800
F800
F801
FB20
F830
F850
FB60
F870
F871
=
=
=
=
=
=
=
=
=
LRAI'I
MAXRL
IPUTL
ARL
SRL
ATL
BTL
TASK!
TASK2
equ
equ
equ
equ
equ
equ
equ
equ
equ
Of800h
Of800h
OfB01h
Of820h
(lf830h
OfB50h
Of860h
OfB70h
OfB71h
52
45
46
47
48
49
50
51
52
53
54
55
56
F872
F873
F874
F875
F876
=
=
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
Of872h
Of873h
Of874h
Of875h
OfB76h
; Task countH
; Sav~ maximum no. or rows
; Error flag
;*iittttttttttttttttttttttttttttt
t
MAIN PROGRAI'I
;
;tttttttttttttttttttttttttttttttt
org
0000
LASI'I3 11/01/84
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
TASK3 ~qu
TASK4 ~qu
TSKCNT ~qu
SVI'IAX ~qu
ERRFLG equ
=
=
=
OOOOh
002
Pag~
;
Initializ~ th~
lxi
0000 31FFFF
stack
sp, Offffh
; I/0 Initialization
mvi
out
0003 3EOO
0005 D3FD
;
a,O
oport
Cl~ar
output port
;tttttttttttttttttttttttttttttt
POWER UP DIAGNOSTICS
:t
;tttttttttttttttttttttttttttttttt
i
0007
0009
OOOB
OOOE
OOii
0013
0014
0015
0016
0019
0018
001C
001D
DBEF
FE01
C20700
210080
3EOO
77
23
77
210480
3EOO
77
23
77
STRT
in
o:pi
RSTRT
lxi
jnz
MVl
mov
inx
mov
lxi
mvi
mov
cport
lh
STRT
h,CF2
a,O
m,a
ch~ck valu~
of Control port
; jump to b~ginning
; Clear s~miphores for CPU2
h
m,a
h,CF3
a,O
m,a
inx
h
mov
m,a
;
Cl~ar
semiphores ior CPU 3
;tttttttttttttttttttttttttttttttt
I/0 PORT TESTS
t
;tttttttttttttttttttttttttttttttt
;
87
88
89
001E 1EOO
0020 1C
cont
mvi
inr
; Cl ~ar counter
e,O
e
53
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
lOB
109
110
111
112
0021
0022
0024
0027
0028
002A
002D
002F
0031
0033
0034
0035
0037
003A
0038
003C
003E
78
D3FD
CD3E02
78
FE09
C22000
OE09
1EOO
3E10
83
5F
D3FD
CD3E02
OD
79
FEOO
C23100
cont1
mov
out
call
mov
cpi
jnz
fllVi
mvi
mvi
add
fllOV
out
call
dcr
a,e
oport
Output pathrn
d~lay
a,~
Compare if reached last decimal value
9h
CONT
c,9
; Clear counter
; Initialize ace for H58 digit display
; add valuf! of counter
~,o
a,lOh
~
e,a
oport
delay
li!OV
a,c
cpi
jnz
0
; Output data pattern
Compare ii reached last decimal value
CONTl
;*******************************
; LOCAL HEI10RY TESTS
*
;*******************************
0041 2100FB
1xi
h,LRAM
Load start address
mov
mov
mov
cmp
jnz
a,l
m,a
Write memory location
inx
h
mov
cpi
jnz
jmp
mvi
out
call
mvi
out
call
lxi
xchg
mvi
xchg
jmp
a, l
OFFh
MCNT
HCNTl
a1 99h
oport
delay
LASI'I3 11/01/84 Page 003
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
0044
0045
0046
0047
0048
0048
004C
0040
004F
0052
0055
0057
0059
005C
005E
0060
0063
0066
0067
0069
006A
7D
77
7D
BE
C25500
23
7D
FEFF
C24400
C36DOO
3E99
D3FD
CD3E02
3EOO
D3FD
CD3E02
1176FB
EB
3601
EB
C34400
11CNT
HERR
a, I
Compare the written value
Set the flag if error occurred
Continue
fll
MERR
; Compare if reached maximum limit
; Continue if not
; Display that memory error has occurred
a,O
oport
delay
d,ERRFL6
m,l
MCNT
54
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
0060
0070
0071
0073
2176F8
7E
FE01
CA4400
MCNTl
h,ERRFLG
a,m
lh
MCNT
lxi
mov
cpi
jz
;*iiittttttittiiiitiiiitiiiiitii
t
COMMON RAM TESTS
i
;tiiittiiiiiiiiiiiiiiiiiiiiiiiii
0076
0077
007A
007C
007F
0081
0082
0085
0087
0088
0088
008C
008D
008E
008F
0092
0093
00'34
0096
0099
009C
009E
OOAO
OOA3
OOA5
OOA7
00
2176F8
3600
210080
3EOO
77
210480
3EOO
77
210040
7D
77
7D
BE
C29COO
23
7D
FE30
C28BOO
C3B400
3E98
D3FD
CD3E02
3EOO
D3FD
CD3E02
nop
1xi
mvi
1xi
mvi
mov
lxi
mvi
mov
lxi
; Clear Error Flag
m,a
a,l
m
CERR
h
a,l
30h
CCNT
CCNTl
a,98h
oport
delay
a,O
oport
delay
; Write data pattern
IIIOV
IIIOV
cmp
jnz
inx
mov
cpi
jnz
.jmp
mvi
out
call
mvi
out
call
OOAA
OOAD
OOAE
0080
0081
0084
0087
0088
OOBA
1176F8
EB
3601
EB
C38BOO
2176F8
7E
FE01
CA8BOO
CCNTl
; Load start address of common ram
; Compare data pattern
; Jump if does not match
; Go to next memory location
;
;
;
;
LA5113 11/01/84 Page 004
169
170
171
172
173
174
175
176
177
178
179
; Clear semiphores again
a,l
CCN mov
CERR
h,ERRFLG
ro,O
h,CF2
a,O
ru,a
h,CF3
a,O
rn,a
h,MAXRC
lxi
xchg
mvi
xchg
jmp
I xi
mov
cpi
jz
d,ERRFLG
m,1
CCNT
h,ERRFLG
a,m
1
CCNT
Signal CPU2 to test commom ram
55
Compare if reached •aximum limit
If no continue testing
Else exit form this test case
Display if error occurred
{l
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
19&
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
; Load semiphore address
; Load value
h,CF2
a,51h
m,a
Wait for aknowledgement
OOC3
OOC6
OOC7
OOC9
210080
7E
FE61
C2C600
c~Jait
lxi
lllOV
cpi
jnz
h,CF2
a,m
61h
C'Jai t
Signal cpu3 to test comllion ram
oocc
lxi
ravi
fllOV
210480
oocr 3E71
OOD1 77
Load Semiphore value
h,CF3
a,71h
rt,a
Load value
Wait for cpu3 aknowledgement
OOD2
OODS
OOD6
OOD8
210480
7E
FEB1
C2DSOO
1xi
c~Jatl
h,CF3
a,a
cpi
81h
jnz
cwat1
I!IOV
Display 88h indicating the user that the system passed power up test
OODB 3EB8
OODD D3FD
OODF CD3E02
SAGN
mvi
out
call
a,88h
oport
delay
Display value
;titt.t.tt.tt.tttt.ttttttttt.t.t.tt.t.itit
END OF DIAGNOSTICS
:t:
;
;tiiiiiiiiiiitiiiiiiiiiiiiiiitii
213
214
215
216
217
218
219
220
221
222
223
224
lxi
II!Vi
IOV
OOBD 210080
OOCO 3E51
OOC2 77
OOE2
OOE5
OOE7
OOEA
OOEC
OOEE
OOFl
OOF3
OOF6
2100F8
3609
2100F8
DBEF
FE01
CA0601
FE02
CA2501
FE04
READ INPUT DATA
h,MAXRL
lxi
mvi
m,9h
lxi
h,I1AXRL
cport
in
ready
cpi
1h
jz
rdata
cpi
2h
jz
bkup
cpi
4h
; Initialiu max no. or rows
; Load start address
Check status of control port
Data ready
; Call backspace routine
LASH3 11/01/84 Page 005
225
OOFB CACE01
jz
Display results again
DDATA
56
•
226 OOFB 2100F8
227 OOFE 7E
228 OOFF BO
229 0100 C2EAOO
230 0103 CA3101
231 0106 70
232 0107 FE01
233 0109 CA1501
234 010C OBF7
235 010E 77
236 010F 03FO
237 0111 23
238 0112 C3EAOO
239 0115 7E
240 0116 2175F8
241 0119 77
242 011A 47
243 0118 80
244 011C 3C
245 0110 2100FB
246 120 77
247 0121 23
248 0122 C30C01
249 0125 28
250 0126 2B
251 0127 C3EAOO
252
253
254
255 012A 110040
256 0120 2100F8
257 0130 5E
258 0131 7E
259 0132 EB
260 0133 77
261 0134 EB
262 0135 70
263 0136 BB
264 0137 C23001
265 013A C34101
266 0130 23
267 013E C33101
268 0141 00
269
270
271
272 0142 210080
273 0145 3E52
274 0147 77
h,IIAXRL
a,m
mov
cmp
ready
jnz
CIOVp
jz
a,l
rdata mov
1h
cpi
CIIAX
jz
iport
nexti in
mov
m,a
oport
out
h
inx
ready
jmp
a,m
mov
CMAX
h,SVIIAX
lxi
ro,a
mov
b,a
mov
b
add
a
inr
h,IIAXRL
lxi
mov
m,a
h
inx
nexti
jmp
h
bkup
dcx
h
dcx
ready
jmp
lxi
Save maximum no of
ro~s
value
load maximum input read operation value
Copy input data from local memory to common memory bank
1xi
lxi
cmovp
cmov
cmovn
mov
mov
xchg
mov
xchg
IIIOV
crap
jnz
jmp
inx
jmp
nop
; Load common ram address
; Load local ram address
d,MAXRC
h,I1AXRL
e,M
-:i,l
m,a
a, 1
e
Check if maximum limit reached
craov
cmovn
h
cmovp
; Signal CPU2 to read the input data
PROC
1xi
mvi
mov
h1 CF2
a,52h
m,a
; Load semiphore address
; Load value
57
275
276
277
278
27'3
280
Wait for acknowledgement from CPU2
0148 210080
0148 7E
014C FE62
wat2
I xi
lllOV
cpi
a,m
jnz
\Jat2
Load semiphore address
h,CF2
Compare value
62h
LASM3 11/01/84 Page 006
281
282
283
284
285
286
287
288
28'3
2'30
291
2'32
293
294
296
297
298
2'39
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
014E C24B01
Signal cpu3 to read the input data
l xi
avi
mov
0151 210480
0154 3E72
0156 77
h,CF3
a1 72h
m,a
; Load semiphore address
; Load value
Wait for acknowledgement from cpu3
0157
015A
0158
0150
210480
7E
FE82
C25A01
wat3
lxi
mov
cpi
jnz
Load semiphore address
h,CF3
a,m
82h
wat3
Compare value
;Initialize Task table
0160
0163
0165
0166
0167
0168
016A
0160
0170
0172
2170F8
3E01
77
23
3C
FE04
C26501
2174F8
3E05
77
lxi
mvi
It able mov
inx
inr
cpi
jnz
I xi
IIIVi
IIIOV
h, TASK!
a, 1
m,a
h
; Load address
; Load value
a
Check if reached maximum value
4h
It able
h,TSKCNT
a, 5h
m,a
Initialize task counter
Assign task to CPU 2 and CPU 3
Check if task counter is less then 5
0173
0176
0179
017A
017C
017F
0182
0183
1170F8
2174F8
7E
FE04
CAA601
210180
7E
FE10
1xi
fstcpu lxi
rliOV
cpi
jz
lxi
!liOV
cpi
d,TASKl
h,TSKCNT
a,m
4h
; Check if all task done
DONE
h, TSKCPU2
; Load address of semiphore
a,m
; Check if CPU 2 is ideal
!Oh
58
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
0185
0188
0189
018A
0188
018C
018D
0190
0191
01'34
0195
0197
019A
0198
019C
0190
C29101
EB
7E
23
EB
77
2174F8
35
210580
7E
FE10
C27601
EB
7E
23
EB
jnz
xchg
mov
inx
xchg
fllOV
l xi
dcr
nxtcpu lxi
mov
cpi
jnz
xchg
mov
inx
xchg
nxtcpu
a,m
h
a, a
h, TSKCNT
Oecr~m~nt
m
h,TSKCPU3
a,m
10h
fstcpu
task counter
Check if CPU 3 is ideal
a,m
h
LAS"3 11101/84 Page 007
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
019E
019F
01A2
01A3
mov
lxi
dcr
jmp
77
2174F8
35
C37601
m,a
h, TSKCNT
Decr~m~nt
Ill
task counter
fstcpu
;Copy results form common ram to local ram
01A6
01A9
01AA
01AD
0180
0183
0186
0189
01BC
018F
01C2
01C5
01C8
01CB
2175F8
5E
1120F8
212040
CD3202
1130F8
213040
CD3202
1150F8
215040
CD3202
1160F8
216040
CD3202
DONE
lxi
h,SV"AX
IIIOV
e,m
hi
l xi
call
!xi
d,ARL
h,ARC
copy
d,SRL
h,SRC
copy
d,ATL
h,ATC
copy
d,BTL
h,BTC
,,;
• A.
call
l xi
l xi
call
l xi
lxi
call
;Load
;Load
;load
;LOad
address of SVMAX variable
counter
address for add results local ram
address for add results comm ram
; Load addr~ss for sub results local ram
; Load address for sub results comm ram
;Load address for Atran results local ram
;Load address for A tran results comm ram
;Load address for B tran results local ram
;Load address for B tran results comm ram
C•)PY
;tiiiiiiiiitiiiiiiiiiiiiiiiiiiii
i
; DISPLAY DATA
;iiiiiiitiiiiiiiiiiiiiiiiiiiiiii
OlCE 2175F8
01D1 5E
0102 2120F8
DDATA
!xi
mov
lxi
h,SVMAX
e,•
Load ram address addition results
h,ARL
59
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
01D5
01D6
01D8
01D9
OlDA
OlDC
01DD
OlEO
OlEl
01E3
01E6
01E9
OlEA
01ED
01EE
01FO
01F1
01F3
01F4
01F7
01F8
01FA
QIFD
0200
0201
0204
0205
7E
D3FD
23
7E
D3FE
23
CD3E02
lD
3E04
C2D501
2175F8
5E
2130F8
7E
D3FD
23
D3FE
23
CD3E02
1D
3E04
C2ED01
2175F8
5E
2150F8
7E
D3FD
ad spy
sdspy
mov
out
inx
mov
out
inx
call
dcr
mvi
jnz
lxi
mov
lxi
lilOV
out
inx
t)
tadsp
inx
call
dcr
IIIVi
jnz
lxi
mov
lxi
mov
out
a,m
oport
; Display value
h
a,m
oport 1
Display sign
h
delay
e
a,4
ad spy
h,SVI'IAX
e,m
h,SRL
Check if maximum limit is reached
If not continue
; Load ram address for sub results
a,m
oport
h
oport 1
; Display value
Display sign
h
delay
e
a,4
sdspy
h,SVI1AX
e1 m
h,ATL
a,m
•)port
Check if maximum limit reached
If not continue
Load ram address tran A results
Display value
LASI13 11/01/84 Page 008
393
394
3'35
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
0207
0208
0209
020B
020C
020F
0210
0212
0213
0216
0219
021A
021D
021E
0220
0221
0222
0224
0225
23
7E
D3FE
23
CD3E02
lD
3E04
8B
C20402
2175F8
5E
2160F8
7E
D3FD
23
7E
D3FE
23
CD3E02
inx
mov
out
inx
call
dcr
mvi
cmp
jnz
lxi
IDOV
tbdsp
lxi
mov
out
inx
fliOV
out
inx
call
h
a,m
oportl
Display sign
h
delay
e
a,4
Check if maximum value reached
e
tadsp
h,SVMAX
e,m
h,BTL
a,m
oport
; Load ram address tran B value
Display value
h
a,m
oport1
h
delay
60
Display sign
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
41!4
436
437
438
439
440
441
442
443
444
445
446
447
448
0228
0229
0228
022C
022F
dcr
fi!Vi
cmp
jnz
jmp
1D
3E04
BB
C20402
C30BOO
~
a1 4
e
tadsp
SA6N
; All done read to read next set of input data
;ttttittttiittittitiiiitttttttt
i
; COPY SUBROUTINE
;iiittttttttttttttttttttttitttt
0232
0233
0234
0235
0236
0237
0238
0239
023A
0230
7E
EB
77
23
EB
23
7D
BB
C23202
C9
IDOV
a,m
xchg
m,a
mov
inx
h
xchg
h
inx
mov
a, I
; Check if maximum limit reached
e
cmp
copy
jnz
ret
;tttttttttiiittittttttttiitttttt
; DELAY SUBROUTINE
;ttitttttttttttttttttttttttttttt
copy
*
023E
023F
0240
0241
0243
0245
0246
0249
E5
C5
05
06FF
16FO
15
C24502
05
delay
lp2
lp1
push
push
push
mvi
mvi
dcr
jnz
dcr
h
b
d
; Save registers
b,Offh
d,OfOh
; Load counter
; Load counter
d
lpl
b
LASH3 11/01/84 Page 009
449
450
451
452
453
454
024A
0240
024E
024F
0250
0251
C24302
01
Cl
El
C9
.jnz
pop
pop
pop
ret
end
lp2
d
; Load registers back
b
h
;End of Program
61
"\CPU22.PRN
LASM3 11/01/84
Pag~
001
;fiiiiitiiiiiiiiiiiiiiiiiiiiiiiiiiitiif.iiiiititiitiiiiiiiiiiiiiil
ll
;H
2
3
4
5
; It MULTI PROCESSOR COMPUTATIONAL SYSTEM
;It
r
tl
if
CPU 2 MICROCODE
if
D
;It
I
;ltitttiiiilliiiitlilliiiiiliiiiiiiiiiiiititiittlttitttiititiiitl
..,
8
9
10
11
12
13
14
15
16
17
18
; I/0 PORT DEFINITIONS
OODF =
007F =
cport
oport
~qu
equ
; Control Port
; Output Port
Odfh
07fh
; REGISTER FILE SEMIPHORE DEFINTIONS
8000 =
8001 =
CF2
t'QU
TSKCPU2 equ
CPU2 - CPU 1 Handshak~ flag
Task Assignment Flag
08000h
08001h
; COMMON RAM DEFINITIONS
19
20
21
22
23
24
25
26
27
4000
4001
4020
4030
4050
4060
=
=
=
=
=
=
41
42
43
44
45
equ
~qu
equ
equ
equ
equ
;
;
;
;
;
;
04000h
04001h
04020h
04030h
04050h
04060h
Maximum
of rows
of Matrix A ~l~aents
addition r~sults
subtraction results
ATranspos~ results
B Transpose r~sults
numb~r
B~ginning
Matrix
Matrix
Matrix
Matrix
; LOCAL RAM DEFINITIONS
28
29
30
31
32
33
34
35
36
37
38
39
40
i'IAXRC
IPUTC
ARC
SRC
ATC
BTC
F800
FBOO
F801
FB20
F830
F850
F860
F875
F876
F877
=
=
=
=
=
=
=
=
=
=
LRAM
MAXRL
IPUTL
ARL
SRL
ATL
BTL
SVIIAX
ERRFLG
COUNTR
equ
equ
equ
equ
equ
equ
equ
equ
~qu
equ
OfBOOh
OfBOOh
OfBOlh
Of820h
Of830h
Of850h
Of860h
Of875h
Of876h
Of877h
;
;
;
;
;
;
;
;
;tttttttttttttttiitttttitt.ttitii
MAIN PROGRAM
;tttitt.ttttttttttttititttttiitti
;
*
62
Beginning of matrix el~m~nt input
Beginning of matrix element inputs
Matrix addition results
Matrix subtraction results
Matrix ATranspose results
Matrix B Transpose results
Save maximum no. of rows
Error Flag
General purpos~ counter
46
47
48
4'3
50
51
52
org
0000
OOOOh
;Initialize stack pointer
lxi
mvi
out
0000 31FFFF
0003 3EOO
0005 D37F
; Load stack pointer
; Clear display
sp,Offffh
a,o
oport
53
;ttttttttttttttititiitiiiiittttt
t
POWER UP DIAGNOSTICS
;ttttttttttiitttttttitittitttttt
54
55
56
i
LASI13 11/01/84 Page 002
57
58
5'3
60
fi1
62
63
fi4
65
66
67
68
!i9
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
0007
000'3
OOOB
OOOE
0011
0013
DBDF
FEOl
C20700
210080
3EOO
77
STRT
in
cpi
jnz
lxi
mvi
mov
Check status of control port
cport
lh
STRT
h,CF2
a,O
m,a
Clear semiphore value
;tttitittttttttitittttttttttt
i
l/0 PORT TEST
*
;tttttttttttittttiitittttttttttt
0014
0016
0017
0018
001A
lEOO
1C
7B
D37F
CD7A02
cont
call
0010 7B
001E
0020
0023
0025
0027
0029
002A
0028
002D
0030
0031
0032
0034
FE09
C21600
1600
lEOO
3E10
82
57
D37F
CD7A02
lC
78
FE09
C22700
mvi
inr
mov
out
contl
mov
cpi
jnz
mvi
mvi
mvi
add
lllOV
out
call
inr
mov
cpi
jnz
Clear counter
e,O
~
a,e
oport
delay
a, e.
3h
CONT
d,O
e,O
a,10h
d
d,a
oport
delay
Output pattern
Compare if reached last decimal value
; Clear Counter
; Initialize Ace for MSB digit display
; Add value of counter
; Display data pattern
e
a,e
9h
contl
;tttttttttttitttit.ittiitiitttttt
63
Check if maixmum limit reached
,, .
g2
93
94
95
LASI'I3 11/01/84
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
t
;tt.t.t.t.t.t.t.t.t.t.tt.t.t.t.t.t.tttt.ttt.ttt.tt.t.
0037 2100F8
% 003A 70
97 003B 77
98 003C 70
99 0030 BE
100 003E C24BOO
101 0041 23
102 0042 70
103 0043 FEFF
104 0045 C23AOO
105 0048 C36300
106 004B 3E99
107 0040 037F
08 004F CD7A02
109 0052 3EOO
110 0054 037F
111 0056 CD7A02
112 0059 1176F8
113
114
115
116
117
118
119
120
121
LOCAL MEMORY TESTS
i
005C
0050
005F
0060
0063
0066
0067
0069
006C
006F
0070
0072
!xi
MCONT
mov
mov
cmp
jnz
inx
IIIOV
cpi
jnz
jmp
ravi
out
MERR
call
addr~ss
; Compar~ cont~nts of m~mory
; Jump to ~rror routin~ if not o.k.
; Els~ t~st n~xt location
h
a,l
Offh
MCONT
I'ICNT1
a1 99h
oport
;
Ch~ck
if maximum limit
display 99h
~rror
reach~d
occurred
d~lay
mvi
out
call
1xi
a,O
oport
d~lay
d,ERRFLG
s~t
Errorflg
003
Pag~
EB
3601
EB
C33AOO
2176F8
7E
FE01
CA3AOO
210080
7E
FE51
C26FOO
lfiOV
load Start
h,LRAI'I
a,l
m,a
a,l
m
MERR
MCNT1
xchg
mvi
xchg
jmp
1xi
BlOV
wait
cpi
jz
lxi
mov
cpi
jnz
m,1
MCONT
h,ERRFLG
a, a
1
MCONT
h,CF2
a,m
51h
wait
; Check if error flag is set to 1
; Is error flag s~t to 1
; Th~n r~p~at th~ t~st
Load Semiphor~ address
Wait to ex~cut~ common ram test
;t.t.tt.t.t.t.t.t.t.t.t.t.t.tt.tt.t.t.t.t.t.t.t.tt.t.t.t.t.
;
COMI'ION RAM TEST
t
;t.t.t.t.tt.tt.t.t.t.t.t.t.t.t.t.t.t.t.t.ttt.t.t.ttt.tt.
0075
0076
0078
007B
007E
0080
0083
0084
7E
D37F
CD7A02
2176F8
3600
210040
75
7D
ffiOV
CCONT
out
call
1xi
mvi
!xi
mov
mov
a,m
oport
Display
Semiphor~
Value
d~lay
h,ERRFLG
m,O
h,I'IAXRC
m,l
a,l
64
; Cl~ar error flag
; Load comm ram beginning address
138
139
140
141
142
143
144
145
146
147
148
149
150
0085 BE
0086 C29300
0089 23
OOSA 7D
0089 FE30
OOSD C28300
0090 C3ABOO
0093 3E98
0095 D37F
0097 CD7A02
009A 3EOO
009C D37F
009E CD7A02
151 OOA! 2176FS
152 OOA4 EB
153 OOA5 3601
154 OOA7 EB
1 OOAS C38900
__,')56 OOAB 2176F8
157 OOAE 7E
158 OOAF FEOl
159 OOBl CA8300
160
161
162
163 0094 210080
164 0097 3E61
165 OOB9 77
166
167 OOBA 3EB8
168 OOBC D37F
cmp
jnz
inx
mov
cpi
jnz
jmp
mvi
out
call
mvi
out
call
NXT
CERR
h
a, I
30h
CCONT
NXTl
a,9Sh
oport
delay
a,O
oport
delay
lxi
xchg
mvi
xchg
jmp
NXT1
Compare memory contents
If not same jump to error routine
ill
CERR
Check if maximum value reached
Display error occurred
h,ERRFLG
; Set error flag
m, 1
NXT
lxi
h,ERRFLG
IIIOV
a11
cpi
1
CCONT
jz
Check if error flag set
;SIGNAL CPU! that the test was completed
LOOP
hi
mvi
mov
h,CF2
a1 6lh
m,a
mvi
out
a,88h
oport
call
delay
; Load semiphore address
; Load value
Display diagnostics done
LAS"3 11/01/84 Page 004
169
170
171
OOBE CD7A02
;t.t.itit.iiit.t.tt.t.tiit.tt.t.it.t.t.t.t.it.tt.
END OF DIAGNOSTICS
i
; :t.UU:it.Ut.t.Ut.t.t.iiUUt.UUit.U
172
173
174
175
176
177
178
i
Waiting to read input data
OOC! 210080
OOC4 7E
1
.
lXl
'Jat2
mov
h,CF2
a,m
65
Load Semiphore address
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
52h
~Jat2
; Compar!! val uf!
; Try again
Start copying data to local mf!mory
OOCA
OOCD
OOCE
0001
OOD4
0005
OOD6
OOD7
OODB
OOD9
OODA
OODC
210040
5E
210040
0100FB
7E
02
23
03
1D
7B
FEOO
C2D400
CONT2
lxi
mov
l xi
l xi
mov
stax
inx
inx
dcr
mov
cpi
jnz
h,MAXRC
~,Ill
h1 11AXRC
B,LRAM
a,m
b
h
b
~
;
D~crf!mf!nt
Countf!r
a,~
0
; Comparf! if all
don~
CONT2
Signal CPU 1 all done with copying data
OODF 210080
OOE4 77
l xi
mov
h,CF200
OOE2 3E62
mvi
ri 1 a
Display data read
OOE5
OOEB
OOE9
OOEC
OOED
OOEF
OOF2
OOF4
OOF6
OOF9
OOFA
OOFB
OOFC
OOFE
0101
0!04
2100FB
5E
2100F8
7E
D37F
CD7A02
3EOO
D37F
CD7A02
23
1D
7B
FEOO
C2ECOO
210180
3610
.....
CONT4
1xi
mov
lxi
mov
out
call
mvi
out
call
inx
dcr
mov
cpi
jnz
1xi
mvi
h1 11AXRL
~,.
fl,LRAM
Load local ram address
a,fll
oport
delay
a,O
Output data
oport
delay
h
~
a,~
0
Chf!ck if all done
CONT4
h,TSKCPU2
m, 10h
CPU 2 in id!!al mode
;Start Computation
')'l'l
223
224
cpi
jnz
OOC5 FE52
OOC7 C2C400
0106 00
WTSK
nop
LASI13 11101184 Page 005
66
a,62h
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
0107
010A
0108
0100
0110
0112
0115
0118
0118
011C
011E
0121
0124
0127
0128
012A
0120
0130
0133
0134
0136
0139
013C
210180
7E
FE10
CA0601
FE01
C21801
CD3F01
210180
7E
FE02
C22401
CD9D01
210180
7E
FE03
C23001
CDFA01
210180
7E
FE04
C20601
CD3802
C3BAOO
lxi
proc
mov
cpi
jz
cpi
jnz
call
!xi
procl
cpi
jnz
call
1xi
IIIOV
lilOV
proc2
cpi
jnz
call
!xi
mov
cpi
jnz
call
jmp
h,TSKCPU2
a,m
10h
WTSK
; Load
s~miphor~ addr~ss
Wait for task
lh
proc
ADDROT
h,TSKCPU2
a,m
2h
proc1
SUBROT
h, TSKCPU2
a,m
3h
proc2
TAROT
h,TSKCPU2
a,a
Call matrix addition
subroutin~
Call subtraction subroutine
Call Transpose ix A subroutine
4h
WTSK
TBROT
LOOP
Call Transpose Matrix B subroutine
;iiiiiiiiiiiiiiiiiiiiiit.iit.it.t.t.t.
ADDITION SUBROUTINE t.
i MATRIX
;t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.t.
013F
0140
0141
0142
0145
0146
0149
014A
0140
0150
0151
0152
0153
0154
0155
0156
0157
0158
E5
C5
05
2175F8
7E
2177F8
77
0120FB
2101FB
SE
23
70
83
SF
54
EB
7E
EB
ADDROT push
push
push
lxi
mov
1xi
mov
1xi
lxi
ruov
inx
mov
add
mov
mov
xchg
CADD
mov
xchg
Save registers
h
b
d
h,SVMAX
a,m
h,COUNTR
m,a
b,ARL
h,IPUTL
e,m
h
a,!
Initalize counter
Load beginning of input
; Compute beginning of Matrix A
; Compute beginning of matrix B
e
e,a
d,h
CDE> = Address of Matrix B
CHL) = Address of Matrix A
a,m
CHL) = Address of Matrix A
67
273
274
275
275
277
278
279
280
0159
015A
015B
015E
0151
0162
0154
0165
85
02
FA5101
F25801
03
3E01
02
C36C01
LASI'I3 11/01/84
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
0168
0169
0168
015C
0160
0170
0171
0172
0173
0174
0175
0176
0177
Pag~
03
3EOO
02
E5
2177F8
35
7E
E1
23
13
03
88
C25701
nsign
add
stax
jm
jp
inx
mvi
stax
jmp
fJl
b
nsign
psign
b
a,1
b
.:hkm
006
psign
chkm
inx
mvi
stax
push
l xi
dcr
b
!OOV
a,•
pop
inx
inx
inx
cmp
jnz
a,O
b
h
h,COUNTR
Ill
h
h
d
Increment all pointers
b
0
CADD
Ch~ck
if all done
Compl~ted addition operation
Copy results in common ram
017A
0170
017E
017F
0180
0181
0184
0187
0188
0189
018A
0188
018C
2100F8
7E
7B
83
5F
2120F8
112040
7E
12
13
23
10
C28701
Ccopy
lxi
mov
mov
add
mov
lxi
lxi
mov
stax
inx
inx
dcr
jnz
h,I'IAXRL
a,m
a,~
~
e,a
h,ARL
d,ARC
a,m
d
Initailize
Initailize
Sav~
result in common ram
d
h
e
Ccopy
; Check if all done
Signal CPU 1 all done
018F
0192
0194
0197
210080
3653
210180
3610
lxi
mvi
1xi
mvi
h,CF2
m,53h
h,TSKCPU2
m, !Oh
68
to max count
pointers
r~gist~r ~
m~mory
; CPU 2 is ideal
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
0199
019A
019B
Ol9C
D1
C1
El
C9
pop
pop
pop
ret
d
b.
II
Back to main program
;tt.t.t.t.tt.t.tttttt.t.tttt.tttttttttt.tt.tt.tt
; MATRIX SUBTRACTION SUBROUTINE
;t.ttt.tt.tt.t.tttttttttttttttttttttttt.t.t.
*
019D
019E
019F
01AO
01A3
01A4
01A7
01A8
E5
CS
D5
2175F8
7E
2177F8
77
0130F8
SU8ROT push
push
push
lxi
mov
1xi
mov
lxi
h
b
d
h,SVMAX
a,m
h,COUNTR
m,a
b,SRL
Sav~ r~gisters
Initailize Counter
Set pointer to local ram address
LASM3 11101184 Page 007
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
01A8
O!AE
OlAF
0180
0181
01B2
0183
0184
0185
0186
0197
OlBB
0189
O!BC
01BF
01CO
01C2
01C3
01C6
01C7
01C9
01CA
01C8
O!CE
01CF
0100
2101F8
SE
23
7D
83
5F
54
E8
7E
EB
96
02
FA8F01
F2C601
03
3E01
02
C3CA01
03
3EOO
02
ES
2177F8
35
7E
El
mov
inx
IIOV
add
IIIOV
mov
xchg
CSU8
mov
xchg
sub
stax
jm
jp
snsign inx
Ill Vi
stax
jmp
spsign inx
mvi
stax
s•:hkm push
h,IPUTL
e,m
Set pointer to
b~ginning
of input
h
a, 1
e
e,a
d,h
(DE) = address of Matrix B
(HU = address of Matix A
a,m
m
b
Perform subtraction operation
snsign
spsign
b
a, 1
Check Sign
b
schkm
b
Save sign
a,O
b
h
lxi
h,COUNTR
dcr
lllOV
pop
iii
a,m
h
69
Check if all
don~
'
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
0101
0102
0103
0104
0105
inx
inx
inx
crop
jnz
23
03
13
BB
C2B501
h
b
d
0
CSUB
; Compeleted subtraction operation
; Copy results to common ram
0108
0108
OlOC
0100
O!DE
010F
01E2
01E5
01E6
01E7
01E8
01E9
2100F8
7E
78
83
SF
2130F8
113040
7E
12
23
1D
C2E501
fliOV
h1 11AXRL
a,a
a,e
add
£'
fiiOY
e,a
h,SRL
d,SRC
a,m
; Set counter i.e register e
; Point local ram
; Point to common ram
d
h
; Move data to common ram
; Incr~nt address pointer
; Check if all done
lxi
fliOY
1xi
lxi
Scopy
mov
stax
inx
dcr
jnz
e
Scopy
; Signal CPU 1 all done
01EC
01EF
01Fl
01F4
O!F6
210080
3653
210180
3610
Dl
lxi
mvi
lxi
mvi
pop
h,CF2
m,53h
h,TSKCPU2
m, 10h
pop
b
h
; Set CF2 semiphore
Set Task Assignment flag
load all regiters
d
LASI13 11101/84 Page 008
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
01F7 C1
O!F8 E1
01F9 C9
pop
return to main routne
ret
;~tiiiiiiiiittitttititttttiiiiiiti
;MATRIX A TRANSPOSE SUBROUTINE t
;tiiiiiittiiiiiiitiittttttiititttt
O!FA
OIFB
OIFC
O!FD
0200
0201
E5
C5
D5
2175F8
5E
7E
TAROT
push
push
push
1xi
mov
mov
; Save registers
h
b
d
h,SVI1AX
e,1
a,m
70
.
il
408
40'3
410
411
412
413
414
415
416
417
418
41'3
420
421
422
423
424
425
426
427
428
42'3
430
431
432
433
434
435
436
437
438
43'3
0202 56
0203 83
0204 Sf
0205 0150f8
0208 2101F'B
020B 23
020C 7E
0200 10
020E 02
020f 03
0210 82
0211 6f
0212 7E
0213 02
0214 1D
05 C20f02
2175F'B
5E
7B
83
2150F'B
115040
7E
12
1D
C22402
d,m
e
fl!OV
e,a
b,ATL
h,IPUTL
h
a,m
lxi
lxi
inx
ll!OV
TCNT
Initailize Counter
Initalize Point~r to local ram
Initalize pointer to beginning of input
move matrix element to ace
dcr
stax
inx
add
b
Store matrix element
b
d
Compute address on next element
I!IOV
l, a
e
a,m
mov
stax
b
~
dcr
jnz
TCNT
Copy
0218
0218
021C
0210
021E
0221
0224
0225
0226
0227
mov
add
r~sult
1xi
fl!OV
IIIOV
add
lxi
lxi
Tacopy mov
stax
dcr
jnz
Check if all
don~
form local ram to common ram - Matrix A
h,SVMAX
e,a
a,e
e
h,ATL
d,ATC
a, a
Initialize local ram point~r
common ram pointer
Initializ~
d
Check if all done
e
Tacopy
Signal CPU 1 all done
440
441
442
443
444
445
446
447
448
022A
0220
022f
0232
0234
0235
0236
0237
210080
3653
210180
3610
Dl
C1
E1
C'3
lxi
mvi
lxi
mvi
pop
pop
pop
ret
Set Cf2 semiphore
h,Cf2
m,53h
h,TSKCPU2
m, !Oh
d
Set Task Assignment flag
load all regiters
b
h
return to main routine
LASH3 11101184 Page 009
44'3
450
451
452
;itttitt.t.iitiittt.t.iitttt.itt.tt.t.t.tt.t.
; MATRIX B TRANSPOSE SUBROUTINE
*
;ittt.ttt.t.t.t.tt.t.t.t.tt.t.t.t.tt.tt.t.tt.t.t.t.t.it
71
.
453
454 0238 E5
455 0239 C5
456 023A D5
457 0238 2175F8
458 023E 7E
459 023F 5E
460 0240 56
461 0241 83
462 0242 SF
463 0243 2101F8
464 0246 0160F8
465 0249 23
466 024A 7D
467 0248 83
468 024C 83
469 024D 6F
470 024E 7E
471 024F 10
472 0250 02
473 0251 03
474 0252 82
475 0253 6F
476 0254 7E
477 0255 02
478 0256 10
479 0257 C25102
480
481
482
483 025A 2175FB
484 0250 5E
485 025E 78
486 025F 83
487 0260 2160F8
488 0263 116040
489 0266 7E
490 0267 12
491 0268 10
492 0269 C26602
493
494
495
496
497 026C 210080
498 026F 3653
499 0271 210180
500 0274 3610
501 0276 D1
T8ROT
push
push
push
lxi
mov
h
b
d
h,SVIIAX
a,m
lllOV
~,.
d,m
mov
add
mov
1xi
I xi
inx
~
e,a
h,IPUTL
b,8TL
Initialize Counter
Initialize address pointer
h
fllOV
a,l
add
add
mov
I?
~
!,a
a,m
DlOV
dcr
stax
TBCNT inx
add
mov
Save registers
Compute address of Matrix B
~
b
b
d
I ,a
RlOV
a,a
stax
dcr
jnz
b
e
TBCNT
Copy result form local ram to common ram - Matrix B
Tbcopy
1xi
h,SVMAX
IIJOV
fllOV
~,·
add
!xi
l xi
~
IIOV
stax
dcr
jnz
a,e
h,BTL
d,BTC
a,m
Initialize local ram pointer
Initialize common ram pointer
d
e
Tbcopy
Check if all done
Signal CPU 1 all done
!xi
mvi
I xi
mvi
pop
h,CF2
m,53h
h, TSKCPU2
m,10h
d
72
Set CF2 semiphore
Set Task Assignment flag
Ioad all regiters
502
503
504
LASI13 11/01/84
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
pop
pop
0277 C1
0278 El
0279 C9
b
h
return to main
r~t
Pag~
routin~
010
;ttttttttttttttttttttttttttt.tttt
t
i ttU:UttttttttUttttttitHttttt
; DELAY SUBROUTINE
027A
0278
027C
027D
027F
0281
0282
0285
0286
0289
02BA
E5
C5
D5
06FF
OEFO
OD
C28102
05
C27F02
C9
d~lay
lp2
lp1
push
push
push
mvi
mvi
dcr
jnz
dcr
jnz
ret
h
b
d
b,Offh
c,OfOh
Sav~ r~gist~rs
i Load countH
i Load Count~r
o~cr~m~nt count~r
lpl
b
lp2
end
73
Decrement counter
Check
if one
i
; Return to main program
; End of main program
LASM3 11/01/84 Page 001
;/tttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt/
if
;fl.
il
;It MULTIPROCESSOR COMPUTATIONAL SYSTEM
t/
CPU 3 MICROCODE
;It
')
L
3
4
5
t./
;It
6
7
;liiiiiitiiiiiiiiiiiiiitiitiiiiiiiiiiiitttiiiiiiiiiiiiiiiiiiiiiil
8
; I/0 PORT DEFINITIONS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
OODF =
007F =
cport
oport
equ
equ
Odfh
07fh
; Control Port
; Output Port
; RESISTER FILE SEMIPHORE DEFINTIONS
8004 =
8005 =
equ
CF3
TSKCPU3 equ
08004h
08005h
; CPU3 - CPU 1 Handshake flag
; Task Assignment Flag
; COMMON RAM DEFINITIONS
4000
4001
4020
4030
4050
4060
=
=
=
=
=
=
MAXRC
IPUTC
ARC
SRC
ATC
BTC
equ
equ
equ
equ
equ
equ
04000h
04001h
04020h
04030h
04050h
04060h
;
;
;
;
;
;
MaxiMum number of rows
Beginning of Matrix A elements
Matrix addition results
Matrix subtraction results
Matrix A Transpose results
Matrix B Transpose results
;
;
;
;
;
;
;
;
;
Beginning of Matrix element input
Beginning of matrix element inputs
Matrix addition results
Matrix subtraction results
Matrix A Transpose results
Matrix B Transpose results
Save maximum no. of rows
Error Flag
General purpose counter
; LOCAL RAM DEFINITIONS
F800
FBOO
F801
FB20
FB30
FBSO
FB60
F875
FB76
F877
=
=
=
=
=
=
=
=
=
=
LRAH
MAXRL
IPUTL
ARL
SRL
ATL
BTL
SVMAX
ERRFLG
COUNTR
~qu
OfBOOh
equ
equ
equ
equ
equ
equ
equ
equ
equ
Of800h
Of801h
Of820h
Of830h
Of850h
Of860h
Of875h
Of876h
Of877h
;iiiiiii************************
MAIN PROGRAI'I
t
;
i*******************************
74
45
46
47
48
49
50
51
52
org
0000
OOOOh
;Initialize stack pointer
0000 31FFFF
0003 3EOO
0005 D37F
l xi
IIi Vi
out
; Load stack pointer
; Clear display
sp,Offffh
a,O
oport
;tttititiiiiiiiiiiitiiiiiiiiiiii
t
POWER UP DIAGNOSTICS
;
53
54
55
56
;tttt.tt.tttt.tt.t.tt.tt.t.t.tt.tt.tttt.t.t.tt.
LASH3 11/01/84 Page 002
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
"7<:
f.,J
76
77
78
79
BO
81
82
83
84
85
86
87
88
89
90
0007
0009
0008
OOOE
0011
0013
DBDF
FE01
C20700
210480
3EOO
77
STRT
in
cpi
jnz
l xi
mvi
fllOV
Check status of control port
cport
lh
STRT
h,CF3
a,O
m,a
Clear semiphore value
;ttttt.t.t.ttt.t.t.tt.t.t.t.t.t.t.t.tt.t.t.t.t.t
;
I/0 PORT TEST
*
;tt.tt.tt.tt.t.t.t.t.t.t.t.t.t.t.ttt.tt.t.t.t.t.t.t.t.t.
0014
0016
0017
0018
001A
0010
001E
0020
0023
0025
0027
0029
002A
0028
0020
0030
0031
0032
0034
1EOO
1C
7B
D37F
CD7A02
78
FE09
C21600
1600
1EOO
3E10
82
57
D37F
CD7A02
1C
78
FE09
C22700
cont
contl
mvi
inr
fllOV
out
call
IIIOV
cpi
e,O
e
a,e
oport
delay
a,e
jm
CONT
d,O
e,O
a,tOh
mvi
mvi
mvi
add
IIIOV
out
call
inr
fllOV
cpi
jnz
Clear counter
; Output pattern
Compare if reached last decimal value
3h
d
d,a
oport
delay
; Clear Counhr
; Initialize Ace for HSB digit display
Add value of counter
Display data pattern
e
a,e
9h
contl
75
Check if maixmum limit reached
91
92
;*******************************
t
LOCAL MEMORY TESTS
;ttttttttitittttttttiittttttitit
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
lOB
109
110
111
112
;
0037
003A
0038
003C
0030
003E
0041
0042
0043
0045
0048
0048
0040
004F
0052
0054
0056
2100F8
70
77
70
BE
C24BOO
23
70
FEFF
C23AOO
C36300
3E99
037F
C07A02
3EOO
037F
CD7A02
MCONT
lxi
mov
lllOV
MERR
mov
cmp
.jnz
inx
mov
cpi
jnz
jmp
mvi
out
call
mvi
out
call
h,LRAM
a, 1
ra,a
a, l
Til
MERR
h
a,l
Offh
MCONT
MCNTl
a,99h
oport
delay
a,O
oport
delay
; Load Start address
; Compare contents of m~mory
; Jump to error routine if not o.k.
; Else test next location
; Check if maximum limit reached
; display 9 error occurred
LASI'I3 11/01/84 Page 003
113
114
115
116
117
118
119
120
t'lt
ll.l
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
0059
005C
0050
005F
0060
0063
0066
0067
0069
006C
006F
0070
0072
1176FB
EB
3601
EB
C33AOO
2176F8
7E
FE01
CA3AOO
210480
7E
FE71
C26FOO
MCNT1
lxi
xchg
mvi
xchg
jmp
!xi
mov
cpi
..
;,
1xi
wait
mov
cpi
.jnz
d,ERRFL6
; Set Errorflg
m, 1
MCONT
h,ERRFLG
a,m
1
MCONT
h,CF3
a,m
Check if error flag is set to 1
Is error flag set to 1
Then repeat the test
; Load Semiphore address
; Wait to execute common ram test
7lh
wait
;*******************************
i
COI11'10N RAM TEST
;tttttttttttttttttt.ttttttttttttt
;
0075
0076
0078
0078
007E
0080
7E
D37F
CD7A02
2176FB
3600
210040
lllOV
a,m
out
call
lxi
mvi
lxi
oport
delay
h,ERRFL6
m,O
h,MAXRC
76
Display Semiphore Value
; Clear error flag
; Load comm ram beginning address
137
138
139
0083 75
0084 7D
0085 BE
140 008&
141 0089
142 008A
143 0088
144 0080
145 0090
14& 0093
147 0095
148 0097
149 009A
150 009C
151 009E
152 OOA1
153 OOA4
154 OOA5
155 OOA7
15& OOA8
157 OOAB
158 OOAE
159 OOAF
1&0 0081
161
162
1&3
1&4 0084
1&5 0087
1&& 0089
167
1&8 OOBA
mov
mov
cmp
CCONT
C29300
23
7D
FE30
C28300
C3ABOO
3E98
D37F
CD7A02
3EOO
D37F
CD7A02
217&F8
E8
3&01
E8
C38900
217&F8
7E
FE01
CA8300
NXT
m1 l
a,l
[a
.jnz
inx
II!OV
CERR
cpi
jnz
jmp
mvi
out
call
mvi
out
call
1
.
.Xl
NXTl
xch
mvi
xchg
jmp
lxi
mov
cpi
jz
CERR
Compare memory contents
; If not same jump to error routine
h
a, I
30h
CCONT
; Check if maximum value reached
NXT1
a1 98h
oport
delay
a,O
oport
delay
h,ERRFLG
Display error occurred
Set error flag
ra, 1
NXT
Check if error flag set
h,ERRFL6
a,m
CCONT
;SIGNAL CPU! that the test was completed
!xi
mvi
210480
3E81
77
3E88
LOOP
fiiOV
h1 CF3
a,81h
m,a
mvi
a,88h
out
call
oport
delay
; Load semiphore address
; Load value
Display diagnostics done
LASii3 ii/Oii84 Page 004
1&9
170
171
172
173
174
175
17&
177
178
179
180
181
182
OOBC D37F
008E CD7A02
;ttttttttttttttttttttttttttttttt
END OF DIAGNOSTICS
t
;ttttttttttttttttttttttttttttttt
i
Waiting to read input data
OOC1
OOC4
OOC5
OOC7
210480
7E
FE72
C2C400
'Jat2
I xi
mov
cpi
jnz
h,CF3
a,m
72h
11at2
; Load Semiphore address
; Compare value
; Try again
183
184
185
186
187
188
189
190
191
1'32
193
1'34
195
196
197
198
1'3'3
200
201
202
203
204
5
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
Start copying data to local memory
OOCA
QOCD
OOCE
OOD1
OOD4
0005
OOD6
OOD7
OODB
OOD9
OODA
OODC
210040
5E
210040
0100F8
7E
02
23
03
1D
78
FEOO
C2D400
lxi
l!lOV
lxi
CONT2
l xi
mov
stax
inx
inx
dcr
h,MAXRC
e,m
h,MAXRC
B,LRM
a,m
b
h
b
e
a,e
; Decrement Counter
IIOV
cpi
jnz
0
; Compare if all done
CONT2
Signal CPU 1 all done with copying data
OODF 210480
OOE2 3E82
OOE4 77
lxi
mvi
lOY
h,CF3
a,82h
rn,a
; Display data read
OOE5
OOE8
OOE9
OOEC
OOED
OOEF
OOF2
OOF4
OOF6
OOF9
OOFA
OOFB
OOFC
OOFE
0101
0104
2100F8
5E
2100F8
7E
D37F
CD7A02
3EOO
D37F
CD7A02
23
!D
7B
FEOO
C2ECOO
210580
3610
1xi
mov
1xi
CONT4
lliOV
out
call
mvi
out
call
inx
dcr
h,MAXRL
e,m
h,LRAM
a,a
oport
delay
a,O
oport
delay
; Load local ram address
; Output data
h
e
l!lOV
a,e
cpi
jnz
lxi
mvi
CONT4
h, TSKCPU3
m, 1011
; Check if all done
0
CPU 3 in ideal mode
;Start Computation
LASM3 11101/84 Page 005
225
226
227
228
0106
0107
010A
0108
00
210580
7E
FE10
WTSK
nop
l xi
lllOV
cpi
h1 TSKCPU3
a,m
1011
78
Load semiphore address
22'3
230
231
232
233
234
235
236
237
238
23'3
240
241
242
243
244
245
246
247
248
24'3
250
251
252
253
254
255
256
257
258
25'3
260
261
262
263
264
265
266
267
268
26'3
270
271
272
273
274
275
276
277
278
0100 CA0601
0110 FE01
0112 C21801
0115 CD3F01
0118 210580
0118 7E
011C FE02
011E C22401
0121 CD'3001
0124 210580
0127 7E
0128 FE03
012A C23001
0120 COFA01
0130 210580
0133 7E
0134 FE04
01320601
013'3 CD3802
013C C38AOO
jz
cpi
jnz
call
1xi
mov
cpi
jnz
call
lxi
mov
cpi
jnz
call
lxi
proc
procl
proc2
jnz
Wait for task
WTSK
1h
proc
ADDROT
h, TSKCPU3
a,m
Call matrix addition subroutine
2h
IIIOV
procl
SU8ROT
h,TSKCPU3
a,m
3h
proc2
TAROT
h, TSKCPU3
a,1
cpi
4h
Call subtraction subroutine
Call Transpose Matrix A subroutine
WTSK
call
TBROT
jmp
LOOP
Call Transpose Matrix B subroutine
;iiiiiiiiiiiiiiiiiiittitiittiiti
; !'lATRIX ADDITION SUBROUTINE
;ttt.iiiittttiiiitiiiiiiiitittiti
*
013F
0140
0141
0142
0145
0146
014'3
014A
0140
0150
0151
0152
0153
0154
0155
0156
0157
0158
015'3
015A
0158
015E
0161
E5
C5
D5
2175F8
7E
2177F8
77
0120F8
2101F8
5E
23
7D
83
SF
54
E8
7E
E8
86
02
FA6101
F26801
03
ADOROT push
push
push
lxi
IIIOV
1xi
llOV
lxi
1xi
IIIOV
h
b
d
h,SVI'IAX
a,m
h,COUNTR
m,a
h,IPUTL
e,ra
inx
h
a,l
e
e,a
d,h
add
mov
xchg
CADD
«rOY
nsign
xchg
add
stax
jm
jp
inx
Initalize counter
b,ARL
l!iOV
IIIOV
Save registers
Load beginning of input
; Compute beginning of Matrix A
; Compute beginning of matrix 8
<DE) = Address of Matrix B
(HL) = Address of Matrix A
a, Ill
<HL) = Address of Matrix A
lB
b
nsign
psign
b
79
mvi
stax
279
280
0162 3E01
0164 02
LAS~3
11/01/84 Page 006
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
0165
0168
0169
0168
016C
0160
0170
0171
0172
0173
0174
0175
0176
0177
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
C36C01
03
3EOO
02
E5
2177F8
35
7E
El
23
13
03
B8
C25701
psign
chkm
jmp
inx
mvi
stax
push
1xi
dcr
mov
pop
inx
inx
inx
cmp
jnz
a, I
b
chk111
b
a,O
b
h
h,COUNTR
ill
a,m
h
h
d
b
0
Increment all pointers
Check if all done
CAOO
; Completed addition operation
; Copy results in common ram
017A
0170
017E
017F
0180
0181
0184
0187
0188
0189
01BA
018B
018C
2100F8
7E
7B
83
SF
2120F8
112040
7E
12
13
23
10
C28701
1xi
h,MXRL
a,ra
mov
a,e
e
add
lllOV
e,a
h,ARL
lxi
lxi
d,ARC
f!IOV
a,m
stax
d
inx
d
inx
h
e
dcr
jnz
Ccopy
lllOV
Ccopy
Initailize register e to max count
Initailize memory pointers
Save result in common ram
Check if all done
Signal CPU 1 all done
018F
0192
0194
0197
0199
019A
019B
019C
210480
3673
210580
3610
Dl
C1
E1
C9
lxi
mvi
lxi
mvi
pop
pop
pop
ret
h,CF3
m, 73h
h,TSKCPU3
m, 10h
CPU 3 is ideal
d
b
h
Back to main program
;tttttttttttitttttttittttttttttttttt
80
326
327
328
329
330
331
332
333
334
335
336
i
MATRIX SUBTRACTION SUBROUTINE
~
i***********************************
0190
019E
019F
01AO
01A3
OIA4
01A7
E5
C5
05
2175F8
7E
2177F8
77
SUB ROT push
push
push
lxi
mov
l xi
mov
Save registers
h
b
d
h,SVIIAX
a,m
h,COUNTR
rn,a
Initailize Counter
LASII3 11/01/84 Page 007
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
01A8
OlAB
O!AE
OlAF
OlBO
0181
0182
0183
0184
0185
0186
0187
0188
0189
OlBC
018F
O!CO
01C2
01C3
01C6
01C7
01C9
01CA
01CB
OlCE
O!CF
0100
0101
0102
0103
0104
0105
0130F8
2101F8
5E
23
70
83
SF
54
EB
7E
E8
96
02
FABF01
F2C601
03
3E01
02
C3CAOI
03
3EOO
02
E5
2177F8
35
7E
El
23
03
13
B8
C28501
lxi
I xi
mov
inx
mov
add
mov
IIIOV
xchg
rnov
xchg
sub
stax
jm
jp
snsi gn inx
mvi
stax
jrnp
spsign inx
mvi
stax
schkm push
lxi
dcr
mov
pop
inx
inx
inx
cmp
jnz
CSUB
b,SRL
hI IPUTL
; Set pointer to local ram address
; Set pointer to beginning of input
e,M
h
a, 1
e
e,a
d,h
<DEl = address of Matrix B
i <HU = address of Matix A
a, a
; Perform subtraction operation
Ill
b
snsign
spsign
i Check Sign
b
a,!
b
s.:hkm
b
a,O
b
h
h,COUNTR
Save sign
; Check if all done
Ill
a,m
h
h
b
d
(l
CSUB
; Compeleted subtraction operation
; Copy results to common ram
81
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
01D8
OIOB
01DC
0100
01DE
OIDF
01E2
01E5
OIE6
01E7
01E8
01E9
2100F8
7E
78
83
SF
2130F8
113040
7E
12
23
1D
C2E501
lxi
mov
lllOV
Scopy
add
mov
lxi
l xi
mov
stax
inx
dcr
jnz
h,HAXRL
a,m
a,e
e
e,a
; Set counter i.e register e
; Point local ram
Point to common ram
h,SRL
d,SRC
a,m
d
Move data to common ram
Increment address pointer
Check if all done
h
e
Scopy
Signal CPU 1 all done
OlEC
OIEF
01FI
OIF4
210480
3673
210580
3610
I xi
mvi
lxi
mvi
h,CF3
m,73
h,TSKCPU3
m1 10h
01F6
OIF7
01F8
OIF9
Dl
C1
E1
C9
pop
pop
pop
ret
b
h
Set CF3 semiphore
Set Task Assignment flag
load all regi ters
d
return to main routne
;tiiiiiiiiiiiiiitiiiiiiiiiiiiiiiii
;MATRIX A TRANSPOSE SUBROUTINE l
;iiiiiiititiiiiiititttiiiiitiiiitt
01FA
01FB
OlFC
01FD
0200
0201
0202
0203
0204
0205
0208
0208
020C
0200
ES
C5
D5
2175F8
SE
7E
56
83
5F
0150F8
2101FB
23
7E
!D
TAROT
push
push
push
lxi
mov
mov
lllOV
add
mov
lxi
lxi
inx
mov
dcr
; Save registers
h
b
d
h,SVMX
e,m
a,m
d,m
e
e,a
b,ATL
h, IPUTL
tailize Counter
; Initalize Pointer to local rarn
; Initalize pointer to beginning of input
h
a,m
; move matrix element to ace
e
82
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
020E
020F"
0210
0211
0212
0213
0214
0215
02
03
82
6F"
7E
02
1D
C20F"02
TCNT
stax
inx
add
mov
;
b
b
d
Stor~
matrix
el~m~nt
; Compute address on
n~xt
lilOV
a,lll
stax
dcr
jnz
b
Ch~ck
e
TCNT
if all done
Copy result form local ram to comMon ram - Matrix A
0218
0218
021C
021D
021E
0221
0224
0225
0226
0227
2175F"8
5E
7B
83
2150F"8
115040
7E
12
1D
C22402
1xi
mov
h,SVI1AX
e,a
IIIOV
a,~
add
e
h,ATL
lxi
1xi
d,ATC
Tacopy mov a,m
stax
d
dcr
e
jnz
Tacopy
Signal CPU 1 all
022A
022D
022F"
0232
0234
0235
0236
Ixi
mvi
lxi
ravi
pop
pop
pop
210480
3673
210580
3610
Dl
C1
E1
Initialize local ram pointer
Initialize common ram pointer
Check if all done
don~
h,CF"3
.,73h
h,TSKCPU3
m, 10h
d
; Set CF"3
semiphor~
; Set Task Assignment flag
; load all regiters
b
h
LASI13 11/01/84 Page 009
449
450
451
452
453
454
element
!,a
0237 C9
; return to main routine
ret
;~********************************
; MATRIX B TRANSPOSE SUBROUTINE l
;ttttttttttt.tttttttt.ttt.t.ttt.tt~tttt
83
p •
455
456
457
458
45'3
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
4]'j
480
481
482
483
484
485
486
487
488
48'3
490
491
4'32
4'33
494
4'35
496
497
4'38
499
500
501
502
503
0238
023'3
023A
023B
023E
023F
0240
0241
0242
0243
0246
0249
024A
024B
024C
0240
024E
024F
0250
0251
0252
0253
0254
0255
0256
0257
E5
TBROT
cs
DS
2175F8
7E
SE
56
83
SF
2101F8
0160F8
23
7D
83
83
6F
7E
10
03
82
6F
7E
02
10
C25102
2175F8
5E
7B
83
2160F8
116040
7E
12
10
C26602
h
b
d
a,m
mov
e,a
d,m
e
e,a
h,IPUTL
b,BTL
fllOV
II'IOV
1xi
lxi
inx
mov
add
add
Initializ~ Counter
Initialize address pointer
h
a,l
e
e
l,a
a,m
e
IIIOV
mov
dcr
b
stax
TBCNT inx
b
add
d
mov
l,a
mov
a,m
stax
b
dcr
e
TBCNT
jnz
r~sult
Sav~ r~gist~rs
h,SVMX
JllOV
add
Copy
025A
0250
025E
025F
0260
0263
0266
0267
0268
0269
push
push
push
lxi
Compute address of Matrix B
form local ram to com1on ram - Matrix B
l xi
h,SVMAX
e,a
a,e
IIIOV
mov
add
lxi
lxi
Tbcopy mov
stax
dcr
jnz
~
h,BTL
d,BTC
a,a
Initialize local ram pointer
Initialize common ram pointer
d
e
Tbcopy
Check if all done
Signal CPU 1 all done
026C
026F
0271
0274
0276
0277
210480
3673
210580
3610
D1
C1
h,CF3
m,73h
h,TSKCPU3
m,10h
lxi
mvi
lxi
mvi
pop
pop
d
b
84
; Set CF3 semiphore
; Set Task Assignment flag
load all
regit~rs
504
pop
0278 E1
h
LASI13 11/01184 Page 010
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
ret
0279 C9
return to main routine
;*******************************
t
;tttttttttttttitttttttiiitttttit
; DELAY SUBROUTINE
027A
0278
027C
027D
027F
0281
0282
0285
0286
0289
028A
E5
C5
D5
06FF
OEFO
OD
C28102
05
C27F02
C9
delay
lp2
lp1
push
push
push
mvi
mvi
dcr
jnz
dcr
jnz
ret
end
h
b
d
bI Of fh
c, OfOh
c
lpl
b
lp2
Save registers
; Load counter
; Load Counter
Decrement counter
Decrement counter
; Check if all done
Return to main program
; End of main program
85