CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
AUDIO DELAY USING DIGITAL TECHNIQUES
\\
A project submitted in partial satisfaction
of the requirements for the degree of Master of Science in
Engineering
by
Roy .--Nabel
August, 1980
The Project of Roy Nabel is approved:
Jack o•Brien
Raym d Davidson
California State University, Northridge
ii
TABLE OF CONTENTS
Page
List of Figures . . . . . . . . . . . . . .. .. .. .. . . . . . .. . . . . .• .. . . .. . . . . . .
v
List of Tables...............................................
vi
Abs tract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi i
Chapter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
General Description of Project ....•..................
Audio Information ................................... .
Purpose ...................... · · ·. · · · · · · · · · · · · · · · · · · · ·
1
7
8
Chapter 2 ................................................... .
12
Ha rdwa r'e Theory of Operation ........................ .
Ana 1og Input Board .................................. .
Central Processing Unit Board ....................... .
Memo·ry Board .................................•.......
Ana 1 og Output Board ................................. .
12
12
Chapter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
Software Theory of Operation .... ......... ............
System Flow of Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Subroutines . .. . .. .. . .. . .. .. .. .. . .. .. . .. . .. ..
21
25
27
'27
27
Chapter 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
13
19
l9
Problems ............................. .
Results .............................. .
Results .............................. .
Improvements ......................... .
3G
Jl
32
Bib1 ioqraphy ................................................ .
33
Development of
Description of
Explanation of
Future Project
iii
32
Page
Appendices
1.
Ha rdv1a re Schematics ..................................... .
2.
Hardware Parts Layouts .................................. .
3.
Hardware Timing Diagrams ................................ .
4.
Hardware
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . • . • . . . • . . .
58
5.
Backplane Wiring Tab 1e . .. . . .. . .. .. .. . . .. . .. .. .. . .. . . . . .. .
63
6.
I/0 Ports Description .. .. .. .. . .. .. .. .. . .. . . . . . . .. .. . . • .. .
G6
7.
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
8.
Software Flowcharts . .. .. . . .. .. .. ... .. ... .. . . . .. . . . . . . . . . .
71
9.
Software .A.ssembly Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
iv
46
List of Figures
No.
Description
1.1
Frequency Sealing .................................•..
2
1.2
System Block Diagram .........................•......•
3
1.3
Detailed System Block Diagram ....................... .
4
1.4
Sampling and Output Process ......................... .
5
1.5
The Audible Spectrum ................................ .
9
1.6
Audio Range
10
1.7
Au d i o Ma skin g ............•...........................
11
2.1
Filter Amplitude Attenuation ........................ .
16
2.2
Filter Phase Response
17
2.3
Filter Envelope Delay
18
3.1
Software Development Process .......................•.
22
Page
v
List of Tables
No.
Description
Page
2.1
Two•s Complement Coding ............................. .
15
3. l
Program Description ................................. .
23
3.2
Subroutine Description
24
3.3
State Transition Table
26
vi
ABSTRACT
AUDIO DELAY USING DIGITAL TECHNIQUES
by
Roy Nabel
Master of Science
in Engineering
Audio delays can be used in a variety of signal processing
applications.
Audio delays can be used in music synthesizers to
create special effects.
The system described in this project takes
an input signal x(t) and performs frequency scaling:
a<
y(t) = x(at)
1
The output y(t) is then a lower frequency than the input x(t) by
the factor a.
The use of digital techniques allows the coefficient
a to be remotely changed under software control.
vii
Chapter 1
General Description of Project
The purpose of this project was to build a system capable of
performing the following function of frequency sealing:
y(t) = x(at)
a
<
Eq. 1 . 1
1
Figure 1 illustrates the frequency scaling operation in the ideal
case.
The bottom waveform is a stretched version of the top wave-
form by the coefficient which in this case is 0.5.
There are three main sections included in this project as
shown in figure 1.2.
The input section converts signals from the
Analog domain into the Digital domain.
The input signals can be any
voltage between -5 and +5 volts and have a frequency range from 0 to
60 hertz.
The output of the first block is a stream of parallel
binary words.
Stage 2 takes the output of stage 1 and performs the
necessary operations to execute eq. 1. 1.
The output of stage 2 is
also a stream of parallel words, not always equal to the input stream,
which represent y(t).
Stage 3 takes the stream of binary words and
converts them into a corresponding voltage.
Figure 1.2 represents
a simplified picture of what the system does so that the reader understands the system from a general view.
Each stage can be further sub-
divided into blocks which perform an important function.
2
A
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= Asinawt
= sin 2t
a=1 no scaling
Input Waveforrr:
A
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1
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y(T)
= x(at)
= sin t
a
= 0.5
Cu tpu t >12. ve form
Figure 1.1 Frequency
Scaling
(ideal case)
Stage
Stage
1
Input Section
2
Stage
Processing Section
}
Output Section
Output
Input
Analog-7Digi tal
Conversion
~
Processing
Figure
1,2
Digi tal-7 Analog
Conversion
System
Block
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Diagram
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Figure 1.4
Cutput Fainter
~ample
\
Fainter
Sa~pling ~ Gutpu~ rrocess
6
A more detailed block diagram of the project is shown in
figure 1.3.
The stages of figure 1.2 have been subdivided into
separate blocks as follows:
Stage 1:
Input Section
l - Low pass filter
2 - Sample and Hold module
3 -Analog to Digital conversion
Stage 2:
Processing Section
1 - Microcomputer
2 - Priority encoder
3 - EPROM
4 - RAM
Stage 3 - Output Section
l
Digital to Analog conversion
2 - Low pass filter
A detailed explanation of the function of each of the above can be
found in the references (5, 7-9, 19).
How Does the System Work
Imagine 2 clocks that tell you when an operation will be
performed.
The sample clock tells you when to convert a sample from
the input waveform.
this clock.
The sampling theorem determines the rate of
The converted samples are then stored in Random Access
Memory (RAM) in the memory area called BUF.
The output clock tells
you when to output the signal stored in memory.
The memory to store
7
the data is finite, so that no more samples are taken when the
memory area is full.
When all the samples have been outputted the
process starts over.
Note that in figure 1.4 the samples between tl
and t2 are lost and that there is a discontinuity when the cycle of
sampling and outputting is repeated.
This differs from the ideal
case in figure 1.1 where the waveforms are continuous.
The dis-
continuity shown in figure 1.4 will cause some distortion.
One
must remember that typical audio signals do contain discontinuities.
Chapters 2 and 3 give a detailed description of how the
system works.
To fully understand the system requires an under-
standing of both hardware and software.
Purpose
You may ask why one would want to digitize signals and then
stretch the frequency.
The use of digital techniques offer several
advantages over analog techniques:
1.
Ada pta bi 1i ty
2.
Noise immunity
3.
Testing
4.
Size of components
5.
Faster development time
6.
Component reliability
Applications in which frequency scaling can be used are
limited only by the imagination.
One application is to reduce audio
feedback, thereby allowing increased volume control.
Another
8
application is music synthesizers that create special effects.
Using a computer to process the signals allows one to change
the scaling under software control.
A person can program the scaling
to occur at random times or to follow a predetermined sequence.
The
result, in the case of music synthesizers, allows a musician to
extend his or her playing ability which is normally limited by the
speed with which he or she can move.
In addition the hands become
free to perform other arrangements concurrently.
Other applications
of signal processing can be found in references (1, 12, 16).
Background Information
No complete control system model exists for the human ear.
Such a model would be invaluable for the audio design engineer.
Figures 5, 6 and 7 give some numerical data to allow the reader a
method of relating experienced perceptions to numbers.
signals are in the range of 0 to 5 kilohertz.
Most audio
To satisfy my own
curiosity about hearing I used an oscillator and a speaker to examine the effects of different frequencies on my ear.
Using a 20
volt peak-peak signal at 2 KHZ and 16KHZ I was able to experience
different frequencies.
feet away easily.
At 2KHZ I could hear the signal from 15
At 16 KHZ I could barely perceive a signal with
my ear pressed against the speaker grillcloth.
A great deal of
work remains to be done in both applied and theoretical audio
engineering.
I
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levels of equ•l Joudncs< 0< porec1ved by normal ~dulL< for sinusoidal
Signals. The lowc:sr curve (0 phonsl i• the <hresnold of audibili<y
(aircr Flerchcr and :o.tunson1.
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~zoo
ot SliCOnll<rf tone
FIGURE Z-7. Masking of a so:oadary <inusoid of varying ampli·
tude ana frequm~~:y by a primarY <inusoia at 1200 Hz. 30 dB above
thrc::silolcl. When tile secondary tone falls below tbe solid CU1"'o'e.
it has :10 orfect on tbo ~tion of the primarY tone. Above tho
solid curve, tho secoadar/ tone pro<iuc=s a complex effect which is
pcn:eiYed as either a beat, a mixture of tones. or both. (From
Lid<lid:r, 19,1, after F!etcilsr, 1929, from W"%'d and Lane, 1924.
By penni.ssi011 from John Wiley ana Sons. Inc., i'rom Speech ana
Hearing by H:lrvcy F!etchct', Ccpyrigllt, 1929, by D. Van Nourana
Company, by permission of Van Nostr.u~a R.cinl!ol<i Company;
and from Bell Tele;moo.t Uborawries.)
Fi 0ure 1. 6
•ooo
11
F~inHZ
FIG1JRE l-3. Masking re;ion produced by rwTOW-band no~ :u
410Hz and a bandwidth oi 90 Hz. at various amplitudes. A test
siiiJI.Li below a given curve will remain inaudible. The bandwidtll
oi masKing incnoascs as the intensitY oi the noise is increased.
(lteprinte<i with permission oi tho Acousticai Soc:ier;y or America.
from Egan and Hake, 19SO.)
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Masl<inq ll!fernal in msac
FIGOJU;: l-~. Forward all<1 bac:Xwatd muking oi white noi.., with
a ptal:e tone. A whote noi.., bum is presented and a test tone at
a reduced level is ~ed later (forward masking) or earlier
(bac:Xwani masking). The threshold shift oi the tone :is a function
of the time dill"eretlal to the noise ma.tker is shown. The effect is
.ven stronga- ii the masker is also a rona rathec than broadband
white noise. (RC!)rinted with permission oi the Acoustical Socior;y
oi America, Volume .l4, No. 8, 1962.)
Fi.gure 1. 7 ·
Chapter 2
Hardware Theory of Operation
Five printed circuit boards are required for the system:
l.
Analog input board
2.
Central processing board
3.
Memory board
4.
Analog output board
5.
Backplane board
The backplane is a printed circuit board with eleven 56-pin connectors
which the four other boards plug into.
The backplane connects sig-
nals, power and ground that are common to the four other boards.
The analog input board takes an input signal of -5 volts to
+5 volts and a maximum frequency of 60 hertz (HZ) and converts a
sample into a tW0
1
S
complement number.
of the voltage to digital conversion.
Table 2.1 gives an example
The filter attenuates frequen-
cies above one half the sampling area (500HZ) to less than 42 decibels
(dB), which is the resolution of the analog-digital converter (ADC
module).
The filter was designed using reference 5 for a C0?-20-51
7 stage elliptic filter.
Figures 2.1-2.3 give the characteristics
of the filter.
An elliptic filter has ripple in both the passband
and stopband.
ihe cutoff of the filter was designed for 100 HZ but
using components that were available reduced the cutoff to 65 HZ.
The filter is a passive LC design with an input immediance of 1000
12
13
ohms.
After the signal has been filtered the signal passes through
a sample and hold module.
The sample and hold (S/H) module is con-
trolled by the software.
Output port FC controls the sample and hold
module and the ADC module.
After a hold command is sent to the S/H
module, a command to start conversion is sent to the ADC module.
The
ADC module takes four microseconds to convert a voltage to its corresponding two 1 s complement digital code.
The ADC module uses a
successive approximation register (SAR) technique to determine the
input voltage.
After four microseconds the software inputs the con-
verted data from port F8 which is an 8-bit latch.
The subroutine
ADC controls all the operations just discussed.
The Central processing Unit (CPU) board performs the execution of all software instructions.
All signals such as data address
and control are generated on the CPU board.
The main component of
the CPU board is an integrated circuit chip, the l8085A, which is an
8-bit microcomputer.
Most of the operation of the CPU chips can be
found in references (7-10).
14
On the prototype area of the CPU board are circuits that perform the
functions of:
15
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19
1.
Timer
2.
Interrupt control
3.
Address modification
There are other circuits on the prototype area which will not be
discussed or documented as they do not directly apply to the project.
The address modification extends the address range of the normal
SDK-85 kit to a range from
3000-FFFF.
The timer is a programmable
unit which generates the sample and output clocks.
synchronized by the gate control signal.
These clocks are
The two clock outputs of
the timer trigger two SN 7474 flip flops to latch an interrupt signal
to the priority encoder.
The priority encoder is also programmable
and generates a positive pulse on the interrupt (INT) line of the
CPU.
If the interrupts are enabled then an interrupt acknowledge
(INTA) signal is returned from the CPU to the priority encoder.
At
this time the priority encoder releases a Call instruction which is
synchronized by successive INTA's.
The call instruction vectors the
CPU to the appropriate interrupt handling software routine.
The memory board is a 16K x 8 bit volatile static RAM
organization.
There are 32-4K x 1 memory chips that have an access
time of 450 nanoseconds.
The memory is located at location COOO-FFFF
hex.
The analog output board has an update rate of 5 megahertz
(MHZ).
Two's complement data is sent to this board to be converted
to a voltage level.
An output filter is used to eliminate frequen-
cies greater than 65HZ.
The digital-analog (D/A) converter generates
20
high frequency components due to the staircase output.
The hardware required to run the system is:
1 -
Tripple outpout DC power supply+ 15v at
1 amp and +5v at 5 amps.
1 -Audio oscillator
1 - Oscilloscope
Chapter 3
Software Theory of Operation
The expansion EPROM located on the SDK-85 kit contains all
the software needed to execute Eq. 1.1.
The basic and expansion
RAMs also located on the SDK-85 kit are used to store various pointers
and variables.
The sampled data is stored starting at location
$0000.
There is one main program which uses six subroutines.
The
program and the subroutines are described in table 3.1 and 3.2
respectively.
The software was written with modularity in mind,
so that each subroutine performs only one major task.
All the soft-
ware was produced using the flowchart shown in figure 3.1.
All software processing must occur between sampling periods
or so that the sampling rate is more than twice the greatest input
frequency.
If a 500HZ sampling rate is chosen then all the software
processing must be accomplished in less than 2 milliseconds (ms).
The sampling software takes approximately 0.13 ms and the output
routine takes 0.12 ms.
21
22
Lg~~e-~ op Fl owch~ 'C~s
.-------t_ _ _ _ --- --'
·-
~r·- ·-·~
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---~·-r
Write High Level language
i
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\
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i
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Mai~e-~~=~
.
! Key in Machine language ~
i
1
Using SDK-85 Keypad
·----= ----r=-------------_-~
A.-------,
Program Running
L _________ -
--
?
i
- ---------- ------------------
No
Yes
(..___En_d___.)
Figure 3. l
Software Development Process
23
Table 3.1
Program
Address
0800
Description
AUDDLY - Audio delay is the program that calls the
subroutines in Table 3.1 to produce a delay as specified by the input parameters.
24
Table 3.2
Subroutines
Description
Address
08E3
ADC - Converts input signal into digital data using
a sample and hold and an 8-bit A-D converter.
Con-
verted sample is in A register.
0811
INIT- Initializes the system pointers and calculates
end of file markers.
0880
INTHND- Interrupt handler calls appropriate routine
and generates an EOI for 8259.
0880
Resets the 7474's.
OUTPUT - Output takes samples stored in BUF at a
rate specifiec by clock (clk)l.
0859
PICINIT- PICINIT initializes the I8259 priority
encoder.
08A5
SAMPLE - Samples the input signal at a rate
specified by clkO which must be twice the
highest input frequency.
0838
TIMINIT- TIMINIT initializes the I8253 timer.
25
System Flow of Control
The system flow transition table 3.3 shows the main program
Audio Delay (AUDDLY) has 2 phases:
1.
Initialization
2.
Execution
After the program enters the execution phase there are two states:
1.
Data buffer is not full
2.
Data buffer full
Table 3.3 shows how control (what code the CPU is executing) flows.
As an example let us examine the flow of control in the execution
phase.
The system has already been initialized and is running.
Control goes from the main program, which is level 1, and waits for
an interrupt at which time control goes to level 2.
At this point
there is a branch depending on what the interrupt was.
If the
interrupt was from the sample clock, control goes from the INTHND
routine to the SAMPLE routine which is level 3.
After finishing
the sample routine, control goes back to level 2 and then back to
level 1, the main program, to await another interrupt.
If the
interrupt was from the output clock, control goes from the interrupt handler level 2 to the output routine level 3 and then to the
ADC routine level 4 and then back to level 3 to 2 to l.
The level
of control also shows the depth of subroutine nesting.
This is how
many return addresses can be in the stack at any given time.
To get the number of nestings, subtract 1 from the level of
control.
.26
Execution
Phase
Buffer Not \ Buffer Full
Name
1
AUDDLY
2
INir.':''
1
'L-----,-----
Initialization ?hase
Full
Lst Smnl
OUT p:;r:
5
6
7
ADC
:'able
J,J
State
~ransition
Table
Lst Cut
Softvm re Memory
r~aps
Appendix 7 gives two memory maps.
important from the software point of view.
sively during the development process.
the input parameters.
Memory map #2 is more
This map was used exten-
Locations 2800-2805 contain
Note that memory map #2 does not contain
locations for programs or subroutines.
The programs were developed
in RAM locations and then moved to EPROM so their addresses changed.
The locations 2800-2800 remained constant and were used to debug the
software.
Software Program
AUDDLY, the main program, waits for an interrupt to cal1 an
appropriate subroutine.
vent a gap in the output.
AUDDLY outputs a sample immediately to preIt initializes the system to start before
entering into the execution phase.
Software Subroutines
The following paragrahps describe each subroutine.
Appendixes 7, 8 and 9 also clarify the softvJare operation.
Appen-
dix 11 is the actual code in both assembly and machine language.
The style of documentation was copied from the code written for
the SOK-85 monitor which was found to be well organized and easy
to read.
INIT is used to initialize the system.
The routine TIMINIT
is called to initialize the sample dock and the output clock.
The
two pointers, SMPPTR and OUTPTR, are initially pointing to the top
2o
of the data buffer called BUF.
End of file markers EBUF and EBUFl
a.re calculated from the imput parameter buffer length that is initially keyed into memory by the user at location $2800.
PICINIT is
called to initialize the priority encoder.
TIMINIT initializes the I8253 timer chip for Mode 2 binary
counting.
The two clocks are synchronized by the gate control
signal.
PICINIT initializes the 18259 programmable priority encoder.
The step interval between interrupt routines is set for eight.
The
priority encoder is programmed to respond to the highest priority
first.
INTHND disables interrupts and then calls the appropriate
subroutine.
After the subroutine returns to the interrupt handler,
an EOI instruction is sent to the I8259 and a preset is sent to the
appropriate 7474 to clear the interrupt.
SAMPLE calls a routine ADC to get an input sample.
This
sample is stored in BUF at the memory location pointed to by SMPPTR.
This pointer is incremented until the end of BUF has been reached.
At this point the SAMPLE routine ignores interrupts to sample the
input until the output routine finishes outputing all the data
stored in BUF.
The OUTPUT routine will then reset the SMPPTR.
OUTPUT outputs the data stored in the buffer called BUF.
OUTPPTR specifies the location from which to output and is incremented by one after each output.
When the data has all been out-
putted both the OUTPTR and SMPPTR are reset to point to the top of
BUF.
ADC controls the timing of the sample-and-hold module and the
ADC converter.
by
AUDDLY.
The ADC routine is used
by
the OUTPUT routine and also
The ADC routine waits for two microseconds
by
using two
no-operations (NOP's) instead of having to use the ADC's ECC signal
to go to an interrupt routine.
method.
Using two NOP's is a more efficient
After inputting the sample, the sample-and-hold module is
reset to the track position while the ADC converter is set to no
operation.
Chapter 4
Development of Problems
The first solution approach to the problem was to use a two
pole butterworth filter and a maximum frequency of five KHZ.
This
approach produced a delayed output but a lower frequency alias
appeared.
There was also a lot of noise since there was no filter
on the output.
A priority encoder
code to identify the interrupt.
~,<;as
used that generated a device
A software problem that was ·annoy-
ing to find resulted from not having an intruction to pop a valve off
the stack when an RST 6.5 interrupt arrived.
The second approach v;as the solution that has been documented.
~Jith
this method there are two filters with extremely sharp rolloffs
and a lower input frequency to allow the processor more time.
avoids the aliasing problem.
This
In the construction of low frequency
filters of an LC design many coils are not commercially available
and all contain a significant resistance value that tends to attenuate the input.
and bulky.
The inductors and capacitors also tended to be large
An LC design was chosen over an active RC design because
it required fewer connections.
A software development system would
have decreased the development time but wasn't used because of
their expense.
30
31
Description of Results
The project stretched a 60HZ 4 volt peak-peak input sinewave
by 37 HZ.
The resulting output of the system was a 4-volt peak-peak
sinewave of 23 HZ.
The input parameters needed by the software to
accomplish the above stretching were:
Location (Hex)
Value (Hex)
Description
2800
FF
Blen
2801
00
2802
00
2803
oc
2804
00
2805
20
Sample
Frequency
Audio
Delay
The value FFH represents a memory area of 256 bytes staring at RAM
location DOOOH.
If the value of Audio Delay is set equal to the
Sample Frequency, then the output is an exact replica of the input.
The output waveform has both a hardware filter phase shift and a
software time shift which make the output appear shifted when displayed on an oscilloscope.
More delay than 37HZ can be accomplished but serious distortion due to aliasing appears.
The maximum value that can be
used for Audio Delay with no distortion is 2000H.
32
Explanation of Results
The project demonstrated that digital signal processing of
audio signals is possible and economically realizable.
distortion introduced at the end of each cycle.
There is
The only drawback
at this time is that the slow speed of the microcomputer does not
allow the full 20 KHZ range of audio signals to be processed.
The
advantage of digital techniques over analog is the ease of changing
the hardware configuration under software control.
Future Projects
There are an infinite number of new areas in digital signal
processing to be explored.
Digital audio is just coming of age
with the recent advances in digital technology.
If I were to con-
tinue this project I would implement the following changes.
1.
A better software development system
2.
Faster processing
3.
Logarithmic compression of data
4.
Programmable digital filter
5.
Mixing multiple inputs
6.
Higher and faster resolution A/0 and D/A components
BIBLIOGRAPHY
1.
Blesser, Barry A. 11 Digitization of Audio: A Comprehensive
Examination of Theory, Implementation and Current Practice, 11
Journal of Audio Engineering Society, Oct. 1978, val. 26,
no. 10, p. 739-770.
2.
Bracewell, Ron. 11 The Fourier Transform and Its Applications,"
McGraw Hill, 1965.
3.
Debo, Gordon J. "An RC Active Filter Design Handbook, 11 pub.
NASA, 1977, NASA SP-5104.
4.
Gabel, Robert A.; Roberts, Richard A.
tems," John Wiley and Sons, 1973.
5.
Hansell, Grant E. "Filter Design and Evaluation," Van Nostrand
Reinhold Co., 1969.
6.
Hewlett Packard, "Electronics Instruments and Systems, 11 Genera 1
Cata i ague, 1977.
7.
Intel Corp.,
11
SDK-85 User's Manual, 1' Dec. 1977.
8.
Intel Corp.
11
Intel Component Data Catalogue," 1979.
9.
Intel Corp.
11
MCS-85 User•s Manual," Jan. 1978.
10.
Intel Corp.
11
Peripheral Design Handbook, 11 April 1978.
11.
Johnson, D. E.; Johnson, J. R.; Moore, H. P.
Active Filters,•• Prentice Hall, 1980.
12.
Oppenheim, Alan V. 11 Applications of Digital Signal Processing:•
Prentice Hall, 1978, chp. 2.
13.
Passey, Douglas. "Low-Cost Processor Package Programs E-PROMS, 11
Electronics, June 7, 1979, p. 146-149.
14.
Peebles, Peyton Z. 11 Coll1Tlunication System Principles:• Addison
Wesley, 1976, p. 294.
15.
Peled, Abraham; Liu, Bede.
Wiley and Sons, 1976.
11
Signal and Linear Sys-
"A Handbook of
"Digital Signal Processing," John
33
34
16.
Rabiner, LavJrence R.; Gold, Bernard. 11 Theory and Application
of Digital Signal Processing,~~ Prentice Hall, 1975.
17.
Ramirez, Robert W. 11 The Fast Fourier Transfonns Errors are
Predictable, Therefore Manageable, 11 Electronics, June 13,
19i4.
18.
Ramirez, Robert~~. 11 Fast Fourier Transforms Male Correlation
Simpler, 11 Electronics, June 26, 1975.
19.
Sheingold, Daniel H. 11 Analog-Digital Conversion Handbook, 11
Analog Devices, 1972.
20.
Souchet, Louis A. 11 An Eight Bit Data Acquisition System, 11
MS Thesis, CSUN, 1979.
21.
Spiegal, Murray R. 11 Fourier Analysis,'' McGraw Hill, Schaumb
Outline Series, 1974.
22.
Texas Instruments.
11
The MOS Memory Data Book, 11 1979.
23.
Texas Instruments.
11
The TTL Data Book," 1976.
24.
Valkenburg, ~1. E. Van.
ed. , 1974.
11
Network Analysis," Prentice Hall, 3rd
APPENDIX 1
HARDWARE
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I
300
I
250
!
I
30
I
I
1
I
I
MAX.
UNIT
I
I .,
I
I
I
I
I
7/
"'
"'n,
-
n<
,.
~·
c
-
READ TIMING
---···--'
-:..."'-
c:
X
JATA&VS
..
a----x"--:.,. ___
;<
"~
~
;ji)
·-'-:~·--"·-
-~,or-
\_/
___ ,_
OATA. SYS/'.;.· ~:
. "'lGH
lM~'"OA!.IC£
X
-
l
' •
F
....
-:
.
-~.,,-
·:,1.~10
:l-ltGHI .... ,I;!JANC!
,
G-
G-
INPUT WAVEFORMS FOR A.C. TESTS:
Z.4
Z.2
H
O.B
0...+5
>
TEST POINTS
<
2.2
J.l
0.8
-
..,-
..l-
.1
2.
I
oa&w"
~c
CM(Cl£0
'"'~OVtD
Y
N~6~L
OAf[
IH'l'-50
I
3
s- ":l
c:
5~:.ALC:.
/..1I
:
;;
. 110 we.
Il
-~-...•
~("":::,1!:,.1
.5
~
,;:.
~
T!Tl(
'
7
CPU
),M/N(;r
OIUWIMii
I
/
•o.
3o~-<;{1>
VIA6.'?AM
2
54
+
1
7
5
A
8253, 8253-5
r~
A. C. CHARACTERISTlCS (CAnt'd):
• a'c
to
;o•c:
Vee •
:;.ov !5%: GNO • ov
CLOCK ANO GATE nMING
3253
PARAMETER
tCLK
:~
r
...
MAX.
MIN.
MAX.
Clock ?'!nod
380
de
380
1c
High Pulse Width
230
230
,,
,,,
,.
Low Pulse Widtn
:so
150
Gate ltJidtl'1 Hign
ISO
I SO
ns
tat.
Gate Width Low
100
100
os
:oo
100
os
so
so
1S
i
tcs
tGH
.\1011 ':
UNIT
tGw
'""''-
-
3253-5
MIN.
SYMSOI.
Gate
!
~t
UQ rime to CLK:
Gats Hold Time A her CLK ~
<oo
Outcuc Oe1av From CLK~i 1 1
roo a
Out::Jut Oelav From Gate- t.i II
r~tt
Cono1uons: 37:53:
c'- • 1ooor=: S2SJ.S:
c~
i
ns
400
•co
300
300
-
ns
----·1S
• ISOaF .
. r-'-.-
;-~- -~
---""-·---·
:-;,--
-
'
F
r.------
-"3a-
JU~O---------------------------J ~------------rL~--------------
H
..,..
<.}
J.'
3
I
OUWM
RO'{
OAf[
3 oF C,
SI2E
NON E.
I
I
Till£
OIUWHUi
oOA.:<'D
C.f'IJ
TIMING.
liJQ
!:IAG-R.4M
3
55
3
1
4
7
A
A
-
-
TIMING DIAGRAM FOR AOC-EHBB
Output: 10101010
~;;:~~· ~ -;_
--:
---·~
----··---------------·--'
---·.--··
:
-
,.--, r--··11
,.----. . - .-,J., --•. . . . , '"-:--.-- -'
··~·
~
"'
'I·-, J'
~ :- '• "U
~
•
l_j
~
L.
:...
i
-i-- " - ...
wI
!I,
~~
£
l _ ·- - ·
-- __ ..,_-
:~:.~<.~.~ .:: ~-~:L:·:J ~tfl:~-=:.:J:~ J•H·~t~~i~~--~~
:~.
-
..______ _
_:,_
_;_~~-
:r--i·-----
p
'
.; L . . - - ·
_ _ __.:.j
....
--~--
--------
.:.;11.
G
&
H
..J.,.
.l
:L
ouwo Ro>f
CHtCIE.D
NA8E.L
i
3
--- ...
out
:::IJ....-:!C
'+•'l.'l-10
,5C.ALS
I
:
~
A
.voi-J e:..
I
I
5U
5
~a-r;
!.!-
-~
7
5
TITlE
AI'IALOc;. I.N<>IJ7'
""i!MiN&-
o•aw'"' .. o.
3QA,;(?
'JrA&~~~M
i..J,
/
56
J.
7
ACCURACY CHARACTERISTICS VS. CH
Typi031 at 25" C, •lSV SU9pli..
OPEN LOOP FREQUENCY RESPONSE
Typical at 25" C. ~15V Supplift
A
I~
:~J!!\1!! 11111\ill
11\ln! 11111\ll \11\IU
111\11
11\II:U \IIIII\~ liliili! lltil\ 11/lii•
~ '1-IJ!!!! ).J.JII\!t':!JiUJc" • •.ocao•l i!i\11! 1111\!il 111\IH.
~ • I !I~ Ill~ i'S tlycM••-•illllil
i\111\i 1111111
,1 ~ · '1-IJI\i'i 1-!Jil[l '\J ,,~ u~ ..... 1\li 1111\!l : 11!1!:'
~
11\il':iill:'":':lli~lilli\\!!li
illiil\!1! 1
~ : c" • ,.,..~1\liLx.lliiiil 'I..J.i~ r! !iili! IIIII~ Ill!!:::
:iii~ ~~~·~~lliii lll!i!rt\ i\Ji\11:
!"' ~ 1/C"·•·•••rf~
,, ~ il\liill !1\iiil~
iliiili ·ll!ll loll•;,
j ~ \'il;i1l :1\!ii i\1111!! lli\11\! 1\!lll•.~"l!i!\ \1\lli\i
.~ ;11\IH' i!!!\\ lllillli !i\11114 11\lll! 1'\.'\tlill l!!ll!iil
~ li\iliii ilill!\ 1\ill!in lllllilllil'illii illf~ll!lll
• Ifill\]:, ! ! !l!fl Ill ii!il i llll:ll ! IIIII\! ' 1!lllill i filili;l
II~
•
1~
I
l
I
I
~~Oiol00t"'--I.T.4GA
OIM)Qtl't ..w~
,.!'\:
.
..
..
_
'"'
I
"'"
I
I
'
"\.
,_. ,..._,. ~ MOt,Q Oll•'l•T ... t!Ml•:
lottt,I.J¥0t.ts
...
'"
-- - ·- - ·I
I
'
:,
c
...
"\.
-
SPE!O CHARACTERISTICS VS. CH
Typical ..
25" C. :15V Supplift
HOLD MODE VOLTAGE DROOP VS. TEMPERATURE
Typical, : 15V Su11010..
1/
::.
!
!/
1/
T/
·--
...I
- -
..
.....
I
:
I
I
·-T-·'
1I
I
.
I I
I
i:,;
~ 1
? 9
"". ,I '''""'"" / ..L
.... 1<..
L...,..J
G.UAIMJ
~
o,:•~t
r~tt•
I
I
I
II
II
I
SAMPLE & HOLD. UNITY GAIN,
NONINVERTING
i
I
~
,,~
l
I
I
OCGI1At,
I
I
I
I
J I.
c:
c,..•,Oiu.IJ
T.,._...,.. 0.,... C
··VO<
.,';). ......
,:,) ·"
I
-
.j
~
r
I
./'
P'
....
...
-
I
I
I
'"""''
GAIN,.+1
The lOOK onm offset trimming potentiometer
should be a 100 ppmfC cermet 15 turn type:
These are available from Oatal System~ at SJ.OO
each. To zero, ground input (pin 2) and digital
control (pin 14) and adjust lOOK offset trim
for zero output (pin 7).
•lt'WOC
~
7
I
OU[
tiTU
A 1'1/ AL :J Go !IVf'UT
-;'IMI!Jii.
CHBUD
I
I
0
::.~.\f;l
i'i
57
5
3
.l
i
A
TMS 4044 JL, JDL, NL; TMS 40L44 JL, JDL, NL;
TMS 4046 JL. JOL, NL; TMS 40L46 JL, JDL, NL
4096-WORO BY 1·BIT STA TlC RAMs
=O"C to 70"C.
switcning characteristics ovet recommended voltage ranqe, T A
1 sltfflts 74 TTl. load. Ct.:: 100 pF
0
,---------------..------,--1
r
I
PASIAMV"EII
1
-----------.---------~
TMS (I)U-151 T~ ..,...,~....:10! TMS 4044/~ ....t! I TMS 4044/~.....S!
!
TMS...,...,, iT>ISJOo&O/L4 ..201 TMS40441/L46o25l TMS4046o<.-5l UNIT !
~----------------l.'- ~IN
!:!(At
~S(Imltltt'l'nadl:2f'MS
i
'I"VX
OurcutdatallattdaMet~@'!scnange
]
'-fAX
ISO
Mut
I.
Il-l_,:.:::':.:;!::.\--~~cce.:._,ss.,.,..:-=.:::::=.:._:_"l::_n__-+~--,.---'~C-;~!-
c.
MAl
~00
I
,'0
;
~
!~AX
MIN
~I
!
MIN
~50 i
I
~~ ·~
20
I.AAX
-150
\
~
,.,.,
!
-
_!
::~n",:l,
20
c
to
read cycle timing-
'D
1
I• - - - - - - - - elr<tt
. ,. .
-------------------1\
- - - - " \
r'l~:'-------
'c'
AOOFIII!SS.A
." - - - - ·{
.ao.. ss
••ua
-
1
CHIP Si~ICT
$
OUTPUT OATA. Q
'"'
vo,.,
\i'\
.
I
l
-t:.
!
~-'.-vt.s
;
~------------------.~'t•Sl
'N:C~!
------:----w•-•----'1:.,•:-------------::~&-.'""~:'"'.:;"':}- ~-•!
•oc
~.~-------------:--~~~~
.-'at.t.l~
F
!
F
.utl\mlf'iqnrfllf'ei'Ot(!Oir'!Sattt08V a'ld2.0VMJI'ICNiS_..,08'1 ..-.12.2V'-"'CIJIOUCSl90'!'ooo-11.1"""-I'IMi1114fallllmii'S
......,~ •
..,...,tS~torarMdctCM·
;I-------------------.-~,-N'!--.......
-.~
l
'ino-.-s-......
--,-L...
-:10-,i-TM-S-4044/- L.U.t5 l TloiSlCU/L....:;-S-~
i
---1
TMS ...,.._,, i T>IS ...,..,L, .. tD I T>IS ....._,L"3-25 T\154046/L..._.S I UNIT
i \CIH
lriiA.l\
loftH
.WAX
l
tr.tiH
&.4A.X I
l.oltH
\tAX
PAAAMaTI!II
:.:it'd)
"'
H
-l
·s
"3
~'t
•••w•
-
I
':?o Y
NFI9~L 1'1-.:1.9-50
l
APPIO'ftD
l
2
~
,-
If.
:
;cAL S:.!
.-1
NON~
I s;.;;: t::l!
I
..:J
~
,;:
~
ORAWIMC.
'10
~
APPENDIX 4
HARDWARE PARTS LISTS
58
:=-:.~:r--[
------~~-
I_
---------------~-_}CONIRACl
__ _!our_d_________________________
01<1
N~~~~?LII
111M
\)I¥
llQlJ
~1¥
j-----
RQO
UNII
Of
MtASUBt
UI<AWING
COOL
IOHil
OH
OOCUM(Nl HUMU~ H
__l AIJIIIENIICATION
I]
>XOM
Pl
tru
------- - - - - - - -
PAtH
OJ!
Wli~IIfYING
llifVISJON
-,-::----=(>ATE 6-26-UO I
llfV AU Ill NO.
tllfEI 1
Of
4 SIIHf$
IWMlNCtAlUH( OH ()[SCHIPIION
NliMULH
--·---·---1------1----1
116
Qf't
RQO
NO
rd. 9
SCJK-85
HicrocomlJuter l.Jevelopmcot K1t
) ,4
141.530
3,4
74LSo4
ll~:x
2
741JU
Qu•d. 2-lupul flus. ANU Gate
11-lu~ut ~ositlve
NAND Gate
Inverter
IJ5
2
/432
IJI
3
14112
lA
3
IU25J
Prog. lu tl::rv..~ l 1 iu~~.:r-
64
4
18259
hoy. lnlerrllJll Cunli'Oiler
C2
3
1474
Oll
Uual 0 fdye Triy. f/f's
)fi .. J'iu
l__J__t__...L.___J______J _ _ _ _ L____
Gate
llua l J-K Ney. [dye l r19. f /f' s
15 kcsbtors IK oh01
L---------'------------------.J
f,W ~~~::~~~~~:-::~~~';~U lllC
U1
t.D
c--·---
I
PAHTS LIST
liS! fiTI E:
·-rNTRACf~fSCM NO
~
~IITIIHiliCATION
I)Afl
JflEVAIJTii NO
-
Aua log Input Uoa.nJ
ill:M OH
fiNO
arvQO
Ql¥
RQO
NUMlll:H
c - - - 1-----
Ql¥
RQD
urm
Of
Ml:ASUHt
-----
CUOt.
lOt til
r--- - - ---- - -
---Of< AWING
PAll[
IUl NIH VING NUMU£U
on
C6
I
6
CIO
Ul
1
6
Oat Si"u-IC1
U4
l
1
l
2
2
2
6
6
6
6
6
6
AUC-fiiUUl
I
2
1
2
1
I
I
1
I
l
5
C7
05
AI
Ab
U5
C/
oc
04, U3
Co
C5
C4
C4
Cl
C2
Cl
5
5
5
5
5
5
5
5
5
RIO
Rll
7404
14lSIJJ
18212
Cl
l2
l4. l6
C2
C3
C4
cs
C6
()
Ill
r·m
Of
NOMI'NCI Allllll OR lltSCHII'IION
Oil
!
5-10-80
Q
-
UUCUMlNJ NUMUtH
A
I:EVISION
LTH
IPL
2
I
~HtTI·s:
I
!
IKpf
Sample
Hold module
dUd
A-0 t.:onvertcr
lOOK 20 turn tl'iuo pot
lOOK 20 turn trim pot
llex lnv~rtcr
ll-lnput Pos. NAIIO Gate
8-~it l•tch
~-mlc•·ofarad
(mf)
2 llcou·y (II)
1.511
0. 205 mf
2. 7 ouf
mf
l
2. 4 ouf
0. I ouf
I. bU 111f
1K oluu
)/4 Wdll
(ijJ ~~~~:~~ ,:·:~~l'I;:~~H IN!;
en
0
,-------·
I
PARTS liST
liST Till L
Aualo~
IJLM UH
FINil
NuMtU:H
QIY
RQO
02
C2
Cl
C6
QIY
RQO
2
I
1
1
1
1
1
82
83
1
1
U4, 86
I
I
I
I
1
I
I
1
BJ
84
85
B6
B7
U7
!:£VISION A
IPl
] AIJTtltNliCAliON,
ll~
llATt
I REV AUltl NO.
QIY
RQO
UNII"
Of
Mt.ASUUf
5-10-80
riEH
Of
l
4 SIIHIS
COU£
IClENT
-r--- - - -
A7
85
64
tSCM NO
Output Bo•rd
1 - --Ill
ICON i"RACl NO.
3
OR
PAHI
Oil
OUCUMl Nl NUMU(U
Jl)fNIU·YING NUMUt"H
OHAWING
7
7
7
7
HIO, ltl3
Rll
lt12
!lAC 29UIJ 1
1
IU212
7
7
741504
74lSllJ
8
Cl
l2
8
8
8
8
8
8
8
8
0
l4. l.b
C2
C3
C4
C5
C6
C7
R7
NOM£NCIAIUHf. OH
OESCIII~IION
IOU ~
20 turn trim pot
4.7 M ohm
1 111 olno
8-~it 0-A COIIV~rter
8-l>ll Ia tclo
l~x invert~r
13-lnput PosItive NAND Gate
2 ouf
2 II
l.b II
0. 2U5 onf
2. 7 onf
1 mf
2.4 mf
0. 7 mf
1.58 mf
IK oluu 1/4 wall
I
i
I
I
'---
iJI) ~::;::~;, ~~~~~·~~~~.~j, IHG
en
L_
4_ _ _ _ _ _ _ _ _ _ _
PARTS LIST
liSl'IIILL
.
IILM OU
FINO
NUMI3lH
rNIRACl
~~~CM NO
==rUIIIHIJil:ATlON
I:EVISION A
l fll 5-10-80
{)AI[
IPL
.. rEV Alllll NO
rEET4
Of
~
QIY
RQO
QIY
RQCl
QIY
RQD
UNIT
Of
MfASUJcl
t:OU(
lllENl
t----- --- - - - · - - · - - -i -
Of<
OUCUMlN"I NliMUI:.H
SII<EIS
PAll I
UI(AWING
on
NOMfNClAlUUt. OH Of$CUIPIION
lllHIIlfYlNG NllMUfl!
IJ3
3
9, Ill
Hes. P.1k
16-p·in ltl res is tors lK otuu
Uti
4
9, 10
lil~
ll-1> it lo tch
Ill>
I
9, 10
IU~U5
I uut of 8 l>inory decoder
12
0/
I
9, 10
)4L~04
liex 1nvt!rlt!r
Ul
I
9, 10
741510
Triple 3-lnpul Pus. NAND Gote
M
12
IO
11154044
4096 x I Stotic lldm
i
I
i
I
I
I
!
i
I
- - - - - ---- L _ _ _
------
-----
!
--~--------
~-
fli) ~:~~~~~ ,f~?:'~~:::-~" INC
0"'1
N
APPENDIX 5
BACKLANE WIRING TABLE
63
64
Side
fin
1
2
~
,(
32
33
J4
JS
~6
!f
Si2:nal Gen.
ff
( Corr.ponent Side)
1
~
·1
·
~J.2:TI2.
1
Used
Si.t?. Descr.
Ext.
t
T
+5V
+5V
+Sv
Ii
l
I
I
.'
!
l
Intr
Cpu
Cpu
All
Cpu, AIn, t'l~em
Cnu Aout, r::em
- .. I
.Lnc.a
J.0-f;:/
Rd/
T~j,...;
I~ J..
j
ll
65
Side
,,
.?ir1 =
Si,:rnal ·:Je n.
...!J....
:::~{ t
3
Ext.
•
c
E~<:t.
D
'"'"CT.
I
2
if
I
Si,:rnal descr.
·u:sea·
-
-.:::.l';r-n~:
......,
c ..... a.-
All
All
All
'
I
+
+
+
5V
5V
I
'"""'•
II
.....
i
I!
1:.
7
-
b
J
.,
i\
Cpu , Ii.e m, A • I •
...tJ'
... v .
I
\
:
..AJ
'
I
II
l
t
I
!
1
r;.
r:
l
I
I
r
\
R
I
0
,.,..
~
L
I
v
x-m
'}'
l'·~ot
I
I!
u
\
i
v
t
;;::
....
"
!
l
w
A4
A5
A6
A?
A8
A9
A10
All
A12
AlJ
A14
used
All
CpujA. In
ti
b
r
lI
\l .
il
"
AO
Al
A2
t
DO
Dl
i
D2
I
DJ
D4
D5
I
!
l
l
De
~
l
D7
l
~':- ;oU_D
~\ot
- +
..:.X"' •
~
~
\
Used
I'
I
Il
·'
i'\. •
In, .A.• Cut
T
. l l
.~:-\
\
..
_p
r ...... -.
~
Y''i
\
::;nd
Cnd
\
::;nd
.h.~
;.1
Ai.. .. '
-15V
-+1
. -
.4_ tJ
.....
v
I
APPENDIX 6
I/0 PORT DESCRIPTION
66
67
I/0 PORT DESCRIPTION
PORT #
28
78
DESCRIPTION
Timer presets and gate control
Bit - 0
SMPACK
1.
OUTACK
2
Gate
3-7
Not used
Ti""!er
!82~3
counter #0
79
counter #l
7A
counter #2
73
~1ode
FC
control /'JOrd (MCW)
1
Analog input board control
Bit - 1
2
0 -
Hold
1 -
Sample Mode
0 - Start conversion
1 -
3-8
F8
ADC
data
FE
DAC data
no-operation
Not used
(input)
(output)
APPENDIX 7
MEMORY MAPS
68
69
GENERAL MEMORY
~AP
0000
EPROM
#1
-ll
SDK-85 Monitor
\
\
07FF
~---------------------;
0800
.J
l
>=
J
OFFF
1 Audio Delay
Program
6 Subroutines
2000
BASIC RAM
20FF
2800
1
?
\
(- PTRS; CTRS ; UARS
\
Ex pan ion Ram
_/
I
28FF
0000
RAM
9000
l
I
Samp 1ed Data
Storage
+- Bl en
)
!
RAM
·r
Return Address
of Subroutines
FFFF
Top of Stack
70
ME~lORY
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
280A
2808
280C
2800
0000
f---·
f'i'AP #2
LSB
MSB
LSB
-----~---~----~
MSB
"--·-~~Lss·~-
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
BLEN
Sample Frequency
(timO frequency)
Audio Delay Timl
Frequency)
OUTPTR
SMPPTR
EBUF
EBOFl
= BUF
+ 1
BUF
0000 + BLEN
FFFF
= BUF
TOS
+ BLEN
+ BLEN
APPENDIX 8
SOFTWARE FLOWCHARTS
71
72
Flowchal~t
Audio Delay Main Program
Start ./
Call Initialize
l
Call ADC
I
con vert 1 samp 1e
___.1
'----~
J Ou~put _1 sa~2-~~=-1
~
Set Interrupt Mask
-----...···-....----·--·"-···--·-!
[
,---------- . ______1:
l
Enable Interrupts
------~---·--··---·-~
- - -.. ---
--
1
_;Y.:"_ _ _ _
~ ----
Samp 1e Timer -~ Wait for Interrupt
'!
l
_____
Output Timer--?!......_
__
I
__;i
8259 Interrupt Handler
7.;;. ,
Initialize Routine Flowchart
Start
~-Set Expansion RAM
I
I
Command Status register
PA, PC - Output Mode
PB - Input Mode
I
Set outptr
=
smppt r
=
~t-o~ BI=- ___j
I
I
I
I
Call Timer initialize
1
'---·-·--------·-·--·-·-r-
'1!_.- - - --...,
!
Call Priority Encoder
______[ _____
Initialize
,_
f
= BUF
Set EBUF
L
r
I
__)
+ BLEN
-~-B~F~ =t~~:.-':__2
'
I
Return
____ l
·---------·
_J
/
74
Timer Initialize Routine Flowchart
,(
·---
~,
'•,
Start
j
i
J
Set Timer I2253
Mode Control Word
Mode 2 - Rate Generator
Binary Counter 16-bits
Counter
a.:- s~
e
1
F~;~-.;;;;,-;-~
-·----··-r-------~--"-··-·-----·
--.--.. --·---·---· -··-·· --· r... ·-·-··-·-·-------,.
· Counter 1 - Output Frequency
1
·-:=c~~:~~-----l.
Return
'-·-----~---
75
Priority Encoder Initialize Routine Flowchart
/---·--·--······.
"'·
I
.
!·..
--··----
i
·
.~-···-···--
. .- . . .
Star__:__)
--1....-..
~,A·~~----~J
, .
··-·"'~--·-····----- .1•'"- -~.<.--~-·~--"!
Set Priority Encoder 8259
I
l
l
I
ICWl = Step interval 8
Single encoder A5-A]_____ j
l
I
____________z.J[ ___________~
I1
I
I
Set
IC\~2
A8-A15 to start
address of Interrupt
Handler
l
t
----~-- ......
.·...._
Return
____
\:
.......-/
;
75
Interrupt Handler Routine Flowchart
r-------------------·-·--
8259 calls appropriate
rI
subroutine
I
. - -___ __j{
___,_ _ _ __
I,__
Sample Interrupt
I _____,
~--C~-ll.-S-~mp 1e routine
I
·---~
r-
r
1
Output Interrupt
~-----
,
-··_j
[~tr:~-ti~-;~
I
I
~-------··· ---1~----
i
Reset 7474 with Preset
1
l
Port 28 bit 0 Pulse
!L---Port 28
Reset 7474 with preset
Bit 1 Pulse
.-------------~'~
Send EOI to 8259---re_s_e-ts-~
last interrupt of highest
priority
(
Return
\,
--~
77
Sample Routine Flowchart
Start
\
__J. ___/
;
i
- -.)¥___ ---'- .... -.... - ··-1
Smpptr
._
=/=
I
No
________
j
Call ADC
j
Store Sample
_______l _____
~--~--J~~=~~-:~~~--
1
j
Smpptr
= Smpptr
+
L-~------·"·"-·--·. ---~-·--~-~----_;
I
_____
/"
1------;t\\.__
Bl en
.. ~-;--------
~----~\L_
Yes
{;~urn ~I
Return
·,_
./i
78
Output Routine Flowchart
(
~;
Start
--r-1
~
!
Yes
l
~----,.
I
I
I
I
I
I
l
j No
r------·-----*--·-
_______,y____--.
I
Output BUF _Sample
t1___________
__________ y_____. _ _ _ _ _
Outpptr
Sampptr
= BUF
= BUF
l
Output BUF Sample
\
'
i
'
'
!'
I
¥
Outpptr = Outpptr +1
I
I'
----~-----~-_____,!;
····--------~
,
\
Return
\
)
ADC Routine Flowchart
.(
Start
I
Strobe S/H Module
I
....----·-·---·~----~---·~----
1
1
Strobe ADC module
I
J
--~---r··------Wait for conversion
j
r-;:-:____1_____,_________. ~
I
.l.llf-lut 1 sample
- - - -... --.. • r-•.,.,-~____._. __......... ~
-~ ..._~..._,_,.,.. ___._ _ _ _
I
,'-----··-------~--~---- ..--.. ~-----· ..1
ResetS/Hand ADC centrals I
' - - - - - - - - -..··-.. ·-··---------_..;1
~turn
APPENDIX 9
SOFTWARE ASSEMBLY LANGUAGE
80
81
*********************************************************************
Function:
Audio Delay (Main)
Inputs:
Location - 2800 Buffer length (1 sb)
2801 Buffer 1ength (MSB)
2802 Sample Clock (lsb)
2803 Sample Clock (msb)
2804 Output Clock (1sb)
2805 Output Clock (msb)
Outputs:
Ca 11 s:
None
Init, Adc, Dac
Destroys:
Sp
Description:
Audio Delay waits for an interrupt.
outputs one sample.
In addition it
The program is only halted by
pressing the RESET key on the SDK-85 keyboard or by
a power failure.
*********************************************************************
Symbolic
Location
Code
Comments
31FFFF
0800
START: LXI, SP, TOS
CDll 08
CALL IN IT
CDE308
CALL ADC
get 1 sample
D3FE
OUT DAC
and output it
080B
FB
76
OBOE
00
C30B08
L1 :
EI
HLT
NOP
JMP L1
wait for
interrupt
82
*********************************************************************
Function: Init- Initializes ptrs, cons.
Inputs: None
Outputs: None
Calls: Timinit, Picinit
Destroys: A, D, H, L, F/F•s
Description: This routine is used to initialize output ports and
pointers.
*********************************************************************
Location
Code
Symbolic
Comments
0811
3EOD
INIT: MVI A,OD
Set CSR
D328
PA, PC = P8 = Input
Out 28
3E 00
D328
MVI A,OO
OUT 28
2100DO
220628
220828
LXI H, 8UF
SHLD OUTPTE
SHLD SMPPTR
CD 3808
CD 5908
CALL THHN IT
CALL PICINIT
2A0028
E8
210000
LHLD 8LEN
XCHG
LXI H, 8UF
Set smpack, outack,
gate = 0
OUTPTR = 8uf
SMPPTR - 8UF
DE = 8LEN
. 83
-------··----
- -- ---- -------.
-
Location
Code
Symbolic
Comments
DAD D
SHLD EBUF
INX H
Shld EBUFl
RET
HL
0837
19
220A28
23
220C28
C9
= BUF
+ BLEN
84
Function: TIMINIT- Initializes I8253 timer
Inputs: Memory locations - 2806 Outptr
2807 Outptr
2808 Smpptr
2809 Smpptr
Outputs: NONE
Ca 11 s: None
Destroys: A
Description: TIMINIT initializes
rate counter. ClkO
Clkl is used as the
elks are determined
2806 - 2809.
(1sb)
(msb)
(1 sb)
(msb)
the I8259 Timer to act as a binary
is used as the sample clock while
Output elk. The rates of the
by the RAM memory locations
*********************************************************************
Location
Code
0838
3E36
D37B
Symbolic
TIM IN IT:
MVI A,36
OUT 7B
Comments
CtrO MCW.
= Mode
3A0228
0378
LDA SMPFRQ
OUT 78
3A0328
0378
LOA SMPFRQ+ l
OUT 78
ctrO msb
3E76
D37B
MVI A,76
OUT 7B
ctrl MCW
ctr 0 lsb
3
85
···---~-------
Location
0858
-.
.
-- -. ---
-
-
·---
---
·----
Code
Symbolic
Comments
3A0428
0379
LOA AUOOLY
OUT 79
ctrl 1sb
3A0528
0379
LOA AUOOL Y+ 1
OUT 79
ctrl msb
3E07
0328
MVI A,07
C9
RET
OUT 28
enable gate ctrl.
36
********************************************************************
Function: PICINIT- Initializes the I8259 Priority Encoder
Inputs: None
Outputs: None
Calls: None
Destroys: A
Description: PICINIT initializes the I8259 Priority encoder to
handle interrupts from clko and clkl of the I8253
timer chip. Clk) (Sample elk) gets priority over
clkl (output elk). The 8259 is set up for a step
interval of eight with priority encoding of
interrupts.
*********************************************************************
Location
Code
0859
3E92
D38E
3E08
D38F
C9
0861
Symbolic
PICINIT:
MVI
OUT
MVI
OUT
RET
Corrments
A, ICWl
8E
A, IC'W2
SF
87
*********************************************************************
Function:
INTHND - Calls the appropriate subr. and clears the
interrupt
Inputs:
None
Outputs:
Calls:
None
SAMPLE, OUTPUT
Destroys:
A
Description:
INTHND calls the appropriate subroutine depending on
the interrupt, clears the interrupts by presetting
one of the 7474 and then sends an E01 to the 18259.
The 18259 generates a Call to the appropriate address.
********************************************************************
Location
Code
0880
F3
CDA508
C39808
F3
CDBD08
3E05
D32B
3E07
D32B
0887
Symbolic
INTHND:
OUT:
DI
CALL SAMPLE
JMP SA
DI
CALL OUTPUT
MVI A,05
OUT 2B
MVI A,07
OUT 2B
Comments
88
-
Location
--
- --
~--
-------
--
-
Code
Symbolic
3E20
038E
C9
MVI A,20
OUT 8E
RET
0898
3E06
0328
3E07
0328
3E20
D38E
08A4
C9
Sa: MVI
OUT
MVI
OUT
MVI
OUT
RET
A,06
28
A,07
28
A,20
8E
·--
----
- -------
.
Comments
-- -------···
89
********************************************************************
Function: SAMPLE - Stores 1 sample in BUF.
Inputs: None
Outputs: None
Ca 11 s: ADC
Destroys: A, D, H. L, E, F/F's
Description: Sample gets one sample from the A-D converter as
specified by the sample clock. When BUF is full,
no more samples are taken until the OUTPUT routine
resets the SMPPTR.
********************************************************************
Location
Code
08A5
2AOC28
EB
2A0828
7C
BA
C2B408
7D
BB
C8
SAMPLE:
CDE308
A1:
0884
77
Symbolic
LHLD
XCHG
LHLD
MOV
CMP
JNZ
MOV
CMP
RZ
EBUFl
Comments
SMPPTR = EBUFl
SMPPTR
A, H
D
Al
A,L
E
Call ADC
MOV M,A
Store sample
90
Location
08BC
Code
Symbolic
23
220828
INX
SHLD SMPPTR
C9
ret
Comments
H
SMPPTR =
SMPPTR +1
91
********************************************************************
Function: OUTPUT- Outputs samples stored in BUF
Inputs: None
Outputs: A - sample stored in BUF
Calls: None
Destroys: A, H, L, M, F/F•s
Description: OUTPUT outputs the samples in BUF one at a time each
time the output clkl interrupts the CPU. When BUF
has been emptied the ptrs OUTPPTR and SMPPTR are
reset to point to the start of BUF.
********************************************************************
Location
Code
0880
2A0628
3AOA28
80
C2DB08
3AOB28
BC
C2Db08
7E
03FE
210000
220628
Symbolic
OUTPUT:
LHLD
LOA
CMP
JNZ
LOA
CMP
JNZ
MOV
OUT
LX I
SHLD
OUTPPTR
EBUF
L
Al
EBUF+l
H
Al
A,M
DAC
H,BUF reset
OUTPPTR
Comments
OUTPPTR = EBUF
Out sample
ptr to start
of BUF
92
Location
08DB
08E2
Code
Symbolic
220828
C9
SHLD SMPPTR
RET
7E
03FE
23
220628
1"0
'-'-'
Al:
MOV
OUT
INX
SHLD
RET
A,M
DAC
H
OUTPPTR
Comments
output sample
93
********************************************************************
Function: ADC - Gets one sample from A-D converter
Inputs: None
Outputs: A - Sample of input waveform
Calls: None
Destroys: A,B
Description: ADC gets one sample from the Analog Input board by
pulsing the Sample and Hold module and then pulsing
the A-D converter.
********************************************************************
Location
Code
08E3
3E02
D3FC
3EOO
D3FC
00
00
DBF8
47
3EFF
D3FC
78
08F5
C9
Symbolic
ADC:
OUT
Comments
MVI A,2
strob S/H module
A,CTRL
MVI A,O
strobe ADC
OUT A,CTRL
NOP
wait for conversion
NOP
IN ADC
get 1 sample
MOV B,A
reinit. S/H
MVI A,FF
OUT A,CTRL
~10V A,B
RET