CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
HARDWARE
IMPLEMENTATION
CONTROLLED
COMBINATIONAL
OF
A
COMPUTER
CIRCUIT
TESTER
USING SYNDROME TESTING METHOD
A project submitted in partial satisfaction
of the requirements for the degree of
Master of Science in
Engineering
by
Vigen Edward Babayan
January 1987
The Graduate Project of Vigen E. Babayan is approved:
Prof. Astrid Gautier Levine
Prof.
Prof. Mohammad Roosta
Committee Chair
California State University, Northridge
ii
I'
TABLE OF CONTENTS
LIST OF TABLES
v
LIST OF FIGURES
v
vi
ABSTRACT
CHAPTER
1.
2.
3.
4.
5.
INTRODUCTION
1
1.
Introdution
1
2.
Testing
2
3.
Syndrome testing
4
OVERALL VIEW OF THE IMPLEMENTATION
7
1.
Tester board
7
2.
Block diagram of the tester
8
3.
Host computer program
11
INTERFACING THE TESTER BOARD WITH
HOST COMPUTER
13
HARDWARE DESCRIPTION
22
1.
Components of the block diagram
22
2.
How the board works
29
TEST CLOCK
31
1.
Description
31
2.
Implementation of test clock
32
6. CONCLUSION
35
iii
•
REFERENCES
36
APPENDIX
38
A.
Program Listing
38
B.
Memory Map of APPLE II+
44
iv
LIST OF TABLES
Table
1.
Peripheral Connector Signal Description
16
LIST OF FIGURES
Figure
1.
Block diagram
10
2.
APPLE's Peripherial Connector Pinout
15
3.
Tester board schematic diagram, part 1
25
4.
Tester board schematic diagram, part 2
26
5.
Tester board schematic diagram, part 3
27
6.
Tester board .schematic diagram, part 4
28
7.
Test clock schematic diagram
34
v
ABSTRACT
HARDWARE
IMPLEMENTATION
CONTROLLED COMBINATIONAL
USING
SYNDROME
OF
A
CIRCUIT
COMPUTER
TESTER
TESTING METHOD
by
Vigen Edward Babayan
Master of Science in Engineering
The objective of this project is to design and
build
a circuit that will test combinational circuits under
supervision of a computer.
The
testing procedure will be handled by the
tester
board using the syndrome testing method [6].
The
computer will serve as an input/output device to
the
user and will store necessary information
the circuit under test.
vi
about
CHAPTER ONE
INTRODUCTION
1. Introduction
The
"TESTER BOARD" is designed to test combinational
circuits under control of a "host computer"
(in
this
case an APPLE II+).
The
host
computer
is
used
only
necessary information like number of
of
outputs,
and
also to serve as
to
supply
inputs,
an
the
number
input/output
device for the user. In other words the host computer
.is not involved in the actual testing process,
which
is all done by the tester board itself.
All
circuits are tested at their speed of
which
may be as high as tens of MHz.
operation
Microcomputers
are based on CMOS technology which have a cycle
of
only a few MHz.
takes
more
than
Since each instruction
one
cycle,
directly by the microcomputer,
if we
usually
to
the test speed
have been reduced to about 100 KHz.
1
were
time
test
would
2
2. Testing
Integrated-circuit technology has evolved from largescale to very-large-scale integration. Gate densities
are
increasing
decreases
in
performance.
solved
by
factors
gate
costs
However,
a
of 3 to
and
problem
along
5
with
improvements
never
in
adequately
for large-scaled-integration (LSI)
is
still
with us, and it is getting much worse: the problem of
determining,
component,
in
a
cost-effective
module,
or
way,
board has been
whether
a
manufactured
correctly.
The
testing problem has two major factors:
generation
and (2) fault simulation.
the ability to
(1) test
With the
vast
generate
test
increase
in density,
patterns
automatically and conduct fault simulations
on them has drastically waned.
Classical testing of combinational circuits
a
requires
list of the fault-free responses of the circuit to
the test set. For most practical circuits implemented
today,
the large storage requirement for such a list
makes such a test procedure very expensive. Moreover,
the
computational
cost
to generate
the
test
set
3
increases exponentially with the circuit size.
In this project we are using a testing procedure that
requires the knowledge of only one characteristic
the
This
fault-free
circuit,
procedure,
procedures,
does
unlike
called the
most
of
syndrome
other
generation,
thus
[6].
testing
not have any storage problem.
syndrome-test procedure does not require test
eliminating
expensive
generation and fault simulation stages.
of
The
vector
test
4
3. Syndrome testing
Syndrome testing is a method of testing combinational
circuits with a single stuck-at-fault.
Single stuck-
at-fault is the most common fault and it is very rare
that a multiple stuck-at-fault may occur.
The
syndrome
ratio
of
(S) of a function is
as
the
the number of minterms (K) divided by
the
number of all input combinations.
defined
Thus for a circuit
with n inputs:
K
s =
n
2
Since
syndrome
is
a
property
of
function,
the
different realizations of the same function will have
the same syndrome.
Furthermore,
have
a
a
faulty
different
circuit,
unless
circuit may not
necessarily
the
fault-free
syndrome
it
is
than
designed
to
be
syndrome
testable.
A
syndrome
single
syndrome
testable circuit is one that
stuck-at-fault
will
provide
than the fault-free circuit.
a
under
any
different
I
.
5
has
It
been
that
combinational
irredundant
OR,
determined
NAND,
NOR
and
every
fanout-free
circuit composed of
inverter
gates
is
AND,
syndrome
testable.
Using
the XOR gates usually can cause
problems
for
syndrome testing, since they could imply reconvergent
fanout.
This problem, however, can be resolved by using extra
gates
that will not change the functionality of
the
circuit, but will make it syndrome testable.
Further informations on syndrome testing and syndrome
testable
designs
can
be found
in
references
[1)
through [4).
Syndrome
testing
generation
thus,
requirements.
or
does
not
require
test
eliminates large storage
vector
capacity
Also, it is independant of complexity
characteristic of the combinational circuit since
modular testing of the circuit is possible.
On the other hand syndrome testing is limited to only
combinational
than
twenty
combinations
However,
the
the
For circuits
input lines,
requires
generation of
unreasonably
having
more
all
input
long
time.
this problem can be overcome by subdividing
circuit
drawback
circuits.
into
smaller
modules.
of this method is that it can
The
only
biggest
detect
presence of a fault and is not capable to locate
6
the fault.
CHAPTER 2
OVERALL VIEW OF THE IMPLEMENTATION
1. Tester board
The
tester
board is capable to
test
combinational
circuits up to eleven inputs and eight outputs.
It
the
will
receive all the necessary information
host
(number
displayed
computer and will send
of
minterms)
to the host
on the screen.
the
test
computer
from
results
to
The interpretation of
results will be done by the host computer.
7
be
the
8
2. Block diagram of the tester
Refer to FIG. 1 for the following discussion.
The board consists of:
a)
A
12-bit counter (COUNTER1) and a fast clock
to generate all the input combinations at the
actual
working
speed of the
Circuit
Under
Test (C.U.T.).
b)
An 8-bit register (REGISTER1),
6
bits
are
used
to control
of \vhich only
two
8
to
1
multiplexors (MUX1 and MUX2). MUX2 is used to
monitor
time.
the
at
a
MUX1 is used to monitor the last input
combination
will
value of each output one
(end of i-th output
test),
inhibit COUNTER1 and provide
the
and
DONE
signal for host computer through a 1-bit tristate buffer (TRI-STATEl).
c)
A
1-bit
flip/flop
(COUNT CONTROL
F/F)
to
enable and disable the counting of COUNTERl.
9
d)
An
11-bit counter (COUNTER2) to count number
of minterms generated by the C.U.T.
e)
An
11-bit tri-state buffer
TRI-STATE3)
to
(TRI-STATE2
provide the readout
of
and
the
number of minterms for the host computer.
f)
A
3-line
to
8-line decoder as
an
address
decoder for addressing all above devices.
NOTE: All
devices
used
provide high speeds.
in
the board
are
TTL
to
TEST
CLOCK
f
+
1
c
c
c.
0
u
'"Ij
I-'·
lQ
J::
t1
ro
I-'
N
T
E
R
1
1-
u.
r---
3
s
0
u
M
inputs)
..-
outputs)
u
~
X
2
T.
~
N
T
E
R
minter~
T
A
T
E
coun~
H
0
2&3
.....___
2
s
T
c
tJj
f-'
ADDRESS K address lines
DECODER
0
()
M
X'
u
p,
inputs>
I-'·
OJ
lQ
t1
OJ
,..--
M
p
u
X
1
0
<select lines
select lines
I
3
I
REGISTER1
< data
T
E
R
lines
DONE
l
COUNT CONTRor,_!/ F
J
START
-
I-'
0
11
3. Host computer program
Since for all practical purposes of this tester,
speed
of the host computer program is not
anymore,
the
an
the
issue
program is written in BASIC instead of
assembly language.
Any
user
of
combinational
various
first
the tester may have several
circuits
of inputs I
numbers
starts
to
be
tested,
outputs.
by asking the user
going to be tested,
types
each
The
which
of
with
program
circuit
is
at which point a number shall be
entered to indicate circuit identification number.
The
program
information,
along
will
will
such
then
print
the
all
as number of inputs
and
with number of minterms for each
prompt
the
user to press a key to
board
outputs
output,
and
start
the
testing.
The
program
will
test each
output
separately
by
loading a value corresponding to the number of inputs
and
the output under test in a certain
the
tester board,
test each output,
register
on
and let the tester board start to
one at a time by
issuing a
START
signal. The tester board will inform the program when
~
.
12
testing
of that particular output is
completed,
by
issuing a signal called DONE.
After receiving the DONE signal for each output,
program
will
read
the number of minterms
of
the
that
output from designated counters on the board, display
it on the screen and compare with the value
by
the program for a fault-free output .
provided
The result
will then flash on the screen.
This process is repeated for each output of
C.U.T.
Appendix A contains the program listing.
NOTE:
The
necessary
circuit
information for each
must be provided by
the
type
user,
of
only
once. These values are: circuit identification
number,
number of inputs,
number of outputs,
and number of minterms for each output.
CHAPTER 3
INTERFACING
THE
TESTER
BOARD
WITH
THE
HOST
COMPUTER
The
host
II+
computer used in this project is an
APPLE
which in this project will be referred to
as
APPLE.
The
APPLE is a 6502-based microcomputer and does not
have
any built-in ready-to-use I/O
eight
full
50-pin connectors (FIG.
16-bit address bus,
ports,
but
has
2) each providing
a
an 8-bit data bus and some
control lines (TABLE 1).
As far as the tester board hardware· is concerned,
can
he
plugged in to any
unused
connector
it
except
connector #0 (an APPLE restriction). For this purpose
connector
#3
was selected and control software
was
written based on this connector address location.
In
memory map of the APPLE (appendix B),
are devoted to each connector.
at
hex
(base 16)
256
bytes
Each connector starts
address $Cn00 and ends
at
$CnFF
where "n" denotes the connector number ranging from 0
to
7 (total of eight).
Therefore connector
13
#3
is
14
addressable from $C300 through $C3FF, inclusive.
Among
control lines provided in each connector there
is a line called I/0 SELECT.
in
each
connector
location
is
connector.
between
and is activated
addressed
For
$C300
This line is
example,
within
any
different
every
that
location
and $C3FF will cause the
time
a
particular
addressed
I/0
line in, and only in, connector #3 to go low.
SELECT
15
GNO
O~.IA
IN
iNT
::'J
N~M
liiQ
<I
20
29
Jo
2G 5'-1 .:••23
L...; ::= 122
c: :::J I 21
~sv
c~.1A
our
11,JT OUT
uT.iii
ROY
31
32
qbj;:o
LJ
·~0
34
35
36
37
38
39
40
DEVICE SELECT
07
41
;:J
:a
J"
r-"'
9
a
Al
AG
JJjC:::I--J
7
t\5
6
5
A4
A3
4
A2
3
AI
AO
RES
f~jH
-12V
-sv
N.C.
7M
03
·~1
USER 1
o.:;
05
04
03
Q2
01
DO
+12V
Figure 2
J~t
0
C'
331Cc1 El
1
G :::J 1
C::iwl
C:::!CJ,
C1lr.l
D!t=
etc
c::: I
a
J;! §j
45
q
4o
CJ
2~
d
f:::;
41
48
~
.........l
"~
,,,~1
19
18
1."
16
T.S
14
13
12
TT
2
1/0 STAOBE
N.C.
R/W
A•·,.J
A14
A13
A12
All
AlO
A9
A
a
170SELECT
APPLE's Peripheral Connector Pinout.
16
Table 1
Peripheral Connector Signal Description.
~==========~~~=====~
Dcscnpuon:
=---This line. nornwlly high. will become low when
the microprnce~sor references page SC 11. where
n is the individual slot number. This signal
becomes active during <1>0 and will dri\·e I 0
LSTTL loads*. This signal is not present on
peripheral connector 0.
2-17
A0-A15
The buffered addres~ bus. The address on
these lines becomes valid Juring 'I> I and
remains valid through <Nl. These lines will
each drive 5 LSTTL loads*.
18
R/W
Ouffered Read/Write signal. This becomes
valid at the same time the ac.ldre~s bus does.
and goes high during a read cycle ;md low during a write. This line can drive up to 2 LSTTL
loads•.
19
SYNC
t)n peripheral connector 7 onll•. thi~ pin is connected to the video timing gener:llor's SYNC
signal.
l/0 STROOE
This line goes low during <1>0 when the address
bus contains an atltlre~s between SC3111l and
SCFFF. This line will drive 4 Lsn·l loads*.
RDY
The 6502's RDY input. Pulling this line low
during r!Jl "ill halt the microprocessor. with the
adtln:ss bus holding the atltlres~ of the current
location being fetched.
I iO
Ii
I
21
Pulling this line low disables the 6.'02's address
bus and halts the microprocessor. This line is
held high by a JK!l resistor to +5v.
23
INT OUT
Daisy·chaincd interrupt output to lower priority
dr:vicl's. This pin is usually connected to pin 28
(INTlNJ.
24
OMA OUT
Daisy-chained DMA output to lower priority
devices. This pin is usually connected to flin 22
(D~lA
. 26
JNl.
+5v
+ 5 volt power supply. 500mA cur rent is available for all peripheral cards .
GND
Svstem electrical ground.
I
I
Table 1 (continued).
r;;~:==~=:-=~~;~::::fi\ input from high:~~:i:l
dcvi~es.
OUT).
i
I
I
28
!NT IN
I
129
·NMI
,
I
i
I
I
Dai~y-chamcd
priority devices.
UNT OUTJ.
1
interrupt input from higher
U:;ually connecteli to rill 2.1
Non-~faskanl.::
I
!j
I
lntcrn:pt. When this line is
rullcd low th.:: Apple b~gins an interrupt cvdr I
and jumr~ to the interrupt handling wutinc.: at
location S3fl!.
\
I
1
II
Usually C\>nnected to pm 24 (DM:\
~()
IRQ
I
II
! 31
RES
I
I13~•
!
imcrrupi RcQuc~l. When this lin.:: is pulled I
low the .-\Jlpi..: b<'!_'ins an interrupt q de only 1f /
!he o502's ( llnterrupt disable) llag is not SCI. !
If so. the 6502 "ill jump to the interrupt h••n- j
dling subroutine "IH,.,e addc.:~s !s stored in i
locations SJfE ami SJfF.
i~
microproces~or
When this line
pulled low tl;e
begins a RESET ..:\"L·Ic t -;ce P<lt!C .16i.
i
1
j
When tl,is line is ;lUlled low. all R0\1s on the i
Appic bq;,rd ,If.; dt~,,bl·:rl. This line is hc!d hi!;il
by a J K !l rcsi~tor to + 5v.
(
i
I
IJJ
-12v
-12 volt p(lwcr o;uppl\·. :\I.1XI11um current is
200mA for all rcrrpilt'ral boards.
iI J4
-5v
-5 volt power o;urrly. \l;,ximum curtcnt
200m:\ fur Jli t'eripilcral boards.
COLOR REF
On r~riphnal c:o~ncc:tor 7 onh·, this pin is con-,
nccted to the J.J~IIlz COLOR REFcren'e stgn.l! ol the video generator.
I
I"
I
I
136
i~
Thi~
7M
7M llz rlock.
lint> will dri\'c 2 LSTTL
QJ
2:\.1117 asymmetrical cio(k. This line will drive
2 LSTTL load:;•.
I
I J7
I
38
L_
•I> I
USER I
Microprocessor·~ phase one clock.
·will drive 2 LSTrL loaus•.
!'his line
This line. when pu~led low, disables all intcrn,ll
110 address decoding••.
II
J
I
I
i
@ •
18
Table 1 (continued) •
Name:
<1>0
141
DEVICE
SELECT
I
Description:
Microp~ocessor's
phase zero clock.
will drive 2 LSTTL loads•.
This line
This line bcce>mes active (low) on each pt=ripheral connector when the address bus is holding an address between SC0n'.1 and SC0nf'.l
where 11 is the slot number plus S8. This line
will drive I 0 LSTTL loads•.
I
142-49
00-07
BuiTcred bidirectional data bus. The data on
this line becomes valid 300nS into •1>11 on a
write cycle. and should be stable no less than
I OOns before the end of <!>0 on a read cycle.
Each data line can drive one LSTTL load.
+12v
+ 12 volt power supply. This c;;n supply up to
250mA total for all peripheral cards.
I
I
\so
19
To interface the tester board, the I/0 SELECT line of
connector #3 is connected to the chip select pins
the
on-board
lines
(AO,
decoder,
A1
and
and the 3 least
A2)
of
the
of
significant
address
bus
are
connected to the input pins (A, B, C) of the decoder.
This
will provide access for APPLE to different
board
devices
to
perform
different
functions
onas
follow:
Each time the following locations are
corresponding function(s)
addressed, the
will be performed:
LOCATION
FUNCTION
HEX
DECIMAL
$C300 ·
-15616
Set the output of the COUNT
CONTROL F/F to 1 to
enable
COUNTER1 as long as all the
input combinations have not
been· generated.
$C301
-15615
Reset
the output of
COUNT
CONTROL F/F to 0 to inhibit
COUNTER1.
20
LOCATION
FUNCTION
HEX
$C302
DECIMAL
-15614
Pull TRI-STATE1 control pin
LO to read the value on the
output
of MUX1 to
testing
DONE
$C303
-15613
is
over
see
if
{monitor
signal).
Generate
a
single
clock
pulse for REGISTER1 to load
the
register with
encoded
information from the
APPLE
data bus.
$C304
-15612
Clear COUNTER1.
$C305
-15611
Clear COUNTER2.
$C306
. -15610
Pull
pins
order
TRI-STATE2
LO
control
to read the
byte of the
low-
content
of COUNTER2.
$C307
-15609
Pull TRI-STATE3 control pin
LO, to read high-order byte
of COUNTER2.
21
NOTES:
1-
The
hexadecimal
interest
but
address
values
are
of
from the hardware point of view,
in
BASIC
language
programming
the
equivalent decimal values must be used.
2-
The minus sign in front of the the decimal
address
values
APPLE's
BASIC
interprets
it
translator
the
(decimal).
most
are due to
The
addresses
the
way
the
(APPLESOFT)
above
32767
APPLESOFT interprets
the
significant address bit (A15) as
is
a sign bit.
So any address
that
is less than or equal to 32767
have
A15
positive
=
0 and will be regarded
address,
that will set A15
if
value
will
as
a
and any address beyond
= 1 and will be regarded
as a negative address.
CHAPTER 4
HARDWARE DESCRIPTION
1. Components of the block diagram
The block diagram was explained in chapter 2. In this
chapter
detail.
the
components
Refer
to
will be discussed
FIGs.
3
to
6
for
in
more
following
discussion.
a)
COUNTER1
is
cascaded by three
edge-triggered
synchronous
74161,
counters,
4-bit
all
of
them clocked by the same testing clock.
Each 74161 has:
i.
2 count-enable pins which both should be
HI to enable counting.
ii.
RCO
output that goes HI only when all
output pins are HI.
This pin is provided
for cascading counters together.
22
4
23
iii.
The
An asynchronous CLEAR pin.
way that 74161-s must be cascaded is
that
any higher order stage must be enabled by RCO-s
of all previous stages (AND operation).
b)
REGISTER1
is a
74374
positive-edge-triggered
octal D flip-flop.
This register is not clocked by the test clock,
but
by
DECODER1 only once during each
output
test. The reason is that it should maintain the
same information during the test.
c)
COUNT CONTROL FLIP-FLOP is 1/2 of 7476 dual J-K
F-F with preset and clear.
Only the PRESET and
CLEAR inputs are used to change the Q output by
DECODER1.
COUNTER2
is
COUNTER1.
But
cascaded
it
in
the
is enabled
same
only
way
when
as
the
output under test is "1", so that it will count
the number of minterms.
e)
TRI-STATE2 and TRI-STATE3 are both 74240
octal
buffers with 3-state outputs, but in the latter
only 3 bits are used.
24
f)
DECODER1
but
only
is a 74154 4-line to 16-line decoder,
8
outputs are
used.
The
extra
outputs are reserved for future expansion.
8
25
I
~sv ~"t:IC7
.,.sv
fs 74LS76
t,~
VcG
z
23 A
Yo
y,
At 3
A2 4
2t 8
Yz
Aj ~
ICl
Y4
74LS154fs
18 -DecoderG,
Y6
Ao
-I/O SEl.
I
'ZI
c
zo 0
Iii Gi.
~
-
I
2
.3
4
~
PI?E
I
I
I
I
Vu.
Q IS
~
c"ZR
GND
~13
6
7
y1 ~
GNO
~z
/'I
ii
>, II
JlziC3
74LS240
APPLE
COMPUTER
I
II
'----
Cl..l<
Oo
~.,
o,
48
Ol.
47
3 ID
4 lO
z
s
tQ
7 3D
3Q
03
4'-
8
Oq
4S
13
os
~4
lt-D
50
l'f &;.D
IQ
IC14
~Q
74L~374
5Q
Reglster
~o
Oc
t
Figure 3
'I
61>10
~0
Tester board schematic diagram part 1.
" '
26
+tV
'"
~ICll
lice.
74LS08
I
I~
1..0
,,0
T
~ ~Ct.X IC4
7
3
I
I
Qa
74LS161
Counter
P
()A 14
UR
13
IZ.
Gc.
Go II
RC.O IS
GNO
is
rfY
'"
lfcc
~
Itt
t.O
Ito
T
14
I
-
~ I>CLk"
ICS
,.2. P 74LS161
13
IZ
I
,_..
I
1-- Ct.,R
-
"
Counter
M
GNO
+-5V
'"
lice
,.,
U>
-i!
,__:r_
p
,__!_ C.C.R
4
"-r;;
[10
7
...!. ~Cl.K
'--
I
QA
14
Qs /3
IC6
Qc
74LS161
Counter Qo
12.
II
GNO
~
Figure 4
Tester board schematic diagram part 2.
27
I
L----z--11 o
Yzrc18
I,
Zz
13
3
02
c. 03
e
14
Is- u. 04
17
la
I
lq
o,
y 5
D~
03
14
07
Dt;
13 Dftl
08
12 07
Ito
IC13
74LS151
Mux
G
8
A
Io
l-4
o,
15 0
4
0!{
T.
74LS74
4 Do
o,
1~
~~~--~~------
ct. I(
II
-
6ND
C
10 <f
L
~
...
-Do
-- -I
o,
- -L-
--1 - 0-z
-- 1 - 03
04
IC12
74LS151
Mux
w~
o5·
0(t,
o,
G ]_
C,ND
A 6
-
,§..
c
T' ror
I I I
'
I I
--'I
Figure 5
Tester board schematic diagram part
3.
28
--
1-
+fiV
-
tt.?
1/cc.
'q
LD
Q,. 14
Qs 13
~ t-cLKrcs
74LS161 Qc
~
,..19 r Counter Qo
RCO
,....!
~
CZR
- - -
,_z p
It
lh
/I
15
Vee
~ ,,,1(
~
-
,...1. p
T
'Z
I...7
L
LO
I
sft:
l'l..
I I
T
oe
Gc;.
UR
o,
47 De
4"
D~
APPLE
COMPUTER
45
.,'t
I
I I 44
I I
I I I
4~
4l.
04
Os
Or;,
D7
l'l
8
QA
74LS161
Oo
~c 1
L~
110
!>Ct.K IC 10
p
/4
rLL- l_!!.f<t: s
oo ~ ,_aft ~
~B
I<J
f:(
Qc
f
I'Vc.c
t!t!J
~ I__!!_
os ~ I-Ll!<(
GN:co~
+SV
I~
QA
IC9
74LS161
t-- ,..1. Ct.R
4(!(
IC2
74LS240
,,0
LD
4'J
I
4-8
l'f
18
~
GNO
~tv
?[',..
14
/3
IZ
1(,,
I 4~~
I Go!<( 14
V'
1
~C3
74LS240
GNO
~8
Figure 6
Tester board schematic part 4.
29
2. How the board works
When the test starts, the following takes place:
a)
COUNT
CONTROL
F-F
is reset
to
prevent
the
counting of COUNTER1.
b)
Both
COUNTER1
and
COUNTER2
are
cleared.
REGISTER1 contains an encoded value to:
MUX1
monitor that
that
will be "1" after all input
are generated,
particular bit of
1)
let
COUNTER1
combinations
and 2) to let MUX2 monitor
any
output that is to be tested during this cycle.
c)
At
this time the COUNT CONTROL F-F
testing
starts.
Each
clock
pulse
sets,
and
will
now
generate the.next input combination.
The very first combination is 00 •.. 01 and
up
11 ••• 11;
to
00 .•. 00
HI.
then
the last one
goes
which
is
will make the next bit of COUNTERl
go
This is the bit that MUX2 is
monitoring;
its output will go LO and will freeze COUNTERl,
and stay LO until furthur command from the host
30
computer.
During
the
period) ,
time
that
COUNTERl
runs
(test
MUX2 is monitoring a specified C.U.T.
output
and
output
is
enables
"1"
output is "0".
COUNTER2
and disables it
whenever
whenever
that
the
CHAPTER 5
TEST CLOCK
1. Description
The
test clock,
which so far was referred to as the
clock, is a variable speed square wave generator. The
clock
speed
provide
under
is controlled by the host
reasonable
test.
speeds
for
Depending on the
computer
different
application,
to
circuits
testing
speed could be chosen by the host computer to be
one
of the following values:
1 MHz,
500 KH2, 250 KHz, 125 KHz, 60 KHz, 30 KHz,
15 KHz and 7 KHz.
31
32
2. Implementation of TESTING CLOCK
The
schematic diagram of the testing clock is
in FIG. 7. It is composed of a 1MHz
shown
clock built from
3 TTL inverter gates (part of IC1 74LS04).
Output of
the 1MHz clock is used to drive an 8-bit counter (IC2
and IC3:
TWO 4-bit counters 74ls169 in cascade). The
output
pins
speed
clocks,
lower
each half the speed of
significant
significan~
its
of the counters will produce
bit.
For
different
its
example
adjacent
the
least
bit will provide a speed of 500 KHz,
and
adjacent higher-order bit will provide a 125 KHz
clock pulse, and so forth.
The
original 1MHz
produ~ed
by
multiplexor
the
clock
tester
are
are
fed
to
an
8-to-1
one
of
ratings to become the test clock for
connected
from
counters
(IC4 74LS151) which will select
board.
74LS374)
The select lines of this
to
an 8-bit D
type
which will contain a certain
the
multiplexor
flip-flop
value
(IC5
loaded
the host computer at address -15608 during
entire
the
the
clock pulse and the next 7 clocks
test procedure.
This value is determined
host computer and loaded in the register when
the
by
a
33
circuit under test number is inputted by the user.
34
/'Z 07
+5V
~
IK
q
1/1•
lte IC1 1.. Go4 Rl
~c,
y
U/D
t..O
Cl.l<
IC2
74LS169
Counter
Rz.
rI •"'V\rvv
o.ool)'lr
I
ozo 51.
-
p
T
-
TEST
CLOCK
RCO
15
IC4
74LS151
Mux
"
'I
r ""'"s___
II
Qo r----.!...f'
D3
,,
+S~
l/4
13 Dh
13
t=---__.:..;;14~05"
Qa
1Syo4
12
Qc ~--~
QA
U/li P T
t.O
~>CLK
IC3
74LS169
Counter
"A ,_14..:........._ _
Qs 13
Qc I'Z
....;-e;,.; D~:.
3 0,
4 Oo
A 8
6NO
II
! +SV
fzo
APPLE
COMPUTER
Do 49
o, 48
Dz
47
3 o,
4 De
1
OJ
Vee
1&/
z
ZQ 5
res
3Q
"
74LS374
Register
oc
GND
Cl.K
~I
II
From tester board decoder
IC1, pin 11 line Y10 ~-----'
Figure 7
Test clock schematic diagram.
t:;
10
'f
CHAPTER 6
CONCLUSION
Syndrome
testing
procedure
combinational circuits.
to
was
employed
to
test
A tester board was designed
carry out the syndrome procedure on circuits with
up to 11 inputs and 8 outputs.
the
tester board,
In order to
control
an APPLE II+ was used which
also
served as I/O device to user.
Several circuits with various number inputs, outputs,
and
different
operating
speeds
were
tested
many
times, always with correct results.
Syndrome
sense
testing is a very efficient procedure in
that
it
does
not require
generation and storage.
home-computer
(48K)
did
not
any
As a result,
with all speed and
face any
tester board.
35
~emory
problems
test
a
vector
the APPLE II+
limitations
controlling
the
36
REFERENCES
[ 1]
Savir,
J.
"Syndrome-testable
Design
of
Combinational Circuit" in Proc. 9th Annual Int.
Symp.
on Fault-tolerant Computing,
June 1979,
pp. 137-140.
[2]
D.
set
E.
Armstrong, "On finding a nearly minimal
of fault detection test for
combinational
circuits", IEEE Transactions on Computers, Vol.
EC-15, Feb. 1966, pp. 66-67.
[ 3]
P.
K.
Parker
"Probabilistic
Combinational
E.
and
Treatment
Network",
MacCluskey,
J.
of
General
IEEE Transactions
on
Computers, Vol. C-24, June 1975, pp. 668-670.
[ 4]
J.
Hayes,
P.
Function
Number
"On
Requiring
of
Tests",
Realization
of
Boolean
a Minimal or Near
Minimal
IEEE
Transactions
on
Computers, Vol. C-20, Dec. 1971, pp. 1506-1513.
[5]
T. W. Williams and K. P. Parker, "Testing Logic
Network
and Designing for
Oct. 1979.
Testability",
IEEE
37
[6]
J.
Savir,
Combinational
"Syndrome-Testable
Circuits",
Design
of
IEEE Transactions on
Computers, Vol. C-29, No. 6, June 1980.
APPENDIX A
Program Listing
38
39
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
REM ***********************
REM *
*
REM *
SYNDROME TESTER
*
REM *
*
REM *
FOR APLLE
*
REM *
*
REM *
BY
*
REM *
*
REM *
VIGEN E. BABAYAN *
REM *
*
REM *
SEPTEMBER 1986
*
REM *
*
REM ***********************
REM
REM
CARD AT $C300
REM
REM VARIABLES:
REM
REM BN: BORAD NO.
REM NI: NUMBER OF INPUTS
REM NO: NUMBER OF OUTPUTS
REM K(I): NO OF MINTERMS OF
THE I'TH OUTPUT
REM 0: OUTPUT
REM LC: LEAST SIGNIFICANT B
YTE OF COUNTER 2
REM HC: MOST SIGNIFICANT BY
TE OF COUNTER 2
REM CN: CONTENT OF COUNTER
2
270 REM
280 REM
290 REM
300 REM
310 L1 =
STER
320 PS =
--------------------LOCATIONS:
- 15613: REM
LOAD REGI
1
-
15616: REM
330 CL = - 15615:
340 DN = - 15614:
350 C1 = - 15612:
UNTER 1
360 C2 = - 15611:
NTER 2
370 RL = - 15610:
OUNT
380 RH = - 15609:
OUNT
PRESET JK
REM
REM
REM
CLEAR JK
DONE?
CLEAR CO
REM
CLEAR COU
REM
READ LO C
REM
READ Hl C
40
390 REM
400 TEXT
410 REM --------------------420 REM SELECT THE BOARD
430 REM
440 PA = O:FA = 0
450 HOME
460 INPUT "ENTER THE BOARD NO. "
;BN
470 IF BN = 1 THEN 540
' = 2 THEN 590
480 IF BN
490 IF BN = 3 THEN 640
491 IF BN = 4 THEN 681
500 PRINT "INVALID BOARD NO."
510 GOTO 460
520 REM
530 REM ------------------540 REM BOARD NO. 1
550 NI = 10:NO = 2:CR = 7
560 K(1) = 784:K(2) = 576
570 GOTO 700
580 REM ------------------590 REM BOARD NO. 2
600 NI = 9:NO = 2:CR = 6
610 K(1) = 392:K(2) = 192
620 GOTO 700
630 REM ------------------640 REM BOARD NO. 3
650 NI = 9:NO = 2:CR = 5
660 K(1) = 392:K(2) = 237
670 GOTO 700
680 REM ------------------681 REM
BOARD NO. 4
682 NI = 10:NO = 2:CR = 0
683 K(1) = 784:K(2) = 576
684 GOTO 700
685 REM
-------------------690 REM *******************
700 REM TEST ROUTINE
705 POKE CK,CR: REM SET CLOCK R
ATE
710 REM
720 HOME
730 HTAB 10: PRINT "BOARD NO. ";
BN
740 PRINT NI;" INPUTS & "NO" OUT
PUTS";
41
741
742
743
744
745
746
747
748
749
750
760
770
780
790
800
810
820
830
840
850
860
870
880
890
900
910
920
930
940
PRINT
IF CR
"
IF CR
HZ"
IF CR
HZ"
IF CR
HZ"
IF CR
Z"
IF CR
Z"
IF CR
Z"
IF CR
"
"
SPEED: "~
PRINT "1 MHZ
= 7 THEN
= 6 THEN
PRINT "500 K
= 5 THEN
PRINT "250 K
= 4 THEN
PRINT "120 K
= 3 THEN
PRINT "60 KH
= 2 THEN
PRINT "30 KH
=
PRINT "15 KH
1 THEN
=0
THEN
PRINT "7 KHZ
PRINT
PRINT "OUTPUT
NO. OF
TEST
REMARK"
PRINT "NO.
MINTERMS
RESULT"
VTAB 24: PRINT "1 "~: INVERSE
:PRINT "CHG BRD NO."~: NORMAL
:PRINT"
2 "~: INVERSE
:PRINT "EXIT"~: NORMAL
VTAB 22: HTAB 1: PRINT "TEST
S:
PASSED:
FAILED
."
FOR 0 = 1 TO NO
VTAB 6 + 0
HTAB 3: PRINT 0~: HTAB 13: PRINT
K(O)
NEXT 0
REM
F - 0
PRINT
VTAB NO + 8
PRINT "PRESS RETURN WHEN REA
DY ";
GET K$: IF K$ = CHR$ (13) THEN
930
IF K$ = "1" THEN 420
IF K$ = "2" THEN END
GOTO 890
REM
VTAB NO + 8: HTAB 1: PRINT "
"
.
42
950
960
FOR 0 = 1 TO NO
VTAB 6 + 0: HTAB
24~
PRINT "
"
970 NEXT 0
980 REM ---------------------990 FOR 0 = 1 TO NO
1000 VTAB 6 + 0: HTAB 2: PRINT "
>"i: HTAB 29: PRINT "TESTING
".
'
1010 REM
1020 REM -------------------1030 REM PREVENT COUNT
1040 REM
1050 X = PEEK (CL)
1060 REM
1070 REM -------------------1080 REM LOAD REGISTER 1
1090 REM
1100 POKE L1,8 * (0 - 1) + NI 4
1110 REM
1120 REM --------------------1130 REM CLEAR COUNTER 1
1140 REM
THEN COUNTER 2
1150 REM
1160 X = PEEK (C1)
1170 X = PEEK (C2)
1180 REM
1190 REM ---------------------1200 REM START COUNT
1210 REM
1220 X = PEEK (PS)
1230 REM
1240 REM -------------------1250 REM WAIT FOR "DONE" SIGNAL
1260 REM
1270 X = PEEK (DN)
1280 IF X INT (X I 2) * 2 = 0
THEN 1270
1290 LC
255 PEEK (RL)
1300 HC = 255 PEEK (RH)
1310 HC = HC - 8 * INT (HC I 8)
1320 CN = 256 * HC + LC
1330 VTAB 6 + 0: HTAB 2: PRINT "
"i: HTAB 24: PRINT CNi
1340 HTAB 28
43
1350
1360
IF CN = K(O) THEN PRINT II
CORRECT"
IF CN < > K(O) THEN PRINT
WRONG!":F =
CHR$ (7); II
1
1370 NEXT 0
1380 IF F = 0 THEN PA = PA + 1
1390 IF F = 1 THEN FA = FA + 1
1400 TE = FA + PA
1410 VTAB 22: HTAB 8 : PRINT TE;:
HTAB 21: PRINT PA;: HTAB 35
: PRINT FA;
1420 GOTO 840
APPENDIX B
Memory Map of APPLE II+
44
45
,____
: l·'r,ge '\;umucr:
' ,,
II I
~ccimai
HI.!)(
Sll-:-0--.--------l
S01
Sfl2
12
I·,.
Ii i90
SBE
SBr
l 193
Kl
~~~~
RAM (48KJ
~2----s~c~0~-----
i.
II
•
1·198
I~:~
I ':201
SC6
SC7
I
1/0 (2K)
L_---i
~~~ I
I
1 110 Ro:-1 !2K>
I
'-~_;_~-~---~~~ !_·______·203
$00
20'i
SDI I
i
i
I
R0!\1 (12Kl
I
254
SFE
1_2."_J5 ___S:_F~l _______,
System Memory Map
of APPLE II+
(l
•