CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
THE DESIGN AND CONSTRUCTION OF A MC6800 MICROPROCESSOR
WITH AN INTERFACE TO CONTROL ANY ENVIRONMENTAL TEMPERATURE
~
A graduate project in partial satisfaction of the
requirements for the degree of Master of Science in
ENGINEERING
by
YOUSEF BABADJOUNI
/
AUGUST, 1978
I. Hashimoto,
Commit tee Chai rnan
California State University, Northridge
ii
Table of contents
Page
Figures • .•.........•...•.•....•........•.•.. • .... • • • • • • •..••..
Symbols and Abbreviations •••••••••••••••••••••••••••••••••••
Abstract ....••....•.....•••..•.••••....•••••......••••........
iv
v-vi
vii
Section
1
1.
Introduction •••••
2.
Typical System configuration••••••••••••••••••••••••••••••
8
3.
Design .•..•••••••.•••..•.....•..•.•••...••..••.••••.•.••••
10
4.
Application of Microprocessor •••••••••••••••••••••••••••••
31
5.
Discussion and Conclusion •••••••••••••••••••••••••••••••••
40
6.
Microprocessor CPU Architecture •••••••••••••••••••••••••••
47
7.
The Microprocessor ••••••••••••••••••••••••••••••••••••••••
51
8.
Men10ries ••••••••• "' ••••••••••••••••••••••••••••••••••••••••
61
MC6810 RAM Bus Interface..................................
62
MC6830 ROM Bus Interface••••••••••••••••••••••••••••••••••
64
MC6820 Peripheral Interface Adapter •••••••••••••••••••••••
66
MC6850 Asynchronous Communication Interface Adapter.......
72
10. Temperature Interface Program and Flow Chart..............
73
11. Bibliography .......•..••.•......•......••...........•
89
9.
••
l't
•••••••••••••••••••••••••••••••••••••
iii
Figures
Page
1.
MPU Minimum System ••••••••••••••••••••••••••••••••••••••••
2.
Block Diagram of Printed Circuit Board •••••••••••••••••••• 11
3.
Power SupplY•••••••••••••••••••••••••••••••••••••••••••••• 23
4.
Circuit Design•••••••••••••••••••••••••••••••••••••••••••• 24
·5.
Application Interface ••••••••••••••••••••••••••••••••••••• 38
6.
Temperature Control Board ••••••••••••••••••••••••••••••••• 39
7.
Microprocessor Architecture••••••••••••••••••••••••••••••• 47
8.
Operation of a Stack •••••••••••••••••••••••••••••••••••••• 48
9.
Functional Blocks of a Microprocessor ••••••••••••••••••••• 51
10.
A Small MC6800 Microcomputer System••••••••••••••••••••••• 52
11.
MC6800 •••••••••••••••••••••••••••••••••••••••••••••••••••• 54
12.
Initialization of MPU After Restart ••••••••••••••••••••••• 56
13.
MCM6810 RAM Functional Block Diagram•••••••••••••••••••••• 63
14.
MCM6830 ROM Functional Block Diagram•••••••••••••••••••••• 65
15.
MPU Parallel I/O Interface•••••••••••••••••••••••••••••••• 66
16.
MPU/PIA Interface••••••••••••••••••••••••••••••••••••••••• 68
17.
MC6820 PIA Bus Interface•••••••••••••••••••••••••••••••••• 71
18.
MPU/ACIA Interface•••••••••••••••••••••••••••••••••••••••• 72
19.
Temperature Interface Program and Flow Chart •••••••••••••• 73
iv
9
Symbols and Abbreviations
1.
CPU
Central Process Unit
2.
I/O
Input/Output
3.
LSI
Large Scale Integration
4.
TTL
Transistor Transistor Logic
5.
ALU
Arithmetic Logic Unit
6.
MOS
Metal-Oxide Semiconductor
7.
PMOS
P-Channel Mos
8.
NMOS
N-Channel Mos
9.
CMOS
Complementary-Mas
10.
ROM
Read-Only Memory
11.
PROM
Programmable Rom
12.
RAM
Random-Access Memory
13.
PIA
Peripheral Interface Adapter
14.
ACIA
15.
MHZ
Asynchronous Communication Interface
Adapter
Mega Hertz
16.
KHZ
Kilo Hertz
17.
VMA
Valid Memory Address
18.
R/W
Read/Write
19.
DB
Data Bus
20.
ADB
Address Bus
21.
DBE
Data Bus Enable
22.
BA
Bus Available
23.
A/D
Analog-to-Digital
24.
D/A
Digital-to-Analog
v
25.
TSC
Three-State Control
26.
NMI
Non-Maskable Interrupt
27.
RES
Reset
28.
IRQ
Interrupt Request
29.
GND
Ground
30.
WAI
Wait
31.
PC
Program Counter
32.
CCR
Condition Code Register
33.
SPR
Stack-Pointer Register
34.
SWI
Software Interrupt
35.
DMA
Direct Memory Access
36.
E
Enable
37.
cs
Chip Select
38.
IC
Integrated Circuit
39.
DDR
Data Direction Register
40.
S.R
Shift Register
41.
CR
Control Register
42.
BC
Bus Control
43.
EPA
Electronic Product Association
44.
CRT
Cathode Ray Tube
45.
POS
Point-of Sale
46.
INT
Interrupt
47.
PDC
Peripheral Device Control
48.
MUX
Multiplexer
49.
CLK
Clock
vi
ABSTRACT
The design and construction of a MC6800 microprocessor
with an interface to control any environmental temperature
by
Yousef Babadjouni
Master of Science in Engineering
The
objective of this project is to design, develop, interface,
and fawiliarize
oneself with a
MC6800
microprocessor system.
A MC6800 microprocessor and a temperature
is
built using
controlling
system
the MC6800 CPU ( Central Processing Unit ) , 6810 RAM
( Random Access Memory ) ,
6830
ROM ( Read Only Memory),
used
for
monitor program, and 6820 PIA (Peripheral Interface Adapter). The PIA
is used for Input/Output ( I/O ) ports to the terrperature control system.
The interface includes a Digital to Analog (D/A) converter, a comparator
circuit, and a
output ports,
temperature
which
sensing device. It also
activate
cooling elements of the
of two
relays for switching the heating and
temperature controled system.
vii
consists
SECTION 1
Introduction
The microprocessor is
developments since
the
one of the most exciting
transistor appeared in 1948.
technological
It is predicted
that this device will not only revolutionize the digital electronics
field,
but will also have a great
present and future generations.
influence on the way of life of
When microprocessors were first int ro-
duced many potential users investigated them for possible applications
in new products and concluded that the microprocessor was just not fast
enough to do the job. Closer examination will show,
however, that most
investigators only considered purely software solutions to problems,
thereby
missing
the
correct assessment
of
microprocessor
capa-
bilities.
During
the past year,
as more
and more microprocessors
(as
well as information about microprocessors) have become available, the
competition for the market has become fierce.
has
a
choice
of
many
The potential user now
Central Processing Units
widely in computing power and price.
( CPU's )
The price of the
varying
low-cost CPU's
even in small volume is now $10 and for the powerful microprocessors
decreases
system
towards
the
$2 to $12 range. The cost of the microcomputer
resides predominately in the memory and I/O circuitry.
This
means that additional processors can be added and comptuting power can
be given to applications which might have
been uneconomical in the
past.
Before we get too far afield, some attempt
define a microprocessor.
should be made
to
Specifically, a microprocessor is a CPU of a
1
2
microcomputer,
which
integrated circuit
is
usually
packages.
implemented
It
in one or several
is not the
entire computer
(at
least not at this time), but rather it contains the logical elements
for manipulating data and performing arithmetic or logical operation
on it.
To make a complete computer, the microprocessor must be aug-
mented through several support elements such as memory, input/output
circuits, and other specialized functions. Currently, the term microprocessor also implies
a
single-package
Large
Scale Integration
(LSI) device; but, strictly speaking, microprocessors could be implemented with
more
Transistor-Logic
tremendous
conventional
components,
such as
(TTL) ,or Medium-Scale-Integration
number of
microprocessors
Transistor-
(MSI).
With the
on the market today, it must
be remembered that many microprocessor applications
are relatively
simple by comparison with minicomputer programs. Many microprocessors
are used to replace hardwired logic controllers,
are often less
than
1000 instructions
and their programs
long. Such simple applications
make up the bulk of microprocessor systems to date.
Of course,
for some applications, microprocessors aren't the
sole LSI alternative.
Complex logic decisions can be handled
as well by PLAs (Programmable-Logic-Arrays).
are performed by ALU' s
-from which a
chips
Numerical
(Arithmetic-Logic-Unit)
number of microprocessors
just
computations
or calculator chips
have evolved.
Custom LSI
form yet another alternative, especially when very high volumes
of a system must be produced.
The high chip density needed for microprocessors has generally
been obtained by
the use of
some form of Metal-Oxide-Semiconductor
3
(MOS) technology.
manufacturers
speeds.
At first PMOS (P-Channel MOS) was
turned to NMOS
More
recently,
microprocessors
have
( N-Channel MOS )
power-saving
appeared.
P and N-channel transistors
employed,
then
to obtain increased
Complementary-MOS ( CMOS )
The latter form of MOS
and
features
lower
use
bipolar technology
combines
dissipation
than
either PMOS or NMOS.
Microprocessors
that
produced, and offer the highest speed.
generally
aren't
However,
complete microprocessors.
bipolar-microprocessor building blocks
the bipolar units
In most
must
be
have also been
cases, several
combined to
obtain
the capabilities offered by a single MOS microprocessor chip.
Regardless
are
technology used,
organized in basically
systems.
of
the
microprocessor systems
same way as conventional
computer
The major blocks are a central processing unit (or CPU),
memory and
each
of the
input/output (I/O) facilities.
these
blocks
can be a
In their simplest form,
single chip.
The microprocesssor
(or chips) contains the CPU.
Within memory
there are instructions.
of information that direct the activities
interrelated instructions
Only-Memory
of the CPU.
stored in memory
The memory also holds coded
Typically,
These are coded pieces
data
that
constitutes
From a
ROM,
provides
can be set by
the same
is a
Read-
information can be obtained,
that information cannot be altered during operation.
ROM ( PROM)
a program.
are processed by the CPU.
the kind of memory used for programs
(ROM).
A group of
function,
but
A Programmable
internal bit
the user rather than the manufacturer.
but
patterns
Data, on the
4
other hand,
resides
in Random-Access-Memory
( RAM).
This
kind
of
memory allows information to be written and modified as well as read.
In operation,
uses
can
it
the CPU
to initiate
various
rapidly obtain any
memory may not be
reads each instruction from memory and
processing actions.
data stored in memory.
Also,
Sometimes
the CPU
though,
large enough to store all the data needed.
problem can be solved at the input ports, where
equipment can be stored.
data
This
from external
This allows the data to be obtained by the
CPU at high rates of speed and in large quantities.
A microprocessor also requires output
communicates
to
a
its
display
results
to
ports
the outside world.
or peripheral device,
through which it
The output
or it may consist
of
may go
control
signals that direct another system.
Throughout the operation, the CPU is
The microprocessor
component.
controls
the
functions
the system 1 s supervisor.
performed by an another
It fetches instructions from memory, decodes theirbinary
contents, and
executes them.
During
the execution of instructions,
the microprocessor references memory and the I/O ports as necessary.
It
also
recognizes
and
responds
to various
externally generated
signals.
Recently
there have
duced by various
been a variety of microprocessors intro-
IC manufacturers.
sixteen bit microprocessors.
be favored for dedicated
microprocessors
expensive.
They include four, eight and
The four bit microprocessors seem to
system applications,
approaches
and the
sixteen bit
minicomputer applications and are more
The 8-bit microprocessors are
becoming
the most popular
5
among manufacturers, consumers and home hobbyist.
processors are
the:
from Intel,
F-8 from Fairchild,
3)
1) 2650 microprocessor
Some of the micro-
from Signetics, 2) 8080
4) 6502 from RCA,
Zilog and 6) MC6800 from Motorola.
There are a
5) Z-80 from
few more
but these
are the most popular ones.
When the
single-chip MC6800 microprocessor was introduced in
1974 by Motorola,
it
peting 8-bit units.
address lines and
offered designers
It offered a
three advantages
over com-
dual bus structure for data and
software-controllable interface elements. Further
it could operate from a single, +5V supply. Several other companies
have
since
introduced microprocessors with similiar features
so far few have
equalled the
Motorola has
parts headed by
MPU is
bus
an eight-bit
single
to provide a microprocessor family of
five-volt
of several memory
It
is
interface
ROM (MC6830), a parallel I/O interface
serial
family
concept,
I/O
interface
not
a
Support
of
devices.
chip
each operates
set
requiring
on a
in the sense
for
the MPU consists
To date,
the
family
1024 word by 8 bit
(MC6820 PIA), and an asynch-
(MC6850 ACIA).
and is compatible with the system bus
is
compatible
supply and no external TTL devices
small system.
and I/O
TTL
128 word by 8 bit RAM (MC6810), a
ronous
The MC6800
parallel microprocessor with addressing capa-
65,536 words.
interfacing in a
consists of a
flexibility of the interface circuits.
the MC6800 microprocessing unit (MPU).
bility of up to
only a
elected
but
single
five-volt
signals.
that
In keeping with the
power supply
The family of
the MPU
parts
operation
is
dependent upon other family elements; the MC6800 is a self-contained
6
microprocessor capable of operating with virtually any MOS or standard
TTL device.
The significant point is that the other family members
merely add additional
capability and/or flixibility.
They provide
excellent tools in configuring a full microprocessor operating system.
Therefore,
it
is
the
intent
of
this
project to
design,
develope, and familiarize oneself with a MC6800 microprocessor system,
and
interface
the MC6800 microprocessor to an
microprocessor itself
6820 PIA,
will be
built with MC6800 CPU,
ins ted
of the
6830
ROMs,
because
mask programmble ROM which requires programing
is very expensive when only one is required.
by
the
The
6810 RAM,
Motorola 8T26, and 8T28 buffers, and Harris PROMs.
PROMs were used
are fuse
application.
These
6830 is a
the vendor.
The Harris
linked and can be easily programmed by blowing
this
1024 ROMs
the
fuses
when a high voltage is applied.
The rest of the system was
a
hexadecimal
keyboard, a
and miscellaneous
with a
dual
built with LEDs
phased
I/O port, a
the
display,
clock with multivibrators,
gates and logic devices.
6820 PIA for
for
The interface was
R/2R resistor network for
built
the D/A
converter, a temperature sensor, and a voltage comparator. The output
on the interface consisted of two transistors each driving a relay.
One of the relays switches
the temperature sensor.
temperature
sensor is
ON a
light which controls
The other relay switches a
sensor to control the cooling process.
mounted
between the
fan and the
the heat near
fan ON near the
The
light to
temperature
receive
the
full effect from each, independently of the other.
A temperature range consisting of a low temperature, and high
7
tenperature
is
selected and entered
differential temperature is
adds hysteresis
of an element,
into software program.
selected and entered.
to the heater and
ON and OFF,
Also a
The differential
cooler to prevent the switching
at the high or low temperature of the
range selected.
The program will
by turning
ON the
environrrent
falls
will heat up
differential
light
or
heat,
point. If the
the fan
sensor down past the
The
when the
below the selected
the sensor past the
range selected,
selected.
maintain the temperature of the environment
or
point
cooler will be
can be
board without reseting
low
The heater or light
of the range
to the
environmental temperature goes above the
upper value
program
range.
temperature in the
of
a
turned ON to
range
to
the
cool the
differential
temporarily interrupted by the key
the system,
to change
the
temperature range
and/or the differential temperature.
The display
in the first
the next
shows
two LED's,
two LED's
last two LED's.
in degrees
and
the
selected low temperature of the range
the present teiPperature of the sensor in
the high
temperature
of the
range
All values are displayed in BCD format
centigrade
(CO).
and
read
Centigrade was chosen to be display-
ed because the range used would only require two
however,
in the
decimal
digits;
the program and
could be
changed to display the
(BCD) binary coded
calibration of hardware
temperature in degrees
faranheit.
SECTION II
Typical System Configuration
Only five circuits
A MC6800
system:
are needed to form a mininum microcomputer
microprocessor,
a
MC6820 PIA or a MC6850 ACIA,
a RAM or ROM for program storage and,
of
course,
With the preceding material in appendix, the family
a
power supply.
devices and bus
structure can be combined in a system configuration as shown in figure
( 1 ) • All the timing functions are controlled by the two-phase system
clock,
which
Figure
( 1 )
size of the
can be
set for any frequency
represents
system.
typical
The data
between all devices in the
as required.
associated
from 100 KHz
interconnections
bus and
system,
to
regardless
1MHz.
of the
control bus is shared fully
with each one tapping off signals
The single-supply operation of the microprocessor, its
I/O
circuits
and
compatibility with TTL-level
its
memory
signals and
8
circuits
permit
power supplies.
full
9
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Figure (1), MPU Minimum System
....
,
SECTION III
DESIGN
Let us
for
its
now proceed to the design of the microprocessor system
application. Using the
background
a
ID3.terial found
microcomputer system
diagram
was
in the apendix as
designed
shown in figure
using
is
MC6800
microprocessor.
The
demonstrate the
MC6800 system with their specified loading at clock
frequencies of up to 1.0 MHz.
( 2 )
a
designed to
The MC6800 design is a pre-engineered
assembly that provides one-self with an efficient means of becoming
faiPilia r with
most
of the MC6800
microprocessor family
The computer contains a MC6800
X 4 bit ROMs,
two
microprocessor, four
128 word X 8 bit RAMs,
stepping
all the
service
routines
( 2 )
shows
a
layout
board and figure ( 3 A.B.C.D.E.F .G)
the entire system.
PIA.
The
1024 word by 4 bit
for loading programs; single
forward and backward through memory; editing and execution.
Figure
MC6800 CPU
two PIAs, one hexadeciool
board in 128 word increments.
ROMs contain
1024 word
The RAM nemory ooy be expa-
keyboard, and six 7-segment LED displays.
nded off the
of parts.
As
diagram of the
provides
can be seen,
chip supported
the
by MC6810
the
RAM,
(8.5v@
1.5a),
circuit
circuit design of
computer is
based on the
MC6830 ROM,
The power supply which is shown on figure
a wall-plug transformer,
printed
( 4 )
and MC6820
consists of
4-IN4001 rectifiers, a 0.1
mfd. capacitor, 1000 mfd. filter capacitor, and a LM309K 5V regulator;
which is
The
not
particularly sophisticated,
computer clock is
monostable
provided
by a
9602
I!llltivibrator which produces a
10
but
more
than adequate.
chip containing a
dual phase clock.
dual
There
11
are
two
critical adjustments
of the MC6800 system.
by adjusting
ROMs, and PIAs.
by a
And VMA.
in to
results
a
to 470 msec
(bit
for ¢2,
as
The VMA from the CPU is
To get the
wall), it
computer up and
"EPA-UP"
must be
set
required by the RAMs,
combined with 02 of the
to get
running
is necessary to depress
in initializing the keyboard
display of
rate)
operation
to 450 msec for ¢1 and adjusting
NAND gate and an inverter gate
'/J2.
the
made before
clock frequency
potentiometer R1
potentiometer R2
clock
The
that must be
both VMA.¢2
(After plugging
the Reset key.
This
control program and provides
on the LED displays.
Now the computer will
respond to the keyboard commands.
1
1 1
1 1
1 1
1
1 LED 1 1 LED 1 1 LED 1 1 LED 1
1
1 1
1 1
1 1
1
1
1 1
1 1
1 1
1
1
1 1
1
1 LED 1 1 LED 1
1
1 1
1
1
1 1
1
1
1 1
1 1
1
1 8T 1 1 8T 1 1 8T 1
1 28 1 1 28 1 1 26 1
1
1 1
1 1
1
..L
Light Emitting Diode
1
1 74S
104
1
1
1
1
1
1
174S
104
1
1000000
1
1
1
Transistor
_L
I
'V 'V
.c::,.ZTT
Diode
_j_
T
..J_
T
1
PIA
1
1
CPU
1
,.
-L
_L
.J_
_L
T
T
I
Q
POT
~
Q;
POT
I
1
1
1
1
!PIAl
1
1
_j_ -Ll
1
1
T T 1
1
1 1
1 1
1
1 96 1 1 74LS 1 1 74LS 1
1 02 1 1 04 1 1 00 1
1 1
1
1
1 1
1 8T26
1
...Ll 8T26
1
..Ll 8T26
1 RAM 1 T
.J_l 8T26
T
1 RAM 1
~1
_Ll 8T26
I
Auto Back Change
1 A 1 B 1 c 1 D 1 Do
1
1
1
1
1
1 1 1 2 1 3 1 E 1 Examine
1
1
1
1
1
1 4 1 5 1 6 1 F 1 Forward
1
1
1
1
1
1 7 1 8 1 9 1 0 1 Reset!
1
1
1
1
1
1
RTI
Load
1
T
1 ROM 1
1 ROM 1
1 ROM 1
1 ROM 1
T
1 RAM 1
Figure ( 2 ) , Block Diagram of Printed Circuit Board
1
1
!L
In figure
3 A
one
can see
that
the two phased
clock is
generated by a 9602 chip, containing a dual monostable nultivibrator.
The clock was set to run at about 800 KHZ which is 20 % below a maxilll.lm
of 1 MHZ,
that will operate
the
CPU.
VMA.~2,
The
CPU control function is combined with NAND
and R/W from the
gate and INVERTER gate
to synchronize the microprocessor system.
The CPU chip is also shown in figure 3 A. The data and address
lines are
organized
in bus
structure as
are
the control lines
to
and from the CPU. All or most of these buses go to the other figures.
Figure 3 B of the
Each RAM has
both RAMs,
system.
a
as
design shows
128 X 8 bit
they are
The R/W
a
matrix.
All the Data Bus
important
control line
is
the RAM memory of the system.
part
of the
connected to
Bus
to each RAM is
AO-A6 common to both RAMs.
of the
each RAM to
control
words in the
RAM 2 7 =
selected from the
128.
connected with the
These addresses
the Data Bus.
The
first 7 addresses
locate each of the
The next six addresses
remaining eight address.
to
Data Bus
when the RAM is inputing or outputing data onto
Address
lines go
to
128
the chip are
The remaining enable is
low active therefore, it is connected to ground.
With this
addressing
system a base address is formed for each
RAM. The addresses that are not connected to the RAM are
A low enable is active when that
its
cycle.
And
for High enables
address
is
don't cares.
in the Low state of
the High state
of the
cycle is
active. The following table illustrates how the base address is formed.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15
X X
X X x987 -129 address128
15 X X X X X 987 --2
0
0
0
0
o.
0
0
8
Address
RAM 1
RAM 2
RAM 1
RAM 2
13
The previous table shows
for
or
RAM.
each
do
not
Indicating a
care,
where
rows of the diagram shows
the binary connection of the addresses
Low active,
no address
is
High active connection,
connected.
The
last
two
the HEX equivalent of the binary address
in its activated state.
This is its Base Address. These six addresses
are connected to
chip enables of
the
the RAM.
The
enables are
internally connected to a six input NOR gate where two of the enable
lines are high active and the other four
are
low active. The figure
below shows the internal RAM enable.
E5--------------
E4---------------
E3-----~o-----E2--------------El---------------
E0----~0-----
The addresses
are
A7,
A8,
A9,
Al5 and a control VMA.~2 to
The VMA.~2 control
keep the RAM in sync with the microprocessor.
line goes
to
the E3 line of both RAM chips.
go to one of the low active Enables each.
Addresses
The remaining
to
the
low active
enable and
the
A9, Al5
two Enables
For RAM one A7
are connected to A7 and/or ground and/or Vee.
connected
A8,
is
remaining Enable is
connected to High threw a 2.2K resistor. For RAM two A7 is connected
to a High
active Enable and
using
this
same method of
address
selection for Enables, the memory can be expanded.
Figure 3 C shows the display interface.
This consists
7-segment LED displays, their driving hardware,
of six
inverter buffers,
switching transistors, and a MC6820 PIA interface chip. The LEDs are
14
all connected in parallel.
and the other half
control the
PIA{ The Reset
line
because
is
Low state at
the Enables
used
to
set all
initialization.
the
7-segments
for each display
transfer through the
register bits
to a
The IRQA, and IRQB are not
to indicate interupt
being used as an output
and CB2 lines
the
the PIA in phase with
direction of data
the CPU or any where
this PIA is
CBl, CA2,
the PIA drives
VMA.¢2 and R/W keep
the system, and
connected to
of
of the PIA drives
chip. Control functions
logical
Half
port
condition
only.
The CAl,
are all pulled Low to ground so that the
CPU is the only control over the PIA and nothing external is allowed
to interrupt it.
The complete Data Bus is connected to the PIA as
acting as
an output
memory map
of the
port for
data.
shown in table
The PIA is also a part
system and addressed as memory.
display PIA is selected just like a
the PIA is
of the
Therefore,
RAM with a
basic address as is
below.
15 14 13 12
11 10 9 8
7 6 5 4
3 2 1 0
Address Bus
15
X
X X X X
3 X 1 0
Address select
8,9,A,B
Base address
X 13
X
X
8
X X
0
There are five
CSl, CS2 and
the
the
0
select lines. Three are chip select lines CSO,
other two are
register select lines
RSO,
RSl.
The basic address for this chip is 8008 and when the register select
lines are
formed.
enabled the
With these
and BOOB
basic addresses of 8009 ,800A
basic addresses
both
registers
are
of the PIA can
be controlled
Figure 3 D
shows
the key board
interface.
It
contains
the
I
15
key board switches with their pull up resistors and the PIA.
PIA is
set up as
an input
port
only.
Both halves of the
used as key switch inputs. Control functions
are also
and IRQB
PIA has
connected as
are
they were
connected
data
to
for the
directly to
transefer.
VMA.¢2,
The CAl,
display
the CPU
CA2,
PIA are
R/W, and Reset
PIA.
The IRQA
to indicate
CBl,
This
that the
and CB2 lines are
all pulled High for an input port only condition.
The complete Data Bus is connected to the PIA as it was for
the display
interface.
The five
select
CSl, and CS2 form basic addresses
lines
of RSO,
RSl,
of 8004,8005,8006, and 8007.
CSO,
The
key board also generates the reset of the system with the reset key.
Figure
system.
3 E of the design shows
Four 8T26 buffer
the address
chips were used.
buffers
for the
These buffers have
two
inverters in line with each other for each address line. (see figure
below)
::.~~~~~~~~~~-----~-----~·----------:~~b::
1
1
1
AO
These
buffers
provide
for external addressing
both an inverted and
convenience.
eriabled High and Low because
The
a
Non-inverted output
buffers
are hard wired
the monitor ROMs are wired externaly,
and get their address lines from these buffers.
16
The
buffers are needed so
are needed
to the
the CPU or
rest
bus
lines
that when more and more peripherals
the fan out load does
of the main system.
not load down
If many external devices are
added, more than one set of buffers may be needed.
Figure 3 F
shows
Control Bus buffer.
the bidirectional Data Bus
The Control Bus
the
one used for
the Address
for
constant
The
data buffers are 8T28
buffer is
Bus, and
a
buffers and the
8T26 chip,
is also hard wired enabled
BA, and VMA.~2.
output of cant rol functions, R/W, VMA,
chip.
like
These are connected and enabled so
that they may pass data in either direction on the data line • (seediagram below)
TO
TO
OR
OR
FROM
D~
CPU
PERIPHERAL
Enable B
The
line was
line will
pass
selected.
Both enable
same time. Enable A is
diagram and
data
to
direction that
lines
It
cant rols
the peripherals.
the
enable
are never selected at
generated from gates
is VMA.~2 .R/W.
microprocessor
in the
in the clock
the
circuit
the data coming from the
Enable B is
generated by a
8
input NAND that enables the monitor ROMs and is R/W.Al2.Al3.Al4.Al5.This
enables
data
the microprocessor system.
to move
from
the peripheral ROMs
to
17
Figure 3 G shows
the
monitor ROM interfacing.
has a chip select NAND gate and four Harris
256 x 4 bit memory matrix each.
The Harris
not
1024 was chosen as
lines
eight
wide,
two
Data Lines.
Since
chips have
Two
pairs
the
the programming
available and the programing facilities
the Harris ROM were available.
data
diagram
1024 ROM chips with a
monitor ROM instead of the Motorola M6810 because
of the M6810 was
The
for
the Harris ROMs are only four
to be placed in series
to
form
(A pair, B pair) of these series are
placed in parallel (tristate outputs) to form a monitor ROM system
matrix
of
buffers
for
512 X 8 bits.
to all
256 words).
low activated.
address,
Data Lines
transfer to the MPU system.
are connected
( 28 =
These
four ROMs
There are
The
CS1
for the
is
to the
data
Eight address A0-A7 lines
individual word locations
two chip selects
select
then go
CS1
and CS2 that are
enabled with the A8 or the A8
depending on which series pair is selected.
The A pair is
selected with A8 and the B pair is selected with the A8 address.
The
other chip select CS2 is connected to all four ROMs and enables
the
group as
A12,
a
A13, A14,
VMA.¢2 and
whole memory block.
A15,
R/W
microprocessing
This
enable is generated from
R/W, and VMA.¢2 through eight input NAND gate.
control lines
system.
synchronize ROM enabling with the
The addresses help
for the ROMs as shown in next page.
form
the
base address
18
15 14 13 12
11 10 9 8
15 14 13 12
X
X
X 8
15 14 13 12
X
X
X
7 6 5 4
28
B
3 2 1 0
256 words
Pair A select
28 = 256 words
Pair B select
F
0
0
0
F
1
0
0
This chip select also enables
transfer data from
Pair A base add
F 0 0 0
Pair B base add
F 1 0 0
the
Data
Bus
buffers
to
the ROMs to the microprocessor system. The diode
and pull up resistor in the diagram improve
the
fan out load of the
eight input NAND gate.
The hexadecimal keyboard
keys which double
command mode.
shown in figure
( 2 )
indicates
the
as command keys when the computer is in the expect
The following
lists indicate
the
type and scope of
the available keyboard commands.
The examine
command:
The "E" key doubles as examine.
This
command lets you enter a personally selected address (memory location)
of four digits:
ENTER EXAMINE (E)
----------Displayed
ENTER 0003
0003 00*--Displayed
* 00 is used as
The forward
command lets
Repeating
the
you
command:
increment
command
lets
The "F" key
the
doubles as
displayed address
you step forward
an example.
forward.
by
one digit.
through memory and
examine the contents of each succeeding address:
ENTER FORWARD
ENTER FORWARD
(F)
This
0004 FF*--Displayed
0005 04*--Displayed
19
ENTER FORWARD
0006 A8*--Displayed
and so on.
The back comtmnd:
lets you decrement the
The "B" key doubles as BACK.
displayed address
This command
by one digit.
Repeating
the comtmnd lets you step back through memory and examine the contents
of each preceding address:
ENTER BACK (B)
0005 04*--Displayed
ENTER BACK
0004 FF*--Displayed
The change
comrrand:
The "C" key doubles
co11lmlnd lets you
modify the
no
at the
memory exists
display
contents
selected
undefined data and
no
of the
location,
modifications
as
change.
rremory location.
This
If
the last 2 LEDs will
can be
nade.
The
appearance of two dashes (--), after entering changed data, indicates
that you are
trying
to modify the contents of
a nonexistent memory
location.
ENTER CHANGE (C)
0004------Displayed
ENTER
0004 86---Displayed
86
The auto comrrand:
The "A" key
doubles as AUTO.
This command
causes the contents to be cleared and the address to be automatically
incremented:
ENTER AUTO (A)
---------Displayed
ENTER 0004
0004-----Displayed
ENTER 86*
0005-----Displayed
ENTER 00
0006-----Displayed
ENTER 14
0007-----Displayed
---------And so on
20
* When
the second digit key is depressed, content
displayed.
When the key is released,
increnented and the
insertion.
The Do
contents
is registered and
the address is automatically
is cleared and
ready for new content
Automatic command is exited by pressing reset.
command:
lets you enter the
The
"D" key doubles as DO.
starting address of
This command
a program, and
imnediately
enables MC6800 to execute the program:
ENTER DO (D)
-------DO Displayed
ENTER 0007
At this point,
the MC6800 will
start executing
instructions beginning at 0007 as shown in table (2).
Address
1
1
1
F F F F
1
1
1
F D F F
1
1
1
0 0 7 F
1
1
1
0 0 6 7
FEOO
1
1
1
Keyboard control ROM location
1
1
1
User's memory expandable to 64K
1
1
1
Keyboard control p rog ram uses
1
1
1
MPU registers get stored here
1
1
1
1----------------------------------------------------------l
0 0 8 0
of RAM plus ROM
1
1
1
l----------------------------------------------------------1
0 0 6 8
this area for temporary storage
1
1
1
l----------------------------------------------------------1
0 0 6 1
when an interrupt occurs
1
1
1
l----------------------------------------------------------1
1
1
1
0 0 6 0
1
1
1
0 0 5 A
0 0 5 B
1
1
1
Stack area for monitor subroutine
address save
1
1
1
l----------------------------------------------------------1
0000
1
1
1
User's area
1
1
1
l----------------------------------------------------------1
Table (2) Memory Map
21
The return from
interrupt
return from interrupt (RTI).
from the keyboard.
command:
The "8" key doubles as
This command lets you handle interrupts
Pushing the RTI key causes a return from interrupt
instruction to be executed in the keyboard control program.
The load memory command:
(LOAD).
This command lets you
The
"9"
key doubles as
load memory
load the random access memory
automatically from an external device
(RAM)
such as a paper tape reader
or rna rk-s ens e card reader.
Upon execution of the program, the stack pointer is
at location 0067.
Let us assume
left pointing
that one's program does not modify
the value of the stack pointer, therefore an interrupt will have the
following effect:
The status of the MPU will be saved in location
0061 through 0067.
The stack pointer will be left pointing at location
0060 and
control passes
examine and
interrupt
change
program,
to
the keyboard control program.
the saved status of the MPU.
enter the RTI
command.
You can
To return to the
This causes
to be reloaded with the current values in the saved stack.
the MPU
Execution
then resumes.
Now if the program happens
pointer, an interrupt will have
except the
was left
value
of
save
stack will be
pointing.
the
to modify
the value of the stack
the same effect as just
located wherever the
After the status of the MPU has
explained,
stack pointer
been saved, the
stack pointer is stored in location 0068 and 0069.
It can be determined exactly where
the save stack is
locations 0068 and 0069 after an interrupt.
the MPU to be reloaded from
by examining
The RTI command causes
the save stack wherever it was
located
22
after the interrupt occurred.
RAM location
Contents at location
0 0 6 1
Condition Code Register B Accumulator
0 0 6 2
B Accunn.1la tor.
0 0 6 3
A Accumulator
0 0 6 4
Index Register, high order 8 bits
0 0 6 5
Index Register, low order 8 bits
0 0 6 6
Program Counter, high order 8 bits
0 0 6 7
Program Counter, low order 8 bits
0 0 6 8
Stack Pointer, high order 8 bits
0 0 6 9
Stack Pointer, low order 8 bits
Except for
destination.
the
reset
The destination
the keyboard
control
the
request,
interrupt
interrupt
of these
interrupt, we can specify the interrupt
is
also
after the reset
program.
non
rnaskable
the keyboard
three interrupt
By default,
interrupt
is always
the destination after
interrupt,
control program.
and
the software
The
destination
can be specified by the user by changing
the following RAM location:
Specification
LOCATION
0 0 6 A
High order 8 bits
0 0 6 B
Low order 8 bits
0 0 6
c
High order 8 bits
0 0 6 D
Low order 8 bits
0 0 6 E
High order 8 bits
An external 5V 3 Amp
which is shown in figure 4.
IRQ Destination Address (16 bits)
SWI Destination Address (16 bits)
NMI Destination Address (16 bits)
supply powers the entire
sysrem design
23
Bridge
Rectifier
Power SW
<-----0"'0
1
1
117 VAC
1
+SV DC
~
1
+ 1
1
1
1
1
1
!Output
1
1
1
- 1
1
1
1
1
1
t
1
1
+ 1
lLM 309K 1
1
1
1000uF
1 35V
1
1
1
t
1
Figure 4, Power Supply
sv
t
1
1 1
1
1
1
1
1 0.1
1 uF 1
1
1
1
1
t
1
1
1
1
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SECTION IV
APPLICATION of MICROPROCESSORS
The potential applications
of
microprocessor technology extend
over a broad spectrum of products. their principle use to date has
been in two general areas, dedicated
The dedicated
control function is now being largely performed by
hard-wired logic.
machines,
traffic
and
examples
electronic cash
control lights,
process
control and data processing.
include calculators, pinball and slot
registers and scales,
medical
test
monitoring systems,
controllers •••• in
fact
almost
any
equipment,
and
machine
situation
in
which a man interfaces w·ith a machine. Data processing applications
are now
most
handling,
often handled by computers.
accounting,
inventory
Examples include record
control, and scientific analysis
•••• wherever a larg volume of varying data has to be manipulated.
Low-cost
data
terminals
handling
tasks. Remote
use
microprocessors
ter~~nals,
for
simple
data
by the addition of a microproc-
essor become "intelligent" and perforrnoff-line edditing, compiling,
and processing. Point-Of-Sale (POS) terll'inals perform calculations,
data
storage
and inventory
control keyboard,
control
functions. the tag
reader,
display and printer peripherals will be under
microcomputer control.
Microprocessors are useful for tasks normally associated with
large-scale systems. In addition
to performing
channel
control
functions, they relieve the large central processor of the overhead
associated with scheduling, and text
editing or file managerrent.
In a similar manner,
can be used for sequencing,
microprocessors
31
32
controling,
formating, and error detection in
tape or disc units.
It is probable that more microprocessors will be buried in computer
peripherals than will be used as computing devices.
LSI microprocessors, combined with low-cost memory and moderate
performance peripherals
speed
printers,
can
many applications.
like
floppy
discs,
CRT displays or medium-
provide all the processing power needed for
A large multi-user computer system may soon be
needed only for accessing large, on-line data bases, or for a
CPU-bound
program
or soon will be,
tasks.
applied
few
Microprocessors and Microcomputers are,
to the following
types
of equipments:
Medical Equipment
Process and Machine Control
Computer Peripherals and System Control
Small Business/Accounting Computers
Calculators, both Programmable and Fixed-Function
Measurement
System, from
Panel Meters
to Full-Scale
Monitoring Systems
Automotive Systems and Traffic controls.
In automobiles a
ssors to meet Federal
recirculation systems.
ssors
both
ments to
few 1977 models
already employ microproce-
emission standards
by cont roling exhaust-gas
More
1978 models will
include
microproce-
for emission control and for optimizing engine adjust-
improve gasoline mileage. In the near future microprocess-
ors will also
be connected to safety
devices, such as
sensors
to
prevent skidding on wet or icy surfaces.
In
business
offices
microprocessors
will
be employed to
33
distribute information and
control the access of
conputers will becone nearly as
common as
data.
Desk-sized
type-writers.
They will
handle
snall specialized data bases appropriate to each person's
job, as
well
as accounting infornation
transfer of typewritten documents
by
replaced
electronic
and personnel
data.
between offices will be
memorandums, relayed
The
largely
through the office
computer systems.
In the home
of video games,
and
food
controls,
microprocessors have already appeared
and such
blenders.
They
household appliance as
in a host
microwave
will rapidly be extended to
temperature
telephones, solar-energy system,
refrigerators,
or burglary-alarm systems,
ovens
building energy and envi ronrrent
to fire
nainte-
nance systems.
The
greatly,
characteristics
and
applicat ons.
categorized by the
4-bit
gane
systerrs:
machines,
8-bit
inst runents,
the
different
microprocessors are
some
in particular
machines,
of
control
vary
suitable than others
applications
for different
rrachine size, include the following:
accounting
intelligent
system:
Typical
more
microprocessors
systerrs, appliances, calculators,
instrumentation,
terminals
systems, intelligent
point-of-sale terminals, traffic
(simple)
terminals
and
controllers, commmi-
cations preprocessors (data concentrators), process control systems.
16-bit
process
systems:
control,
data aquisition systems, nunerical
intelligent
control,
terminals, supervisory control (gas,
power, water distributions), automatic testing system.
Although
microprocessors are not
extremely flexible, they are
34
not particularly fast.
hardwired logic,
example,
microprocessores
but often they take
100 to
functions.
many
equivalent
perform
For
Thus ,
1000 tines
can replace
longer to
applications require
additional hardware to perform high-speed functions.
One of the new and
processor control
onnent for
most
interesting applications
is in the environnental area.
Sensing our envir--
chemicals, hutr.idity and temperature could be easily done
with microprocessors.
The data could be analized
be taken to adjust the environmental
made by the
temperature
and actions could
through decisions
microprocessor system.
A system such as
small scale.
Therefore
control
temperature
sort
for micro-
the
this
could
one
of
can show
be easily deiTJOnstrated
how a
the air in a
microprocessor might
room or building.
rrd.croprocessor
of interface between the
on a
Sore
and the air in the
room must first be designed then build.
The interface
converts
analog signals of the outside world
to digital signals that the microprocessor can operate on and understand. In this application the PIA acts as an interface which outputs and
inputs
in figure
( 5 )•
signals
from the surrounding environment, as shown
The B side of the PIA is initialized as an output
port. These 8 bits are connected to a R/2R resistor ladder network,
which forms
a
digital to analog
converter.
fed into the inverting side of an OP amp.
as
feed back for slight gain adjustments.
then fed
into
gain pot.
The offset
This
It
analog signal is
uses a calibrate pot
The
output of this
another inverting OP Amp with a offset
pot adjusts
is
pot and a
for an internal zero offset. When
35
the PIA
outputs
Zero volts
(00)
Hex,
the
offset pot is adjusted to output
at the second OP Amp's output.
The gain pot adjusts
the
amplification of the analog signal. If the PIA outputs (FF) Hex and
it is 2 volts DC out
it one
to 5
of voltage
into a
Amp
times
of the R/2R ladder,
to output 10 volts.
change per bit.
comparator OP
comes from the
located on the
The
Amp.
application
high
the
a
is
has
resistance value
pot
Since this
resistance
is
a
resistor it will heat
voltage divider with a zener diode and
to
limit the
then fed
into an
current.
The voltage across
OP Amp with a
The output
of
temperature
this OP Amp
fed into the other input of the comparator OP Amp. The comparator
some feedback on it to
output.
OP Amp
to
as
thermaistor, its
through it; therefore to keep the current
for feedback amplification.
of the
fed
a
( 6 )•
low voltage and current is allowed to flow through
thermistor is
gain
The temperature sensor is
The temperature sensor chosen changes
the thermistor by using a
a
comparator OP
linearly over the range of temperatures used in this
(0-100°C).
mininurn,
wider range
of the second OP Amp is fed
sensor.
sensor is
itself when current passes
at a
can amplify
temperature control board as shown in figure
temperature.
its resistance
This gives a
The other input of the
temperature
temperature
changes with
The output
the gain pot
output
make
it
input line.
lines.
sone hysteresis
to the switching
A 3 .6V zener is also added to the output of the
into the LSB
an
add
of
TTL
compatable with
port
The
Two of
A of the PIA.
rest
the
of
the PIA.
The output is
This bit is initialized
port A lines are initialized as
lines are
connected
to the bases of
36
These
two transistors.
relays
have diodes
transistors are
connected across
connected to relays.
their coils
to prevent
back EMF from harming
the transistors.
fan or a
temperature sensor is placed between the
light.
The light
represents a
the
The relays turn ON or OFF a
The fan represents a cooling effect
and light.
ditioner.
The
The
fan
such as an aircon-
heating effect such as a
heating
element. The fan and light are both powered by 120V AC.
The OP-Amp pots are adjusted as follows: Place the temperature
probe into boiling water (I00°c)
tenperature OP Amp where
Then leaving
the
measure
temp gain pot
gain set at
freezing water (0°c).
location as
the
and
Measure
naximum
the
the
output of the
is set at rnaxinum gain.
and placing
the probe into
output voltage from
the high temperature was
measured.
This
is
the
same
repeated
with the gain set at a mininum. The range of voltages and temperatures
are compared.
voltage above
The
the
lowest value so
voltage is
temperature gain pot is adjusted to a convenient
lowest
possible voltage at (0°c),
that when the probe is
but
placed into
near the
(100°c), its
lower than the naximum possible, but still create a large
enough voltage range
range. A 2.00 VDC
to work with when compared with the D/A output
output was selected for a (0°c)
temperature
by
adjuEting the temperature gain pot. Leaving the pot set, the probe is
placed into (100°c)
and
measured. For 2.00 VDC setting at (0°c) the
output is 7.55 VDC at (I00°c). The PIA is then initialized so that
port B has all
the
output lines for
D/ A is adjusted
to lowest gain, and
the D/A converter.
to (00 HEX), the
the voltage is
The output for
calibration pot is adjusted
measured
at
the
output of the
37
first OP Amp. The D/A is
pot set
for maximum,
of these voltages
that the
output
and the voltage
of the OP Amp
OP Amp
is
on the D/A converter.
on the D/A, so
equal
measured.
being measured
1. 75 VDC at the output.
with (00 HEX)
is
the PIA, the calibration
is found and the calibration pot
set up with (7F HEX)
adjusted to
loaded with 7F from
The mid
range
is adjusted
so
reads mid scale when
My
calibration pot was
Next the offset pot is adjusted
that the outout voltage of the second
to the voltage
of
the temperature OP Amp
output
when it is at (0°c). For me this is 2.00 VDC.
Next the value (64 HEX) is
of ( 64 HEX)
is
100.
The gain pot
the second OP Amp is equal to
when the probe
offset
is
is
then
the gain was
the
range
in
is now set
the output
(100°c).
adjusted,
of
so
of the
that the output of
temperature OP Amp
For the set up this was 7.55
rechecked and adjusted for
voltages are set
for
loaded into the D/A. The BCD value
the slight
v.
The
change when
then the gain is rechecked again until all
right.
The
(0°c) to
temperature
(127°c)
probe is
using a
now calibrated
D/A compare
range of
(00 Hex) to (7F) Hex.
The software
the D/A
and
when to
comparator OP Amp
value
of
program
also displays
turn
tells
the D/ A is
tells
the
the
ON
computer what
or
computer through
equal to
the Low and High
the
are
HEX to BCD.
displayed
light
of the temperature
in BCD therefore
or fan.
on
The
the PIA when the
temperature value.
When the temperature is found it is also
values
OFF the
to output
displayed.
The program
range selected.
All temperature
the program also converts
. 38
07
06
05
To CP11
J;>~
D3
27
1
R2
31-
D1
DO
Al
'34
33
'32
? eset
A7
AS
9
7
Ot·il fii .S"'
. Fan
+5
500ACa 11 hrate
t
3
k
lOK
Offset
~ -15
r.ai'\
3.flv .
-15
6
Fi2ure (5) Application Interface
39
Temp
probe
8
2
White
Violet
11rv
Whtte
Violet
0
~
Orange
7
Blue
Yello\o.·
4
1~914
1~914
200.t\.
Relay
lhht
Lhht
n
200 .(\.
Relay
Fan
Figure (~.) Temp control board
+
Vee
SECTION V
DISCUSSION AND CONCLUSIONS
The main objective of this project was
to demonstrate how a
microprocessor could be used to sense, measure, and control air temperature. A microprossesor was chosen, designed, and built from scratch.
Next a
demonstrative
circuit was
designed and
show how the microprocessor could be used
built. This was
to
to control the air temper-
ature.
The temperature sensor chosen was an inexpensive thermistor.
Since the
object was
to be able to sense and
not for accuracy, economy was
accuracy was
adequate.
accuracy over a
range
used
in choosing
The thermistor is
of (0°C) to
control only; and
most parts.
A+_ 1 °C
linear and it gave
(100°C).
this
However one could have
chosen a better temperature probe for greater accuracy when used in
more critical applications.
The thermistor was
The
a
light
heater.
represented
a
dangerous
cooler.
in front
heating
between a
eleme~t
fan and a
and worked
light bulb.
quite well as
A heating element would have been trore expensive and
probably more
as
a
placed
This
of the
is
for just a
demonstration.
done with a
The fan is used
cup of ice or dry ice placed
fan, which is much cheaper than an air conditioner.
The fan and light also
required smaller amounts of
current than an
air conditioner or a heating element.
The interface
to
PIA I/O device and a
from an R to
2R
the
microprocessor was made of the standard
D/ A convertor.
The D/ A converter was
resistor ladder network.
40
The
resistors were
made
one
41
to five % toleranced. This was enough accuracy for the demonstration.
For rore
complex and accurate
systems
a
D/ A chip
can be used but
it would he more expensive.
The basic idea behind the operation was to set up a temperature /
range.
This
I
temperature range could be changed through programming f
at any time.
I
The range consists of the highest
and lowest allowedf
i
{
terrperature
of the
air around the sensor.
than the highest set value the
fan or cooler was activated to bringi
it back down into the desired temperature
cooler than the
When the air got warme:d
lowest set value
range.
When the air got
the light or heater was activated
to bring it back up into the desired temperature range •
..
The
could be
temperature
changed at
represented
pass
the
any
amount
back within the
turned
off.
range
also had a
time.
of
that
The differential temperature value
change that the air temperature had to
range limits
For example;
differential value
i f the
before
range is
the
fan or light were
set at (50°C) to (60°C)
and the differential is set for (4°C), when the air temperature falls
below (50°C) to
(49°C) the
then rises past (50°C) to
off.
The
When
cooling down
(54°C) where
(4 °C) differential works
temperature passes
turned
light is activated.
off.
The
from (61 °C)
differntial
is
the light would then be turned
for the high range case as well.
where
(60°C) on down
The air temperature
to
the
fan is
(56°C) where
very useful
activated
the
the
fan is then
in this application,
because it prevents cycling of the controllers. When the differential
is set for
range
a
(0°)
and the
air temperature passes above or below the
controller will be activated.
In a
very short time
the
42
temperature would be within the
turned off.
range and the
controller is
then
If the air temperature rises or falls shortly after-
wards the controllers will cycle between ON and OFF. This can cause
current surges in the relays of the controllers and voltage spikes
on the system power supply, possibly causing an IC
Fast cycling of the heating elerrent
chip failure.
or an air conditioner could
shorten their operating lives.
The programwas set up in order that the keyboard could interrupt
the
system operation so that
range
a temperature range and differential
could be placed within the program. The keyboard would then
return the program back to the
If this were not
to be
location where it was interrupted.
provided in the software
the system would have
reset, the proper locations in the program memory would be
changed and then the program must restart again.
All values displayed or entered by the keyboard during operation
of the program were BCD values.
The
microprocessor works with
hexidecimal and binary values, therefore
subroutines
for Hex to
BCD and BCD to Hex had to be generated within the program.
The method
of
obtaining the air temperature was successive
approximation. When the air temperature changes the resistance of
the sensor also
changes,
causing
the voltage drop across it to
change.
This voltage was sent to a voltage comparator.
side of
the
The input
PIA ports.
comparator was
of the D/ A was
When a
PIA the D/A
connected to the output
connected to the output of
digital word was
converted it to analog
The other
of the D/ A.
one of the
placed at the output
and the
of the
analog value was
43
compared to the actual temperature analog value. The output of the
conparator was
value outputed
at
fed
to first
the second port
had changed
the actual
into
that
the
port
other
of
port
of
the PIA.
the PIA the CPU would then look
the PIA to see i f it had
of
For every
changed.
neant that the value sent to the first
temperature at the
tine.
This value was
If
it
port was
then
compared
with the range, proper action was then taken if needed, the temperature
was then displayed and
a
new search
cycle started to find
a
new
air temperature value.
The search
PIA then setting
value was
cycle consisted of clearing the first port of the
the MSB
of the port high.
compared with the
sensor value.
The
resulting
analog
If the value of the port
was higher than the air temperature value the MSB would be cleared
and the next MSB
value was
less
in line would be set high and
than
reuain set high and
they would be
LSB
the air temperature value,
l/256th of the
approxiuations possible.
is the value
This would
If the
the MSB bit would
the next MSB bit would be set high.
compared.
represents
tested.
Together
continue down to the LSB.
analog value
When the LSB
of the air temperature.
The
uaking very accurate
is set and tested this value
This
method
requires only 8
loops of testing the bits making approximations very fast.
Another nethod would be
starting with the LSB,
lOOK for a
change
temperature value
could
take as
add
on the
has
many
as
to
clear the PIA output port then
one bit at
input.
When a
been reached.
255
steps
a
This
time to
change
is a
the
output and
occurs
slow
the air
process and
to find the right voltage.
One
44
problem
that may occur during this process is
may be missed in the search process.
terrperature
value
drops
would
never find
This can happen when the air
below the current test value suddenly,
continue
the
to be incremented to its
proper temperature.
a
8 loop
Using the
If this happens
cycle, not
8 loop cycle
times per second.
accuracy.
if no
nuch
the
This
to the
time is
is
the test
maxinum value and
It would then start
zero starting a new cycle which would add time
search cycle.
that the proper value
over at
to the already long
successive approxirration in
lost and
can be
tolerated.
temperature is updated approximatly 120
nuch
more
than needed
for its
(1°c)
The other method would update about 4 times per second
mistakes are
made.
This
is
probably still fast
enough for
this application.
Future applications for a system such as this could be easily
incorporated using
the
change in interface
hardware.
control an oven for a
has to be grown at
that
same basic microprocessor and
One
silicon
such application would be
wafer company.
a precise temperature.
temperature with a
heating
only slight
to
The silicon crystal
This system could control
element and a vent.
Also a very
sensitive thermistor would be needed.
Another application for home use or industrial use would be
to control the temperature of
each individual room in the building.
This could be accomplished by having a
rooro. The
microprocessor would
conditioning units.
temperature sensor in each
control the central heating and air
It would also control the opening and
of each air vent in the room.
closing
This could be done with solinoids on
45
I
each vent.
Using
this method, rooms in different parts of the same
building
can have different temperatures;
sources.
The
temperature sensors,
This would greatly
reduce
the
cost.
reduce
energy and
cost.
increased;
therefore
In this
the amount
more
of hardware needed and also
modify and
when hardware is
memory
software is
may
less
could be nultiplexed.
this would be
and easier to
However,
instance
and vents
A system such as
conventional methods
with air from only two
operate, saving
reduced
be needed
cheaper than
software is
in the
expensive than the cost
system.
of the
increased hardware needed.
In conclusion this system design worked as well as expected.
The accuracies
obtained in temperature measurment were better than
those anticipated.
be
modified
to
increase in cost
It was
run a
also shown how easily
more
or size.
complex operation
As
time
goes
and ideas will be thought of, using this
the system could
without tremendous
on many more applications
basic design as a guide.
•
46
APPENDIX
SECTION VI
Microprocessor CPU Architecture
The MC6800 microprocessor is a single-chip, 8-bit parallel processor housed in a 40-pin dual in-line package. The microprocessor has a
variable-length stack,
maskable interrupt vectoring,
direct nemory
addressing capability and six internal registers, as well as 72 variablelength instructions and seven addressing modes as shown in figure 7.
3-State Control-39--1
HALT 2----------1
1
CLK
CLK
----~--~-------
Ph1---~31
1
1
1
Ph2--~371
1
1
1
RST------~401
1
1
1
NON-MASK-1 1
1-61
INTPT---~1
1
1
INTPT----1 1
1
1
1
1
1
1
1
1
1
1
EN~361
1
~41
REQ------1
DTA BUS
INSTRUCTION
DECODE AND
CONTROL
A15 ~
~ A8
25 1 •••• 1 17
----1----1---1 OUTPUT
1
1 BUFFERS
1
1
A7 .1
& AO
16 1 •••• 1 9
----1----1---1 OUTPUT
1
1 BUFFERS
1
---------------------------
1
1
---------------------------
---------------------------
1
1
---------------------------
--------------------------
1
1
---------------------------
--------------
1
1
---------------------------
1
1
---------------------------
1
1
1
1
1
1
PROGRAM H 1 1 1
COUNTER
1--1--1
STACK
H1 1 1
---POINTER
1 1 1
INDEX
H1 1 1
---REGISTER 1 1 1
1
1
1
1
PROGRAM L 1
COUNTER
1
STACK
L 1
POINTER
1
INDEX
L 1
REGISTER 1
ACCUMU1
LATER
A 1
1
1
BUS AVAIL<-71
1
VALID MEM~-51
1
1
1
1
1
1
R/W~------341
1
~1---------1
1
1
1
--------------
--------1--------
1~----8-Bit Bus--~1
1
ACCUMU1
LATER
B 1
1 ---------------------1-------1
1 1 CONDITION 1
1
1--1 CODE REG. 1
1 INSTRUCTION 1
1 REGISTER
1
1
1 ------1----------1
1
-------------- 1 ------1------1 DATA
1 1 1
ALU
1
1 BUFFERS
1--1--1
1
---~---~-VCC=Pin 8
26 1 ••••• 1 33
VSS=Pin 1,21
D7 ~
~DO
Figure (7), Microprocessor Architecture
--------------
47
48
Inside the microprocessor are three 16-bit
form the Stack Pointer,
Program Counter and Index Register.
are also three 8-bit registers
There
that are known as the Condition-Code
Register and accumulators A and B.
16
registers, which
Since
the address register is
bits wide, up to 64K words can be directly addressed.
The stack pointer contains a
address
of the next
2-byte register that holds
available location in an external push-down/
pop-up stack (usually part of the external RAM).
placed in the stack,
down one location.
When a word
one location.
is
the
all words
When a word is
previously in the stack are moved
This is referred to as a push operation.
retrieved from
This
the stack,
all words
is referred to a pop operation.
are moved up
The procedure
illustrated in Fig. (8).
AS---1
ASt(--1
-------1-------1
A4
1
1
A4
1
------~------1
AS
1
1
A3
1
1
A4
1
1
A3
1
1
A2
1
1
A3
1
1
A2
1
1
Al
1
1
A2
1
1
Al
1
1
1
1
A1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure (8), Operation of a Stack
In this example, the stack consists of seven registers.
As a word,
let us say that AS is pushed onto the stack, it is placed in the top
register,
and A1
through A4 are moved down one
register.
A pop
49
operation will then recall AS and shift Al through A4 up one register
We
in the stack.
A4 before AS.
should note that
it
is not
possible to recall
The elements are automatically accessed on a last-in,
first-out basis.
The stack is usually used
of the program counter,
to store the contents
accumulators, index register, and other in-
formation necessary for the microprocessor to resume operation after
an interrupt is serviced.
The arithmetic and logic section of the microprocessor (the ALU)
does all the
bit manipulation
conjunction with the ALU,
under instruction-set
the
two accumulators
control.
hold the data
In
that
goes into and comes out of the logic array.
The instruction
control-logic
processor.
register,
array,
manage
along with the onchip decoder and
the
internal
operation of the micro-
Combinations of commands and addressing modes produce a
total of 197 executable instructions that
are assembled in one, two
or three bytes of machine code.
A two-phase
processor.
clock
Using a
controls
all the
1-Mhz clock, each
the
cycle is
timing of the micro1 microsecond long.
A minimum of two cycles are required to execute a single instruction.
On the first
phase
of
a
fetch
cycle,
the
counter are transferred to the address bus.
contents of the program
The Valid-Memory-Address
line then goes high to indicate a valid address is on the
bus.
On
the negative transition of the clock, the program counter gets incremented.
When phase 2 of the clock goes HIGH,
bus.
data are put on the data
(The direction of data flow- to and from the microprocessor is
50
determined by the Read/Write control line.)
Then, when phase 2 goes
LOW, data are latched into either the microprocessor or the memory.
This sequence occurs
every
time
the microprocessor
addresses
a
location and transfers a data word.
Incoming commands go into the instruction register and are then
decoded by the Instruction Decode and Control array, which in turn
controls the ALU.
All the registers and input and output buffers are
interconnected on an 8-bit wide data bus.
The nine
control lines available on the MC6800 package permit
various machine operations or provide special control functions.
Go/Halt line permits you
The
to stop all microprocessor operations when
put into the Halt position (LOW).
The Three-State Control line permits
you to cause the Read/Write line and all the address lines to go into
the OFF (high impedance)
state.
You can then use
the address
bus
for DMA applications.
The Read/Write
line
tells
the peripheral devices whether the
microprocessor is in the read (HIGH) or write (LOW) state.
Three-State
Control line
(high impedance).
peripheral
goes HIGH,
it
A Valid Memory Address
devices
forces
When the
the R/W line
OFF
line tells the memory and
that the information on
the address
bus is a
valid address.
For control of the data bus, two lines are available -the Data
Bus Enable (which enables the bus drivers when it is placed in the HIGH
state) and the Bus Available (which when brought HIGH, indicates that
the microprocessor has stopped and that the address bus is available).
SECTION VII
The Microprocessor
The state-of-the-art of microprocessor
A microprocessor is a general purpose digital processing unit
contained on a MOS-LSI chip.
Contained on the microprocessor chip is
the processing unit itself, a set of registers for temporary storage
and manipulating of data and
microprogrammed,
and
instructions, a control unit--usually
rudirrentary set
of I/0 and
interrupt logic.
The input devices convert
input signals into the proper binary
for the
Some typical devices are analog-to-digital
microprocessor.
form
(A/D) converters, teletypewriter, cassette tape decks, and etc.
An
interface is usually necessary to transform the input data into
the
proper digital form.
Also, output devices convert the binary output
data into a useful form.
Examples of these devices include printers,
tape punches, cathode ray tube (CRT) displays, digital-to-analog (D/ A)
converters,
and
many others.
Frequently,
required for buffering and level
with the
microprocessor unit
write rremory
for data,
several TTL packages are
conversion of
signals.
Required
in any system application are a read/
another memory usually read-only memory
the na.ster control program, and circuits
for performing
I/O operations.
functional blocks of
Figure ( 9 )
shows
the
the required
processor with bidirectional interfacing between each block.
1
PROCESSING
1
1
REGISTERS
1
-------&-------1--------------------------.
-------~-------------~-----1
CONTROL
1
------~------1
I/O
1
Figure (9), functional blocks of a microprocessor
51
for
micro-
52
The design of
microcomputers is
blocks as shown in figure ( 10). Motorola
based on four basic building
supplies a MC6800 Evaluation
module as a means of evaluating the MC6800 in a particular application.
This system consists of a Microprocessor 128 word x 8 bit Random Access
Memory MC6810 (RAM) for the storage of temporary data, a 1024 word x
8 bit Read Only Memory MC6830 (ROM) for the storage of
instructions
and permanent data tables, and cine Peripheral Interface Adapter MC6820
(PIA).
Note
that the entire system has
been implemented with four
NMOS packages from the MC6800 family.
1
1
1
MC6800
MICROPROCESSOR
1
1
1
-----1--------1----1
1
1
1
1
1
1
1
-------------------1
MCM6830
1
~
t-i
1
1
1
1
1
1
}
1
~
i
1---1
1
1
1
1
1
1
1
1
1
1
i
--------------------
1
\
1
1---1
!
ROM
1
1
1
BUS
DATA
BUS
MCM6810
RAM
1
1
1
MC6820
PIA
1
1
1
~
Figure (10), a small MC6800 microcomputer system
Before
describing
the
individual parts
in any detail,
an
53
explanation of the MPU
bus
and
control structure will serve to
demostrate how a system is brought together.
to show
the
processor's inputs
Figure 11 is organized
and outputs in
four
functional
categories; data, address, control, and supervisory.
The width and drive
capability of the Data Bus has
standard means of measuring microprocessors.
( DO-D7 ) bidirectional Data Bus
memory and peripheral devices
to
become a
The MC6800 has an 8-bit
transfer data to and from the
It also has
on each line.
three-
state output buffers capable of driving one standard TTL load and up
to 130 pF. As a result of the
and PIA,
the NPU can drive
load characteristics of the RAM, ROM,
from
7 to 10
family
devices without
buffering.
the
family
Address
Bus
Using
( AO-A15)
the NC6800 system.
but it
becomes
connections
a
I/O interface devices
to assume additional
Not
only does
tool
converse
16-bit
responsibility
I/O devices.
By means
of
Control Bus, and selected address
the I/O interface is allocated an area of memory.
user may
the
in
the Address Bus specify memory,
to specify
to Data Bus,
allows
with I/O using
lines,
As a result,
any of the memory
its
the
reference
instructions, selecting the desired peripheral with a memory address.
The
outputs
are
standard TTL load
is
turned
off,
three-state
bus
it
is
of driving one
essentially an open circuit.
This
drivers
permits
in direct memory accessing applications.
addition to the data and address
the
capable
each at 130pF max. When the output of bus
the MPU to be used
for
drivers
memory and interface
bus,
a
devices.
control bus
is
In
provided
The Control Bus consists
54
of a
heterogeneous
mix of
signals
to
regulate
system operation.
Figure (11) shows a symbolic representation of the MC6800 microprocessor
system with its control and its microbus interface.
+SV
GND
1
1
-----1--------1----1
1
1
1
~US
AVAILABLE
~~~~~-----------------1
~HA~LT~--------------------~1
1
1
1
I
1
>1
THREE-STATE CONTROL
~~~~~~~~~------~·1
~D=AT~A~B~U~S_E~N~AB~L~E~----------7>1
MC6800
NON-MASKABLE INTERRUPT
!
1
1
1
-------------------------71
1
1
02
1
1
1
1
1
1
&
1
1
1
1
1
1
1
1
1
1
1
1
1
1
01
TO/FROM
6800 CONTROL
CIRCUITS
16
DATA
BUS
f'......_ ADDRESS
I~ BUS
1
1
1
1
1
1 VALID MEM. ADR.>
1
1
1
1 READ/WRITE
>
1
1
1
1
RESET
~l'-..,.
1~
INT.REQ
RESET
TO/FROM
MEMORY AND
PERIPHERALS
Figure (11), MC6800
Phase
one
are applied to
inputs of the
( 01 ) and phase two (02) are the system clocks that
the MPU.
family
02 is also applied to the enable or chip select
parts
to insure
that the
devices are enabled
55
only when the Address Bus and Valid Memory Address (VMA) are stable.
The MC6800 has three hard ware interrupts which are Reset (RES),
Non-Maskable Interrupt (NMI) and Interrupt Request (IRQ).
based interrupts
such as
can be incorporated
the
Software-
SWI and the WAI (wait for interrupt)
into a program.
Except for
the RES input, all
interrupts cause the MC6800 to store the current contents of the useraccessible
registers (accumulators A and B, index register, program
counter,
and condition-code
known as
the
stack - a
register in read/write memory locations
last-in first-out
memory space.
A stack-
pointer register assigns the contents of the stack to seven sequential
locations and is used to retrieve the contents of the register after
the interrupt is serviced.
RESET, a low activated signal, is used to reset
MPU from
a
power
down
PIAs forinitialization.
condition,
and
and start the
to reset the inputs of the
If a positive edge of the clock is detected
on the input, this will signal the MPU to begin the restart sequence,
and
begin execution of a
its reset condition.
to go high.
routine to initialize the processor from
It also forces all the higher order address lines
For the restart,
the
last two address locations (FFFE,
FFFF) in memory will be used to load the program that is addressed by
the program counter.
During the restart routine, the interrupt mask
bit is set and must be reset before the MPU can be interrupted by IRQ.
The initialization of the microprocessor after restart is shown
in figure (12). Reset must be held low for at least eight clock periods
after thesupplyvoltage reaches 4.75 volts.
to the
leading edge of
02,
on the next
01
I f Resetgoes highprior
the first restart memory
56
vector address (FFFE) will appear on the address lines.
should
contain the higher order eight bits
program counter.
This location
to be stored
into the
Following, the next address FFFF should contain the
lower order eight bits to be stored into the program counter.
~
1
¢1 vee
_IL-rL___!Lil_l u
--1
~
I' n_n
- ' ,_ ,_
-
n-
n ·-n· -II-
rl
-
07
[Ln_ILJI_I_U_I_fl_!-\~llr-L1LSIJ,\~rl_n_
.
I'
II
':• ·~ st
y
RESET
instru•
ct ton 1 oaded
· into NflJ
1I
1 ,
--~~~~------~
~-------· ~8
clock times ------------~~~
7I I Ill! I I I I I I I I I I I 77I I I 1 I II / I / '0-
I
+1
V?v!A
/<1+
1
Address out
I
•
----'
Address
out •
contents
:: FFFE
FFFE
Address
+
out::F~<'FF
FFFF
Figure (12), Initialization of MPU after restart.
Interrupt Request is a level sensitive input that
interrupt sequence to be generated within the machine.
will wait
until it completes
executed before
it
the
At that time,
if the
the
sequence, and the Index Register,
Accumulators, and Condition Code Register will be
stored away on the stack.
request by setting
request.
being
Condition Code Register is not set,
machine will begin an interrupt
Program Counter,
The processor
the current instruction that is
recognizes
interrupt mask bit in the
requests an
Next the MPU will respond to the interrupt
the interrupt mask bit high
so
that
no further
57
interrupts may occur.
At the end of the cycle, a 16-bit address will
be loaded in two 8-bit bytes that point to a vectoring address which is
located in the last fewmemory locations FFF8 and FFF9, (see table Ill).
An address loaded at these locations causes
the MPU to branch to an
interrupt routine in memory.
Non-Maskable
input
Interrupt
mentioned earlier,
regardless
is
similiar to the interrupt
except that NMI will always
be
of the state of a programmable interrupt mask
within the processor.
request
serviced
contained
A low going edge on this input requests
a non-mask-interrupt sequence be generated within the processor.
with the
current
Interrupt Request
As
the processor will complete
the
instruction that is being executed before it recognizes
the
NMI signal.
signal,
that
The interrupt mask bit in the Condition Code Register has
no effect on NMI. The Index Register, Program Counter, accumulators,
and Condition Code Register are
end
of
the
byte that
cycle,
points
a
stored away
16-bit address will be
to a vectoring address which
on the stack.
At the
loaded in two 8-bit
is
located in memory
location in the last few memory locations FFF8 and FFF9, (see table
Ill).
An address
loaded at these
locations causes the MPU to branch
to a non-maskable interrupt routine in memory.
Inputs IRQ and NMI are hardware interrupt lines that are sampled
during 02
following
clock and will start the interrupt routine on the
the
completion of an instruction.
interrupt vectors is shown next page:
The memory
01 Clock
table
for
58
CONTENTS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADDRESS
RES (low b~te)
FFFF
RES (high b~te)
FFFE
NMI (low)
FFFD
NMI (high)
FFFC
SWI (low)
FFFB
SWI (high)
FFFA
IRQ (low)
FFF9
IRQ (high)
FFF8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 1, Memory table for interrupt vectors
The Read/Write
whether the MPU is
line
in a
tells
the peripheral and memory
Read (HIGH)
or Write
(LOW)
normal standby state of this signal is Read (HIGH).
state control line goes high, it forces
devices
state.
The
When the three-
Read/Write to
the OFF (high
impedance)
state.
Also, when the processor is halted, it will be
in the off
state.
This TTL compatible output is capable of driving
one standard TTL load and 130pF.
Valid Memory Address (VMA) line tells the memory and peripheral
devices that the information on the address
Also, VMA indicates
read or write
bus is a valid address.
to memory and I/O that the MPU is performing a
operation in a given cycle.
This signal is applied
to the enable or chip select input of each family device in order to
disable
data transfer when VMA is
In normal operation,
this
signal should be utilized for enabling peripheral interfaces
such
as PIA and ACIA.
This signal
low.
is not three-state; one standard load
59
and 30pF may be directly driven by this active high signal.
Data Bus Enable
(DBE)
is
the
the MPU data
bus and will enable
state.
input
This
driven by
MPU read
data
When it
as in
is
the
bus
is TTL comatible;
this signal would bE
cycle,
three-state control signal for
the
desired that
bus
however,
in normal
operation
the phase two (02) clock. During an
drivers will be disabled internally.
another device
Direct Memory Access
drivers when in the high
control the
( DMA) application,
data
bus such
DBE should be held
low.
Three-State Control
( TSC )
affects
the address
R/W line in the same manner that DBE controls
input causes all
go into the
500 ms
off
of the address
or high
after TSC=2 .4v.
lines
the
This
phase
one
clock.
high state and the 02 in the
properly.
The
01
to
occur
and Bus
The Data Bus is not affected
by TSC and has its own enable (Data Bus Enable).
the
( VMA)
This
line
state will
The Valid Memory Address
the three-state cant rol line should be
and the
bus.
and the Read/Write
impedance state.
Avaialable signals will be forced low.
edge of
data
bus
In DMA applications,
brought high
on the
clock must be held
leading
in the
low state for this function to operate
The address bus will then be available
for other devices
to directly address memory.
Halt is a level sensitive signal.
the MPU will stop all processing •
When Halt is low activated,
In the Halt state the machine
will stop at the end of an instruction, all three-state signal will
be in high impedance state (address, data and R/W), VMA will be low,
and Bus Available will be high.
Transition of the Halt must go high
60
for one phase one clock cycle.
Bus Available
MPU, is
the
instruction,
of
the Halt
indicating
that the address
drivers
their normally
of
is
the
Available will
state
by
that
inactive
the
brought high by
At
a wait
stopped and
such times, all three-state
state and
If the MPU has
other outputs
to
stopped as a result
Bus Available will remain high untill the Halt
If
occurs.
the MPU has
stopped as
a
result
It is waiting for an interrupt and Bus
remain active
The
until a
non-maskable interrupt
processor is removed from
occurance of a maskable
maskable interrupt.
is
the microprocessor has
level.
instruction,
request
It
low or by execution of
will go to their off
again taken high.
wait
interrupt
input
bus is avaialble.
of the Halt signal,
input
the Bus Available output signal from the
normally in an inactive low state.
occurance
output
(BA),
(mask bit 1 or 0)
or
the wait
or non-
Bus Avaialable may be used to signal external
hardware that the MPU is off bus for multiprocessor or Direct Memory
Access applications.
SECTION VIII
Memories
Another system advantage
byte-organized
systems.
family
memories
Just
designed to
as useful
nemories
of the MC6800 family is
maximize efficiency
in sone situations is
also fit
in,
the set
usually without
the
of
in many
fact that
sacrifice.
non-
MC6800
implementation is enhanced by availability of bus oriented memories
with 8-bit
organization and 5-V operation to match the basic system
philosophy.
devices
as
Motorola
part
of the
directly
two word
microprocessor family:
These N-channel MOS
the 1024X8 ROM.
operate
currently provides
from the
bus
memories,
system and
oriented
nemory
the 128X8 RAM and
both RAMs and ROMs,
require no additional
components in most MPU applications.
Program steps
and
data
Dllst be stored and
recalled at the
appropriate time in order for the computer to perform its function.
The ROM
is
used to
store
and
program steps
It is
difficult
tine consuming
it is
used in situations where
the
and
constant data values.
to write into ROM;
nemory values
for example in dedicated systems.
Read/write
to store data which
changes
the
for example,
of
results
during
caculation,
therefore,
do not
change,
memory RAM is used
operation of the
systems,
or programs which are changed
frequently.
The
two
classes
of
RAM are
static and dynamic.
A static
RAM stores each bit of information in a flip-flop, and this information
is retained as
long as
power is
supplied to the circuit.
Dynamic
RAMs are devices in which the information is stored in the form of
61
62
charge on the
electric
transistor.
element
This charge dissipates in a
must
be
Block diagrams· of
respectively.
permitting
refreshed
the
Notice
(E)
capacitance of a
MOS
few milliseconds, and the
(capacitance
recharged)
periodically.
RAM and ROM are shown in figure
(13) and (14),
that the
the memory
system data bus.
enable
gate-to-substrate
data
data signals
lines have three-state buffers
to wire-or directly on to the
Address decoding is minimized by providing multiple
or chip
select (CS)
inputs.
The enable
inputs,
when
active, select the specified device as defined by the address inputs.
The memories
compatible.
operate from
a
single 5V power supply and are TTL
Here are the family memories:
MC6810 RAM BUS INTERFACE
The MC6810 RAM is organized as a 128X8 bit memory and designed
for bus-organized
systems.
no clocks or refresh.
data bus,
three-state
The RAM is a static unit
It has TTL-compatible inputs,
I/O bus,
negative and two positive
chip-enable
achieved with six chip select
activated
chip
selects
address
on
lines.
inputs.
the
requires
A bidirectional
read/write and four
Memory expansion is
The four low and two high
MC6810
partial address decoding in the system.
operation of the memory element
lines,
and
are also used to provide
From a
terminal standpoint,
can be described
in terms of two
cycles, a READ and a WRITE cycle. In order to read a bit of information
stored in the memory requires the following steps. 1) The Read/Write
line is
placed
in a
READ
state.
2) The address of the memory cell
to be read is loaded onto the Address Lines. 3) The memory is enabled
by applying
the proper level to the
chip select line.
4) After a
63
length of time required to propagate the information to
the bit is read from the Data Out line.
the output,
The WRITE cycle is similiar
to the READ cycle with the exception that the Read/Write
reach the WRITE state only after the address
a time sufficient for the address
Steps in the WRITE
which the
to propagate
cycle areas are as
is
follows:
applied
been applied for
through the memory.
1) The address at
bit
is
to
2) The memory
is
enabled by applying the proper level to the chip
select line.
be stored
has
line must
to the Address Lines.
3) A pulse is applied to the Read/Write
bit to be written is applied to the Data In line.
line.
4) The
Figure (13) shows
the MC6800 RAM functional block diagram.
AO
1
",1
1'-----,z>il'l
1
7 .__1
~1
1
A
1 ADDRESS 1
D A2 1 DECODER 1
1
R.__1
~1
1
I
1
1
NcM-1
1
p.
1
1
T AS 1
1
S.__l
1
A6 1
1
e---1
1
1
1
1
1
1
1
1
1
1
1
>,1
7
1
1,..
...,1
7 1
l.<E-.;;:::'-----31!
MEMORY
MATRIX
(128X8)
~
CS4 - - 1
1 1
1
CS3
-vv
f'-..,.,. _ _
CS2
CS1
1
1 1
"i
~<
cso
1
t{>J
1
1
1" • • • "1
----1-----1---1
1
1
D-r-1
MEMORY
1
CONTROL
1
1
1
1
1
1~
8
1<
~
~
l l THREE-STATE 1
D
),.....
-1
BI
1- D2 A
1"'"
DIRECTIONAL ~ T
1,....
~ TTL BUFFERS 1_ D3 A
l""'l
~
1<
>1
~B
1
1
1
u
1...,...
-1
L D5 S
1-..;;:~
~
1,......,,1
L D6
7
1-..;:1
~
---~----~---
css
1 _ DO
>~
~
-------1------1
1
1
1
1
______1 _______
READ/WRITE
Figure (13), MCM 6810 RAM functional block diagram
64
MCM6830 ROM BUS INTERFACE
Read-only
memory
forms
an important
non-volatile;
is
malfunction does not
ROMs have
for example,
change
of
The ROM,
requirement in most microcomputer systems.
memory
part
loss
of
the
being a
memory
fixed
power or system
the contents of the memory.
Also, most
the feature of random access, which means that the access
time for a given memory
locations.
As
ROMs
in many forms.
exist
a
location is
result
of the
the same as
recent
The
advances in IC technology,
technique
information in the ROM (called programming)
method for
classifying all ROMs
The first
category
consists
into one
of
ROMs
as specified by
employed for storing
provides a convienent
of the
that
or masked programmed when manufactured.
that for all other
are
three categories.
custom
programmed
These ROMs are programmed
the user during fabrication and
cannot be changed
after packaging.
A second
category includes
A common form
the user.
which can be modified by
have
the
contents
ROMs which are
of this
the user.
type
programmable by
of ROM uses
These ROMs,
of the memory permantly fixed
fusible
links
once programmed,
as
those of the
first category.
The
third
category of
programmable again and
often referred to as
type
of ROM is
electrical,
ROMs
again.
PROMs
and
reprogrammable
optical,
etc.,
either static or dynamic.
consists
of those which are
These are reqrogrammable and are
read-mostly memory
in
(RMM).
This
an off-line procedure using
techniques.
Semi conductor memory is
Information stored in static memory,
65
requires
in general,
Dynamic
is
The MC6830 ROM
1024 bytes
clock and
refresh.
It
by 8-bits memory and
The ROM is a static unit
bus-organized systems.
lines as
retain this
cycle which must performed periodically.
a
however,
to
circuitry for a
organized as
memory,
circuitry
requires
information.
refresh
no additional
is
shown in figure
mask
(14).
and
requires no
programmable and has
four enable
The Chip
used to enable the outputs DO through D7.
for expanding
the memory size
designed for
Select
(CS) terminal is
This terminal is necessary
by employing multiple ROM
••A_O_ _~----------~--_,.~---------~
circuits.
~----------~--D~Cj.
7
10
A
D
D
R
E
S
s
I
N
P
u
T
S
••A_1_ _1
1 ADDRESS
A2
1 DECODER
0
1
A3
1
0
1
...A_4_ _1
0
1
AS
1
1
OA6
1
o-_- - - 1
0
0
0
A7
1
1
1
1
1
A8
A9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MEMORY
MATRIX
l ___~;J
ll
1
,I
1----;;oo:-71
1
>1
1
1
1
;}
1
1
1
~
1
1
1
-1
1
'1
1
1
1
1
1
: __________:----,)>~~----------~
cso* E*___11_ _ _ ___
CS1
E*
1
1
CS2
E*
1
THREESTATE
OUTPUT
BUFFER
1
1
Db>
1---7
1
1
D)
1
1
1
D~
1
1
1
D~
1---~~
>1
1
>1
1
1
~----r
1
1
D;
1--~
1
1
D~
___:---:7'
1
1
1
~------------
Figure (14), MCM6830 ROM functional block diagram
D
A
T
A
B
U
s
SECTION IX
MC6820 Peripheral Interface Adapter
The totally unique PIA is a univeral interface between peripheral
equipnent and the
interface
to the
MPU
bus.
Various
outside world
peripheral
of connecting byte-oriented peripherals
of
used to
can be controlled by software.
MC6820 Peripheral Interface Adapter (PIA)
relatively
circuits
provide a
to
The
flexible nethod
the MPU. The PIA, while
complex itself, permits the MPU to handle a wide variety
equipnent
types with
programming.
The PIA can be
and controls
busses,
additional logic
and
simple
tied directly to the MPU data, address
and transfer signals
the MPU under program
designed to provide
minirrum
control.
16 bits of
between peripherals
and
The PIA in the MC6800 system is
external
interface and four control
lines at addressable locations in standard system memory. Naturally,
the
I/O bits are
accessed
peripheral data buss,
to act
as
and each I/O bit
either an input
All operating
in two words
of 8 bits
bidirectional
is individually programmable
or an output as shown in figure
characteristics
of
the
interface are
( 15).
established by
writing from the processor to the Data Direction and Control registers
of the PIA. This is required at the tine of system Reset and permitted
at any other time.
1
1
MPU
1
1
1
----i-------_-_--&-:-l-_-_-_-_-+_1:--------------:J~l
DATA
1
1
;>;1
ADDRESS!.-------~.,_1
CONTROL
1
PIA
t
CONTROL
1 (8) PERP~
1 (8) DATA >
1
1 CONTROL
Figure (15), MPU Parallel I/O Interface
66
>
67
The
MPU/PIA
interface
consists
of three elements:
8 data
lines, 5 address lines, and 5 control lines as shown in Figure (10).
The data
lines are bidirectional common to the MPU data
PIA taps off 5 bits from the 16-bit MPU address bus.
are utilized to select the PIA (CSO, CS1,
within the PIA (RSO and RS1).
CS2)
bus.
The
These 5 inputs
as well as registers
The register select lines
(RSO, RS1)
in the PIA serve the same purpose as the address lines do in a memory.
For this
reason,
order address
they are normally connected directly
lines of the system.
the PIA's internal
address
registers
bus using
the MPU' s
point
these
of
that are treated
The MPU
by addressing
to the
can read or write into
the PIA via
the system
five input lines and the R/W signal.
view, each PIA is simply
four memory
From
locations
in the same manner as any other read/write memory.
The PIA uses all of the signals on the MPU control bus.
R/W input ties
of data
also
flow.
Other lines
protect the device
not used
in the memory interface are
from a spurious read
cycle with no intended memory reference.
a read operation can change
IRQ line
operation during a machine
This is necessary, since
The PIA has two
ouputs that may be wire-ORed together
of the Control Bus
circuitry.
( 16). VMA is used to
the state of the PIA.
independent Interrupt Request
to prioritizing
The
directly to the MPU R/W output to control direction
shown in the PIA interface in figure
and tied to the
low-
Since
or applied separately
the PIA may be used to
detect
incoming interrupt signals on any of its cont rollines, this connection
must
be
processor.
made
in order to initiate
the interrupt
sequence at the
The IRQ will be pulled down by the PIA following detection
68
of an active transisition on any control line which has been enabled
as a system interrupt.
I t will hold IRQ down until the
is serviced.
Thus
even if
interrupt mask is
the
input may be
no interrupts will ever be lost
tied
directly
the PIA
to an all
provides
a
Enable
timing signal
(E)
control
zero
set
in the system
at the processor.
to the MPU cant rol bus
condition when
required.
interrupt
The Reset
to initialize
The MPU also
to the PIA via the Enable input.
The
pulse is used to condition the PIA's internal interrupt
circuitry and for the timing of
Since all data
transfers
take
place
peripheral control signals.
during the
02 portion of the
clock cycle, the Enable pulse is normally 02.
1
1
1
1
1
1
MPU
----~--~--~---1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
!
1
1
1
DATA
1
1
1
1
ADDRESS 1
1
1
1
1
1
.l
1
1
CONTROL
-----------------------1
DO
Dl
D2
D3
D4
l D5
l D6
l D7
'1
1 cso
l :1 CSl
>1 CS2
1 RSO
). ~1 RSl
1
1
'1?1 E
~1 R/W
1! 1 IRQA
~1 IRQB
1 RESET
i
PIA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-----------------------
Figure (16), MPU/PIA Interface
69
The "peripheral side"
directional data buses
control
lines,
CAl,
of the PIA includes
(PAO-PA7 and PBO-PB7),
CA2,
CBl,
and
CB2.
All
two eight-bit bi-
and four interrupt/
of the
lines on the
"peripheral side" of the PIA are compatible with standard TTL logic.
In addition,
all lines
PIA ( PBO-PB7,
CBl,
serving as
CB2 ) will
output
supply
up
on the
"B" side of each
to one milliamp of drive
current at 1.5 volts.
An expanded block diagram of the PIA is shown in figure
The PIA is programmable in the sense
Write into its internal
i~
registers
t:.h~
registers.
PIA.
(17).
that the MPU can Read and/or
There are a
The PIA is
total of six
internally divided
8~pit
into
symmetrical (noted as A and B side), but independent, circuits
two
that
consist of three circuits each.
Each half contains a Data Direction
Register,
a
and an Output Data Register.
registers
are
is these
Control
Register,
eight bit wide and are externally controllable.
registers
that the MPU treats
It
as memory locations, i.e.,
The Output and Data
they can be either read from or written into.
Direction Register on each side represent
a single memory
location
to the MPU. Selection between them is internal to the PIA and
determined by a
The
bit in thier Control register.
is
The Data Direction
Register (DDR) are used to establish each individual peripheral bus
line as
either an input
having the
of the DDR.
or an output.
This is
MPU write "ones" or "zeros" into
Zeros or ones causes
accomplished
by
the eight bit position
the corresponding peripheral data
to function as input or output, respectively.
The output
register,
ORA and ORB,
when addressed, store
the
70
data present
on the MPU
Data Bus
during an MPU write operation.
This data will also appear on those peripheral lines that have been
programmed
as
as an input,
If a
output.
the corresponding bit
can still be written into
influenced by
line.
peripheral line has
by
been programmed
position of the output
the MPU;
however,
the
the external signal applied on that
register
data will be
peripheral data
During an MPU read operation, the data present on a peripheral
line programmed as
Data Bus.
Due
an input is
to
differing
positions programmed as outputs
transferred directly
circuitry,
to the system
the results of
differ slightly
reading
between side A and
B of the PIA. On the B SIDE, there is three-state buffering between
Output Register B and the peripheral lines
read the current
such that the MPU will
contents of ORB for those bit
positions programmed
as output.
The
two
control
registers,
establish and control the
lines,
CAl,
CA2,
CBl, and CB2.
devices.
To define
an eight-bit word is
and
define
loaded into
the actual
to be
PIA ouput data register.
together as
PIA is
by means of these
the
follows:
four lines
operation of the PIA A or
loaded into the Control
the PIA/peripheral data
an 8-bit word is
data
It is
control
passed back and forth between the MPU
B side,
to
allow the MPU to
operating modes of the peripheral
that control information is
and peripheral
CRA and CRB,
lines
as
input
Register;
or output,
the Data Direction Register.
transferred
to peripherals
goes
Finally
into
the
Basically the PIA and microprocessor operate
When the interrupt
read into accumulator B of
occurs,
the B side of the
the microprocessor.
Then the
71
A side
of the PIA is
read to define
the memory location of where
the data stored in accumulator B should be placed.
transferred from the accumulator to
Next the data is
the memory location, and then
the microprocessor goes back to waiting for another interrupt.
11 shows the MC6820 PIA bus interface.
l
-
~nO
CAl
rCA2
Figure
A
Controls
DO-DO
1
1
Dl-Dl ~11 Control Reg
11 11 11
1 ~PAO
D2-D2 ~11
11 11 11
A
1 BPAl
~11 Data direction 1 ~PA2
11 11 11
A
/D3-D3
D4-D4 ~1
1111 11
Reg A
1 ~PA3
Data
11 11 11
D5-D5 ~1
~PA4 Interface
D6-D6 ~1
1111 11
~PAS
D7-D7 ~
11 11 11
~~PA6
11 11 11
~
~~PA7
11 11 11
Data Reg
1 1
AO-RSO __::;,._1 1
1111 11
1
1 1
A
Al-RSl
11 11 11
1
A2-CSO ~1
1111 11
1
1
1
11 11 11
11 11-11
1
11 11 11
1
11 11 11
1
1
11 11 11
1111 11
1
11 11 11
A14
1
1
1111 11
VMA
1
1
11 11 11
02-E
Control Reg 1 ~PBO
:;:1 1
11 11 11
1 1
B
1 ~PBl
11 11 11
B
R/W-R/W~l 1 Data Direction 1 ~PB2
1111 11
1 1
Reg
B
1
l~PB3
Data
-- -11 11 1~ RST- Rsr__;
L.PB4 Interface
1111 1
k--7PBS
/
1
11 11 11
_
IRQA<
1
~PB6
1111 11
IRQ<__
1
k--7PB7
11
1 1
Data Reg
1 1
IRQB <
v11
11 11
1 1
1 1
B
11
+SV
1
Data
Bus
11
1
Address
GRD
1
Bus
1
1
Bus
B
Control
LcB2
CBl Controls
Figure (17), MC6820 PIA Bus Interface
--i
>\CSI
>~
Al:~l
\7
i
\1
:J
i
72
Motorola has
to accommodate
also
made available a serial interface device
asynchronous
data
interfaces, the MC6850 Asynchronous
interface.
For serial-data
Communication Interface Adapter
(ACIA) can provide serial-to-parallel data conversion.
simplify
the
It
can also
interface requirement between the microprocessor and
such serial devices
as
modems,
typewriter terminals
and printers.
The ACIA ties into the MPU Address, Data, and Control Busses enabling
the MPU to handle the serial I/O using memory reference instructions.
The MPU/ ACIA interface
consists
of three elements:
4 address lines, and 3 control lines.
common to the MPU data
bus.
sixteen MPU address signals
are used to select a particular ACIA (CSO, CS1,
figure
( 18)
are Read/Write
is common to
(R/W)
the MPU control bus
in a typical application is
the
lines,
The data lines are bidirectional
Four of
the register within the ACIA (RS).
8 data
The
CS2), and to select
control
and Enable
signals
(E).
The R/W input
R/W signal, and the
02 clock.
shown on
enable input
In this project the ACIA
has not been used.
1
1
MP U
1 1
1 1
1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
Data
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
1 1
1 1
1 1
Address
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
1
1 1
Control
1
1
~
?> 1 DO
I~
; 1
1
1
7 1
7
::;:.1
1
7
1
;1
~1
---71
1
>1
<E-- 1
1
1
Figure (18), MPU/ACIA Interface
D1
D2
D3
D4
D5
D6
D7
cso
CS1
CS2
RS
R/W
IRQ
E
A C I A
1
1
1
1.
1
1
1
1
1
1
1
1
1
1
1
1
73
Temperature Interface Program
The over all idea of this program is to control the interface
hardware.
It also provides capability,
to
the programer,
to change
the temperature variables and "differentials, with minimal interuption
of system operation.
values
The
and BCD values
program also converts HEX values
to HEX values.
to BCD
The BCD values are used for
real world input and output temperature values. These BCD values are
converted to HEX values, which the microprocessor can understand and
use in its calculation.
The program
activate.
tells
the
interface which
The fan for cooling and the
are activated
or deactivated
by a
control
device
to
light for heating. When they
software,
compare of
previous
stored values and values received from the interface hardware sensor
is also done by software program. The software program also controls
the output display of the
three
range and actual temperature.
proper key
to initiate a
programer to make
temperature values,
high range
low
The key board is also scaned for the
software interupt.
temperature range
This will
inable the
changes' without having to reset
the entire program.
The program is versatal
range may be utilized and
enough so
control
only a few more program steps.
of
a
that
a wide
temperature
few more outputs would add
74
(:oacC'rL, TH
'
I
I
I
I
I
THD
TLD
= TH= TL +
TD
TD
T'
I
I
I
I
I
I
I
I Converts loaded BCD values to HEX I
I
I
f---~-------;..1
I
I
I Clear binary results I
I
I
I
I
I
I
I
I
I
I Load hundreds digits I
I
I
I
I
I
I
I -----------~1
Yes
I
I
I
I
I
I I
I Load tens digits I
I
I
I
I
I
I
I
I
I
II
Yes
II
I I Decrement hundreds digits I I
f
II
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
II
I
I
I
I
Store hundreds digits
I
I
I
I
I
I
I
I
I
I
Load binary result
I
I
I
I
Add 100 10
I
I
I
I
I
I
I Store binary result I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I No
I Load binary I
result
I
i
I
I
I
I
I Decrement ten I
digit
I
I
I
I
I
I
I
I
I
I Add units
digits
I
I
I
i
I
I Store tens digit I I
I
I
I
I
I
I
i
I I
I Load binary result I I Store binary I
result
I
I I
I
I
I
I
I
I
I
I
Add 1010
I
I
I
I
I
I
I
I Store binary result I
I
I
I
r
8
75
I
I
I Initilize interface I
I
PIA
I
~I~------~~--------I
I--------------~I
I
I
I Approximation routini
I
I
I
I
I
I
m
I
I
I
0
I
I
I
I
Clear WA and load into D to A I
~I~------------~--------------- I
1-------------~-----------~----I
I
I
I
I
I
I
I
I
I
I
I
BO = 8 - m
I
I
I
I Set bit BO = "I" I
I
I
I
i
~
I
I
I
I
I
I
Read temp convert bit from PIA
~--:=:_____~__
m_~-----I
c_l_e_a_r_b_1_·t__s__-__
X
~
i
I
I
II
I
I
I m=m+l
I
I_______I _______ I
I
I
I
I~______________I
I
I
~----------------~
No
~
~-m~y
~
I Yes
~---------------
I
I
I
I
I WA = TA I
I
I
cb
76
y
I
I
I
I
Read TA
I
I
I
I
I
~Yes
1------------- I
~---------"---i
Turn fan ON
i-------~
I No
I
I
I
~ Yes
I
~-------------i
i
i----1
I
Turn light ON
I No
I
I
I
~ Yes
I
~------------i
i
I
Turn fan OFF
i----~
I No
I
I
I
I
Yes
I
--------------I
I
I NO
I
I
I
I
ConverfTA HEX to BCD
I
I
I
I
I
0
I
Turn light OFF
I
I---~
I
I
77
cp
I
I
I Clear hundreds digit
I
I
I
Clear ten digit
I
I
I
I
Clear unit digit
I
I
r~-------"-7>!
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Load binary number
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Subtract 10010
I
I
I
I
I
i
I
I
I
I
I
I
I
I
I
I
fr======~
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I Load binary
I
number
I
I
I
I
Subtract
I
1010
I
I
the
I
I
I
I
I
I
I
I
Yes
I
I
No
I
I
I Store binary I
I
number
I
Is
I
I
Yes
he result
I
negative
I
I
digit
Load
tens
I
I
I
I
I No
I
I
I
I
I
I Increment tens I
Store binary number I
I
digit
I
I
I
I
I
I
I
I
I
Load hundred digit I
I Store tens digit I
I
I
l--=-------I
I
I
Increment hundreds digit I
I
I
I
Store hundred digit
I
I
I
I
I
I
I Load binary!
I
number
I
I
I
I
I
I
I Store in I
I unit digit I
I
I
I
I
I
IClear display!
I
I
I
cb
78
cp
I
I
I
I
I
I
Load display
TL , TA , and TH
I
I
I
I
I
I
I
I
I
I
I
Scan key board
for interupt
I
I
I
I
--------~I~--------
I
Di~
interupt
occure
~~---------------~
I Yes
I
I
I
I
Fan and light latched
to present status
I
I
I
I
I
I
I
I
I
Call EPA up routine
I
I
I
Wa
Approximation word loaded into D to A
B0
Operating bit of WA
TB
temp
bit set, indicates if WA is grater than TA when
analog compared.
Examin, Forward, Backward, and Change keys can be used to
change TH , TL , or T0 without restarting whole program. Returen
from interrupt key 8 restarts program where it left off.
79
Temperature Interface Program
Temporary Registers
0000
Heat ON point
(BCD)
Low Temp
0001
Fan ON point
(BCD)
0004
Differential
(HEX)
0005
Heat ON
0006
Fan ON
0007
D/A out
0008
Pointer
0009
BCD to HEX in
OOOA
BCD to HEX out
OOOB
HEX to BCD in
oooc
HEX to BCD out (units & tens)
OOOD
HEX to BCD out hundreds
OOOE
HEX to BCD out tens
OOOF
HEX to BCD out units
0010
Display digit 1 & 2 (HEX) in
0011
Display digit 3 & 4 (HEX) in
0012
Display digit 5 & 6 (HEX) in
0013
Display digit control
0014
Pointer
0015
Pointer
High Temp
0002
0003
(HEX)
(HEX)
80
Temperature Interface Program
HEX/
ADDRESS
HEX CONTENTS/
INST/DATA
MNEMONICS CONTENT
COMMENTS
Initilize Tenp PIA
0080
CE 81 00
LDX
0083
6F 01
CLR
0085
6F 03
CLR
0087
86 FE
LDA A
0089
A7 00
STA A
008B
86 FF
LDA A
008D
A7 02
STA A
008F
86 04
LDA A
0091
A7 01
STA A
0093
A7 03
STA A
This sets up data
direction registers
within the PIA.
Load HEX Routine
0095
96 00
LDA A
0097
97 09
STA A
0099
BD 01 C3
JSR
009C
96 OA
LDA A
009E
97 OS
STA A
OOAO
96 01
LDA A
OOA2
97 09
STA A
OOA4
BD 01 C3
JSR
OOA7
96 OA
LDA A
00A9
97 06
STA A
Junp to subroutin
that converts BCD
to HEX.
81
HEX/
ADDRESS
HEX CONTENTS/
INST/DATA
MENEMONICS CONTENT
COMMENTS
Clear Display Rout in
OOAB
96 00
LDA A
OOAD
97 10
STA A
OOAF
96 01
LDA A
OOB1
97 12
STA A
OOB3
86 33
LDA A
OOBS
97 13
STA A
This clear the display.
Initialize App roxi rra t ion I
Rout in
OOBS
86 80
LDA A
OOB9
97 07
STA A
OOBB
97 08
STA A
Run Approxirration Routine
OOBD
BD 01 4B
JSR
ooco
7E 01 DA
JMP
OOC3
7D 00 08
TST
OOC6
27 EF
BEQ
OOC8
74 00 08
LSR
OOCB
96 07
LDA A
OOCD
B7 81 02
STA A
DODO
86 01
LDA A
OOD2
B4 81 00
AND A
ODDS
27 08
BEQ
OOD7
96 08
LDA A
OOD9
9A 07
ORA A
This routin finds the
approximation value of
TA by co ll{Ja ring
successive bits through
the D to A converter
and the analog
conparator.
82
HEX/
ADDRESS
HEX CONTENTS/
INST/DATA
MENEMONICS CONTENT
OODB
97 07
STA A
OODB
20 E1
BRA
OODF
7A 81 02
DEC
OOE2
86 01
LDA A
OOE4
B4 81 00
AND A
COMMENTS
Read Te nperature
OOE7
2E 16
BGT
OOE9
96 08
LDA A
OOEB
9A 07
ORA A
OOED
78 00 08
ASL
OOFO
73 00 08
COM
OOF3
94 08
AND A
OOF5
97 07
STA A
OOFA
74 00 08
LSR
OOFD
20 C1
BRA
OOFF
96 07
LDA A
0101
90 06
SUB A
This block takes the
te nperature values and
decides if it is within
the allowed range that
has been selected.
FAN ON
0103
2E 2B
BGT
0105
96 07
LDA A
0107
90 05
SUB A
If te npe ra tu re is not
in the range and is to
high the fan is activated•
83
HEX/
ADDRESS
HEX CONTENT/
INST/DATA
MENEMONIC CONTENT
COMMENTS
Light ON
0109
2D 29
BLT
010B
96 06
LDA A
010D
90 04
SUB A
010F
90 07
SUB A
0111
2F 08
BLE
If the tenperature is not
in the range that is
selected, and is below
the range, it is to cold
therefore, the light is
activated.
Fan Off
0113
B6 81 00
LDA A
0116
84 DF
AND A
0118
B7 81 00
STA A
011B
96 07
LDA A
011D
90 04
SUB A
011F
90 05
SUB A
0121
2F 08
BLE
If light is ON fan should
be OFF and is turned OFF.
Light Off
0123
B6 81 00
LDA A
0126
84 7F
AND A
0128
B7 81 00
STA A
012B
20
If fan is ON light should
be OFF and is ture.nd OFF.
oc
BRA
Fan ON
012D
86 20
LDA A
012F
B7 81 00
STA A
0132
20 05
BRA
84
HEX/
ADDRESS
HEX CONTENT/
INST/DATA
MENEMONIC CONTENT
COMMENTS
Light ON
0134
86 80
LDAA
0136
B7 81 00
STA A
Temperature Display
0193
86 FF
LDA A
013B
97 13
STA A
Ol3D
96 07
LDA A
013F
97 OB
STA A
Display tenperature
of sensor.
Call HEX-BCD
0141
BD 01 8F
JSR
0144
96
oc
LDA A
0146
97 11
STA A
0148
7E 00 BD
JMP
Calls subroutin to
convert HEX-BCD.
Load Display BCD
014B
C6 40
LDA A
014D
80 00
SUB A
014F
97 14
STA A
0151
86 10
LDA A
0153
97 15
STA A
0155
BD F1 BA
JSR
0158
54
LSR B
0159
D5 13
BIT B
015B
2E 05
BGT
015D
7C 00 77
INC
This block loads the
converted temperature
into the display routin.
It also loads and
displays the high and
low tenperature range.
BS
HEX/
ADDRESS
HEX CONTENT/
INST/DATA
MENEMONIC CONTENT
0160
20 OB
BRA
0162
DE 14
LDX
0164
A6 00
LDA A
0166
44 44
LSR A
0168
44 44
LSR A
016A
BD F1 AS
JSR
016D
54
LSR B
016E
DS 13
BIT B
0170
2E OS
BGT
0172
7C 00 77
INC
017S
20 09
BRA
0177
DE 14
LDX
0179
A6 00
LDA A
017B
84 OF
AND A
017D
BD F1 AS
JSR
0180
96 1S
LDA A
0182
4C
INC A
0183
97 1S
STA A
018S
80 13
SUB A
0187
2C 02
BGE
0189
20 CD
BRA
018B
BD F1 C7
JSR
018E
39
RTS
COMMENTS
86
HEX/
ADDRESS
HEX CONTENTS/
INST/DATA
MENEMONIC CONTENT
COMMENT
HEX to BCD
018F
4F
CLR A
0190
97 OD
STA A
0192
97 OE
STA A
0194
97 OF
STA A
0196
96 OB
LDAA
0198
80 64
SUB A
019A
25 09
BCS
Ol9C
OB
STA A
019E
96 OD
LDA A
OlAO
4C
INC A
OlAl
97 OD
STA A
01A3
20
BRA
01A4
Fl
CMP B
01A5
96 OB
LDA A
01A7
80 OA
SUB A
01A9
25 09
BCS
OlAB
97 OB
STA A
OlAD
96 OE
LDA A
OlAF
4C
INC A
OlBO
97 OE
STA A
01B2
20 Fl
BRA
01B4
96 OB
LDA A
01B6
97 OF
STA A
This subroutin converts
HEX values of the temp
conversion to BCD values
to be displayed in
understandable terms.
87
HEX/
ADDRESS
HEX CONTENT/
INST/DATA
MENEMONIC CONTENT
01B8
96 OE
LDA A
01BA
48 48
ASL A
01BC
48 48
ASL A
01BE
9A OF
ORA A
01CO
97
oc
STA A
01C2
39
COMMENTS
RTS
BCD-HEX
01C3
96 09
LDAA
01C5
16
TAB
01C6
84 OF
AND A
01C8
97 OA
STA A
01CA
54 54
LSR B
01CC
54 54
LSR B
01CE
27 09
BEQ
01DE
86 OA
LDA A
01D2
96 OA
ADD A
01D4
97 OA
STA A
01D6
SA
DEC B
01D7
20 FS
BRA
01D9
39
RTS
Key Board Scan
01DA
B6 80 06
LDA A
01DD
84 10
ANDA
01DF
2E OS
BGT
This subroutin converts
the loaded values of the
terrperature range and
differential to HEX
values. These values
will be compared to the
present air te rrperature
value where a decission
can be mde.
88
HEX CONTENT/
INST/DATA
MENEMONIC CONTENT
ADDRESS
OlE!
3F
SWI
OIE2
. 4F
HEX/
CLR A
OIE3
7E 00 80
JMP
OIE6
BD Fl C7
JSR
OIE9
7E 00 C3
JMP
COMMENT
This block scans the key
board for an interrupt •
When key C is depressed
the program is frozen
and EPA up is displayed.
The tenperature range
or differential can be
changed. To get back to
where it left off key 8
is depressed this
eliminates need for
restarting the whole
progra rn.
BIBLIOGRAPHY
I.
"Microprocessors and Minicomputers," Scientific
American, September 1977
2.
"Microprocessors Application," EDN, April 1977
3.
"Microprocessors Design," Computer Design, March 1977
4.
"Microprocessors and Minicomputers," John L. Hilburn,
December 1976
5.
''Microprocessors Application," Computer, August 1974
6.
"Microprocessors," Michael S. Elphick, January 1977
7.
''Microprocessors Family," Fairchild Semiconductor,
Electronics, March 1975
8.
"Microprocessors Application," Motorola Semiconductor,
Decemer 1975
9.
"A new Approach to the Microprocessor MC6800," Kilobaud,
March 1977
10.
"Survey of Microprocessors Reveals Limitless Variety,"
EDN, Ap ri 1 1 9 7 4
11.
"Survey of 8-Bit Microprocessors Reveals Wide Choice for
Users," EDN, June 1974
12.
"The Microprocessor Takeover," Spectrum April 1976
13.
"Microprocessor Design," Electronic Design, April 1977