Practical Course of Design, Fabrication and Testing of CMOS Gate Array YOSHIO MITA, Satoshi Komatsu, Makoto Ikeda, Minoru Fujishima, and Kunihiro Asada VLSI Design and Education Center (VDEC), the University of Tokyo [email protected] Introduction Education of VLSI is important Learning of Electronics with Practical Experience is specially emphasized. Type Title Grade Hour Area Lecture Basics on VLSI Engineering 3rd 21hrs General Lecture VLSI Design Engineering 4th 21hrs Design Lecture Electronics Material Process 4th 21hrs Process Seminar VLSI Layout and Simulation 3rd 18hrs Backend Seminar C-Based Hardware Design 3rd 18hrs Frontend Practical CMOS Gate Array Design and Fabrication 3rd 30hrs Backend to Process Gate Array Practical Course Backend design - Process - Measurement Process: 0.6um 1-layer Aluminum lithography & Etching Schedule 10-days’ course Day Group #1 Group #2 1st - 4th Gate Array Design 5th Visiting In-house Mask Fabrication Facility 6th Process Measurement Preparation 7th Measurement I Supplemental Study 8th Measurement II Supplemental Study 9th Supplemental Study Measurement I 10th Supplemental Study Measurement II Design at VDEC’s seminar room 1st day: CAD literacy, 2nd -4th : Design Practice Bulding Blocks 7 x 7 = 49 building blocks 3 common-gate PMOSFET and NMOSFET Design procedure Design (Virtuoso) Circuit Extraction (DRACULA) Simulation (HSPICE) Examples on Year 2003 2 students consist a group. A group can: design individually, or in collaboration 2bit full adder 7segment LED decoder 2bit ALU (Adder+Multiplier) 6bit adder 2bit comparator Boolean function selector 2bit carry look ahead adder Edge trigger JK-FF 3bit adder with memory 3input AND Process Cleaning + UV exposure (Shipley S1805)+ Etching (H3PO4 +CH3COOH+HNO3) Fabrication Example Inverter Analysis practice Question: measure delay time Typical reply: Impossible, because frequency is low. Input Output : Not many students can find that they are allowed to magnify only rising or falling period... Students who designed too ambitious circuit: Cannot obtain desired output. : Not many students can find that wiring width is large (50um) enough thus direct probing is possible anywhere Failure reasons.. Damaged sample (results open) Particles (results short) Under development/etching Careless scratch (probing error) .. Students can learn typical failures in university laboratories. Portability I MASK fabrication is the key issue. Portability II Glass immersion mask is possible 35mm reversal film could also be used. Conclusions 10-days’ practical course Experience from Backend to Process Maximum 40 out of 120 students can take Students can acquire knowledge on practical problems out of their computer world.
© Copyright 2026 Paperzz