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A New SystemC-based
Foundation for the CE
Curriculum
Ravi Shankar, Professor and Director,
And
Suryaprasad Jayadevappa,
Center for (VLSI and) Systems Integration,
Florida Atlantic University, FL
EWME Session I
April 15, 2004
ES Level Methodology
Intelligent Testbench
IC Implementation Tools
Large Block Reuse
Small Block Reuse
$10,000,000,000
Thin Tall Engineer
$100,000,000,000
In-House P & P
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SOC Design Cost Model
Productvity
Improvement
Of 50+ needed
To hold Dev Cost
$342,417,579
$1,000,000,000
$100,000,000
$15,066,373
RTL Methodology Only
With All Future Improvements
$10,000,000
1985
1990
EWME Session I
1995
2000
Year
2005
2010
2015
2020
April 15, 2004
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Goal: Enhance Design Productivity
• Historical: 1000 fold productivity
increase in the past 20 years.
• Challenge: 100+ fold productivity
increase in the next 20 years.
• Job Opportunity: EDA growth in
2005 primarily from ESL
(Dataquest)
EWME Session I
April 15, 2004
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Paradigm Shift Needed
• Earlier Paradigm:
– Excel in one area of Specialization
• Paradigm Shift Needed:
– Excel in cross-disciplinary Issues
– Take a team approach
– Maintain expertise in one or two areas
– Develop the ability to abstract
EWME Session I
April 15, 2004
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Issues to Contemplate
•
•
•
•
•
•
Technology – Moving Target
Applications – More Demanding
Integration – Real-Time, Low Power
Communication – Multi-Disciplinary
Complexity – Increases Exponentially
Time to Market – Is Shrinking …
Productivity must improve a lot!
EWME Session I
April 15, 2004
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2001- 2016: 30 X increase in Density
1000
DRAM -> 64 Gb / sq. cm
Processor -> 0.3 GGates/sq. cm
100
Log Scale
Gate Length (nm)
SRAM -> 1.2 Gb /sq. cm
Moore’s
Law
2-Year Cycle
Next
3-Year Cycle
10
1995
1998
2001
EWME Session I
2004
2007
Year
2010
2013
2016
April 15, 2004
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Year of production
2001
2004
2007
2010
2013
2016
Process Technology (nm)
130
90
65
45
32
22
Supply Voltage (V)
1.2
1
0.8
0.6
0.5
0.4
Clock Frequency (MHz)
150
300
450
600
900
1200
Required Standby Power (mW)
2.1
2.1
2.1
2.1
2.1
2.1
Battery Capacity (Wh/Kg)
120
200
200
400
400
EWME Session I
April 15, 2004
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Applications will become
more demanding
Year
2001
2004
2007
Target:
Real Time
Still
Image
Video
Codec
Same
Other
App
Email,
Web,
Sched
uler
0.1
Proc
(GOPS)
Power
Allowed
100
mW
EWME Session I
Same,
TV Tel
(1:1), Security
Voice
Recogn
2
15
100
mW
100
mW
2010
2013
Image
Image
Analysis Interpr
2016
Same
TV Tel
(>3:1)
Voice
Activati
on
Same
103
720
5042
100
mW
100
mW
100
mW
April 15, 2004
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3.00
2.50
Power Dissipation:
Reduce by 25 fold.
Power (W)
2.00
1.50
1.00
0.05
0.00
2001
2004
2007
2010
2013
2016
Year
Total Chip Power Tread for PDA Application
EWME Session I
April 15, 2004
100%
Logic Area Contribution (%) LOP
Total Memory Area (%) LOP
90%
80%
Percentage of Area (%)
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70%
60%
Processor Size: Only
3* current Size
50%
40%
30%
20%
10%
0%
Die Size = 1 Cm2
2001
EWME Session I
2004
2007
2010
2013
2016
Year
Power Gap Effect on Chip Composition
April 15, 2004
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Difficult Challenges: Industry Forum
Productivity:
Exponentially increasing design cost.
Productivity to improve by 20 X in 20 years
Goal: 1000 Fold.
Power:
100 mW Average power dissipation, while
processor performance increases 5000 fold.
Power management in OS and HW – MORE
Interference:
Global Communication and Synchronization
Difficult.
Packet-based Networks on Computers.
Next
EWME Session I
April 15, 2004
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Difficult Challenges: Industry Forum
(Continued)
Tolerance:
Relax 100% correctness for computing
and communication. ‘Reusable Parts’.
Lower cost in production & verification.
Reconfigurable Hardware,
Error Detection and Correction,
Communication Protocol
Integration: Address challenges at one point with
solution at another point in design flow
Design for low interference
EWME Session I
April 15, 2004
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Project Effort Myth
E
F
F
O
R
T
SW-HW (Co)-Design
SW-HW (Co)Development
Prototyping
Analysis &
Specification
TIME
EWME Session I
April 15, 2004
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Project Effort: Reality
Prototype
SW-HW (Co)Development
E
F
F
O
R
T
SW-HW
(Co)-Design
Analysis
and Spec
TIME
EWME Session I
April 15, 2004
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Productivity Effort Estimates
As percentage of Time for Product Development
(Typical: 24 months)
Specification
30%
SW-HW Codesign
30%
Verification
50%
SW Development
50%
HW Development
50%
Prototype
25%
(Iterations
50%)
Yes! Activities Overlap.
EWME Session I
April 15, 2004
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Major Productivity Issues
• Communication Across Disciplines
(and Models of Computation)
• Integrated Tool Flow
• Design Automation
EWME Session I
April 15, 2004
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Major Curriculum Issues
• Integrated Design Examples
• Enhanced Curriculum
• Faculty with Cross-Disciplinary
Training and Research Interests
EWME Session I
April 15, 2004
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Specs
Word/Excel
SystemC, UML, and
SHINE Methodology
Specs:
UML,
SDL
Untimed
SystemC
90’s
Transaction Level
SystemC
RT level
SystemC
Verilog, VHDL
RTL level
Verilog, VHDL
Gate Level
Gate Level
SystemC
Polygon Level
SHINE: Our Contribution to
the Productivity Challenge
EWME Session I
April 15, 2004
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Element No. 1. SystemC for
Software-Hardware Co-Design
• Open source language, industry standard
• C++ based; Supports concurrency and modularity
• Abstraction allows tradeoff between accuracy and
simulation speed
• SystemC Verification extensions available now.
• SystemC supports all the modeling paradigms
• Synergy: SpecC, VCC, European SystemC Group
• EDA Industry supports SystemC and SystemVerilog.
EWME Session I
April 15, 2004
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SystemC Language Architecture
EWME Session I
April 15, 2004
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Transaction Level Modules (TLM) for Abstract Modeling
Open Core Protocol
Layer 3 - Message
SystemC for
Software-Hardware
Co-Design
Layer 2 - Transaction
Layer 1 - Transfer
AMBA 2 Transfer
Layer System C I/F
Layer 0 – RTL PHY
EWME Session I
April 15, 2004
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Element No. 2. UML: For
Executable Specifications
• Unified Modeling Language
• Third Generation full life-cycle modeling language
• Incorporates state of the art software and systems
concepts
• Matches the growing complexity of real-time systems
• Extensible and configurable
• SystemC extensions are planned (as per website)
• Can generate executable code (almost)
• Animation for visualization and verification
EWME Session I
April 15, 2004
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Element No. 3: SHINE
SHINE is an acronym for Software
Hardware INtegrated Design
Environment
Unified HW/SW
Representation
System Description
(Functional)
Hardware
Software
HW/SW Partitioning
Hardware
Synthesis
Evaluation
Software
Synthesis
System
Integration
EWME Session I
April 15, 2004
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SHINE: Principles
9 Synergy of Separation of concerns
9 Support Multiple design domains
9 Flexibility and Modularity
9 Ease of use and Scalability
9 Simple Integrated Environment for HW/SW Co-design
9 Support for multiple levels of abstraction
9 Seamless migration from specification to implementation
9 Support for multiple language modules
EWME Session I
April 15, 2004
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Co-design components in SHINE
System Components
Software Components
Applications
Hardware Components
Operating System
Communication Bus
Initiators
EWME Session I
Terminators
April 15, 2004
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The SHINE cockpit
Operating
Operating
System
System
Performance
Performance
Estimation
Estimation
Memory
Memory
Hierarchy
Hierarchy
System
System
Verification
Verification
EWME Session I
Processor
Processor
Model
Model
Software
Software Hardware
Hardware
Integrated
Integrated Design
Design
Environment
Environment -- Cockpit
Cockpit
(SHINE)
(SHINE)
Software
Software
Reuse
Reuse
Exploration
Exploration
Multiple
Multiple
Abstractions
Abstractions
April 15, 2004
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Components of SW-HW Co-Design and Verification
Software
Verification
Computation
Functional,
Constraints/
Assertions
Host
SW Architecture,
SW Profiles
Communication
None
None
VPM
Petri Nets
Application (OS
Specific),
OS Primitives,
Model Checking,
Concurrency,
Reachability,
Perf. Analysis,
Design for
Tolerance,
Equiv. Checking,
Emulation,
System Software
RTOS,
Device Drivers
EWME Session I
Fault Modeling,
Prototyping
Devices
Instruction
Accurate
(ISS)
Protocol,
Asynchronous Link
Cycle Approximate,
Cycle Accurate
RTL
Untimed,
Message
Level
Switches & Routers
High Level
TLM, Cycle
Accurate
TLM, Timed
Functional
RTL
April 15, 2004
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Courses for Computer Engineering Curriculum
NoC Design
SoC Design
Software Hardware Co-Design
Quality Metrics Study
System Level Modeling
IP Modeling for Reuse
Network Protocol
Device Driver Design
Software Engineering
Verification
VLSI Design
EWME Session I
Data Structures and
Algorithms
Computer Architecture
OS and RTOS
April 15, 2004
C FLORIDA ATLANTIC UNIVERSITY
E
- Bachelor of Science in Computer Engineering Curriculum
i
Two of:
Engineering
D
Introduction to VLSI
CDA 4210
Design II
Intro to Data Communications CDA 4500
Œ
EGN 4411
E
CAD-Based Computer Design CDA 4204
Computer Network Projects COP 4364
Four (4) Technical
N
Electives (approved
Two of:
Structured Computer Arch.
CDA 4105
Intro to Comp. Systems Perf. Evaluation CEN 4410
Intro to Embedded System Design
CDA 4360
Concurrency Modeling (Fall ’04 only)
COT 4930
Approved
for Fall ‘04
Introduction to
Microcomputers
CDA 3331
Introduction to
Logic Design
CDA 3201
Engineering
Design I
ΠEGN 4410
Senior
Seminar
ΠCOT 4935
Computer
Operating Systems
COP 4610
Principles of Software
Engineering CEN 4010
Or
Design and Analysis of
Algorithms COT 4400
by advisor)
Stochastic Models
for
Computer Science
STA 4821
Data Structures &
Analysis of Algorithms
COP 3530
Foundations of Computer
Science
COT 3002 & COT 3002L
Digital
Electronics
EEL 4340
Laboratory 1
EEL 3308L
Intro to
Electronics
EEL 3300
Network
Analysis I
EEL 3111
Discrete
Mathematics
MAD 2104
Differential
Equations
MAP 2302
Engineering Physics I & II
PHY 2043 & PHY 2048L
and
PHY 2044 & PHY 2049L
AND
Fundamentals of
Engineering †
EGN 1002
Introduction to
Programming
in “C”
COP 2220
Calculus I, II & III
w/Analytic Geometry
MAC 2311, 2312 &
2313
EWME Session I
General Chemistry I
CHM 2045 + CHM 2045L
April 15, 2004
Recommended
Co-Requisite
Required
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Our Academic Challenge:
Attract both SW and HW-oriented students
• CAD-Based Computer Design With SystemC
–
–
–
–
–
IP Market Simulation (IP Providers, System Developers, & Vendors)
8 and 16-bit CPU Design (behavioral, cycle accurate, optimized, ..)
Abstraction (Sequential Design: behavioral, implicit, explicit FSM)
Robot Controller (Concurrency; Grotker et al. example)
> Mixed Level System Design with SystemC
• Software-Hardware Co-Design
–
–
–
–
Computers as Components
UML For Real-Time System Design (Student Designs)
Reusable building blocks (and Patterns)
> SW-HW Co-Design with UML and SystemC
• Verification
– Concurrency Modeling with Java and SystemC
EWME Session I
April 15, 2004
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Conclusions
• SystemC and UML have the potential to integrate the
flow, and enhance the design productivity.
• The anticipated demand for systems engineering
skills can be addressed by upgrading the computer
engineering curriculum.
• This computer engineer has systems engineering
skills; can communicate across disciplines; and will
need to have strong software and hardware skills.
• References: Many good books, especially from
Europe. A few mentioned in the conference paper.
EWME Session I
April 15, 2004