MARKET-DRIVEN DESIGN
PROJECT IN INTRODUCTORY
VLSI DESIGN
Elizabeth J. Brauer
Associate Professor
Electrical Engineering
Northern Arizona University
Outline
•
•
•
•
Introduction
Course Overview
Market-Driven Design Project
Summary
Introduction 1
• Complexity of CMOS ICs – truly
astounding!
– 100 million transistors
– 1 to 10 GHz
– Analog, digital and RF
• Enormous market pressures
– Customer expectations
– Competition
• Semiconductor industry needs welleducated VLSI engineers
Introduction 2
• EE482 Introduction to VLSI Design
• Senior UG and graduate students
• Northern Arizona University
– Flagstaff
– No, it’s not hot
• Similar lab course this semester at EPFL
with Prof. Yusuf Leblebici
Introduction 3
• Silicon CMOS
– 70% of world semiconductor market (SIA)
• EE 482
– Digital CMOS
– Fundamental concepts
– Develop intuition about circuit operation
– Market-driven project
• Rewards early completion of assignments
Course Overview
• Taught the past 6 years at NAU using Mentor
Graphics
– Considering changing to Cadence in the next 2
years
– Any advice?
• Grading
–
–
–
–
–
Homework
Class participation and attendance
Hourly exams
Final exam – cumulative
Market-driven project
Course Objectives
1. Design CMOS circuits to meet static,
transient, power and area
specifications
2. Use electronic computer-aided design
software to layout and simulate digital
CMOS circuits
Course Structure
• Per week
– 2, 50 minutes lectures
– 1, 2 hour lab session
• 15 weeks of classes
• Final exam week
Evaluation of Student Performance
•
•
•
•
•
•
Weekly homework (10 %)
Class participation and attendance (10 %)
Two hourly exams (30 %)
Final exam (20 %)
Design project (30 %)
Course evaluation (0 %)
– Online evaluation
– Monitor who completes an evaluation
Course Content
• S. Kang and Y. Leblebici, CMOS Digital
Integrated Circuits: Analysis & Design,
McGraw-Hill, Oct. 2002.
• Digital CMOS
• Semester divided into 3 parts
Part 1
• Treat transistor as switch
– Combinational logic, transmission gates,
latches and flip-flops
– Quickly learn basic operation of static
CMOS
– Students can begin on project right away
• MOS transistor in some detail
– Fabrication, layout, Level 1 IV model, and
capacitances
• Exam 1
Part 2
• Detailed analysis of the inverter
performance
– Static, transient, area, and power
• Interconnect
• More complex CMOS circuits
– Complex static logic, superbuffer, dynamic
logic, and pass transistors
• Exam 2
Part 3
• High-performance dynamic circuits
– Domino, NORA, zipper
• Semiconductor memories
– DRAM, SRAM, Flash
• Final exam
– Cumulative
Market-Driven Design Project
• Full-custom
– Bottom-up design
– Schematic entry, simulation, layout, backannotation, re-simulation
– Excellent learning experience, but time-consuming
• Standard-cell
–
–
–
–
Top-down design
Place-and-route from existing schematic
Logic and circuit simulation
Tasks more similar to industry project
Design Flow
Project
• Cells - neural network application
– nor5 – 5-input nor
– mux5 – 2-to-1 mux, 5 bits
– fa, fa5 – 5-bit full adder
– dff, reg5 – asynchronous clear, 5 bit
register
– Top cell: modulo counter or up-down
counter
• 5 bits
• Basic cells of digital circuits
Up/Down
Counter
Block
Diagram
Project Components
Project
Track A
Track B
Design 1
Schematic: nor5, mux5
Schematic: nor5, mux5
Design 2
Schematic: fa
Schematic: ff
Design 3
Layout: nor5, mux5
Layout: nor5, mux5
Design 4
Layout: fa
Layout: ff
Design 5
Schematic & layout: fa5
Schematic & layout: reg5
Design 6
Std cell: modulo counter
Std cell: up-down counter
Design 7
Schematic & layout: modulo
counter
Schematic & layout: up-down
counter
Design 8
Final report
Final report
Evaluation of Project
• Homework and exams
– Award points based on correctness of
solution
• VLSI design
– No such thing as a “partially” correct circuit
• Project grading
– Circuit must be correct
– Earlier completion earns more points
– Just like the market!
– And don’t get behind...
Project Grading
• Projects are collected every Monday
• Evaluated by instructor within 1 or 2
days with feedback to student
• Score based on completion date
– First week:
– Second week:
– Third week:
– Fourth week and later:
11 pts
10 pts
9 pts
8 pts
Project Schedule
Project
First Week
Track B
Design 1
Week 3
Schematic: nor5, mux5
Design 2
Week 4
Schematic: ff
Design 3
Week 6
Layout: nor5, mux5
Design 4
Week 8
Layout: ff
Design 5
Week 9
Schematic & layout: reg5
Design 6
Week 11
Std cell: up-down counter
Design 7
Week 13
Schematic
counter
Design 8
Week 15 (Friday)
Final report
&
layout:
up-down
Evaluation
Sheet
• Strict rules
– Names
– File location
– Testing
– Documentation
Design Notebook
• Documentation
– Schematics, delays, test plan, notes
• Required entries – before starting task
– Schematic entry – sketch of schematic
– Layout – stick diagram of layout
– Simulation – sketch of waveforms with
breakpoints
• Improve efficiency
– Optimize time spent on computer
Class Web Page
• http://jan.ucc.nau.edu/~ejb3/ee482
• Syllabus
• Handouts
Summary
• EE482 Introduction to VLSI Design
– Northern Arizona University
– CMOS digital circuits
– Design, simulation, layout
– Market-drive project
• Custom and standard cell design
• Rewards for early completion
– Preparation for career in semiconductor
industry