27.1GHz CMOS Distributed Voltage Controlled Oscillators with Body Bias for
Frequency Tuning of 1.28GHz
Kalyan Bhattacharyya, J. Mukherjee and M. Shojaei Baghini
Department of Electrical Engineering, Indian Institute of Technology Bombay, India
E-mail: [kalyan, jayanta, mshojaei]@ee.iitb.ac.in
A 10-GHz CMOS D-VCO with an output power of 4.5 dBm was reported in [2]. There a tuning range of 9.5–
10.4 GHz was obtained using the inherent varactor tuning
and current-steering tuning technique. The output power
variation was 2.7 dB over this tuning range. The tuning
range was extended to 9.3-10.5 GHz by changing gate
line voltage from 1V to nearly 2.8 Volts, when
maintaining a constant output power was not required.
The measured tuning range of the delay-balanced currentsteering tuning technique, where the effective length of
the transmission line is changed by changing the signal
path (as shown in [2]) is 2.5% around the center
frequency. The center frequency is set by the inherentvaractor tuning.
Three monolithic Distributed Voltage Controlled
Oscillators (DVCOs) are reported here. The first DVCO
named OSC-1 uses four stages of the gain cell shown in
Figure 1. The second DVCO, named OSC-2 and the third
DVCO named OSC-3 which is a modified version of
OSC-2 use three stages of the same gain cell.
In this paper we intend to show that varying body bias
can be used effectively as a technique for frequency
tuning. Body bias variation changes the gate and drain
capacitances thereby changing the resonant frequency and
hence the frequency of oscillation.
Abstract
The feasibility of using standard 0.18µm CMOS
technology for low cost wideband monolithic microwave
integrated circuits (MMICs) at ~27GHz is demonstrated.
Three monolithically integrated distributed voltage
controlled oscillators (DVCOs) with a novel gain cell
comprising of n-FET common source with p-FET currentsource load are designed. Two of the DVCO’s have 3
stages of the gain cell while the third has 4 stages. Top
Layer metal is used a coplanar waveguide for producing
on-chip inductive elements. An important feature of these
DVCOs is the use of body bias variation for very large
frequency tuning. Simulation results indicate that the 4stage DVCO achieves a tuning range of 22.43-23.42GHz
i.e 990MHz whereas the 3-stage DVCO has a tuning
range of 25.82-27.10GHz i.e 1.28GHz, with respectively
~0.5dBm and ~1dBm change in output power over tuning
range for DVCOs. The best value of phase noise for 3stage DVCO is obtained by applying reverse body bias on
n-FETs. For a reverse body bias voltage of -1V, the phase
noise is -97.39dBc/Hz at 1MHz offset from 26.87GHz.
1. Introduction
Distributed Oscillators (DOs) [1], [2], [3] designed here
operate in the forward gain mode of a traveling wave
amplifier (TWA). Designs use n-FET common source
with p-FET current-source load, a novel gain cell for DOs
(Figure. 1), coplanar waveguides (CPWs) for gate and
drain transmission lines, a feedback path between output
and input and a loop called ‘folded CPW’ [3]. As the
forward wave travels down the gate line, each n-FET
transfers signal to drain line through its transconductance.
Signals add in drain line in forward propagating direction.
The drain line output is then fed back to the gate line
input. The forward wave in the gate line is collected
across a matched termination and backward wave is
absorbed by a matched termination in the end of drain
line ([2], [3]) as shown in Figure. 1. Traditional nonTWA oscillators use relatively complicated circuits with
large on-chip inductors and capacitors. The use of only nFETs between gate and drain lines and FETs loaded with
coplanar waveguides matched to 50Ω impedance results
in fast rise and fall times [1], and thus a high oscillation
frequency of 27.1GHz is achieved.
978-1-4244-4480-9/09/$25.00 ©2009 IEEE
Figure 1. Schematic of D-VCO with body bias for tuning.
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lines. These series inductive elements, along with shunt
capacitances Cin and Cout (total input and output
capacitances of transistor) at the gate and drain nodes of
the FETs respectively, are coupled by the
transconductance of the gain cells [1], [2]. The Cin and
Cout along with the series inductive coplanar transmission
line elements form a T-type low pass filter structures, LGCin-LG and LD-Cout-LD respectively for gate and drain lines
for each stage of the oscillators [1], [2], [3]. These T type
structures are repeated for each gain cell used in the
oscillator.
The frequency tuning of the D-VCOs are done using
body bias variation of gain cells. The change in body bias
directly changes the drain-bulk capacitance CDB and the
gate-drain capacitance CGD and indirectly changes the
gate-source capacitance CGS [4] through the change in
the threshold voltage VT [4], [5]. The input and output
capacitances of the transistor are given by,
2. Design of D-VCO
The DVCO’s are designed by connecting the output of
the TWA back to the input as illustrated in Figure. 1. For
constraint of space the individual oscillator circuits have
not been shown, but are based on the same basic principle
of connecting gain cells in cascade and connecting the
output to the input as feedback. The oscillators use a
novel gain cell, comprising of n-FET common source
with p-FET current source load as shown in Figure. 1. To
minimize the gate resistance, multiple fingered gates
connected on both sides with finger width of 5µm are
used.
Due to parasitic elements, the performance of the
MOSFETs in common source conFigureuration degrades
at microwave frequencies, creating challenges for the
RFIC designers. The high gate resistance RG has many
undesirable effects like improper impedance matching
thereby reducing the power transferred [4], increasing the
noise Figure of the FET as thermal noise is introduced by
it [4] and also reducing the fmax value [4]. However the
gate resistance RG can be reduced by using multi-fingered,
double-side connected gate [4]. RG can be controlled by
controlling its parasitic part RG, p which is the distributed
gate electrode resistance produced by the polysilicon gate
material [4] and is given by [4],
RG , p
R W
= sh2
, FET width W = n f W f
αnf L
Cin = CGS + CGD + CGB =|
Im ag (Y11 ) |
ω
In saturation, Cin ≈ CGS + CGD =|
CGD =|
Im ag (Y12 )
ω
|
Cout = C DB + CGD =|
…. (1)
(2)
Im ag (Y11 )
ω
| (3)
(4)
Im ag (Y22 )
ω
| (5)
For the gain cell used in this work, Cout consists of the
CDB and CGD of both the n-FET and p-FET transistors,
whereas Cin consists of CGS and CGD of the n-FET
transistor only as is evident from Figure 1. Body bias
variation employs the bias dependent change of CDB and
CGD of both n-FETs and p-FETs resulting in the change of
Cout and of CGS and CGD of n-FETs resulting in change in
Cin.
The body terminal of an n-FET needs to be isolated
from p+ substrate on same wafer [5]. So it is essential to
fabricate the circuit in a process which supports the deep
n-well option, which isolates the p+ body from p+
substrate by deep n-well from all sides [5]. The n-well is
connected to VDD (supply voltage) of the circuit.
For low power VCO operation in CMOS, it is desirable
to use parasitic capacitances of transistor as much as
possible [5] and frequency tuning using body bias
variation. This way of frequency tuning using parasitic
capacitances of MOSFETs also has the advantage of
higher operating frequencies and relatively flat Q over the
tuning range [5].
where Rsh is the sheet resistance, Wf is the finger width, nf
is the number of fingers, L is the channel length and α is a
fitting parameter having a value of 12 when gate fingers
are connect from both sides (as used in the present
designs) and 3 when fingers are connected from one side.
The minimum width for both the n-FETs as well as the pFETs used in OSC-1 is determined to be 35µm from
harmonic balance simulations. For the 3-stage DOs
(OSC-2 and OSC-3), the same values are 50 micron for nFETs and 35µm for p-FETs. OSC-2 is similar to OSC-1
except that it has three stages of gain cells as compared to
four as in OSC-1. In OSC-3, the circuit is slightly
modified in that the body nodes of p-FETs are now
connected to their respective source nodes which are then
separated by R-C-R networks with R of 5KΩ and C of
2pF. For all the three oscillators, body bias variation is
used for frequency tuning. In OSC-1 and OSC-2 body
bias variation is applied on both n-FETs and p-FETs. For
OSC-3 the same is applied only on the n-FETs.
The distributed amplifier achieves a higher gain–
bandwidth product by absorbing the parasitic
capacitances Cin and Cout of transistors into transmission
lines [1], [3]. In a TWA, the FET gain cells are connected
with series inductive elements LG and LD produced by the
transmission line effect of CPWs at the gate and drain
3. Results of Distributed Oscillators
Simulations were done for all three oscillators using
ADS in UMC 0.18µm process. From simulations, OSC-1
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(the spectrum is shown in Figure. 2) achieves a tuning
range of 22.43-23.42GHz i.e 990MHz by forward and
reverse body bias of n-FETs and forward bias of p-FETs.
The output power variation was around 0.5dBm. The
details of simulation for OSC-1 are given in Table-I. The
bias voltage at the gate and drain was set at 1.4 V and the
signal conductor (top metal) thickness was 1.2µm. OSC-2
has a tuning range of 25.35-26.58GHz (i.e 1.23GHz) by
forward and reverse body bias of n-FETs and forward
bias of p-FETs with ~1.25dBm change in output power
(details in Table-II, time domain signal in Figure. 3) . The
bias voltages at the gate and drain were set at 1.1V and
the top metal thickness was 2µm. OSC-3 has a tuning
range of 25.82-27.10GHz (i.e 1.28GHz) by forward and
reverse body bias of n-FETs only with ~1dBm change in
output power (details in Table-III). The gate and drain
bias set at 1.1V and the top metal thickness were 2µm.
The VDD in the source node of p-FETs for all three circuits
is 1.8V. The variation of phase noise during the (body
bias type) tuning of the D-VCOs is reported in Table-I to
III.
The standard RF CMOS processes offer top metal
thickness of either 2µm or 1.2µm. Both the values are
used here in the simulations and the results are reported in
Table-I to III.
Table I. Performance of OSC-1 at different body bias
Vbp(V)
OSC
Freq
(GHz)
Vbn
(V)
Power
Phase Noise
(dBm)
dBc/Hz at
1MHz offset
4-Stage distributed oscillator
1.8
0
22.91
6.91
-99.35
1.35
0
22.76
6.375
-99.932
1.35
0.6
22.43
6.5
-99.03
1.8
-1.0
23.26
6.65
-98.5
1.8
-1.5
23.42
6.45
-97.36
Tuning: 990MHz with Top Metal Thickness T = 1.2µm
Maximum Frequency is 23.78GHz with 6.475dBm O/P
power when T =2µm
The maximum frequency of oscillation of OSC-1 is
23.78GHz for top metal thickness of 2µm as compared to
23.42 GHz obtained when top metal is 1.2 µm thick.
Similarly, if top metal thickness of 1.2µm is considered
Figure 2. Spectrum of 4- stage D-VCO OSC-1 showing
power levels in harmonics.
Figure 4. Phase noise spectrum of OSC-2 with the value
of -96.70dBc/Hz at 1MHz offset from 26.39GHz at Vb = 1V.
for OSC-2 (as compared to 2µm), maximum frequency of
oscillation is 26.15 GHz as compared to 26.58 GHz when
top metal thickness is 2µm. The values are 26.67GHz and
27.10GHz respectively for OSC-3. So for all the three
designs of D-VCOs, higher the top metal thickness,
Figure 3. Time domain voltage output of the carrier of
OSC-2.
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appear as a great concern for such low noise circuit design
[6]. This is supported by Figure 7, which shows that the
phase noise degraded with a forward body bias of 0.6V
for n-FETs. Reference [7] reported that in strong
inversion, the low frequency noise level (low-frequency
spectra are predominantly 1/f like) for both n and p
MOSFETs are approximately independent of the substrate
bias [7].
higher the frequency of oscillations. Maximum frequency
of oscillations occurred for all these three D-VCOs using
reverse body bias of -1.5V for the n-FETs.
Table II. Performance of OSC-2 at different body bias
Vbp
(V)
Vbn
(V)
OSC
Freq
(GHz)
Power
Phase Noise
(dBm)
dBc/Hz at 1MHz
offset
Table III. Performance of OSC-3 at different body bias
3-Stage distributed oscillator, Case-I
1.8
0
25.91
1.24
-90.16
1.3
5
0
25.80
0.778
-89.187
1.3
5
0.6
25.35
1.273
-93.451
1.8
-1.0
26.39
0.69
1.8
-1.5
26.58
-0.065
Sr. No.
Vbn
(V)
OSC Freq
(GHz)
Power
Phase
Noise
(dBm)
dBc/Hz at 1
MHz offset
3-Stage distributed oscillator, Case-II
1
-1.0
26.87
1.824
-97.39
-96.7
2
-1.5
27.10
1.368
-95.65
-94.77
3
0.6
25.82
2.27
-93.48
Tuning: 1.23GHz with Top Metal Thickness T =
2µm
Max. Frequency is 26.15GHz with -0.013dBm O/P
power when T = 1.2µm
Tuning: 1.28GHz with Top Metal Thickness T = 2µm
Max. Frequency is 26.67GHz with 1.27dBm O/P power
when T = 1.2µm
Without the active load of p-FET over n-FET CS, a 3stage DO with n-FET common source (CS) cells
oscillates at 20.07GHz at gate and drain bias of 1.1V.
Hence we see that the gain cell used in this work gives
higher oscillation frequencies and also larger tuning
ranges through body bias variation.
Higher power level at maximum frequency of
oscillation occurred for thicker top metal of 2µm in OSC1 and OSC-3 (Table-I and Table-II). For OSC-2 the
values are much closer for two top metal thicknesses of
1.2µm and 2µm. The best phase noise Figures for both 3stage designs become possible with reverse body bias of
n-FETs of -1.0V. For the OSC-2 it is -96.7dBc/Hz at
1MHz offset as shown in Figure. 4, as compared to 90.16dBc/Hz at 1 MHz offset with no body bias. For
OSC-3 it is -97.39dBc/Hz (Figure. 5). The time domain
signal of OSC-3 is shown in Figure. 6. So for OSC-2,
there is a fair amount of performance improvement for
phase noise using reverse body bias for n-FETs of a
moderate value of -1.0V. Phase noise of OSC-1 around 99dBc/Hz, either with no body bias or forward body bias
of p-FETs only or forward body bias of both n-FETs and
p-FETs (as shown in Table-I). Even in case of reverse
body bias of -1.0V of n-FETs only, it is -98.5dBc/Hz. So
phase noise performance of OSC-1 is almost uniform
over the most part of the tuning range.
Reference [6] has reported that high frequency noise is
increased with forward body bias for nMOSFET. Increase
of minimum noise Figure NFmin and equivalent noise
resistance Rn with the increase of forward body bias may
Figure 5. Phase noise spectrum of OSC-3 with the value
of -97.39dBc/Hz at 1MHz offset from 26.87GHz at Vb = 1V.
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content in the 2nd harmonic frequency does not increase
significantly here as in MOS varactor tuned 3-stage
distributed VCO of [8]. So body bias type tuning has
advantages in distributed voltage controlled oscillators as
compared to MOS varactor type tuning for distributed
oscillators.
5. References
[1] Bendik Kleveland, “CMOS interconnects beyond 10 GHz,”
PhD thesis, Stanford University, California, August 2000.
[2] H. Wu and A. Hajimiri, “Silicon-Based Voltage-Controlled
Oscillators,” IEEE Journal of Solid-State Circuits, vol. 36, No.
3, pp. 493-502, March 2001.
Figure 6. Time domain current output of the carrier of
OSC-3.
[3] Kalyan Bhattacharyya and Ted Szymanski, “Performance of
a 12GHz Monolithic Microwave Distributed Oscillator in 1.2V
0.18µm CMOS with a New Simple Design Technique for
Frequency Changing,” IEEE Wireless and Microwave
Technology Conference, WAMICON’2005, Clearwater,
Florida, USA, April 7 and 8, 2005, pp 174-177.
[4] Yuhua Cheng, M. Jamal Deen and C.H. Chen, “MOS
Transistor Modeling for RFIC Design,” IEEE Transactions on
Electron Devices, vol. 52, No. 7, July 2005, pp 1286-1303.
[5] M. Jamal Deen et al, “Low-power CMOS integrated circuits
for radio frequency applications,” IEE Proceedings - Circuits,
Devices and Systems, vol. 152, Issue 5, pp. 509-522, Oct 2005.
[6] Hao Su et al, “Effects of forward body biasing on the high
frequency noise in deep submicron NMOSFETs,” IEEE Radio
Frequency Integrated Circuits Symposium, 2008, pp. 567-570.
Figure 7. Tuning frequency (GHz) and corresponding
phase noise figures (dBc/Hz) of OSC-3 for varying body
bias (of n-FETs).
[7] M. Marin et al, “Effects of body biasing on the low
frequency noise of MOSFETs from a 130 nm CMOS
technology,” IEE Proceedings - Circuits, Devices and Systems,
vol. 151, Issue 2, pp. 95-101, April 2004.
4. Conclusion
In this paper, we have used the change in input and
output parasitic capacitances of transistors, caused due to
change in body bias voltage, for frequency tuning of
oscillators. Using body bias tuning we get a larger tuning
range for the D-VCOs described in this paper as
compared to MOS varactor tuned D-VCOs reported in
[8]. Tuning range for OSC-2 was 570MHz in [8] at an
oscillation frequency of 20GHz, whereas the tuning range
for OSC-3 is 1.28GHz from the maximum frequency of
oscillation of 27.1GHz. Tuning range achieved by
simultaneously changing the body bias of n-FETs and pFETs for OSC-2 is almost the same as that obtained by
varying the body bias of n-FETs only for OSC-3. This
shows that the body bias type tuning employed in this
work has an upper limit. Using lesser number of stages
(3-stage from 4-stage), we get higher frequency of
operation with larger tuning range. Further the power
[8] Kalyan Bhattacharyya, J. Mukherjee and M. Shojaei
Baghini, “20GHz CMOS Distributed Voltage Controlled
Oscillators with Frequency Tuning by MOS Varactors,” 2nd
International Workshop on Electron Devices and Semiconductor
Technology (IEDST 2009), June 1-2, 2009, IIT Bombay, India.
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