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VECTOR PHOTON MISS DISTANCE INDICATOR
I\
GROUND STATION
A graduate project submitted in partial
satisfaction of the requirements for
the degree of Master of Science in
Engineering
by
-
Paul Ellis Gravdahl
May, 1975
The graduate project of Paul Elll:s Gravdahl is approved:
!
;
Committee Chairman
California ·state University. 1\Tnrt-h
----- ri rlnP
-----~:;~-
May, 1975
ii
TABLE OF CONTENTS
ACKNOWLEDGEMENTS. • • • • • •
.
.
• •
iv
....
v
INTRODUCTION. • • • • • • • • • • • •
1
MEMORY DESIGN ALTERNATIVES. • • • • •
4
OPERATING PROCEDURE • • • • • • • • •
6
MEMORY CIRCUIT BOARD. • • • • • • • •
11
COUNTS PER SECOND CIRCUIT BOARD •
14
ABSTRACT. • • • • • • • • • •
0
•
COMPLETED SYSTEM. • • • • • • • • • •
19
FUTURE DEVELOPMENTS
..
23
BIBLIOGRAPHY • • • •
. ..
"
iii
• • • • • • •
•
• • • •
26
ACKNOWLEDGEMENT
There are a number of individuals that I would like
to thank for their help and patient understanding during
the execution of this project.
Kenneth L. Muther, who was my supervisor, often
acted as an instructor as I atempted to gain an understanding of integrated circuits and their functions.
I
would like to thank our div1sion consultant,
Ted Waddell, for his help with questions dealing with
electronics.
I
would also like to thank Professor Zrnic for his
technical help in organizing this report.
Special praise should be given to William L.
MacDonald, Dr. Pickett, and Dr. Metzler, for the fine
job they have done with the first Technical Professional
Masters Degree Program.
The Pacific Missile Test Center has provided the
financial support necessary for the Technical Professional Program and the work assignments.
iv
"---- ·-·--------------··-·--·-·----··----------·
--·-----------·-·---.
--------~---------~------·-------.
j
ABSTRACT
VECTOR PHOTON MISS DISTANCE INDICATOR
GROUND STATION
by
Paul Ellis Gravdahl
Master of Science in Engineering
May, 1975
The chief purpose of this paper is to provide all of
the information necessary to allow an individual to
understand and operate the VPMDI (vector photon miss
distance indicator) ground station$
The first part deals with alternative designs that
were considered during the initial phase when i t was
necessary to determine what state-of-the-art devices
were
available~
The operating procedure is then covered
to provide a composite reference for interconnecting the
system.
The operation and usefulness of each of the completed
circuit boards is discussed&
the future system is
explairH~d
How these boards relate to
along with two of the
problems encountered in the de3ign and testing of the
ground
station~
The future development goals are covered
to give a composite view of the total system and its
functiono
v
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'
INTRODUCTION
This graduate paper reviews the design process fol;lowed in the development of the VPMDI (vector photon
miss distance indicator) system memory.
between a missile and a target.
Radioactive sources are
;measured to determine levels of radiation at known dis~
itances, and then placed on a missile.
As the missile
approaches the target the count rates at the two photomultiplier tubes, located on the target, increase to a
'
maximum.
In the future there will be eight photo-
!multiplier tubes located on the target when using the
'
!vector photon miss distance system.
The radiation level
is inversely proportional to the square of the distance
between the target and the source.
The design objectives were to construct a memory
,capable of storing 128 ms (milliseconds) of data in a
6 X 4 X 128 bit matrix (figure 1).
The data is composed
of eight words of six bits in length, each of which is
sampled once each millisecond for 128 mso
At the
beginning of each frame there is a synch word.
The
format of the transmitted data is PCM (pulse code
modulated) with eight words per frame, six bits per word,
at a sampling rate of 1000 per second.
1
Due to the fact
2
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Inpu. t -
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Deco mmuJa tot"
BIT
Secondary
for-
Synchronizer-
SynchrDnizer
One Word per
Frame
Buffer
lhpu.t
Fo rtrt.a t ...,...__ _ ____,.
Selector
I
Output
Clocks
---"'" Memory
t----,p.f
Output
·Data
Selector
Counts perSecond
Moh itol"'
Figure 1
VPMDI ground station
3
that the exact system configuration has not yet been
determined the telemetry frame may be either four or
jeight words in length.
'
The completed VPMDI ground station is to be capable
~f
determining the direction of a missile, relative to the
ttarget, to a degree necessary for lethality studieso
MEMORY DESIGN ALTERNATIVES
Static shift registers were to be utilized in the
memory design because they had the inherent advantages
of being capable of storing data indefinitely without
a minimum clock rate.
available were the
The two most promising devices
~~5055
(4 X 128) and the MM5058
:< 1 X 1024) static shift registers manufactured by the
National Semiconductor Corporation.
The MM5055 static
shift register was chosen after a comparison of the circuit design intricacy based on each device.
The initial
designs showed that the circuit employing the MJ.'V!5055
would have fewer IC's (integrated circuits), and the
least complicated method of operation.
The MM5055 static
shirt regist·er also offered the advantage of an easy
access parallel output, and a recirculate mode.
The MM5058 static shift register design required
parallel-to-serial conversion at the input of the memory
storage devices and serial-to-parallel conversion at the
output.
The memory length was set at 128, because 128 ms of
data would accurately record all
The tele-
intercepts~
metry word length was specified at six
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ure 2) which would have the capability of transmitting
'a largest decimal value of 63 counts per millisecond.
This would be a countrate of 63,000 counts per second
4
5
which is considered to be saturation.
Due to the fact
;that 4 input gates were used in the target pod design,
;the largest value transmitted is 60 counts per second.
;since both of these values are well beyond practical
saturation either value could have been chosen as the
~axirnum
transmitted value.
'
Since the ground station was a laboratory device
iand was not designed to fly, non-military specification
;devices
were used throughout the design to lower the
I
·cost, and decrease lead time on parts orders.
CMOS
(complimentary-metal-oxide-semiconductor) devices were
ialso used whenever possible or when they were
available~
'CMOS devices offer the advantages of lower power
:consumption and greater design flexibility.
OPERATING PROCEDURE
The PCM coded telemetry signal first enters the bit
synchronizer (figure 1).
Control settings on the bit
synchronizer consist of adjusting the bit rate to the
correct frequency and making the polarity adjustment
positive,
The bit rate frequency is 32 kHz (kilohertz)
ei~ht
for four word telemetry signals, and 56 kHz for
word telemetry signals.
Data and clock lines are brought from the bit synchronizer to the secondary synchronizer.
Although the
system was designed to·operate with the zero degree
clock, the bit synchronizer has three additional clocks.
The frame synch pattern switches are set to the
values o£ the synch word starting with the least significant bit in the last, or as in this case, the eighth
position.
All other switches are set to the mask
position.
The synch word for this system was specified
as four high, two low, one high, one low, in that order
(figure 2).
The bits per word switch is adjusted to the
number of bits per data word, or six.
The number of
words per frame switch is adjusted to N + 2, where N
equals the number of words per frame.
The
-
-
-
-- -
.::> t:d.L
and the lock switches are initially set at some
mediate value such as five.
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- -- ..! -~. 1I -v- t:L
.J.~ y ,
inter~
After the secondary synchro-
nizer locks on the telemetry signal the search/verify and
6
7
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I Data I
Sync
Wor-d
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Wor-d
+S
-~-·-·
u_ u...-----u_u_u _ _
1 1
---.. .u-----------9v
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End .of Word
nd
of
F't-ame
0
1 - - - - - - - - - - - - - - -9V. M s 8
0
2 ~~.....
1___1____~--.,.-- -9V
(J)
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0
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4
5
6
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0
-9V
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li!BCVF
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0
-9V
--------------------~------------.....
First
bits o-f syttc word
~o-----'~"""'i·
si~
Figure 2
Four data word telemetry frame timing diagram
8
lock switches m9y be set to zero.
The frames checked
switch is usually set to some high value, around ten.
Ocassionally the secondary synchronizer provides a noisy
output.
This is due to a malfunctioning power relay and
can usually be alleviated by turning the power button off
'and on again.
The cross connect plug at the rear of the secondary
synchronizer has been prewired to provide the correct
;outputs at the correct pins of the output connector.l
:These are all the adjustments necessary for the equipment
which operates in conjunction with the ground station.
The portions of the ground station completed and
!included in this report are:
the memory, the display,
!and the counts per second monitor.
A temporary control
;board was built for testing purposes.
The purpose of the
control board is to provide the logic which stores data
;in the memory and to provide the correct clock for the
,particular mode of operation.
The data format was described in the initial design
specifications.
Each telemetry frame consisted of eight,
.six bit, data words 9 and an eight bit synch word.
Each
telemetry frame therefore consisted of a total of eight
bits for the synch word, and forty-eight bits for the
eight data words for a total of fifty-six bits per frame.
lpMR Secondary Synchronizer Preliminary Manual, 1966.
9
-
--
--
-
-- ---- - - - - - - - -
~---
--- - - - - - - - - -
--
Since each data word is the count rate from one detector,
and each detector pod is sampled once per millisecond
this determines the 56 kHz frequency setting for the bit
synchronizer ..
It was later determined that it was not necessary to
store all eight words in the memory at one time.
It
would be possible to store the first four words of the
PCM signal, analyze this data, and then store the
following four words from the telemetry tape recording
for analysis.
When using four data words per frame
telemetry signals each frame consists of eight bits
for the synch word, and twenty-four bits for,the four
data words for a total of thirty-two bits per frame.
This requires a bit frequency setting of 32 kHz for the
bit synchronizer.
The memory can store data £rom PCM signals consisting
of anywhere from two to eight words per frame.
To store
data from PCM signals consisting of one word per frame
it is necessary to build a separate decommutator to
convert the serial data to parallel form.
This is
because the secondary synchronizer is not designed to
work with signals with less than two words per frame.
External memory controls consist of a momentary
switch to reset the memory in preparation for a store
data signal, and a two pole single throw switch for
selecting either the first four or the last four words
1
10
:·------------·--------~-
--------·---........---:_ ---·-·------
.
------- ---·--·--
of a telemetry.signal for storage.
A four pole rotary
switch places one of the four data words on the output
buss for data analysis.
f
There are two methods which can be used to signal the;i
beginning of an intercept.
For storage of real time data'
a threshold detector can provide a signal which stores
data for 128 ms when eight consecutive frames of data
contain information.
There is very little probability
this will occur until an intercept, due to the fact
that the background count rate is approximately 100
counts per second, and the sampling frequency is
re-latively high, at 1000 samples per
i
s~cond.
This means
that, on the-average, one data bit is transmitted for
every ten frames with nine frames remaining empty.
When playing back data from a magnetic tape the
time code translator can be used to determine the time
at which the intercept begins and can provide the pulse
for storing data.
The time code translator uses time
coded information located on the telemetry tape to
' provide a pulse to signal a predetermined location in
the data when the data is played back.
------
r------------------~-_
MEMORY CIRCUIT BOARD
The memory circuit board may be broken down into
four main parts:
decommutator, storage devices, output
selector, and inherent controls.
The decommutator consists of three dual, series
input, parallel output, shift registers.
Four of the
data words from one frame are all shifted from the
decommutator to the correct area of the memory at. the
same instant by the end of the frame pulse.
Eight
signals are brought from the secondary synchronizer to
the memory board:
the six lines of input data, the end
nf frame pulses, and the end of word pulses (figure 3).
The secondary synchronizer converts the data bits from
series to
parall~l
form, and the
d~commutator
separates
the data words and routes them to the correct memory
location.
The end of word pulse clocks the six lines of data
into the decommutator.
When four words are stored in
the decommutator shift registers the data is shifted
l
1
into ten storage devices by the end of frame pulse
I
clocking the memory.
!
I1
1
Data is continuously circulated through the memory
1
I
until the memory controls change the level of the staticl
shift register's recirculate·pin.
Six MM5055•s, (4 X
1
j
I
128) bits, are used to store four data words, each six
~------·-·-·--·-..-----------·----·--··-..·--··---·-·--------------------····----..----·-··-·--11
.........................
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12
128 BIT
Bin a t-v
Counter
~-----Cotltr-ol
Ehd of Wor-d -------1
Data
Ot:?commu.tator
Memorv
End of · Frame ____.........,
Storaae
Devices
Outpu.t
Data
SelectorFigure 3
Memory circuit board
Boat"d
13
bits longt for 128 ms.
The controls located on the
memory board can be set to store either the first fourt
the last four, or any number of words from two to four
of the telemetry signal.
a 128 bit counter.
The memory board also includes
When the counter is reset by the
control board it counts the end of frame pulses which
occur each millisecond.
When the counter reaches 128 it
generates a 1 us (microsecond) pulse which stores. 128 ms
of data.
It also puts out a pulse each time the data
previously stored in memory, is clocked through completely when in the recirculate mode.
The last section of the memory board is the output
; data selector.
It consists of a series of twenty-four
' analog switches of which units of six are conducting
1
at one time.
These six switches comprise one output
data word in parallel form.
THE COUNTS PER SECOND CIRCUIT BOARD
The operation of the counts per second circuit board
consists of two modese
The first is a counts per second
monitor which is used for calibration of the sourcedetector combination, (figure 4), and the second is the
step through monitor.
In the counts per second mode the countrate from
the detectors, which take one sample each millisecond,
is divided by four and accumulated for four seconds.
This average one second count is accumulated by a BCD
(binary coded decimal) counter for four seconds and
displayed for the following four seconds.
The BCD
counter is included on a display board which is also
composed of latch/decoder/drivers and displays.
The required clockrate, of .25 Hz, for the BCD
counter is provided from the 60 Hz power line after
attenuation, division by 240, and the proper pulse
shaping has been accomplished.
Binary values in parallel form enter the counts
per second board from the memory outputs.
These
values enter a binary down counter to obtain a pulse
train with the total number of pulses equal to the value
of the binary number which entered the down counter.
The clockrate of the down counter is controlled by a
clock built with DTL (diode-transistor logic) gates.
14
Memory o
Ou.t pu. t
Binary
Down
Counte.t-
Start-
,.____.. ., Stop
H
DTL
25D K Ht.
c \oc k
Latch-
Disp Ia y l.....ckJe:~.----,1 Decoder-
Divide
by
Four
H
BCD
Cou.nte.r-
Dt-iver
~
GO Hz o
,, .25 Hz
Clock
Figure 4
Counts per second monitor
......
V1
16
--···-·---------
-------------,
The advantage of this clock is the fact that it always
stops operation at a logical 1.
When the oscillator
begins running it will behave as though the output has
just changed from 0 to 1.
With this circuit the down
counter is very precisely controlled (figure 5).
After the DTL clock is turned on it oscillates at
250 kHz until the binary value has counted down to
zeroa 2
Each oscillation counts down one value.
This
pulse train is divided by four, counted for four seconds
by a BCD counter, and displayed for four seconds.
One LED has been included to signal the instant
when the counts per second display changes value.
is
~mportant
This
during calibration since in some instances
the following four second display value is identical to
the previous value which makes it difficult to determine
when the next count has appeareda
counts are recorded during
Ten consecutive
cal~bration
for later deter-
mination of the average countrate.
The second mode is the step through operation
(figure 6).
Once data is stored in the memory it is
possible to use a momentary switch to step through data
independent of any clock.
It is also possible to clock
data out at whatever count rate desired for data
analysis by methods other than visual inspection.
2f-!I. J. Miller, "Transients Do Not Affect This StartStop Oscillator, "Electronic Engineering, March 1973,
P• 27.
.
17
On/Off
=-======"'---
_ _ '=l
Con t t'O I
---- Outpu. t
Figure 5
250 Hz DTL start-stop oscillator
18
In pll t
Qr>----=-1
8ihar-y
Down.
~---~
Counte~
250 Hz.
Start-
DTL
Stop
Cloc.k
LatchD'15 I
p
¢
o
Step
ThroLLSJ h
Clock
ay
....,._---f Deccdet-
1-4-----t
BC D ~
Counter
Driver
.. Delay
r---~-----. . . .
?igure 6
Step through monitor
COMPLETED SYSTEM
The total display consists of an (11 X 6) inch
printed circuit board.
It contains the following
digital displays:
1.
A five digit display for count rate data.
2.
A three digit display for location in
memory when in the step through mode
or low frequency clock modes.
3.
A two digit display for future real time
miss distance.
With the VPMDI system built and operated as described
it is possible to perform calibration and step through
data analysis.
These are the first steps in the design
and utilization of the VPMDI system.
The memory is extremely versatile being capable of
storing two to four words, the first four, or last four
words of an eight word telemetry signal.
To interface the secondary synchronizer with the
ground station memory it was necessary to convert the
-9 volt pulses from the secondary synchronizer to +5
volts levels (figure 7).
Integrated circuits were used for this level shifter
rather than discrete component transistor level shifters
only because it was a slightly more compact design and
19
20
+5 Volts
G.2 K.n.
+ 5 Volts
Vo
Z.5 v
Figure 7
Level shifter
21
it also offered an opportunity to explore a different
technique for utilizing IC inverters.
CMOS inverters
failed to work due to the fact that it was not possible
to drive their inputs far enough negative.
A certain
amount of negative voltage variation has to be allowed
for at the inverter input due to the nonlinearity of the
zener diodes used at the inverter inputs.
Successful
level shifting was accomplished by using a zener diode
and a resistor in combination with a TTL (transistortransistor logic) inverter.
In order to obtain an efficient method for determining the memory output
was constructed.
values a simple test device
It consisted of six LED's (light
emitting diodes) and a dual inline package consisting
of six LED drivers.
This device was used until it was
superseded by the counts per second board which provided
direct decimal readings of the ·memory output
values~
Testing of the ground station was performed by
utilizing the PCM simulator.
This instrument can be
programed to provide a varying output consisting ·of the
eight bit synch word, and two different data words.
remaining words are an identical common
word~
All
Frame
lengths of anywhere from two to eight words can easily
be created&
After data was stored in the memory it was possible
to determine that the correct words were stored in their
proper predetermined positions.
The entire
syste~
22
performed exactly as planned with the exception of one
minor change to the memory board.
During the artwork
layout an incorrect connection had been made to pin six
rather than pin nine of IC number two.
easily corrected on the completed board.
This defect was
FUTURE DEVELOPEMENTS
The VPMDI ground station in its present form has
limited capability for data output.
Some method is
necessary to output the data in a format which is useful
to the system operator.
This can be acco:nplished in a
number of ways.
When receiving data during a missile launch; the
threshold detector would start the storage of
the missile approached.
dat~
as
Since the threshold detector
may occasionally false trigger, the system operator must
be able to quickly scan the contents of memory to
deter:nine if an intercept has occured.
!
This can be
accomplished by recirculating the memory through a
i digital-to-analog converter and
displayi~g
the output
on an oscilloscope (figure 8).
This type of analysis can give a clear, real time
determination as to whether or not a good intercept has
occured.
This information can often be very important
to the people directing the tests..
the test can be performed again
If the data is poor
immediately~
at
substantially less cost than if the entire mission
(launch, recovery,
-
--
...!l
dflU
-
-
~ ~ L
illd .LU
-
-
~ ~ -
-
\
Lt:Uc:11H..~t:)
had to "-.Ut:: ----..C----...1
,tJt::L .L UL J.l:'.:::U
again ..
The next step in data reduction is to interface the
memory output with a teletype machine to obtain a punched
23
24
In out
I
BIT
S y n ch \"oniz.e.r
Oecotnh'lu.tator
SecDn dary
TOr'
One Word pex
Synchronizer
Frame
Buffer
Thput
.----1
Con troIS'-----="" · Fo t mat
1--4---------'
s~lector
Ou.tpLLt
Clocks
Outr.u..t
.________----:"""' Data
S2lector-
Real
Cou.hts(
MDI
Se2cand
IMohitorl
Tim~
I
Display
Figure 8
Future developments
.tJ. ........ I.,...,..
\.I I .:I J '-'';:[
Calculator
25
tape record of the intercept data.
This tape may be then'
used with a time share console for computer miss distance
and trajectory determination.
Development of the VPMDI system also includes plans
for an analog calculator for real time miss distance
data.
Two important benifits of a VPMDI system are now
becoming apparent.
The completed system will allow
faster data reduction and also provide data necessary for
more accurate computer simulation of intercepts and
valuable data for missile designers.
Because the secondary synchronizer is not designed
to work with telemetry signals with less than two words
per frame, a separate decommutator must be built for one
word per frame telemetry signals.
With this board in use
it will be possible to replace the calibration equipment
used in the present photon miss distance system.
BIBLIOGRAPHY
Mahoney, Mathew; Peticolas, Alfred; and Laguzzi, Mario.
Logic Design. New York: RCA Institutes, 1967.
Miller, M. J. "Transients Do Not Affect This Start-Stop
Oscillator." Electronic Engineering, March 1973,
PP• 22-23·
·
Peticolas, A. B., and Weiss, R. E. Digital syst~ms
Engineering. Clark, N. J.: RCA Institutes, 1970.
PMR Secondary Synchronizer Preliminary Manual.
RCA.
1966.
RCA Solid State Databook. Somerville, N. J.:
RCA, 1972. SSD-203: COS/MOS Digital Integrated
Circuits.
26