aVLSI Array of Spiking
Neurons with Dynamical
Synapses
Mike Chi
Spring 20008
VLSI Neural Networks
•
Challenge in representing synaptic connections
between neurons on chip
•
Address Event Representation
•
Use high speed digital bus to time multiplex
spike events
•
Neurons in an array (like RAM or image
data)
•
Dynamic connections between neurons on
array
Row Addressing
AER Array of Spiking Neurons
00
01
02
03
10
11
12
13
20
21
22
23
30
31
32
33
Column Addressing
Control Logic
I&F Neuron Model
•
•
Must be compact
Membrane potential as
voltage on capacitor
•
Synapse as a current
source charging membrane
capacitor
•
Spike generator when
membrane voltage reaches
threshold
•
External reset after spike
Vdd
Vsyn
Vdd
Vmem
Reset
Simple I&F Cell
Spike
VLSI Synapses
• Current Source
• Switched Capacitor Conductance
• Integrator
• Floating Gate
• Full Biophysical Model
Neuron Design
• Integrate and Fire Neuron (Goldberg 2001)
with AER interfacing
• Positive feedback loop to generate spike
events
• Programmable threshold
Membrane Voltage
and Comparator
Vdd
Event Generation and
Reset Service
AER Interfacing
Vdd
Vdd
Vbias
ROW_SCAN
Vmem
Vthresh
Vdd
R_ACK
C_REQ
R_REQ
C_ACK
Goldberg, et. al. 2001
Synapse Design
• Inspired by Batolozzi and Indiveri, 2007
• Simplified and “enhanced”
• Two stages
• Spike Filter and Current Pulse Generator
• Conductance between synaptic reversal
potential and membrane voltage
Spike Filtering/Gain
Current Pulse
Vdd
Vtau
Vdd
Vdd
Csyn
Vdd
Vth
Vr
Vmem
ADDR
Vw
Input Weight
Conductance
Neuron
Synapse-Neuron Pair
• Connected a single excitatory synapse to
I&F Neuron
• Tested synapse-neuron response for
different spike input frequencies