White Paper
®
LogicLock Methodology
Introduction
Available in the Quartus® II software, the LogicLockTM methodology aids in the design and optimization of
programmable logic devices (PLDs). It provides a combination of automation and user control for design reuse and
modular, hierarchical, and incremental design flows. This white paper describes the LogicLock methodology and
how it accelerates various PLD-based design flows.
Background
PLDs can implement large system designs that contain millions of gates, megabits of embedded memory, and
intellectual property (IP) components. Design teams often work on large designs. The design complexity requires
EDA tools to manage and optimize the design. Large design management is difficult, but performance optimization is
even more difficult. Optimization requires many design iterations when adding or modifying components.
Complex, large system designs require the following:
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The use of modular, hierarchical, or incremental design methods
Software that makes management and optimization easier
Use of IP blocks
Reuse of previously optimized design modules
Through its control of placement of specified logic modules, the LogicLock methodology assists in meeting the
requirements of large system design.
Figure 1. Traditional & LogicLock Design Flows
A-WP-LOGICLOCK-1.0
August 2001, ver. 1.0
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Altera Corporation
LogicLock Methodology
LogicLock Design Flow
In both traditional and LogicLock flows, the designer divides the system into modules. The modules can be
individual circuits, parts of circuits, or parts of the design hierarchy. After module design and optimization, the
designer integrates the modules into the system. Finally, the designer tests and optimizes the system. Figure 1
illustrates the traditional and LogicLock design flows.
In the traditional flow, the system may not meet performance requirements despite each module meeting the
requirements before integration. Even with the satisfaction of timing requirements, changes to one module can affect
the performance of others. Re-optimizing modules to meet system performance results in many design iterations.
The LogicLock methodology makes design, testing, and optimization of each individual module easy, along with the
integration of these modules into a system, while retaining the optimized characteristics of the individual modules.
Module integration into the system then requires only system optimization between modules. The LogicLock methodology provides additional flexibility by allowing the Quartus II software to automatically place defined modules,
or allowing the user to control the placement of specific modules, which provide performance preservation and optimization.
The LogicLock Methodology Description
Use of the LogicLock design flow requires the creation of LogicLock regions, which determine the placement of
design modules. A LogicLock region can contain a number of device resources, such as digital logic and memory
bits. The logic assigned to a LogicLock region can include a particular module or parts of different modules as chosen
by the designer. The Quartus II software places any logic assigned to a LogicLock region within the region during
fitting.
LogicLock Region Properties
The use creates LogicLock regions using Tcl command scripts or the Quartus II Floorplan Editor or LogicLock
Regions window. The size and location properties define LogicLock regions. The height and width of the rectangular
area the region covers defines the region’s size. A region’s origin, the position of its top-left corner, defines the
location of a region. The user specifies the location as locked or floating.
If the location is floating, the Quartus II software determines the location during its optimization process. If the region
is specified as auto-size, then the software determines the appropriate size to fit the logic assigned to the region.
When the user specifies both the size and location, the user must include enough device resources to accommodate
the assigned logic. Table 1 shows the valid combinations of the size and location properties.
Table 1. LogicLock Region Properties
Location
Size
Description
Floating
Auto
Floating
Fixed
Locked
Fixed
Most flexible kind of LogicLock constraint. Allows the software to choose
appropriate size and location of the logic assigned to it.
Assumes the size of the LogicLock constraint area is already optimal. Can result in
less efficient use of resources if this is false.
Least flexible LogicLock constraint. Gives full control of the placement to the user.
Most likely to produce “no-fits.”
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LogicLock Methodology
Locking LogicLock Region Content
Following a successful compilation, lock the LogicLock regions to help maintain performance in subsequent
compilations of the design. The designer has two options when locking a region:
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Lock the region’s size and location. In this case, the Quartus II software places the logic anywhere within the
specified region on a subsequent compile. This option only preserves the size and the location of the region.
Back-annotate, the region’s placed contents. In this case, the Quartus II software locks the assigned design
elements, called nodes, to specific positions within the LogicLock region. This option preserves the placement of
logic within the region and more likely maintains the performance of the logic within the region when the
designer integrates the logic with the top-level design.
After locking the properties of the region and the assignment of nodes to locations inside the region, the designer can
make the region floating. This is desirable during the integration phase of the module, because a floating region
allows the Quartus II software to determine the best location for the module. A floating region preserves the relative
placement of the logic within the floating region. Preserving relative placement of the logic means the Quartus II
software can choose the placement of the LogicLock region on the floorplan, but cannot change the relative locations
of the nodes within the region. Floating regions also allow a given module to be reused and integrated more than once
in a design.
Hierarchical LogicLock Regions
The designer can specify a hierarchy for a set of LogicLock regions. A hierarchy provides the designer with
flexibility in specifying LogicLock region constraints. Parent-child relationships among regions define the hierarchy.
Any combination of region types is possible, but a child region must be fully contained within its parent region. If a
child region is floating, then the Quartus II software chooses the appropriate location within the parent region. If the
child region is locked, it maintains its position with respect to the parent region even if the parent region is floating.
A designer must differentiate between a LogicLock region hierarchy and a design hierarchy. A hierarchy of
LogicLock regions is a set of regions among which parent-child relationships exist. It only defines the relationship
between placement constraints imposed by LogicLock regions. The design hierarchy is different, because it reflects
the structure of the source code and defines which modules instantiate others. In general, the LogicLock region
hierarchy need not reflect the design hierarchy.
Figure 2 shows an example of a design hierarchy. The top-level design B consists of two modules: IP and A. The
design hierarchy indicates that the top-level design B creates an instance of module IP and A. The designer defines a
LogicLock hierarchy after defining design hierarchy. A LogicLock hierarchy example is to create a parent LogicLock
region and assign the top-level design B to it and then create two child regions and assign module IP to one and
module A to the other. In this case, the regions reflect the design hierarchy. But, the user may choose to place module
IP in the parent region and the top-level design B in the child region, and also choose to create a child region within
the existing child region and assign a selected part of module A to it. The best organization depends on the circuit
characteristics.
Figure 2. Modular Design Hierarchy Example
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LogicLock Methodology
Improving the Design Flow with the LogicLock Methodology
A shortfall of the traditional design flow is that the performance of a module can be different from the performance of
the module implemented on its own, when the module is integrated with the top-level system. Top-level compilation
can produce different results than by logic synthesis and placement, which can lead to different performance. To
remedy this problem, the LogicLock methodology provides a form of incremental compilation. Information required
for incremental compilation includes:
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An atom-level netlist as generated by a logic synthesis tool. An atom-level netlist specifies the design in terms of
device primitives called atoms. In an atom-level netlist, the names of atoms are persistent, hence, the names do
not change during the synthesis of the system.
The specification of placement using LogicLock assignments, including the LogicLock region properties and the
assignment of nodes or hierarchies of nodes within the region. The names in the atom-level netlist specify the
assignment of nodes. To obey these constraints in the top-level design, the Quartus II software preserves the node
names during integration.
Modular, hierarchical, incremental, and team-based design flows use a module’s preserved placement information
during its integration into a larger system.
Modular Design Flow
The LogicLock methodology enables the modular design flow. Figure 2 illustrates the modular design flow. The
design hierarchy consists of the top-level design B and the modules IP and A. The top-level design B merely
instantiates the two modules and makes connections between them. Module A is specific to this project, while
module IP is likely used in other projects as well. The designer wants to design and optimize these modules
separately and achieve the desired performance once the modules are integrated with the top-level design.
In the modular design flow, the designer first creates separate projects for the modules IP and A. Next, the designer
designs and optimizes modules separately. Optimization places each module in a single LogicLock region or in some
hierarchy of LogicLock regions as determined by the designer. Once the design meets the requirements, the designer
locks the region. Then the designer imports the atom-level netlists and LogicLock assignments for each module into
system B. The designer or the Quartus II software determines the placement of the modules in the top-level design B.
Finally, the designer compiles and tests the system design.
Hierarchical Design Flow
The designer can also improve the hierarchical design flow by using the LogicLock methodology. Figure 3 gives an
example of a hierarchical design G that contains modules D, E, and F. Module E contains the module B from Figure
2. Module D is not critical to the performance of the system, so the designer can use the hardware description
language source code that specifies the module without any placement information. The designer has identifies
modules E and F as critical to the performance and optimizes them separately. Module E consists of a hierarchy of
modules, while module F does not. The designer compiles module F after optimization to generate an atom-level
netlist and placement information for module F. The atom-level netlist and placement information for module E
require two steps. First, the designer generates this information for module B and then imports this information into
module E. Second, once the optimization of module E is done, the designer generates this information for module E
and imports this information into the top-level design G.
In the previous example, the top-level design was done in the Quartus II software. The designer may also choose to
generate the top-level design file with a third-party tool. In this case, the third-party tool must pass the required node
names and LogicLock assignments to the Quartus II software by using specified file formats.
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LogicLock Methodology
Figure 3. Hierarchal Design Flow Example
Incremental Design Flow
The LogicLock methodology facilitates the incremental design flow. Figure 4 shows an example where the designer
implements the top-level design G from Figure 3 and then decides to add a module, H. The LogicLock methodology
allows the module H logic to be added without affecting the synthesis and placement of the existing system.
Figure 4. Incremental Design Flow Example
Team-Based Design Flow
The LogicLock methodology supports a team-based design flow. The LogicLock methodology enables the system
designer to create a floorplan for the system up-front. Figure 5 shows an example of a team-based flow. The
team-based design flow using the LogicLock methodology follows these steps:
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2.
The system designer partitions the design into modules A, B, and C.
The system designer creates the top-level design by instantiating modules A, B, and C, specifying the
connections between the modules, and creating timing assignments and placement constraints. If the system
designer knows an approximation of the size requirements for each module of the design, the designer can place
area restrictions by creating a LogicLock region for each module.
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LogicLock Methodology
The system design assigns the detailed module designs to other designers.
Designers create individual projects for their modules and use the assignments created by the system designer.
Designers design and verify their modules.
Designers add, if necessary, LogicLock constraints to preserve performance of the modules or to help in the
optimization of the overall design.
Once the designers complete their modules, the system designer imports theses modules, along with the specified
constraints, into the top-level design.
The system designer does a final top-level design compilation and verification.
Figure 5. Team-Based Design Flow Example
Design Performance Enhancement Strategies
The LogicLock methodology also improves the performance of designs that do not necessarily consist of individually
optimized modules. The ability of LogicLock regions to group nodes together and provide relative placement
enhances the usability of pure place-and-route.
The design strategies for performance enhancement depend on the structure of a particular circuit. Strategies include:
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Defining regions based on design hierarchy if the hierarchy closely resembles the structure of the circuit. These
designs typically consist of tightly integrated modules, where the logic for each module is self-contained and
modules communicate through well-defined interfaces.
Defining regions based on the critical path, if the critical path is long and spans multiple modules. Keeping the
nodes in the critical path or the modules containing the critical path together may lead to improved performance.
Defining regions based on connections by grouping nodes with high fan-outs and high fan-ins together to reduce
delays in connections and wiring congestion in the device.
With the LogicLock methodology, the user can choose to optimize modules either individually or after they have
been integrated with the top-level design. The user can exercise varying amounts of control over the placement by
using different types of regions. By using auto-sizing and floating location, the Quartus II software can determine the
best size and location for a LogicLock region.
If modules are optimized individually and imported into the top-level design, then the user can follow the approach
described in the Improving the Design Flow with the LogicLock Methodology section of this white paper. LogicLock
assignments made for each optimized module may contain LogicLock regions and back-annotated contents.
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LogicLock Methodology
Another approach is to optimize the top-level design without first optimizing the individual modules. This approach
allows the Quartus II software to place nodes within regions and move regions across the device. The user assigns
modules to LogicLock regions and then compiles the entire design. With this approach the user to can place elements
from different modules in a LogicLock region.
For the reader familiar with Altera terminology, LogicLock regions are similar to cliques in that they allow for the
grouping of LEs. Setting the region size to “auto” results in behavior similar to a previously supported feature called
a “best clique.” Fixing the size of a LogicLock region to an LAB or a row is similar to an LAB or row clique.
LogicLock regions are also similar to “custom regions” in that a definable area can be assigned entities and nodes. If
the location of the LogicLock region is locked, then it behaves similarly to a custom region.
Design Reuse
LogicLock facilitates design reuse by its ability to reproduce the performance of a module designed in a different
project. For frequently used modules, create a library of verified designs that can be incorporated into other larger
designs. The library has to contain the atom-level netlist, the LogicLock assignments, and a report file detailing
useful information to the user, such as performance and size. With a parameterized module, Tcl scripts can specify the
module’s behavioral description and LogicLock assignments.
Targeting the same device used in the original design likely achieves the best results, although other devices in the
same family will likely work well. When using a different device in the same family, the exact placement of the
region may not be possible. Similar performance, however, may be possible by making the region float. The floating
region still groups the logic together and guides the Quartus II software toward achieving a placement that meets the
performance requirements of the module. A similar approach can also be taken if exact placement of a module is not
applicable because of multiple instantiations of a module in a top-level design.
Conclusion
The LogicLock methodology advances the design of large systems on PLDs. It provides the designer with
capabilities in the management and optimization of large systems. Its multifaceted capabilities result in shortened
design cycles and faster time-to-market.
For information on how to use the LogicLock methodology in the Quartus II software please see Application Note
161: Using the LogicLock Design Methodology in the Quartus II Design Software.
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