White Paper
®
Implementing an
IEEE Std. 802.16-Compliant FEC Decoder
Introduction
The IEEE draft standard P802.16/D5-2001, Air Interface for Fixed Broadband Wireless Access Systems, “specifies
the air interface of fixed (stationary) point-to-multipoint broadband wireless access systems providing multiple
services.” (See “References” on page 5.) This standard enables vendors to create and deploy broadband wireless
access products worldwide. This white paper describes the forward error correction (FEC) decoding requirements of
the IEEE Std. 802.16 specification, and explains how you can implement decoders that comply with the requirements
using the Altera® Reed-Solomon Compiler and Viterbi Compiler MegaCore® functions.
IEEE Std. 802.16 Requirements
Table 1 shows the FEC code types that the specification allows. Code types 1 and 2 must be supported, while code
types 3 and 4 are optional.
Table 1. FEC Code Types
Note (1)
Code Type
Outer Code (2)
Inner Code
1
Reed-Solomon over GF(256)
None
2
Reed-Solomon over GF(256)
(24,16) Block Convolutional Code
3 (Optional)
Reed-Solomon over GF(256)
(9,8) Parity Check Code
4 (Optional)
Block Turbo Code
–
Note:
(1) IEEE draft standard 802.16 page 261.
(2) GF = Galois field.
IEEE Std. 802.16 supports different channel sizes and modulation techniques as shown Table 2.
Table 2. IEEE Std. 802.16 Channel Sizes & Modulation Techniques
Channel Size
(MHz)
Symbol
Rate
(MBaud)
Bit Rate
QPSK
(Mbits/s)
Bit Rate
16-QAM
(Mbits/s)
20
16
32
25
20
40
28
22.4
44.8
Notes (1), (2), (3)
Bit Rate
64-QAM
(Mbits/s)
Recommended
Frame Duration
(ms)
Number of
PSs/Frame
(4)
64
96
1
4,000
80
120
1
5,000
89.6
134.4
1
5,600
Note:
(1) IEEE draft standard 802.16 page 285.
(2) QPSK = quadrature phase shift keying.
(3) QAM = quadrature amplitude modulation.
(4) PS = physical slot.
M-WP-IEEE802.16-1.0
December 2001, ver. 1.0
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Altera Corporation
Implementing an IEEE Std. 802.16-Compliant FEC Decoder White Paper
Outer Code Requirements for Code Types 1 through 3
IEEE Std. 802.16 specifies the outer code requirements for code types 1 through 3 as follows:
The specified code generator polynomials are given by:
Code Generator Polynomial: g(x) = (x+µ0)(x+µ1)(x+µ2) ... (x+µ2T-1), where µ= 02hex
Field Generator Polynomial: p(x) = x8 + x4 + x3 + x2 + 1
The specified code has a block length of 255 bytes and shall be configured as an RS(255,255-R) code with
information bytes preceded by (255-N) zero symbols, where N is the codeword length and R the number of
redundancy bytes (R = 2*T ranges from 0 to 32, inclusive).
The value of K and T are specified for each burst profile by the MAC. Both Fixed Codeword Operation and
Shortened Last Codeword Operation, as defined below, are allowed.
When using Code Type 2, the number of information bytes K shall always be an even number so that the
total codeword size (K+R) is also an even number. This is due to the fact that the BCC code requires a pair of
bytes on which to operate.
Inner Code Requirements for Code Type 2
IEEE Std. 802.16 specifies the inner code requirements for code type 2 as follows:
The inner code in Code Type 2 consists of short block codes derived from a 4-state, nonsystematic,
punctured convolutional code (7,5). The trellis shall use the tail-biting method, where the last 2 bits of the
message block are used to initialize the encoder memory, in order to avoid the overhead required for trellis
termination. Thus, the encoder has the same initial and ending state for a message block.
For this concatenated coding scheme, the inner code message block is selected to be 16 bits. The puncturing
pattern is described in Table 95 for the (24,16) case.
Designing an IEEE Std. 802.16 Compliant System Using Altera MegaCore Functions
You can use the Altera Reed-Solomon Compiler and Viterbi Compiler MegaCore functions to create a system that is
compliant with IEEE Std. 802.16. The Reed-Solomon Compiler generates a decoder for the outer codes for code
types 1 through 3 and the Viterbi Compiler generates a decoder for the inner code for code type 2.
The Reed-Solomon decoder must be able to handle data rates up to 134.4 Mbps for code type 1. Code type 2 is only
used for QPSK modulation. Therefore, the Viterbi decoder must be able to handle data rates up to 44.8 Mbps.
Reed-Solomon Decoder Implementation
You can use a variable discrete Reed-Solomon decoder to meet the requirements of IEEE Std. 802.16. The variable
decoder supports real-time changing of N ,the number of symbols in the codeword, and R, the number of check
symbols in a codeword. Therefore, the decoder supports both fixed codeword operation and shortened last codeword
operation as defined in the specification. Additionally, if your implementation does not need check symbols, you can
use the bypass functionality. Figure 1 shows a screen shot of the Reed-Solomon Compiler wizard, in which you set
the parameters of the decoder for IEEE Std. 802.16.
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Altera Corporation
Implementing an IEEE Std. 802.16-Compliant FEC Decoder White Paper
Figure 1. Setting Parameters for IEEE Std. 802.16 Reed-Solomon Decoder
Table 3 shows the Altera device resources used and the throughput achieved by the decoder.
Table 3. Reed-Solomon Decoder Resources & Throughput
Device
Logic Elements
(LEs)
Embedded System
Blocks (ESBs)
fMAX (MHz)
Throughput
(Mbps)
APEXTM 20KE
4,378
APEX 20KC
4,378
3
83
151
3
100
APEX II
4,378
182
2
110
200
Viterbi Decoder Implementation
You can use the Viterbi Compiler to create a parallel block decoder that can decode the convolutional codes specified
in IEEE Std. 802.16. Sixteen bits of data are convolutionally encoded and the puncturing patterns are applied to
obtain a 2/3 punctured code or 24 bits. The data is modulated using QPSK and transmitted to the receiver, which
stores the 24 bits in memory.
To decode the tail-biting method defined in the specification, the received data is read twice from memory and then
feeds the depuncturing unit. The depuncturing unit introduces 0s to the punctured positions, which increases the
number of symbols to 16 pairs. The result from the depuncturing unit feeds twice consecutively to the parallel
decoder for a block size of 32. The number of coded bits of the parallel block decoder (n) is equal to 2. Therefore, a
pair of symbols enter the block decoder during each clock cycle. Of the 32 bits at the output, the first 16 are discarded
and the last 16 are used.
Figure 2 shows the double-pass traceback operation for tail-biting decoding. The first pass converges to a last state
that is the same as the starting state (as defined in the specification). Because the start state cannot be known when
decoding begins, the decoder must use an arbitrary start state. The Altera Viterbi block decoder always starts a block
from state 0. Therefore, the first traceback path bits are discarded, as shown in Figure 2. However, during the first
pass, the decoder converges to the correct path and the first path terminates in the correct start state for the second
pass.
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Altera Corporation
Implementing an IEEE Std. 802.16-Compliant FEC Decoder White Paper
Figure 2. Double-Pass Traceback Operation for Tail-Biting Decoding
Figure 3 shows the additional logic that you need to implement—in addition to the Viterbi block decoder—to meet
IEEE Std. 802.16. The sequencer is a control block that implements the double-pass data feeding and FIFO control
signals. The depuncturing unit performs the 2/3 depuncturing rate required by the specification.
Figure 3. System Overview Implementing Double-Pass Tail-Biting Decoding
Received Data
Dual-Port
RAM FIFO
Depuncturing
Viterbi
Block
Decoder
Decoded Data
Sequencer
Figure 4 shows a screen shot of the Viterbi Compiler wizard, in which you set the parameters of the decoder for IEEE
Std. 802.16.
Figure 4. Setting Parameters for IEEE Std. 802.16 Parallel Block Viterbi Decoder
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Altera Corporation
Implementing an IEEE Std. 802.16-Compliant FEC Decoder White Paper
Tables 4 and 5 show the Altera device resources used and the throughput achieved by the decoder. The value of the
Softbits parameter, which you set in the Viterbi Compiler wizard, depends on the quality you want to implement.
Table 4. Viterbi Decoder Resources & Throughput, Softbits = 3 without BER Block
Device
LEs
ESBs
fMAX (MHz)
Throughput
(Mbps)
APEX 20KE
420
2
113
106
APEX 20KC
420
2
127
119
APEX II
421
2
144
135
Table 5. Viterbi Decoder Resources & Throughput, Softbits = 4 without BER Block
Device
LEs
ESBs
fMAX (MHz)
Throughput
(Mbps)
APEX 20E
452
2
115
108
APEX 20KC
452
2
128
120
APEX II
453
2
165
155
Conclusion
FEC is an important part of the IEEE Std. 802.16 specification. The Altera Reed-Solomon Compiler and Viterbi
Compiler MegaCore functions have easy-to-use wizard interfaces that you can use to implement an IEEE Std.
802.16-compliant system.
References
IEEE Draft Standard for Local and Metropolitan Area Networks – Part 16, Air Interface for Fixed Broadband
Wireless Access Systems, IEEE P802.16/D5-2001, pp 1, 261 – 263.
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