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White Paper
Co-Simulation of Embedded Systems Implemented in FPGAs
Introduction
As the market for embedded systems expands, both hardware and software aspects of these systems are becoming
more complex. In this environment, hardware design is expedited by incorporating pre-developed complex
intellectual property blocks. Adding custom logic brings unique functionality and product differentiation to the
system. Increasingly large software elements, such as real-time operating systems, are then being matched to these
hardware designs.
Each stage of embedded system development brings its own verification challenges. Debugging hardware, software,
and the integration of both of those elements requires comprehensive visibility into the design. Typical verification
methods inevitably focus on one or the other of these areas, but not both. This paper describes how co-simulation of
hardware and software (using the Excalibur™ Stripe Simulator tool from Altera as an example) accelerates
embedded system verification.
Traditional Verification Methods
Hardware verification typically begins with simulation of the various peripherals using either a bus-functional or
register-transfer level (RTL) model. With software, engineers will typically start testing before hardware components
are available, using an instruction set simulator, because trying to simulate software on a hardware model of a
processor can be painfully slow. When verifying complex software, such as a real-time operating system, realistic
simulation using an instruction set simulator is virtually impossible. If the software is to be verified on the actual
target, the validity of such verification is subject to the stability of the hardware design—if changes need to be made
to the hardware, the software often needs to be modified as well. These modifications must be verified. This costly
cycle continues until the software and hardware function properly as the embedded system.
Co-Simulation Benefits
Co-simulation aids in system verification as well as software development. Modifications required as a result of
debugging can be tested without having to rework a board or silicon prototype. Co-simulation models provide virtual
prototypes for the software engineer, accelerating the software design phase.
With FPGAs, routines that run slowly in software can be implemented in hardware logic to meet performance
requirements. Likewise, if additional hardware resources are required, non-time critical hardware functions can be
implemented in software instead. As these resources are re-allocated frequently, an effective verification method such
as co-simulation is essential to ensure coherence between hardware and software.
Excalibur Stripe Simulator
The Excalibur Stripe Simulator (ESS) is a functionally accurate co-simulation tool that can act as both an instruction
set simulator and a logic simulation model, as shown in Figure 1. ESS provides the capability to perform
simultaneous software debugging and logic simulation by synchronizing a software debugger and a logic simulation
environment. This gives the designer valuable insight into the interactions between software and hardware. It models
an Excalibur device embedded processor subsystem containing an ARM922T™ processor and several common
peripherals. The FPGA section of Excalibur devices can be used to implement custom user peripherals that can
interact with the processor subsystem. The interaction between the processor subsystem components and the
programmable logic is via embedded bridges that enable communication in either direction. Because ESS models the
bridge transactions, the custom peripherals in the programmable logic section can be modeled using the standard
hardware models and linked into the simulation. ESS also models the Excalibur device boot-from-flash functionality.
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Co-Simulation of Embedded Systems Implemented in FPGAs
This allows designers to verify the boot code and process of the system without using external memory models. The
simulation of the boot process can also be bypassed in order to quickly initialize internal memory. This is done using
memory initialization files that are read in by the model. The ESS also allows hardware engineers to develop
hardware components targeted for programmable logic faster and more efficiently. The bus functional model in the
ESS is driven by C or assembly code instead of a cumbersome scripting language. Thus, if required, the transition
from an ESS simulation to an RTL simulation is easy.
The ESS supports common hardware simulators such as ModelSim. It works with software debuggers such as the
GNUPro debugger, GDB, as well as the ARM Developer Suite debuggers, AXD and ADW. ESS also allows the user
to simulate interactive programs. The FIFO buffers used for UART receive and transmit functions in the model can
connect to a terminal window on the host machine.
Figure 1. Co-simulation with ESS
ESS
SOFTWARE DEBUGGER:
Full SW debug control.
View ARM/stripe registers
LOGIC SIMULATOR:
View waveforms
View signal values
Table 1 illustrates the advantages of using the ESS over a hardware processor model. The ESS can execute over
500,000 ARM instructions per second. Table 1 shows the performance comparison between simulations of sample
Excalibur designs using ESS and a cycle-accurate hardware model of the processor subsystem.
Table 1. Comparison of Simulation Times
Simulation Time
Excalibur Design
RTL Hardware Model
ESS
25 hours
7 seconds
DPRAM design
20 minutes
9 seconds
Multi-Master Design
5 minutes
5 seconds
15 days (estimate)
3 minutes
Hello World
VxWorks Boot
Figure 2 shows how the ESS can execute system simulation at higher rates than pure hardware models. The processor
instruction set simulator executes code independent of the hardware logic simulation except where the processor
subsystem interfaces to the FPGA portion through the DPRAM interface or by a bus functional model, if such a
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Co-Simulation of Embedded Systems Implemented in FPGAs
model is used. The Verilog HDL/VHDL portion interacts with the C/C++ model using the Programming Language
Interface (PLI) and the Foreign Language Interface (FLI).
Figure 2. ESS Implementation
Embedded Processor
and Peripherals
C/C++ code
PLI/FLI
DPRAM
Interface
Bus Functional
Model
Verilog HDL/VHDL
FPGA Design
Conclusion
The combination of increased embedded system complexity, the quest for shorter time-to-market, and heightened
system performance requirements drive the need for more efficient verification methods. Co-simulation of hardware
and software can accelerate software development and shorten the system verification cycle. Programmable logic
takes advantage of co-simulation benefits when hardware/software trade-offs are made. The ESS provides this
capability for embedded systems based on Excalibur devices.
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